[ /Title (CD74 HC85, CD74 HCT85 ) /Subject (High Speed CMOS Logic 4-Bit Magnitude Compara- CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Data sheet acquired from Harris Semiconductor SCHS136E High-Speed CMOS Logic 4-Bit Magnitude Comparator August 1997 - Revised October 2003 Features Description • Buffered Inputs and Outputs The ’HC85 and ’HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. • Typical Propagation Delay: 13ns (Data to Output at VCC = 5V, CL = 15pF, TA = 25oC • Serial or Parallel Expansion Without External Gating These 4-bit devices compare two binary, BCD, or other monotonic codes and present the three possible magnitude results at the outputs (A > B, A < B, and A = B). The 4-bit input words are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC The devices are expandable without external gating, in both serial and parallel fashion. The upper part of the truth table indicates operation using a single device or devices in a serially expanded application. The parallel expansion scheme is described by the last three entries in the truth table. • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V Ordering Information • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD54HC85, CD54HCT85 (CERDIP) CD74HC85 (PDIP, SOIC, SOP, TSSOP) CD74HCT85 (PDIP, SOIC) TOP VIEW B3 1 TEMP. RANGE (oC) PACKAGE CD54HC85F3A -55 to 125 16 Ld CERDIP CD54HCT85F3A -55 to 125 16 Ld CERDIP CD74HC85E -55 to 125 16 Ld PDIP CD74HC85M -55 to 125 16 Ld SOIC CD74HC85MT -55 to 125 16 Ld SOIC CD74HC85M96 -55 to 125 16 Ld SOIC CD74HC85NSR -55 to 125 16 Ld SOP CD74HC85PW -55 to 125 16 Ld TSSOP PART NUMBER 16 VCC (A < B) IN 2 15 A3 CD74HC85PWR -55 to 125 16 Ld TSSOP (A = B) IN 3 14 B2 CD74HC85PWT -55 to 125 16 Ld TSSOP (A > B) IN 4 13 A2 CD74HCT85E -55 to 125 16 Ld PDIP (A > B) OUT 5 12 A1 (A = B) OUT 6 11 B1 CD74HCT85M -55 to 125 16 Ld SOIC (A < B) OUT 7 10 A0 CD74HCT85MT -55 to 125 16 Ld SOIC GND 8 9 B0 CD74HCT85M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 PFunctional Diagram 15 A3 13 A2 12 A1 10 A0 (A < B) IN (A = B) IN (A > B) IN B3 7 2 3 6 4 5 (A < B) OUT (A = B) OUT (A > B) OUT 1 14 B2 11 B1 9 B0 TRUTH TABLE COMPARING INPUTS A3, B3 A2, B2 A1, B1 CASCADING INPUTS OUTPUTS A0, B0 A>B A<B A=B A>B A<B A=B SINGLE DEVICE OR SERIES CASCADING A3 > B3 X X X X X X H L L A3 < B3 X X X X X X L H L A3 = B3 A2 >B2 X X X X X H L L A3 = B3 A2 < B2 X X X X X L H L A3 = B3 A2 = B2 A1 > B1 X X X X H L L A3 = B3 A2 = B2 A1 < B1 X X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H PARALLEL CASCADING A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H A3 = B3 A2 = B2 A1 = B1 A0 = B0 H H L L L L A3 = B3 A2 = B2S A1 = B1 A0 = B0 L L L H H L H = High Voltage Level, L = Low Voltage, Level, X = Don’t Care 2 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V V -5.2 6 5.48 - - 5.34 - 5.2 - 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS A0-A3, B0-B3 and (A = B) IN 1.5 (A > B) IN, (A < B) IN 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay, An, Bn to (A > B) OUT, (A < B) OUT An, Bn to (A = B) OUT SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 195 - 245 - 295 ns 4.5 - - 39 - 47 - 59 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 6 - - 33 - 42 - 50 ns ns tPLH, tPHL CL = 50pF 2 - - 175 - 240 - 265 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns 4 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Switching Specifications Input tr, tf = 6ns PARAMETER (Continued) TEST CONDITIONS SYMBOL (A > B) IN, (A < B) IN, (A = B) IN tPLH, tPHL CL = 50pF to (A > B) OUT, (A < B) OUT (A > B) IN to (A = B) OUT Output Transition Times (Figure 1) CPD CIN VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 140 - 175 - 210 ns 4.5 - - 28 - 35 - 42 ns 5 - 11 - - - - - ns CL = 50pF 6 - - 24 - 30 - 36 ns 2 - - 120 - 150 - 180 ns 4.5 - - 24 - 30 - 36 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 20 - 26 - 31 ns - 5 - 24 - - - - - pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - - - 10 - 10 - 10 pF tTLH, tTHL CL = 50pF Input Capacitance -55oC TO 125oC CL = 15pF tPLH, tPHL CL = 50pF Power Dissipation Capacitance (Notes 3, 4) -40oC TO 85oC 25oC - HCT TYPES Propagation Delay, An, Bn to (A > B) OUT, (A < B) OUT tPLH, tPHL CL = 50pF CL = 15pF 4.5 - - 37 - 46 - 56 ns 5 - 15 - - - - - ns An, Bn to (A = B) OUT tPLH, tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns 5 - 17 - - - - - ns (A > B) IN, (A < B) IN, (A = B) IN tPLH, tPHL CL = 50pF to (A > B) OUT, (A < B) OUT CL = 15pF 4.5 - - 30 - 38 - 45 ns 5 - 12 - - - - - ns (A > B) IN to (A = B) OUT tPLH, tPHL CL = 50pF CL = 15pF 4.5 - - 31 - 39 - 47 ns 5 - 13 - - - - - ns Output Transition Times (Figure 1) tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns 5 - 26 - - - - - pF - - - 10 - 10 - 10 pF CL = 15pF Power Dissipation Capacitance (Notes 3, 4) CPD Input Capacitance CIN - NOTES: 3. CPD is used to determine the dynamic power consumption, per gate/package. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5 CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Test Circuits and Waveforms GND VCC GND LEAST SIGNIFICANT 4-BITS OF EACH WORD A0 A1 A2 A3 B0 B1 B2 B3 (A > B) IN (A = B) IN (A < B) IN A0 A1 CD74HC85 A2 CD74HCT85 A3 B0 B1 B2 B3 (A > B) IN (A = B) IN (A < B) IN A4 A5 A6 A7 B4 B5 B6 B7 MOST SIGNIFICANT 4-BITS OF EACH WORD A4 A5 A6 A7 B4 B5 B6 B7 A0 A1 A2 A3 B0 B1 B2 B3 CD74HC85 CD74HCT85 (A > B) OUT (A = B) OUT (A < B) OUT (A > B) IN (A = B) IN (A < B) IN A0 A1 A2 A3 B0 B1 B2 B3 FIGURE 3. SERIES CASCADING - COMPARING 12-BIT WORDS 6 CD74HC85 CD74HCT85 (A > B) OUT (A = B) OUT (A < B) OUT OUTPUTS CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 Test Circuits and Waveforms B1 A1 B0 A0 GND VCC GND CD74HC85 B3 CD74HCT85 A3 B2 A2 (A < B) OUT B1 (A = B) OUT A1 (A > B) OUT B0 A0 (A < B) IN (A = B) IN (A > B) IN B6 A6 B5 A5 B4 A4 B3 A3 B2 GND A2 CD74HC85 B3 CD74HCT85 A3 B2 A2 (A < B) OUT B1 (A = B) OUT A1 (A > B) OUT B0 A0 (A < B) IN (A = B) IN (A > B) IN B11 A11 B10 A10 B9 A9 B8 A8 B7 GND A7 CD74HC85 B3 CD74HCT85 A3 B2 A2 (A < B) OUT B1 (A = B) OUT A1 (A > B) OUT B0 A0 (A < B) IN (A = B) IN (A > B) IN NC NC OUTPUTS B3 CD74HC85 CD74HCT85 A3 B2 A2 (A > B) OUT B1 (A = B) OUT A1 (A < B) OUT B0 A0 (A < B) IN (A = B) IN (A > B) IN FIGURE 4. PARALLEL CASCADING - COMPARING 12-BIT WORDS 7 OUTPUTS PACKAGE OPTION ADDENDUM www.ti.com 17-Oct-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8867201EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC 8601301EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC Lead/Ball Finish MSL Peak Temp (3) CD54HC85F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HCT85F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD74HC85E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC85EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC85M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC85PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT85E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT85EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT85M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT85M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT85M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT85ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT85MT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 17-Oct-2005 Orderable Device Status (1) Package Type Package Drawing CD74HCT85MTE4 ACTIVE SOIC D Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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