Burr-Brown ADS8322YB/2K 16-bit, 500khz, micropower sampling analog-to-digital converter Datasheet

ADS8322
ADS
®
832
2
SBAS215 – JULY 2001
16-Bit, 500kHz, MicroPower Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
●
●
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The ADS8322 is a 16-bit, 500kHz Analog-to-Digital (A/D)
converter with an internal 2.5V reference. The device includes a 16-bit capacitor-based Successive Approximation
Register (SAR) A/D converter with inherent sample-andhold. The ADS8322 offers a full 16-bit interface, or an 8-bit
option where data is read using two read cycles and 8 pins.
The ADS8322 is available in a TQFP-32 package and is
guaranteed over the industrial –40°C to +85°C temperature
range.
HIGH-SPEED PARALLEL INTERFACE
500kHz SAMPLING RATE
LOW POWER: 85mW at 500kHz
INTERNAL 2.5V REFERENCE
UNIPOLAR INPUT RANGE
TQFP-32 PACKAGE
APPLICATIONS
●
●
●
●
CT SCANNERS
HIGH SPEED DATA ACQUISITION
TEST AND INSTRUMENTATION
MEDICAL EQUIPMENT
BYTE
SAR
ADS8322
Output Latches
and
Three State
Drivers
Parallel
Data
Output
+IN
CDAC
–IN
S/H Amp
CLOCK
Comparator
REFIN
REFOUT
Internal
+2.5V Ref
Conversion
and Control
Logic
CONVST
CS
RD
BUSY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
NC
NC
+VA
AGND
+IN
–IN
TQFP
REFIN
Top View
REFOUT
32
31
30
29
28
27
26
25
DB15
1
24 CS
DB14
2
23 BYTE
DB13
3
22 RD
DB12
4
21 CONVST
ADS8322
DB9
7
18 +VD
DB8
8
17 BUSY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
DB7
9
10
11
12
13
14
15
16
DB0
19 DGND
DB1
6
DB2
DB10
DB3
20 CLOCK
DB4
5
DB5
ELECTROSTATIC
DISCHARGE SENSITIVITY
DB11
DB6
+IN to GND ................................................................................ VA + 0.1V
–IN to GND ....................................................................................... +0.5V
VA to GND ............................................................................. –0.3V to +7V
Digital Input Voltage to GND ................................... –0.3V to (VA + 0.3V)
VOUT to GND ............................................................ –0.3V to (VA + 0.3V)
Operating Temperature Range ...................................... –40°C to +105°C
Storage Temperature Range ......................................... –65°C to +150°C
Junction Temperature (TJ max) .................................................... +150°C
TQFP Package:
Power Dissipation ................................................... (TJ max – TA) / θJA
θJA Thermal Impedance ......................................................... 240°C/W
Lead Temperature:
Vapor Phase (soldering, 60s) ................................................. +215°C
Infrared (soldering, 15s) .......................................................... +220°C
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
PIN ASSIGNMENTS
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
3
8
9
10
11
12
13
14
15
16
17
18
19
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BUSY
+VD
DGND
Data Bit 15 (MSB)
Data Bit 14
Data Bit 13
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0 (LSB)
High when a conversion is in progress.
Digital Power Supply, +5VDC.
Digital Ground
20
CLOCK
21
22
23
CONVST
RD
BYTE
24
25
26
27
28
29
30
31
CS
–IN
+IN
AGND
+VA
NC
NC
REFIN
32
REFOUT
An external CMOS compatible clock can be applied
to the CLOCK input to synchronize the conversion
process to an external source.
Convert Start
Synchronization pulse for the parallel output.
Selects 8 most significant bits (LOW) or 8 least
significant bits (HIGH). Data valid on pins 9-16.
Chip Select
Inverting Input Channel
Noninverting Input Channel
Analog Ground
Analog Power Supply, +5VDC.
No Connect
No Connect
Reference Input. When using the internal 2.5V reference tie this pin directly to REFOUT.
Reference Output. A 0.1µF capacitor should be connected to this pin when the internal reference is
used.
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
NO
MISSING
CODES
ERROR (LSB)
ADS8322Y
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
±8
14
TQFP-32
351
–40°C to 85°C
"
"
"
"
"
"
ADS8322YB
±6
15
TQFP-32
351
–40°C to 85°C
"
"
"
"
"
"
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
ADS8322Y/250
ADS8322Y/2K
ADS8322YB/250
ADS8322YB/2K
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “ADS8322Y/2K” will get a single 2000-piece Tape and Reel.
2
ADS8322
SBAS215
ELECTRICAL CHARACTERISTICS: +VA = +5V
At –40°C to +85°C, +VA = +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified.
ADS8322Y
PARAMETER
CONDITIONS
MIN
RESOLUTION
+IN – (–IN)
+IN
–IN
0
–0.1
–0.1
Capacitance
Leakage Current
REFERENCE OUTPUT
Voltage
Source Current
Drift
Line Regulation
REFERENCE INPUT
Range
Resistance(5)
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
VOL
Data Format
POWER-SUPPLY REQUIREMENT
Logic Family
+VA
+VD
Supply Current
Power Dissipation
TEMPERATURE RANGE
Specified Performance
MIN
+2VREF
VA + 0.1
+0.5
✻
✻
✻
±8
±2
±0.50
✻
✻
✻
±3
±0.5
±0.12
✻
✻
✻
IOUT = 0
Static Load
IOUT = 0
4.75V ≤ VCC ≤ 5.25V
2.475
IOH
IOL
✻
✻
✻
✻
–90
81
94
–93
83
96
dB
dB
dB
2.50
2.525
10
2.48
✻
2.55
✻
✻
CMOS
✻
+VA
0.8
✻
✻
✻
0.4
fSAMPLE = 500kHz
fSAMPLE = 500kHz
–40
V
µA
pp[/°C
mV
✻
V
kΩ
✻
✻
✻
V
V
V
V
✻
✻
✻
✻
V
V
mA
mW
✻
°C
✻
Straight Binary
CMOS
5
5
17
85
2.52
✻
✻
✻
10
3.0
–0.3
4.0
4.75
4.75
Bits
LSBs(2)
mV
% of FSR
dB
µVr ms
LSBs
50
30
20
100
1.5
IIH ≤ +5µA
IIL ≤ +5µA
= 2 TTL Loads
= 2 TTL Loads
V
V
V
pF
nA
µs
µs
kHz
ns
ps
MHz
ns
20
0.6
to Internal Reference Voltage
±6
±1
±0.25
✻
✻
✻
1.6
0.4
500
VIN = 5Vp-p at 100kHz
VIN = 5Vp-p at 100kHz
VIN = 5Vp-p at 100kHz
UNITS
Bits
15
±4
±1.0
±0.25
70
60
±3
At FFFFH Output Code
MAX
✻
✻
14
At DC
TYP
✻
25
±1
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Aperture Delay
Aperture Jitter
Small-Signal Bandwidth
Step Response
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(4)
SINAD
Spurious Free Dynamic Range
MAX
16
ANALOG INPUT
Full-Scale Input Span(1)
Absolute Input Range
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Offset Error
Gain Error(3)
Common-Mode Rejection Ratio
Noise
Power Supply Rejection Ratio
TYP
ADS8322YB
5.25
5.25
25
125
✻
✻
+85
✻
✻
✻
✻
✻
✻
✻ Specifications same as ADS8322Y.
NOTES: (1) Ideal input span; does not include gain or offset error. (2) LSB means Least Significant Bit, with VREF equal to +2.5V; 1LSB = 76µV. (3) Measured relative
to an ideal, full-scale input (+In – (–In)) of 4.9999V. Thus, gain error includes the error of the internal voltage reference. (4) Calculated on the first nine harmonics
of the input frequency. (5) Can vary ±30%.
ADS8322
SBAS215
3
TIMING DIAGRAM
t1
t3
t2
CLOCK
1
2
3
Acquisition
4
5
17
18
19
Conversion
Acquisition
tCONV
tACQ
20
1
2
3
4
17
18
19
20
t5
t4
CONVST
t6
t9
t10
BUSY
t7
t11
BYTE
t8
t12
CS
t13
t18
t14
t15
RD
t16
t17
t19
DB15-D8
Bits 15-8
Bits 15-8
FF
DB7-D0
Bits 7-0
Bits 7-0
Bits 15-8
TIMING CHARACTERISTICS(1)(2)
All specifications typical at –40°C to +85°C, +VD = +5V.
ADS8322A
PARAMETER
Conversion Time
Acquisition Time
CLOCK Period
CLOCK High Time
CLOCK Low Time
CONVST Low to Clock High
CLOCK High to CONVST High
CONVST Low Time
CONVST Low to BUSY High
CS Low to CONVST Low
CONVST High
CLOCK Low to CONVST Low
CLOCK High to BUSY Low
CS High
CS Low to RD Low
RD High to CS High
RD Low Time
RD Low to Data Valid
Data Hold from RD High
BYTE Change to RD Low(3)
RD High Time
SYMBOL
tCONV
tACQ
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
MIN
TYP
ADS8322B
MAX
MIN
1.6
0.4
MAX
UNITS
✻
✻
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
✻
✻
✻
✻
✻
✻
100
40
40
10
5
20
✻
25
✻
✻
✻
0
20
0
✻
25
0
0
0
50
40
5
0
20
TYP
✻
✻
✻
✻
✻
✻
✻
✻
NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) /2. (2) See timing diagram, above.
(3) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BUSY is 1, bits 15 through 8 appear on DB7-DB0. RD may remain low
between changes in BYTE.
4
ADS8322
SBAS215
TYPICAL CHARACTERISTICS
At –40°C to +85°C, +VA = +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified.
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 100.1kHz, –0.2dB)
90
0
SNR, SINAD (dB)
Amplitude (dB)
–30
–60
–90
85
SNR
80
SINAD
–120
75
–150
0
20
40
60
80
1
100 120 140 160 180 200
10
Frequency (kHz)
0.30
95
–95
0.20
–90
SFDR
THD
THD (dB)
–100
0.10
85
–85
80
–80
–0.10
–75
–0.20
75
1
250
IL+ vs TEMPERATURE
100
Deltas (LSB)
SFDR (dB)
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
90
100
Frequency (kHz)
10
100
0.00
–40
250
–20
0
20
40
60
80
100
80
100
Temperature (°C)
Frequency (kHz)
DL+ vs TEMPERATURE
IL– vs TEMPERATURE
1.0
0.2
0.5
Deltas (LSB)
Deltas (LSB)
0.0
–0.2
–0.4
0.0
–0.5
–1.0
–1.5
–0.6
–40
–20
0
20
40
Temperature (°C)
ADS8322
SBAS215
60
80
100
–40
–20
0
20
40
60
Temperature (°C)
5
TYPICAL CHARACTERISTICS
(Cont.)
At –40°C to +85°C, +VA = +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified.
DL– vs TEMPERATURE
OFFSET ERROR vs TEMPERATURE
0.05
2.5
2.0
0.00
Deltas (LSB)
Deltas (LSB)
1.5
–0.05
–0.10
–0.15
1.0
0.5
0.0
–0.5
–0.20
–1.0
–1.5
–0.25
–40
–20
0
20
40
60
80
–40
100
–20
0
Temperature (°C)
20
40
60
80
100
80
100
Temperature (°C)
GAIN ERROR vs TEMPERATURE
VREF vs TEMPERATURE
8
2.0
1.0
0.0
Deltas (mV)
Deltas (LSB)
6
4
2
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
0
–7.0
–8.0
–2
–40
–20
0
20
40
60
80
100
–40
–20
0
Temperature (°C)
20
40
60
Temperature (°C)
IQ vs TEMPERATURE
1.2
Deltas (mA)
0.8
0.4
0.0
–0.4
–0.8
–40
–20
0
20
40
60
80
100
Temperature (°C)
6
ADS8322
SBAS215
THEORY OF OPERATION
REFERENCE
Under normal operation, the REFOUT pin should be directly
connected to the REFIN pin to provide an internal +2.5V
reference to the ADS8322. The ADS8322 can operate,
however, with an external reference in the range of 1.5V to
2.6V for a corresponding full-scale range of 3.0V to 5.2V.
The internal reference of the ADS8322 is double-buffered.
If the internal reference is used to drive an external load, a
buffer is provided between the reference and the load applied to the REFOUT pin (the internal reference can typically
source and sink 10µA of current). If an external reference is
used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to
recharge all of the CDAC capacitors during conversion.
The ADS8322 is a high-speed Successive Approximation
Register (SAR) A/D converter with an internal 2.5V bandgap
reference. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function.
The basic operating circuit for the ADS8322 is shown in
Figure 1.
The ADS8322 requires an external clock to run the conversion process. The clock can be run continuously or it can be
gated to conserve power between conversions. This clock
can vary between 25kHz (1.25kHz throughput) and 10MHz
(500kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW times are
at least 40ns and the clock period is at least 100ns. The
minimum clock frequency is governed by the parasitic
leakage of the Capacitive Digital-to-Analog (CDAC) capacitors internal to the ADS8322.
The analog input is provided to two input pins, +IN and –IN.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
ANALOG INPUT
When the converter enters Hold mode, the voltage difference between the +IN and –IN inputs is captured on the
internal capacitor array. The voltage on the –IN input is
+5V Analog Supply
10µF
+
0.1µF
+
0.1µF
32
31
30
29
28
27
26
25
REFOUT
REFIN
NC
NC
+VA
AGND
+IN
–IN
–
CS 24
1
DB15
2
DB14
BYTE 23
3
DB13
RD 22
4
DB12
CONVST 21
Analog Input
Chip Select
Read Input
Conversion Start
ADS8322
+VD 18
8
DB8
BUSY 17
DB0
DB9
DB1
7
DB2
DGND 19
DB3
DB10
DB4
6
DB5
CLOCK 20
DB6
DB11
DB7
5
9
10
11
12
13
14
15
16
Clock Input
Busy Output
FIGURE 1. Typical Circuit Configuration.
ADS8322
SBAS215
7
limited between –0.1V and 0.5V, allowing the input to reject
small signals which are common to both the +IN and –IN
inputs. The +IN input has a range of –0.1V to +VA + 0.1V.
The input current on the analog inputs depends upon a
number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8322 charges
the internal capacitor array during the sample period. After
this capacitance has been fully charged, there is no further
input current. The source of the analog input voltage must be
able to charge the input capacitance (25pF) to a 16-bit
settling level within the acquisition time (400ns) of the
device. When the converter goes into Hold mode, the input
impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the –IN
input should not drop below GND – 100mV or exceed
GND + 0.5V. The +IN input should always remain within
the range of GND – 100mV to VA + 100mV. Outside of
these ranges, the converter’s linearity may not meet specifications. To minimize noise, low-bandwidth input signals
with lowpass filters should be used.
DIGITAL INTERFACE
TIMING AND CONTROL
See the timing diagram in the Timing Characteristics section
for detailed information on timing signals and their requirement.
The ADS8322 uses an external clock (CLOCK) which
controls the conversion rate of the CDAC. With a 10MHz
external clock, the A/D converter sampling rate is 500kHz,
which corresponds to a 2µs maximum throughput time.
Conversions are initiated by bringing the CONVST pin
LOW for a minimum of 20ns (after the 20ns minimum
requirement has been met, the CONVST pin can be brought
HIGH), while CS is LOW. The ADS8322 will switch from
Sample-to-Hold mode on the falling edge of the CONVST
command. Following the first rising edge of the external
clock after a CONVST LOW, the ADS8322 will begin
conversion (this first rising edge of the external clock represents the start of clock cycle one; the ADS8322 requires 16
rising clock edges to complete a conversion). The BUSY
output will go HIGH immediately following CONVST going LOW. BUSY will stay HIGH through the conversion
process and return LOW when the conversion has ended.
Both RD and CS can be HIGH during and before a conversion (although CS must be LOW when CONVST goes LOW
to initiate a conversion). Both the RD and CS pins are
brought LOW in order to enable the parallel output bus with
the conversion.
READING DATA
The ADS8322 outputs full parallel data in Straight Binary
format, as shown in Table I. The parallel output will be
active when CS and RD are both LOW. The output data
should not be read 125ns prior to the falling edge of
CONVST and 10ns after the falling edge. Any other combination of CS and RD will tri-state the parallel output. Refer
to Table I for ideal output codes.
DESCRIPTION
ANALOG VALUE
DIGITAL OUTPUT
STRAIGHT BINARY
Full-Scale Range
2 • VREF
Least Significant
Bit (LSB)
2 • VREF/65535
BINARY CODE
HEX CODE
+Full Scale
2VREF – 1 LSB
1111 1111 1111 1111
FFFF
VREF
1000 0000 0000 0000
8000
VREF – 1 LSB
0111 1111 1111 1111
7FFF
0V
0000 0000 0000 0000
0000
Midscale
Midscale – 1LSB
Zero
TABLE I. Ideal Input Voltages and Output Codes.
BYTE
The output data will appear as a full 16-bit word on DB15DB0 (MSB-LSB), if BYTE is LOW. The result may also be
read on an 8-bit bus by using only DB7-DB0. In this case two
reads are necessary. The first, as before, leaving BYTE LOW
and reading the 8 least significant bits on DB7-DB0, then
bringing BYTE HIGH. When BYTE is HIGH, the upper 8 bits
(D15-D8) will appear on DB7-DB0.
NOISE
Figure 2 shows the transition noise of the ADS8322. A lowlevel DC input was applied to the analog-input pins and the
converter was put through 8,192 conversions. The digital
output of the A/D converter will vary in output code due to
the internal noise of the ADS8322. This is true for all 16-bit
SAR-type A/D converters. Using a histogram to plot the
output codes, the distribution should appear bell-shaped
5052
1968
818
54
0014
300
0015
0016
0017
0018
Code
FIGURE 2. Histogram of 8,192 Conversions of a Low Level
DC Input.
8
ADS8322
SBAS215
with the peak of the bell curve representing the nominal code
for the input value. The ±1σ, ±2σ, and ±3σ distributions will
respectively represent the 68.3%, 95.5%, and 99.7% of all
codes. The transition noise can be calculated by dividing the
number of codes measured by six and this will yield the ±3σ
distribution, or 99.7%, of all codes. Statistically, up to three
codes could fall outside the distribution when executing
1,000 conversions. The ADS8322, with five output codes
for the ±3σ distribution, will yield a < ±0.8LSB transition
noise at 5V operation. Remember that to achieve this lownoise performance, the peak-to-peak noise of the input
signal and reference must be < 50µV.
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.25
LSBs. Averaging should only be used for input signals with
frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging: for every decimation by 2, the
signal-to-noise ratio will improve 3dB.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8322 circuitry. This is particularly true if the CLOCK input is approaching the maximum
throughput rate.
As the ADS8322 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good
performance from the converter.
ADS8322
SBAS215
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conversion result. Such glitches might originate from switching
power supplies, or nearby digital logic or high-power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the external event. Their error can change if the external event
changes in time with respect to the CLOCK input.
On average, the ADS8322 draws very little current from an
external reference, as the reference voltage is internally
buffered. If the reference voltage is external and originates
from an op amp, make sure that it can drive the bypass
capacitor or capacitors without oscillation.
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the “analog” ground.
Avoid connections which are too close to the grounding point
of a microcontroller or digital signal processor. If required, run
a ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog circuitry.
As with the GND connections, VDD should be connected to
a +5V power supply plane, or trace, that is separate from the
connection for digital logic until they are connected at the
power entry point. Power to the ADS8322 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low-pass filter a noisy supply. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor, or even a “Pi” filter made up of inductors and
capacitors—all designed to essentially lowpass filter the
+5V supply, removing the high-frequency noise.
9
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