CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
18-Mbit (512K × 36/1M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte write capability
■
3.3 V core power supply (VDD)
■
3.3 V/2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 2.5 ns (for 250 MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
165-ball FBGA package
■
IEEE 1149.1 JTAG-compatible boundary scan
■
Burst capability – linear or interleaved burst order
■
“ZZ” sleep mode option and stop clock option
■
On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
The CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/
CY7C1372KVE33 are 3.3 V, 512K × 36 and 1M × 18
synchronous pipelined burst SRAMs with No Bus Latency™
(NoBL logic, respectively. They are designed to support
unlimited true back-to-back read/write operations with no wait
states. The CY7C1370KV33/CY7C1370KVE33/
CY7C1372KV33/CY7C1372KVE33 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/
CY7C1372KVE33 are pin compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects (BWa–
BWd for CY7C1370KV33/CY7C1370KVE33 and BWa–BWb for
CY7C1372KV33/CY7C1372KVE33) and a write enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Selection Guide
Description
Maximum access time
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-97836 Rev. *H
× 18
× 36
•
198 Champion Court
•
250 MHz
200 MHz
167 MHz
Unit
2.5
180
200
3.0
158
178
3.4
143
163
ns
San Jose, CA 95134-1709
mA
•
408-943-2600
Revised May 19, 2017
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Logic Block Diagram – CY7C1370KV33
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW a
BW b
BW c
BW d
WRITE
DRIVERS
O
U
T
P
U
T
S
E
N
S
E
MEMORY
ARRAY
R
E
G
I
S
T
E
R
S
A
M
P
S
WE
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
INPUT
REGISTER 0
E
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1370KVE33
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BWA
BWB
BWC
BWD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
ECC
ENCODER
OE
CE1
CE2
CE3
ZZ
Document Number: 001-97836 Rev. *H
INPUT
REGISTER 1
E
D
A
T
A
E
C
C
D
E
C
O
D
E
R
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
E
READ LOGIC
SLEEP
CONTROL
Page 2 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Logic Block Diagram – CY7C1372KV33
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BW a
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
BW b
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
E
DQ s
DQ Pa
DQ Pb
E
INPUT
REGISTER 0
E
READ LOGIC
Sleep
Control
Logic Block Diagram – CY7C1372KVE33
Document Number: 001-97836 Rev. *H
Page 3 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Write Cycle Description ..................................... 12
Partial Write Cycle Description ..................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
3.3 V TAP AC Test Conditions ....................................... 18
3.3 V TAP AC Output Load Equivalent ......................... 18
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent ......................... 18
Document Number: 001-97836 Rev. *H
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC®Solutions ....................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Page 4 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1372KV33/CY7C1372KVE33
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
NC(36)
NC(72)
A
A
A
A
A
A
A
NC(72)
NC(36)
VSS
VDD
NC(288)
NC(144)
MODE
A
A
A
A
A1
A0
Document Number: 001-97836 Rev. *H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VDD
(512K × 36)
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
NC(288)
NC(144)
CY7C1370KV33/CY7C1370KVE33
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 5 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1370KV33 (512K × 36)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWc
BWb
CE3
NC/1G
A
CE2
DQPc
DQc
NC
DQc
BWa
VSS
VDDQ
BWd
VSS
VDD
R
MODE
VDDQ
7
8
9
10
11
A
A
NC
CLK
CEN
WE
ADV/LD
OE
A
A
NC
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC
DQb
DQPb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
NC
DQd
DQc
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQb
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQc
NC
DQd
VDDQ
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
NC/36M
Document Number: 001-97836 Rev. *H
Page 6 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Pin Definitions
Pin Name
A0, A1, A
I/O Type
Pin Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous
BWa, BWb,
InputByte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, active LOW. Combined with the synchronous logic block inside the device to control
asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQS
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tristate condition. The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
Document Number: 001-97836 Rev. *H
Page 7 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TDO
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
TDI
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
input
synchronous
TMS
Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK.
select
synchronous
TCK
JTAG-clock
VDD
VDDQ
VSS
NC
NC/(36M,
72M,
144M,
288M,
576M, 1G)
ZZ
Clock input to the JTAG circuitry.
Power supply Power supply inputs to the core of the device.
I/O power
supply
Ground
–
–
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M, 576M
and 1G densities.
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. ZZ
pin has an internal pull down.
Document Number: 001-97836 Rev. *H
Page 8 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Functional Overview
The CY7C1370KV33, CY7C1370KVE33, CY7C1372KVE33
and CY7C1372KV33 are synchronous-pipelined burst NoBL
SRAMs designed specifically to eliminate wait states during
write/read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (tCO) is 2.5 ns (250-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.5 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tristate following the next clock rise.
Burst Read Accesses
The CY7C1370KV33, CY7C1370KVE33, CY7C1372KVE33
and CY7C1372KV33 have an on-chip burst counter that allows
the user the ability to supply a single address and conduct up to
four reads without reasserting the address inputs. ADV/LD must
be driven LOW in order to load a new address into the SRAM,
as described in Single Read Accesses. The sequence of the
burst counter is determined by the MODE input signal. A LOW
Document Number: 001-97836 Rev. *H
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and will wrap-around when incremented
sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (read or write) is maintained throughout the
burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
address register. The write signals are latched into the control
logic block.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370KV33, CY7C1370KVE33,
and DQa,b/DQPa,b for CY7C1372KV33, CY7C1372KVE33). In
addition, the address for the subsequent access
(read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370KV33, CY7C1370KVE33 &
DQa,b/DQPa,b for CY7C1372KV33, CY7C1372KVE33) (or a
subset for byte write operations, see Write Cycle Description
table for details) inputs is latched into the device and the write is
complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370KV33, CY7C1370KVE33 and BWa,b for
CY7C1372KV33, CY7C1372KVE33) signals.
The CY7C1370KV33 / CY7C1370KVE33 / CY7C1372KV33 /
CY7C1372KVE33 provides byte write capability that is described
in the Write Cycle Description table. Asserting the write enable
input (WE) with the selected byte write select (BW) input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations. Byte write capability has been
included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1370KV33, CY7C1370KVE33 and
CY7C1372KV33, CY7C1372KVE33 are common I/O devices,
data should not be driven into the device while the outputs are
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1370KV33, CY7C1370KVE33 and DQa,b/DQPa,b for
CY7C1372KV33, CY7C1372KVE33) inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370KV33, CY7C1370KVE33
and DQa,b/DQPa,b for CY7C1372KV33, CY7C1372KVE33) are
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Page 9 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Burst Write Accesses
Interleaved Burst Address Table
The CY7C1370KV33 / CY7C1370KVE33 / CY7C1372KV33 /
CY7C1372KVE33 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
write operations without reasserting the address inputs. ADV/LD
must be driven LOW in order to load the initial address, as
described in the Single Write Accesses section above. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BW (BWa,b,c,d for
CY7C1370KV33,
CY7C1370KVE33
and
BWa,b
for
CY7C1372KV33, CY7C1372KVE33) inputs must be driven in
each cycle of the burst write in order to write the correct bytes of
data.
(MODE = Floating or VDD)
Sleep Mode
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ VDD 0.2 V
–
65
mA
tZZS
Device operation to ZZ
ZZ VDD 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-97836 Rev. *H
Page 10 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Truth Table
The Truth Table for CY7C1370KV33/CY7C1370KVE33 and CY7C1372KV33/CY7C1372KVE33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE
ZZ
ADV/LD WE BWx
OE
CEN CLK
DQ
Deselect cycle
None
H
L
L
X
X
X
L
L–H
Tri-state
Continue deselect cycle
None
X
L
H
X
X
X
L
L–H
Tri-state
Read cycle (begin burst)
External
L
L
L
H
X
L
L
L–H Data out (Q)
Next
X
L
H
X
X
L
L
L–H Data out (Q)
External
L
L
L
H
X
H
L
L–H
Tri-state
Next
X
L
H
X
X
H
L
L–H
Tri-state
External
L
L
L
L
L
X
L
L–H
Data in (D)
Write cycle (continue burst)
Next
X
L
H
X
L
X
L
L–H
Data in (D)
NOP/write abort (begin burst)
None
L
L
L
L
H
X
L
L–H
Tri-state
Write abort (continue burst)
Next
X
L
H
X
H
X
L
L–H
Tri-state
Current
X
L
X
X
X
X
H
L–H
–
None
X
H
X
X
X
X
X
X
Tri-state
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Ignore clock edge (stall)
Sleep mode
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active.
Document Number: 001-97836 Rev. *H
Page 11 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1370KV33/CY7C1370KVE33 follows. [8, 9, 10, 11]
Function (CY7C1370KV33/CY7C1370KVE33)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1372KV33/CY7C1372KVE33 follows. [8, 9, 10, 11]
WE
BWb
BWa
Read
Function (CY7C1372KV33/CY7C1372KVE33)
H
X
X
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Truth Table on page 11 for details.
9. Write is defined by WE and BWX. See Write Cycle Description table for details.
10. When a write cycle is detected, all I/Os are tristated, even during byte writes.
11. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document Number: 001-97836 Rev. *H
Page 12 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370KV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
The CY7C1370KV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Test Access Port (TAP)
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Clock (TCK)
Bypass Register
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Document Number: 001-97836 Rev. *H
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
Page 13 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
IDCODE
BYPASS
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
EXTEST Output Bus Tristate
SAMPLE Z
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a High Z condition.
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
Document Number: 001-97836 Rev. *H
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 14 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
Document Number: 001-97836 Rev. *H
1
0
PAUSE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
Page 15 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
TAP Controller Block Diagram
0
Bypass Register
2 1 0
Selection
Circuitry
TDI
Selection
Circuitry
Instruction Register
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing
1
2
Test Clock
(TCK )
3
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
Document Number: 001-97836 Rev. *H
UNDEFINED
Page 16 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
13. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 001-97836 Rev. *H
Page 17 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels ............................................... VSS to 2.5 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input rise and fall time (Slew Rate) ............................. 2 V/ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [14]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA, VDDQ = 3.3 V
–
0.4
V
IOL = 8.0 mA, VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.5
0.7
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
GND < VIN < VDDQ
Note
14. All voltages referenced to VSS (GND)
Document Number: 001-97836 Rev. *H
Page 18 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Identification Register Definitions
Instruction Field
CY7C1370KV33
Revision Number (31:29)
000
Cypress Device ID (28:12) [15]
01011001000010101
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Description
Reserved for version number.
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order (165-ball FBGA package)
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to High Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
15. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-97836 Rev. *H
Page 19 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Boundary Scan Order
165-ball FBGA [16, 17]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Notes
16. Balls which are NC (No Connect) are pre-set LOW.
17. Bit# 89 is preset HIGH.
Document Number: 001-97836 Rev. *H
Page 20 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
Ambient
Temperature
Storage Temperature ............................... –65 °C to +150 °C
Commercial
0 °C to +70 °C
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Industrial
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Parameter
DC to Outputs in Tristate ..................–0.5 V to VDDQ + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2001V
Latch up Current .................................................... > 200 mA
VDDQ
3.3 V – 5% / 2.5 V – 5% to
+10%
VDD
Neutron Soft Error Immunity
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
–40 °C to +85 °C
VDD
LSBU
(Device
without ECC)
Test
Description Conditions
Typ
Logical
Single-Bit
Upsets
25 °C
LSBU
(Device with
ECC)
LMBU
SEL
Max*
Unit
<5
5
FIT/
Mb
0
0.01
FIT/
Mb
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
Single Event
Latch up
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [18, 19]
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
[18]
Input LOW Voltage
[18]
Input Leakage Current
except ZZ and MODE
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
–5
5
A
–30
–
Input = VDD
–
5
Input = VSS
–5
–
Input = VDD
–
30
GND VI VDDQ
Input Current of MODE Input = VSS
Input Current of ZZ
Min
Notes
18. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
19. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) of at least 200 ms. During this time VIH < VDD and VDDQ <VDD.
Document Number: 001-97836 Rev. *H
Page 21 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [18, 19]
Description
Test Conditions
IOZ
Output Leakage Current GND VI VDDQ, Output Disabled
IDD
VDD Operating Supply
ISB1
ISB2
ISB3
ISB4
Automatic CE
Power-down Current –
TTL Inputs
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
Min
Max
–5
5
A
4-ns cycle,
250 MHz
× 18
–
180
mA
× 36
–
200
5-ns cycle,
200 MHz
× 18
–
158
× 36
–
178
6-ns cycle,
167 MHz
× 18
–
143
× 36
–
163
4-ns cycle,
250 MHz
× 18
–
75
× 36
–
80
5-ns cycle,
200 MHz
× 18
–
75
× 36
–
80
6-ns cycle,
167 MHz
× 18
–
75
× 36
–
80
Automatic CE
Power-down Current –
CMOS Inputs
Max. VDD, Device Deselected,
All speed
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f=0
× 18
–
65
× 36
–
70
Automatic CE
Power-down Current –
CMOS Inputs
Max. VDD, Device Deselected,
4-ns cycle,
VIN 0.3 V or VIN > VDDQ 0.3 V, 250 MHz
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
× 18
–
75
× 36
–
80
× 18
–
75
× 36
–
80
6-ns cycle,
167 MHz
× 18
–
75
× 36
–
80
All speed
grades
× 18
–
65
× 36
–
70
Automatic CE
Power-down Current –
TTL Inputs
Document Number: 001-97836 Rev. *H
Max. VDD, Device Deselected,
VIN VIH or VIN VIL, f = 0
Unit
mA
mA
mA
mA
Page 22 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Capacitance
Parameter
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
100-pin TQFP 165-ball FBGA Unit
Max
Max
Test Conditions
TA = 25C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
5
pF
5
5
pF
5
5
pF
Thermal Resistance
Parameter
JA
Description
Test conditions follow With Still Air (0 m/s)
standard
test
With Air Flow (1 m/s)
methods
and
procedures
for With Air Flow (3 m/s)
measuring
thermal
-impedance,
per
EIA/JESD51.
Thermal resistance
(junction to ambient)
JB
Thermal resistance
(junction to board)
JC
Thermal resistance
(junction to case)
100-pin TQFP 165-ball FBGA Unit
Package
Package
Test Conditions
37.95
17.34
C/W
33.19
14.33
C/W
30.44
12.63
C/W
24.07
8.95
C/W
8.36
3.50
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317
3.3V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
(b)
2.5V I/O Test Load
R = 1667
2.5V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25V
(a)
Document Number: 001-97836 Rev. *H
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 23 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Switching Characteristics
Over the Operating Range
Parameter [20, 21]
tPower[22]
-250
Description
VCC(typical) to the first access read or
write
-200
-167
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
4.0
–
5.0
–
6.0
–
ns
–
250
–
200
–
167
MHz
ms
Clock
tCYC
Clock cycle time
FMAX
Maximum operating frequency
tCH
Clock HIGH
1.5
–
2.0
–
2.2
–
ns
tCL
Clock LOW
1.5
–
2.0
–
2.2
–
ns
Output Times
tCO
Data output valid after CLK rise
–
2.5
–
3.0
–
3.4
ns
tEOV
OE LOW to output valid
–
2.6
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.0
–
1.5
–
1.5
–
ns
[23, 24, 25]
tCHZ
Clock to high Z
tCLZ
Clock to low Z [23, 24, 25]
tEOHZ
tEOLZ
OE HIGH to output high Z
OE LOW to output low Z
[23, 24, 25]
[23, 24, 25]
–
2.6
–
3.0
–
3.4
ns
1.0
–
1.3
–
1.5
–
ns
–
2.6
–
3.0
–
3.4
ns
0
–
0
–
0
–
ns
Setup Times
tAS
Address setup before CLK rise
1.2
–
1.4
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.2
–
1.4
–
1.5
–
ns
tCENS
CEN setup before CLK rise
1.2
–
1.4
–
1.5
–
ns
tWES
WE, BWx setup before CLK rise
1.2
–
1.4
–
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.2
–
1.4
–
1.5
–
ns
tCES
Chip select setup
1.2
–
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tWEH
WE, BWx hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
tCEH
Chip select hold after CLK rise
0.3
–
0.4
–
0.5
–
ns
Hold Times
Notes
20. Timing reference is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of Figure 3 on page 23 unless otherwise noted.
22. This part has a voltage regulator internally; tPower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.
23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 3 on page 23. Transition is measured ±200 mV from steady-state voltage.
24. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 001-97836 Rev. *H
Page 24 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Switching Waveforms
Figure 4. Read/Write/Timing [26, 27, 28]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW x
A1
ADDRESS
A2
A7
t CO
t AS
t DS
t AH
Data
In-Out (DQ)
t DH
D(A1)
t CLZ
D(A2)
D(A2+1)
t DOH
Q(A3)
t OEV
Q(A4)
t CHZ
Q(A4+1)
D(A5)
Q(A6)
t OEHZ
t DOH
t OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
DON’T CARE
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
Document Number: 001-97836 Rev. *H
Page 25 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Switching Waveforms (continued)
Figure 5. NOP, STALL, and DESELECT Cycles [29, 30, 31]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
t CHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 6. ZZ Mode Timing [32, 33]
CLK
t ZZ
ZZ
I
t
t ZZREC
ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
33. I/Os are in High Z when exiting ZZ sleep mode.
Document Number: 001-97836 Rev. *H
Page 26 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
Ordering Code
CY7C1370KV33-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
CY7C1372KV33-167AXC
CY7C1370KV33-167BZXC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
CY7C1370KV33-167AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1370KV33-200AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
CY7C1370KV33-200BZXI
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
CY7C1370KV33-250AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1370KVE33-167AXI
CY7C1372KV33-167AXI
CY7C1372KVE33-167AXI
200
CY7C1370KV33-200AXC
CY7C1372KV33-200AXC
250
Commercial
Ordering Code Definitions
CY
7
C
13XX KV X
33 - XXX XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = -40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 167 or 200 or 250
167 = 167 MHz; 200 = 200 MHz; 250 = 250 MHz
33 = 3.3V VDD
X = blank or E
blank = Device without ECC; E = Device with ECC
Process Technology: KV =65 nm
Part Identifier: 13XX = 1370 or 1372
1370 = PL, 512 Kb × 36 (18 Mb)
1372 = PL, 1 Mb × 18 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-97836 Rev. *H
Page 27 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.20
c
Document Number: 001-97836 Rev. *H
0.15
NOTE:
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Page 28 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Package Diagrams (continued)
Figure 8. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-97836 Rev. *H
Page 29 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CEN
Clock Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
k
kilohm
FBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
µA
microampere
JTAG
Joint Test Action Group
µs
microsecond
LMBU
Logical Multi-Bit Upsets
mA
milliampere
LSB
Least Significant Bit
LSBU
Logical Single-Bit Upsets
MSB
Most Significant Bit
NoBL
No Bus Latency
OE
Output Enable
SEL
Symbol
Unit of Measure
mV
millivolt
mm
millimeter
ms
millisecond
ns
nanosecond
ohm
%
percent
Single Event Latch-up
pF
picofarad
SRAM
Static Random Access Memory
ps
picosecond
TAP
Test Access Port
V
volt
TCK
Test Clock
W
watt
TMS
Test Mode Select
TDI
Test Data-In
TDO
Test Data-Out
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-97836 Rev. *H
Page 30 of 32
CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Document History Page
Document Title: CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/CY7C1372KVE33, 18-Mbit (512K × 36/1M × 18) Pipelined
SRAM with NoBL™ Architecture (With ECC)
Document Number: 001-97836
Rev.
ECN No.
Orig. of
Change
Submission
Date
*F
5083798
DEVM
01/14/2016
Changed status from Preliminary to Final.
*G
5396610
PRIT
08/09/2016
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to “LSBU (Device
without ECC)” parameter.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*H
5734193
PRIT
05/12/2017
Updated Package Diagrams
Changed Spec 51-85050 from *E to *G.
Description of Change
Updated Cypress Logo and Copyright.
Document Number: 001-97836 Rev. *H
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CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
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© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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Document Number: 001-97836 Rev. *H
Revised May 19, 2017
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