Cypress CYU01M16SCCU 16-mbit (1m x 16) pseudo static ram Datasheet

CYU01M16SCCU
MoBL3™
PRELIMINARY
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• 16-word Page Mode
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The CYU01M16SCCU is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. Refer to the truth table for a complete
description of read and write modes.
1M x 16
RAM Array
SENSE AMPS
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
Writing to the device is accomplished by taking Chip Enable
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A19). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A19).
DATA IN DRIVERS
ROW DECODER
Logic Block Diagram
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE1 HIGH or
CE2 LOW or both BHE and BLE are HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high-impedance state
when: deselected (CE1 HIGH or CE2 LOW), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE1 LOW and CE2 HIGH and WE LOW).
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A7
A6
A5
A4
A3
A2
A1
A0
BHE
WE
CE2
CE1
OE
BLE
Power -Down
Circuit
BHE
BLE
CE2
CE1
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05601 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 25, 2006
CYU01M16SCCU
MoBL3™
PRELIMINARY
Pin Configuration[2, 3]
48-Ball VFBGA
Top View
4
3
1
2
BLE
OE
A0
I/O8
BHE
I/O9
5
6
A1
A2
CE2
A
A3
A4
CE1
I/O0
B
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12 NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Product Portfolio[4]
Power Dissipation
Product
CYU01M16SCCU
Operating ICC (mA)
Speed
(ns)
VCC Range (V)
Min.
Typ.[4]
Max.
2.2
3.0
3.6
f = 1MHz
f = fmax
Standby ISB2 (µA)
Typ.[4]
Max.
Typ.[4]
Max.
Typ.[4]
Max.
3
5
18
25
55
70
70
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip
Select should be CE1 HIGH or CE2 LOW for at least 200 µs
after VCC has reached a stable value. No access must be
attempted during this period of 200 µs.
Stable Power
VCC
First Access
Tpu
CE
Parameter
Description
Min.
Tpu
Chip Enable Low After Stable VCC
200
Typ.
Max.
Unit
µs
Notes:
2. Ball H6 and E3 can be used to upgrade to a 32-Mbit and a 64-Mbit density, respectively.
3. NC “no connect” - not connected internally to the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. Tested initially
and after design changes that may affect the parameters.
Document #: 38-05601 Rev. *B
Page 2 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
Page Mode
This device can be operated in a page read mode. This is
accomplished by initiating a normal read of the device.
In order to operate the device in page mode, the upper order
address bits should be fixed for four-word page access
operation, all address bits except for A1 and A0 should be
fixed until the page access is completed. For an eight-word
page access, all address bits, except for A2, A1, and A0,
Page Mode Feature
should be fixed. For a sixteen-word page mode all address
bits, except for A3, A2, A1, and A0, should be fixed.
The supported page lengths are four, eight, and sixteen words.
Random page read is supported for all three four, eight, and
sixteen-word page read options. Therefore, any address can
be used as the starting address.
Please refer to the table below for an overview of the page
read modes.
4-Word Mode
8-Word Mode
16-Word Mode
Page Length
4 words
8 words
16 words
Page Read Corresponding Addresses
A1, A0
A2, A1, A0
A3, A2, A1, A0
Page Read Start Address
Don't Care
Don't Care
Don’t Care
Page Direction
Don't Care
Don't Care
Don’t Care
Document #: 38-05601 Rev. *B
Page 3 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
DC Input Voltage[5, 6, 7] .................... –0.3V to VCCMAX + 0.3V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to
Ground Potential ..............................–0.3V to VCCMAX + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... > 200 mA
Device
Range
CYU01M16SCCU Industrial
Operating
Temperature (TA)
VCC
–40°C to +85°C
2.2V to
3.6V
DC Voltage Applied to Outputs
in High Z State[5, 6, 7] ........................–0.3V to VCCMAX + 0.3V
DC Electrical Characteristics (Over the Operating Range)[5, 6, 7]
CYU01M16SCCU-70 ns
Parameter
Description
Test Conditions
VCC
Supply Voltage
VOH
Output HIGH Voltage IOH = –0.1 mA
VCC= 2.2V to 3.6V
VOL
Output LOW Voltage IOL = 0.1 mA
VCC= 2.2V to 3.6V
Min.
Typ.[4]
Max.
Unit
2.2
3.0
3.6
V
VCC – 0.2
V
0.2
V
VIH
Input HIGH Voltage
VCC= 2.2V to 3.6V
0.8 * VCC
VCC + 0.3V
V
VIL
Input LOW Voltage
VCC= 2.2V to 3.6V
–0.3
0.2 * VCC
V
IIX
Input Leakage
Current
GND < VIN < VCC
–1
+1
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
–1
+1
µA
ICC
VCC Operating
Supply
Current
f = fMAX = 1/tRC VCC= VCCmax
IOUT = 0 mA
CMOS levels
18
25
mA
f = 1MHz
3
5
mA
ISB1
Automatic CE
Power-Down
Current — CMOS
Inputs
CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC
– 0.2V, VIN < 0.2V f = fMAX (Address and
Data Only), f = 0
(OE, WE, BHE and BLE), VCC = 3.60V
55
70
µA
ISB2
Automatic CE
Power-Down
Current — CMOS
Inputs
CE1 > VCC – 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V,
f = 0, VCC=VCCMAX
55
70
µA
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Thermal Resistance
Parameter
ΘJA
ΘJC
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
8
pF
8
pF
[8]
Description
Test Conditions
Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods
and procedures for measuring thermal
Thermal Resistance (Junction to Case)
impedence, per EIA / JESD51.
VFBGA
Unit
56
°C/W
11
°C/W
Notes:
5. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
6. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
7. Overshoot and undershoot specifications are characterized and are not 100% tested.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05601 Rev. *B
Page 4 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
GND
R2
30 pF
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
3.0V (VCC)
Unit
R1
26000
Ω
R2
26000
Ω
RTH
13000
Ω
VTH
1.50
V
Switching Characteristics Over the Operating Range[9, 10, 11, 15,14]
70 ns
Parameter
Description
Min.
Max.
Unit
40000
ns
Read Cycle
tRC [13]
Read Cycle Time
70
tCD
Chip Deselect Time CE1 = HIGH or
CE2 =LOW, BLE/BHE High Pulse Time
15
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
tHZOE
OE LOW to Low
70
Z[10, 11, 12]
OE HIGH to High
ns
5
Z[10, 11, 12]
ns
5
Z[10, 11, 12]
ns
ns
25
tLZCE
CE LOW to Low
tHZCE
CE HIGH to High Z[10, 11, 12]
25
ns
tDBE
BLE/BHE LOW to Data Valid
70
ns
tLZBE
tHZBE
[10, 11, 12]
BLE/BHE LOW to Low Z
10
ns
ns
5
[10, 11, 12]
BLE/BHE HIGH to High Z
ns
25
ns
40000
ns
35
ns
Page Read Cycle
tPC
Page Mode Read Cycle Time
tPA
Page Mode Address Access
35
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ.)/2, input pulse levels
of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
10. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V)
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high -impedence state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. If invalid address signals shorter than min.tRC are continuously repeated for 40 µs, the device needs a normal read timing (tRC) or needs to enter standby state
at least once in every 40 µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable (CE1 or CE2) controlled. That is, the addresses must be stable prior to Chip Enable
going active.
Document #: 38-05601 Rev. *B
Page 5 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
Switching Characteristics Over the Operating Range[9, 10, 11, 15,14] (continued)
70 ns
Parameter
Write Cycle
Description
Min.
Max.
Unit
40000
ns
[15]
tWC
Write Cycle Time
70
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tCD
Chip Deselect Time CE1 = HIGH or
CE2 =LOW, BLE/BHE High Pulse Time
15
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tBW
BLE/BHE LOW to Write End
60
ns
tSD
Data Set-Up to Write End
25
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[10, 11, 12]
tLZWE
WE HIGH to Low-Z[10, 11, 12]
ns
25
10
ns
ns
Note:
15. The internal Write time of the memory is defined by the overlap of WE,CE1 = VIL or CE2 = VIH, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write
Document #: 38-05601 Rev. *B
Page 6 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[17, 18]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
Read Cycle 2 (OE Controlled)[16, 18, 19]
ADDRESS
tRC
CE1
tCD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
tDBE
IMPEDANCE
tHZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes:
16. Whenever CE1 = HIGH or CE2 = LOW, BHE/BLE are taken inactive, they must remain inactive for a minimum of 5 ns.
17. Device is continuously selected. OE = CE1 = VIL and CE2 = VIH.
18. WE is HIGH for Read Cycle.
19. CE is the Logical AND of CE1 and CE2.
Document #: 38-05601 Rev. *B
Page 7 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
Switching Waveforms (continued)
Page Read Cycle (WE = VIH, 16 word access)[13, 18, 19]
t RC
A4-A19
tOHA
tAA
A0-A3
CE1
t PC
t ACE
CE2
t HZBE
t
DOE
OE
t HZCE
BHE/BLE
tDBE
t PAA
t LZCE
DATA OUT
DATA VALID
High Z
DATA VALID
DATA VALID
DATA
DATA VALID
VALID
DATA VALID
DATA VALID
DATA VALID
DATA VALID
Write Cycle 1 (WE Controlled)[15, 12, 16, 19, 20, 21]
t WC
ADDRESS
tSCE
CE1
tCD
CE2
tSA
tAW
tPWE
tHA
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
DON’T CARE
tHZOE
Notes:
20. Data I/O is high-impedance if OE > VIH.
21. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05601 Rev. *B
Page 8 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
Switching Waveforms (continued)
Write Cycle 2 (CE1 or CE2 Controlled)[15, 12, 16, 20, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
DON’T CARE
tHZOE
Write Cycle 3 (WE Controlled, OE LOW)[16, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tSA
tHA
tPWE
WE
tSD
DATAI/O
DON’T CARE
VALID DATA
tHZWE
Document #: 38-05601 Rev. *B
t HD
tLZWE
Page 9 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 16, 20, 21]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHD
tSD
DATA I/O
DON’T CARE
VALID DATA
Truth Table[22]
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
High Z
Inputs/Outputs
Deselect/Power-down
Mode
Standby (ISB)
Power
X
L
X
X
X
X
High Z
Deselect/Power-down
Standby (ISB)
X
X
X
X
H
H
High Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write (Upper Byte and Lower
Byte)
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High Z
Write (Lower Byte Only)
Active (ICC)
L
H
L
X
L
H
Data In (I/O8–I/O15);
I/O0 –I/O7 in High Z
Write (Upper Byte Only)
Active (ICC)
Note:
22. H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Document #: 38-05601 Rev. *B
Page 10 of 12
CYU01M16SCCU
MoBL3™
PRELIMINARY
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
70
CYU01M16SCCU-70BVXI
BV48
48-ball Fine Pitch VBGA (6 mm × 8 mm × 1 mm) (Pb-Free)
Industrial
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm) BV48
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
4
5
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
51-85150-*D
C
1.00 MAX
0.26 MAX.
SEATING PLANE
MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All
product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05601 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYU01M16SCCU
MoBL3™
PRELIMINARY
Document History Page
Document Title: CYU01M16SCCU MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM
Document Number: 38-05601
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
342199
See ECN
PCI
New Datasheet
*A
386551
See ECN
PCI
Changed from Advance to Preliminary
Replaced TBDs with appropriate values
Changed tPC and tPA from 20 to 25 ns
Corrected footnote # 16 as OE = CE1 = VIL and CE2 = VIH
Added separate waveforms for CE1 and CE2 in Read # 2, Page Read and
Write # 1 Timing diagram
*B
422623
See ECN
HRT
Removed the 55-ns Speed Bin
Changed Isb2 Max value from 60 µA to 70 µA
Added Isb1 to DC Parameters
Added Chip Enable Access Foot Note to AC Parameters
Changed the tCD Min value from 5 ns to 15 ns
Changed the Page Mode Values (tPC and tPAA) from 25 ns to 35 ns
Document #: 38-05601 Rev. *B
Page 12 of 12