APL5325 Adjustable Low Dropout 300mA Linear Regulator Features General Description • • The APL5325 is a P-channel low dropout linear regulator which needs only one input voltage from 3 to 6V, and Wide Operating Voltage: 3~6V Low Dropout Voltage: delivers current up to 300mA to set output voltage. It also can work with low ESR ceramic capacitors and is ideal for 300mV(Typical) @ 300mA • • • • • • • using in the battery-powered applications such as notebook computers and cellular phones. Typical dropout volt- Guaranteed 300mA Output Current Adjustable Output Voltage: 0.8~5.5V age is only 300mV at 300mA loading. Current limit with current foldback and thermal shutdown Current-Limit Protection with Foldback Current functions protect the device against current over-loads and over temperature. The APL5325 is available in a SOT- Over-Temperature Protection Stable with Low ESR Ceramic Capacitor 23-5 package. SOT-23-5 Package Lead Free and Green Devices Available Pin Configuration (RoHS Compliant) Applications • • • SHDN 1 GND 2 VIN 3 5 SET 4 VOUT Cellular Phones SOT-23-5 Portable and Battery-Powered Equipment Notebook and Personal Computers Simplified Application Circuit APL5325 VIN 3 CIN 1 VIN VOUT 4 SHDN SET 5 GND VOUT COUT 2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 1 www.anpec.com.tw APL5325 Ordering and Marking Information Package Code B: SOT-23-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APL5325 Assembly Material Handling Code Temperature Range Package Code APL5325 B: 25RX XXXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VIN VSHDN (Note 1) Rating Unit VIN Supply Voltage (VIN to GND) Parameter -0.3 ~ 6.5 V SHDN Input Voltage (SHDN to GND) -0.3 ~ 6.5 V PD Power Dissipation TJ Junction Temperature Internally Limited TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds W -40 ~ 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter θJA Thermal Resistance-Junction to Ambient θJC Thermal Resistance-Junction to Case Typical Value Unit (Note 2) SOT-23-5 SOT-23-5 240 o 130 o C/W C/W Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol VIN Parameter Range VIN Supply Voltage Unit 3~6 V 0.8 ~ 5.5 V VOUT Output Voltage IOUT VOUT Output Current 0 ~ 300 mA CIN Input Capacitor 0.22 ~ 100 µF Output Capacitor 1.5 ~ 100 µF Junction Temperature -40 ~ 125 o COUT TJ Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 2 C www.anpec.com.tw APL5325 Electrical Characteristics Unless otherwise specified, these specifications apply over VIN = VOUT+1V, IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF, TA = -40 to 85oC. Typical values are at TA = 25oC. Symbol VIN VOUT Parameter APL5325 Test Conditions Input Voltage Output Voltage Range Unit Min. Typ. Max. 3 - 6 V 0.8 - 5.5 V IQ Quiescent Current IOUT =10mA ~300mA - 135 160 µA VREF Reference Voltage Measured on SET, VIN=3V, IOUT=10mA - 0.8 - V Output Voltage Accuracy IOUT=10mA -2 - +2 % Line Regulation ∆VOUT%/∆VIN, IOUT=10mA -0.06 - +0.06 %/V ∆VOUT%/∆IOUT -0.2 - +0.2 %/A VOUT = 2.5V, IOUT = 300mA - 500 650 VOUT = 3.3V, IOUT = 300mA - 300 400 Power Supply Ripple Rejection Ratio f = 10kHz, IOUT = 300mA - 45 - dB Noise f = 80Hz to 100kHz, IOUT = 300mA - 160 - µVRMS 450 550 - mA - 80 - mA SHDN Input Voltage High 1.6 - - SHDN Input Voltage Low - - 0.4 REGLINE REGLOAD Load Regulation VDROP PSRR Dropout Voltage ILIMIT Current Limit ISHORT Foldback Current VOUT = 0V mV V VOUT Discharge MOSFET RDS(ON) SHDN = Low - 60 - Ω Shutdown VIN Supply Current SHDN = Low, VIN = 6V - 0.1 1 µA SHDN Pull Low Resistance - 3 - MΩ Over Temperature Threshold - 160 - o o Over Temperature Hysteresis SET Input Bias Current Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 VSET=0.8V 3 - 40 - -100 - 100 C C nA www.anpec.com.tw APL5325 Typical Operating Characteristics Quiescent Current vs. Supply Voltage Quiescent Current vs. Junction Temperature 160 138 IOUT= 0mV 136 Quiescent Current, IQ (µA) Quiescent Current, IQ (µA) 140 120 100 80 60 40 134 132 130 128 20 126 -50 0 0 1 2 3 4 5 6 7 -25 PSRR vs. Frequency 50 75 100 125 Dropout Voltage vs. Output Current Dropout Voltage, VDROP(mV) VIN=3.3V, VOUT=1.2V, COUT=2.2µF,IOUT=300mA -10 -20 PSRR(dB) 25 400 0 -30 -40 -50 -60 VOUT=3.3V 350 o TJ=125oC TJ=75 C 300 250 200 150 100 TJ=-50oC 50 -70 TJ=25oC 0 -80 1000 10000 100000 0 100 200 300 Output Current, I OUT(mA) Frequency(Hz) Current Limit vs. Junction Temperature Dropout Voltage vs. Output Current 700 600 VOUT=2.5V 600 TJ=125oC 500 VIN=5V TJ=75oC Current Limit, ILIMIT(mA) Dropout Voltage, VDROP(mV) 0 Junction Temperature, T J (o C) Supply Voltage, V IN (V) 400 300 200 o TJ=-50 C 100 550 500 VIN=3.3V 450 TJ=25oC 400 -50 0 0 100 200 300 0 25 50 Junction Temperature, Output Current, IOUT(mA) Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 -25 4 75 100 125 T J(oC) www.anpec.com.tw APL5325 Typical Operating Characteristics (Cont.) Phase vs. Frequency Loop Gain vs. Frequency 160 50 VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF 40 IOUT=100mA 20 10 0 -10 80 60 IOUT=100mA 20 -30 -40 IOUT=300mA 100 40 IOUT=300mA -20 VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF 120 Phase (degree) Loop Gain (dB) 30 140 0 1000 10000 100000 1000 1000000 100000 1000000 Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 10000 5 www.anpec.com.tw APL5325 Operating Waveforms Enable CH1 Shutdown SHDN SHDN CH1 VIN VIN CH2 CH2 CH3 VOUT VOUT CH3 I OUT IOUT CH4 CH4 CH1 : SHDN , 5V/div CH2 : VIN , 5V/div CH3 : VOUT , 2V/div CH4 : IOUT , 100mA/div Time : 200µs/div CH1 : SHDN , 5V/div CH2 : VIN , 5V/div CH3 : VOUT , 2V/div CH4 : IOUT , 100mA/div Time : 10µs/div Load Transient V IN=5V ; C I N=1µF ; C OUT =2.2µF ; T R =1µs Line Transient C IN=1 µF ; C OUT =2.2µF ; T R =5µs ; I OUT =10mA VOUT CH1 V IN VOUT I OUT CH2 CH2 CH1 CH1 : VIN , 1V/div DC CH2 : VOUT , 50mV/div AC Time : 20µs/div CH1 : VOUT , 50mV/div AC CH2 : IOUT , 100mA/div Time : 20µs/div Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 6 www.anpec.com.tw APL5325 Operating Waveforms (Cont.) Power On Power Off VIN VOUT VOUT CH2 CH2 I OUT CH3 VIN CH1 CH1 IOUT CH3 CH1 : VIN , 2V/div CH2 : VOUT , 2V/div CH3 : IOUT , 100mA/div Time : 2ms/div CH1 : VIN , 2V/div CH2 : VOUT , 2V/div CH3 : IOUT , 100mA/div Time : 10ms/div Pin Description PIN NO. 1 2 3 4 5 NAME SHDN GND VIN VOUT SET FUNCTION Shutdown control pin, logic high: enable; logic low: shutdown. Ground pin. Voltage supply input pin. Regulator output pin. Connect this pin to an external resistor divider to adjust output voltage. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 7 www.anpec.com.tw APL5325 Block Diagram UVLO & Shutdown Logic SHDN VIN Thermal Shutdown Foldback Current Limit + 0.8V 3MΩ VOUT SET GND Typical Application Circuit VIN 3 CIN 1µF VOUT VIN 1 SET SHDN VOUT 4 5 R1 GND COUT 2.2µF 2 Enable R2 Shutdown R1 VOUT = 0.8 ⋅ 1 + R2 Designation CIN CIN COUT COUT Supplier Murata Murata Murata Murata Part Number GRM185R61A105KE36 GRM188R71A105KA61 GRM188R61A225KE34 GRM188R71A225KE15 Specification 0603, X5R, 10V, 1µF 0603, X7R, 10V, 1µF 0603, X5R, 10V, 2.2µF 0603, X7R, 10V, 2.2µF Reference: www.murata.com Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 8 www.anpec.com.tw APL5325 Function Description Output Voltage Regulation The APL5325 is an adjustable low dropout linear regulator. The output voltage set by the resistor-divider is determined by: R1 VOUT = 0.8 ⋅ 1 + R2 Where R1 is connected from VOUT to SET with Kelvin sensing and R2 is connected from SET to GND. The recommended value of R2 is in the range of 100 to100kΩ. An error amplifier works with a temperature compensated 0.8V reference and an output PMOS regulates the output to the presetting voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output PMOS which provides load current from VIN to VOUT. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5325. When the junction temperature exceeds +160οC, a thermal sensor turns off the output PMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature is cooled down by 40oC. The thermal shutdown is designed with a 40oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, device power dissipation should be externally limited so that junction temperature will not exceed 125oC. Shutdown Control The APL5325 has an active-low shutdown function. Force SHDN high (>1.6V) enables the VOUT; force SHDN low (<0.4V) disables the VOUT. SHDN is internally pulled low by a resistor (3mΩ typical). If it is not used, connect to VIN for normal operation. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 9 www.anpec.com.tw APL5325 Application Information Input Capacitor Operation Region and Power Dissipation The APL5325 requires proper input capacitors to supply surge current during stepping load transients to prevent The APL5325 maximum power dissipation depends on the thermal resistance and temperature difference be- the input rail from dropping . Because the parasitic inductor from the voltage sources or other bulk capacitors to tween the die junction and ambient air. The power dissipation PD across the device is: the VIN limit the slew rate of the surge current, place the Input capacitors near VIN as close as possible. Input ca- PD = (TJ - TA) / θJA where (TJ-TA) is the temperature difference between the junction and ambient air. θ JA is the thermal resistance pacitors should be larger than 1µF and a minimum ceramic capacitor of 1µF is necessary. Output Capacitor between Junction and ambient air. Assuming the TA=25 oC and maximum TJ=160 oC (typical thermal limit The APL5325 needs a proper output capacitor to maintain circuit stability and to improve transient response over threshold), the maximum power dissipation is calculated as: temperature and current. In order to insure the circuit stability, the proper output capacitor value should be larger PD(max)=(160-25)/240 = 0.56(W) than 2.2µF. With X5R and X7R dielectrics, 2.2µF is sufficient at all operating temperatures. Large output capaci- For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated power dissipation should less than: tor value can reduce noise and improve load-transient response and PSRR, however, it also affects power on PD =(125-25)/240 = 0.41(W) issue. Equation (1) shows the relationship between the maximum COUT value and the VOUT. C OUT(max) = 101 − The GND provides an electrical connection to the ground and channels heat away. Connect the GND to the ground by using a large pad or a ground plane. 19.5 VOUT Layout Consideration Where the unit of COUT is µF and VOUT is V. Figure 1 shows the curve of maximum output capacitor over the output Figure 2 illustrates the layout. Below is a checklist for voltage. The output voltage range is from 0.8 to 5.5V and the output capacitor value should under the line. Output your layout: 1. Please place the input capacitors close to the VIN. capacitors must be placed at the load and the ground pin as close as possible and the impedance of the layout 2. Ceramic capacitors for load must be placed near the load as close as possible. must be minimized. 3. To place APL5325 and output capacitors near the load is good for performance. Output Capacitor (µF) 120 4. Large current paths, the bold lines in figure 2, must have wide tracks. 110 5. Divider resistor R1 and R2 must be placed near the SET as close as possible. 100 90 80 70 60 0 1 2 3 4 5 6 Output Voltage (V) Figure 1 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 10 www.anpec.com.tw APL5325 Application Information (Cont.) Layout Consideration (Cont.) CIN APL5325 VIN VOUT SET VIN 3 VOUT 4 5 R1 COUT GND 2 LOAD R2 Figure 2 Recommended Minimum Footprint SOT-23-5 0.05 0.1 0.076 0.038 0.02 Unit : Inch Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 11 www.anpec.com.tw APL5325 Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 INCHES MILLIMETERS MIN. MIN. MAX. A MAX. 0.057 1.45 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 A1 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC e1 1.90 BSC 0.037 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 12 www.anpec.com.tw APL5325 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOT-23-5 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOT-23-5 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 13 www.anpec.com.tw APL5325 Taping Direction Information SOT-23-5 USER DIRECTION OF FEED Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 14 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw APL5325 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volume mm <350 Volume mm ≥350 <2.5 mm ≥2.5 mm 240 +0/-5°C 225 +0/-5°C 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures Package Thickness Volume mm <350 3 Volume mm 350-2000 3 Volume mm >2000 3 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 15 www.anpec.com.tw