Cypress CY29772 2.5v or 3.3v, 200-mhz, 12-output zero delay buffer Datasheet

CY29772
2.5V or 3.3V, 200-MHz, 12-Output
Zero Delay Buffer
Features
Description
• Output frequency range: 8.33 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 125 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2% max. Output duty cycle variation
• 7 ps RMS typical Cycle-to-cycle jitter
• 6 ps RMS typical Period jitter
• 12 clock outputs: drive up to 24 clock lines
• One feedback output
• Three reference clock inputs: crystal or LVCMOS
The CY29772 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed
clock-distribution applications.
The CY29772 features one on-chip crystal oscillator and two
LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides
the VCO output per SEL(A:C) settings, see Functional Table.
These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1,
3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces,
giving the device an effective fanout of 1:24.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider, see Frequency Table.
• 300 ps max. output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9772 and MPC972
• Industrial temperature range: –40°C to +85°C
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
• 52-pin 1.0-mm TQFP package
Block Diagram
Pin Configuration
SELA(0,1)
D Q
Sync
Frz
D Q
Sync
Frz
/4, /6, /8, /12
2
Sync
Frz
SYNC
Output Disable
Circuitry
FB_SEL1
D Q
SYNC
Data Generator
VSS
SCLK
SDATA
2
QC0
FB_SEL(0,1)
VDDQC
FB_OUT
Sync Pulse
QC1
Sync
Frz
SELC0
D Q
SELC1
0
1
QC2
/2
VDDQC
QC3
/4, /6, /8, /10
V SS
QB0
V DDQB
QB1
V SS
QB2
V DDQB
QB3
FB_IN
V SS
FB_OUT
V DD
FB_SEL0
14 15 16 17 18 19 20 21 22 23 24 25 26
QC2
QC3
2
39
38
37
36
35
34
33
32
31
30
29
28
27
C Y29772
VSS
2
/2, /4, /6, /8
1
2
3
4
5
6
7
8
9
10
11
12
13
INV_CLK
SELB(0,1)
SELC(0,1)
QC0
QC1
/4, /6, /8, /10
SELB1
QB3
Power-On
Reset
SELB0
QB2
MR#/OE
SELA1
QB0
QB1
FB_SEL2
SELA0
Sync
Frz
QA3
A V SS
MR#/OE
SCLK
SDA TA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
A V DD
QA3
D Q
VDDQA
52 51 50 49 48 47 46 45 44 43 42 41 40
QA2
FB_IN
QA2
LPF
VSS
QA0
QA1
QA1
Sync
Frz
VDDQA
0
1
VCO
QA0
TCLK1
TCLK_SEL
Phase
Detector
0
1
VSS
D Q
TCLK0
VCO_SEL
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
12
INV_CLK
Cypress Semiconductor Corporation
Document #: 38-07572 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 1, 2005
CY29772
Pin Description[1]
Pin
Name
I/O
Type
Description
11
XIN
I
Analog
Crystal oscillator input.
12
XOUT
O
Analog
Crystal oscillator output.
9
TCLK0
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input.
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input.
44, 46, 48, 50
QA(3:0)
O
LVCMOS
Clock output bank A.
32, 34, 36, 38
QB(3:0)
O
LVCMOS
Clock output bank B.
16, 18, 21, 23
QC(3:0)
O
LVCMOS
Clock output bank C.
29
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See Table 1.
25
SYNC
O
LVCMOS
Synchronous pulse output. This output is used for system synchronization.
6
PLL_EN
I, PU
LVCMOS
PLL enable/bypass input. When Low, PLL is disabled/bypassed.
and the input clock connects to the output dividers.
2
MR#/OE
I, PU
LVCMOS
Master reset and Output enable/disable input. See Table 2.
8
TCLK_SEL
I, PU
LVCMOS
LVCMOS Clock reference select input. See Table 2.
7
REF_SEL
I, PU
LVCMOS
LVCMOS/LVPECL Reference select input. See Table 2.
52
VCO_SEL
I, PU
LVCMOS
VCO Operating frequency select input. See Table 2.
14
INV_CLK
I, PU
LVCMOS
QC(2,3) Phase selection input. See Table 2.
5, 26, 27
FB_SEL(2:0)
I, PU
LVCMOS
Feedback divider select input. See Table 6.
42, 43
SELA(1,0)
I, PU
LVCMOS
Frequency select input, Bank A. See Table 3.
40, 41
SELB(1,0)
I, PU
LVCMOS
Frequency select input, Bank B. See Table 4.
19, 20
SELC(1,0)
I, PU
LVCMOS
Frequency select input, Bank C. See Table 5.
3
SCLK
I, PU
LVCMOS
Serial Clock input.
4
SDATA
I, PU
LVCMOS
Serial Data input.
45, 49
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks.[2,3]
33, 37
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks.[2,3]
22, 17
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks.[2,3]
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL.[2,3]
28
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs.[2,3]
1
AVSS
Supply
Ground
Analog Ground.
Supply
Ground
Common Ground.
15, 24, 30, 35, VSS
39, 47, 51
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
Document #: 38-07572 Rev. *A
Page 2 of 12
CY29772
Table 1. Frequency Table
Feedback Output
Divider
Input Frequency Range
(AVDD = 3.3V)
VCO
Input Frequency Range
(AVDD = 2.5V)
÷4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 95 MHz
÷6
Input Clock * 6
33.3 MHz to 83.3 MHz
33.3 MHz to 63.3 MHz
÷8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 47.5 MHz
÷10
Input Clock * 10
20 MHz to 50 MHz
20 MHz to 38 MHz
÷12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 31.6 MHz
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
÷20
Input Clock * 20
10 MHz to 25 MHz
10 MHz to 19 MHz
÷24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 15.8 MHz
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.8 MHz
÷40
Input Clock * 40
5 MHz to 12.5 MHz
5 MHz to 9.5MHz
Table 2. Function Table (Configuration Controls)
Control
Default
REF_SEL
1
0
1
TCLK0, TCLK1
Crystal oscillator
TCLK_SEL
1
TCLK0
TCLK1
VCO_SEL
1
VCO÷2 (low input frequency range)
VCO÷1 (high input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock connects to the PLL enabled. The VCO output connects
output dividers
to the output dividers
INV_CLK
1
QC2 and QC3 are in phase with QC0 and QC1
MR#/OE
1
Outputs disabled (three-state) and reset of the device. During Outputs enabled
reset/output disable the PLL feedback loop is open and the
VCO running at its minimum frequency. The device is reset
by the internal power-on reset (POR) circuitry during
power-up.
Table 3. Function Table (Bank A)
VCO_SEL
0
0
0
0
1
1
1
1
SELA1
0
0
1
1
0
0
1
1
SELA0
0
1
0
1
0
1
0
1
QC2 and QC3 are inverted (180° phase
shift) with respect to QC0 and QC1
Table 5. Function Table (Bank C)
QA(0:3)
÷8
÷12
÷16
÷24
÷4
÷6
÷8
÷12
VCO_SEL
0
0
0
0
1
1
1
1
SELC1
0
0
1
1
0
0
1
1
SELC0
0
1
0
1
0
1
0
1
QC(0:3)
÷4
÷8
÷12
³16
÷2
÷4
÷6
÷8
Table 4. Function Table (Bank B)
VCO_SEL
0
0
0
0
1
1
1
1
SELB1
0
0
1
1
0
0
1
1
Document #: 38-07572 Rev. *A
SELB0
0
1
0
1
0
1
0
1
QB(0:3)
÷8
÷12
÷16
÷20
÷4
÷6
÷8
÷10
Page 3 of 12
CY29772
Table 6. Function Table (FB_OUT)
VCO_SEL FB_SEL2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Document #: 38-07572 Rev. *A
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FB_OUT
÷8
÷12
÷16
÷20
÷16
÷24
÷32
÷40
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
Page 4 of 12
CY29772
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
DC Supply Voltage
–0.3
5.5
V
VDD
DC Operating Voltage
Functional
2.375
3.465
V
VIN
DC Input Voltage
Relative to VSS
–0.3
VDD + 0.3
V
VOUT
DC Output Voltage
Relative to VSS
–0.3
VDD + 0.3
V
VTT
Output termination Voltage
–
VDD ÷ 2
V
LU
Latch-up Immunity
Functional
200
–
mA
RPS
Power Supply Ripple
Ripple Frequency < 100 kHz
–
150
mVp-p
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
–
+150
°C
ØJC
Dissipation, Junction to Case
Functional
–
23
°C/W
ØJA
Dissipation, Junction to Ambient
Functional
–
55
°C/W
ESDH
ESD Protection (Human Body Model)
FIT
Failure in Time
2000
–
Manufacturing test
V
10
ppm
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VIL
Input Voltage, Low
LVCMOS
–
–
0.7
V
VIH
Input Voltage, High
LVCMOS
1.7
–
VDD+0.3
V
Low[4]
VOL
Output Voltage,
VOH
Output Voltage, High[4]
IOH = –15 mA
IIL
Input Current, Low[5]
IIH
Input Current, High[5]
IDDA
IDDQ
IOL = 15 mA
–
–
0.6
V
1.8
–
–
V
VIL = VSS
–
–
–100
µA
VIL = VDD
–
–
100
µA
PLL Supply Current
AVDD only
–
5
10
mA
Quiescent Supply Current
All VDD pins except AVDD
–
–
8
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100 MHz
–
135
–
mA
CIN
Input Pin Capacitance
–
4
–
pF
ZOUT
Output Impedance
14
18
22
Ω
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)
Min.
Typ.
Max.
Unit
VIL
Parameter
Input Voltage, Low
Description
LVCMOS
Condition
–
–
0.8
V
VIH
Input Voltage, High
LVCMOS
2.0
–
VDD + 0.3
V
VOL
Output Voltage, Low[4]
IOL = 24 mA
–
–
0.55
V
VOH
Output Voltage, High[4]
IOL = 12 mA
IOH = –24 mA
–
–
0.30
2.4
–
–
V
IIL
Input Current,
Low[5]
VIL = VSS
–
–
–100
µA
IIH
Input Current, High[5]
VIL = VDD
–
–
100
µA
IDDA
PLL Supply Current
AVDD only
–
5
10
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
–
–
8
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100 MHz
–
225
–
mA
CIN
Input Pin Capacitance
–
4
–
pF
ZOUT
Output Impedance
12
15
18
Ω
Notes:
4. Driving one 50Ω parallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series-terminated transmission lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07572 Rev. *A
Page 5 of 12
CY29772
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) [6]
Parameter
Description
fVCO
VCO Frequency
fXTAL
Crystal Frequency Range
fin
Input Frequency
Condition
Min.
Typ.
Max.
Unit
200
–
380
MHz
See Table 7
10
–
25
MHz
÷4 Feedback
50
–
95
MHz
÷6 Feedback
33.3
–
63.3
÷8 Feedback
25
–
47.5
÷10 Feedback
20
–
38
÷12 Feedback
16.6
–
31.6
÷16 Feedback
12.5
–
23.75
÷20 Feedback
10
–
19
÷24 Feedback
8.3
–
15.8
÷32 Feedback
6.25
–
11.8
÷40 Feedback
5
–
9.5
0
–
200
25
–
75
1.0
ns
190
MHz
Bypass mode (PLL_EN = 0)
frefDC
Input Duty Cycle
tr, tf
TCLK Input Rise/FallTime
0.7V to 1.7V
–
–
fMAX
Maximum Output Frequency
÷2 Output
100
–
÷4 Output
50
–
95
÷6 Output
33.3
–
63.3
÷8 Output
25
–
47.5
÷10 Output
20
–
38
fSCLK
Serial Clock Frequency
DC
Output Duty Cycle
%
÷12 Output
16.6
–
31.6
÷16 Output
12.5
–
23.75
÷20 Output
10
–
19
÷24 Output
8.3
–
15.8
–
–
20
MHz
fMAX < 100 MHz
47.5
–
52.5
%
fMAX > 100 MHz
45
–
55
tr, tf
Output Rise/Fall times
0.6V to 1.8V
t(φ)
Propagation Delay
(static phase offset)
TCLK to FB_IN
tsk(O)
Output-to-Output Skew
Skew within Bank A
0.1
–
1.0
ns
–125
–
125
ps
–
–
75
ps
Skew within Bank B
–
–
100
Skew within Bank C
–
–
150
tsk(B)
Bank-to-Bank Skew
–
–
400
ps
tPLZ, HZ
Output Disable Time
–
–
10
ns
tPZL, ZH
Output Enable Time
BW
PLL Closed Loop Bandwidth
(–3 dB)
–
–
10
ns
÷4 Feedback
–
1.3–2.0
–
MHz
÷6 Feedback
–
0.7–1.3
–
÷8 Feedback
–
0.9–1.3
–
÷10 Feedback
–
0.6–1.1
–
÷12 Feedback
–
0.6–0.9
–
÷16 Feedback
–
0.4–0.6
–
÷20 Feedback
–
0.6–0.9
–
Note:
6. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
Document #: 38-07572 Rev. *A
Page 6 of 12
CY29772
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) (continued)[6]
Parameter
tJIT(CC)
tJIT(PER)
Description
Cycle-to-Cycle Jitter
Period Jitter
Condition
Same frequency (125 MHz)
RMS (1σ)
Min.
Typ.
Max.
Unit
–
7
30
ps
Same frequency
–
–
150
Multiple frequencies
–
–
435
Same frequency (125 MHz)
RMS (1σ)
–
6
30
Same frequency
–
45
75
Multiple frequencies
–
–
235
ps
tJIT(φ)
I/O Phase Jitter
–
–
150
ps
tLOCK
Maximum PLL Lock Time
–
–
1
ms
Min.
Typ.
Max.
Unit
200
–
500
MHz
10
–
25
MHz
MHz
AC Parameters (VDD = 3.3V ± 5%, TA = –40°C to +85°C) [6]
Parameter
Description
Condition
fVCO
VCO Frequency
fXTAL
Crystal Frequency Range
See Table 7
fin
Input Frequency
÷4 Feedback
50
–
125
÷6 Feedback
33.3
–
83.3
÷8 Feedback
25
–
62.5
÷10 Feedback
20
–
50
÷12 Feedback
16.6
–
41.6
÷16 Feedback
12.5
–
31.25
÷20 Feedback
10
–
25
÷24 Feedback
8.3
–
20.8
÷32 Feedback
6.25
–
15.625
÷40 Feedback
5
–
12.5
Bypass mode (PLL_EN = 0)
frefDC
Input Duty Cycle
tr, tf
TCLK Input Rise/FallTime
0.8V to 2.0V
fMAX
Maximum Output Frequency
÷2 Output
fMAX
Maximum Output Frequency
(continued)
0
–
200
25
–
75
%
–
–
1.0
ns
100
–
200
MHz
÷4 Output
50
–
125
÷6 Output
33.3
–
83.3
÷8 Output
25
–
62.5
÷10 Output
20
–
50
÷12 Output
16.6
–
41.6
÷16 Output
12.5
–
31.25
÷20 Output
10
–
25
÷24 Output
8.3
–
20.8
–
–
20
MHz
48
–
52
%
MHz
fSCLK
Serial Clock Frequency
DC
Output Duty Cycle
fMAX < 100 MHz
fMAX > 100 MHz
45
–
55
tr, tf
Output Rise/Fall times
0.55V to 2.4V
0.1
–
1.0
ns
t(φ)
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD
–125
–
125
ps
tsk(O)
Output-to-Output Skew
ps
Document #: 38-07572 Rev. *A
Skew within Bank A
–
–
75
Skew within Bank B
–
–
100
Page 7 of 12
CY29772
AC Parameters (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued)[6]
Parameter
Description
Condition
Skew within Bank C
Min.
Typ.
Max.
–
–
150
Unit
tsk(B)
Bank-to-Bank Skew
–
–
325
ps
tPLZ, HZ
Output Disable Time
–
–
8
ns
tPZL, ZH
Output Enable Time
BW
PLL Closed-Loop Bandwidth
(–3 dB)
tJIT(CC)
tJIT(PER)
Cycle-to-Cycle Jitter
Period Jitter
tJIT(φ)
I/O Phase Jitter
tLOCK
Maximum PLL Lock Time
–
–
8
ns
÷4 Feedback
–
1.3–2.0
–
MHz
÷6 Feedback
–
0.7–1.3
–
÷8 Feedback
–
0.9–1.3
–
÷10 Feedback
–
0.6–1.1
–
÷12 Feedback
–
0.6–0.9
–
÷16 Feedback
–
0.–0.6
–
÷20 Feedback
–
0.6–0.9
–
Same frequency (125 MHz)
RMS (1σ)
–
7
30
Same frequency
–
–
100
Multiple frequencies
–
–
375
Same frequency (125 MHz)
RMS (1σ)
–
6
30
Same frequency
–
45
75
Multiple frequencies
–
–
225
I/O same VDD
–
–
150
ps
–
–
1
ms
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The CY29772 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
Document #: 38-07572 Rev. *A
ps
ps
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. Figure 1 illustrates various waveforms for the SYNC output. Note that the
SYNC output is defined for all possible combinations of the QA
and QC outputs even though under some relationships the
lower frequency clock could be used as a synchronizing
signal.
Page 8 of 12
CY29772
VCO
1:1 Mode
QA
QC
SYNC
2:1 Mode
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
QA
QC
SYNC
4:1 Mode
QC
QA
SYNC
4:3 Mode
QA
QC
SYNC
6:1 Mode
QA
QC
SYNC
Figure 1.
Power Management
The individual output enable/freeze control of the CY29772
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
‘0’ state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
Document #: 38-07572 Rev. *A
data. An output is frozen when a logic ‘0’ is programmed and
enabled when a logic ‘1’ is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA
input by writing a logic ‘0’ start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
Page 9 of 12
CY29772
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Figure 2.
Table 7. Suggested Oscillator Crystal Parameters
Parameter
Description
Conditions
TC
Frequency Tolerance
TS
Frequency Temperature Stability
Min.
(TA –10° to +60°C)
Typ.
Max.
Unit
–
–
±1100
PPM
–
–
± 100
PPM
TA
Aging
(First three years @ 25°C)
–
–
5
PPM/Yr
CL
Load Capacitance
The crystal’s rated load
–
20
–
pF
RESR
Effective Series Resistance (ESR)
–
40
80
Ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 4. LVCMOS Propagation Delay t(φ), Static Phase Offset
VDD
VDD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (DC)
Document #: 38-07572 Rev. *A
Page 10 of 12
CY29772
VDD
VDD/2
GND
VDD
VDD/2
tSK(O)
GND
Figure 6. Output-to-Output Skew, tsk(O)
Ordering Information
Part Number
Package Type
Product Flow
CY29772AI
52-pin TQFP
Industrial, –40°C to +85°C
CY29772AIT
52-pin TQFP – Tape and Reel
Industrial,–40°C to 85°C
Lead-free
CY29772AXI
52-pin TQFP
Industrial, –40°C to +85°C
CY29772AXIT
52-pin TQFP – Tape and Reel
Industrial,–40°C to 85°C
Package Drawing and Dimension
52-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07572 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY29772
Document History Page
Document Title:CY29772 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Document Number: 38-07572
REV.
ECN No.
Issue Date
Orig. of
Change
**
129007
09/03/03
RGL
New Data Sheet
*A
395853
See ECN
RGL
Added Lead-free devices
Added Jitter typical specs in the features section
Document #: 38-07572 Rev. *A
Description of Change
Page 12 of 12
Similar pages