CAT5171 256‐position I2C Compatible Digital Potentiometer (POT) The CA5171 is a 256-position digital linear taper potentiometer ideally suited for replacing mechanical potentiometers and variable resistors. The wiper settings are controlled through an I2C-compatible digital interface. Upon power-up, the wiper assumes a midscale position and may be repositioned anytime after the power is stable. The device can be programmed to reset the wiper position to midscale or to go to a shutdown state during operation. An address input pin, AD0, allows the connection of two devices onto the same I2C bus. The CAT5171 operates from 2.7 V to 5.5 V, while consuming less than 2 mA. This low operating current, combined with a small package footprint, makes the CAT5171 ideal for battery-powered portable applications. The CAT5171, designed as a pin for pin replacement for the AD5245, is offered in the 8-lead SOT23 package and operates over the −40C to +85C industrial temperature range. http://onsemi.com SOT23−8 TP, TB SUFFIX CASE 527AK MARKING DIAGRAM Features 256-position End-to-End Resistance: 50 kW, 100 kW I2C Compatible Interface Power-on Preset to Midscale Single Supply 2.7 V to 5.5 V Low Temperature Coefficient 100 ppm/C Low Power, IDD 2 mA max Wide Operating Temperature −40C to +85C SOT−23 8-lead (2.9 mm 3 mm) Package These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications Potentiometer Replacement Transducer Adjustment of Pressure, Temperature, Position, Chemical, and Optical Sensors RF Amplifier Biasing Gain Control and Offset Adjustment AFYM AGYM 1 1 AF = 50 kW AG = 100 kW Y = Production Year Y = (Last Digit) M = Production Month M = (1 − 9, A, B, C) PIN CONNECTIONS W A 1 B VDD GND AD0 SCL SDA (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 2013 July, 2013 − Rev. 2 1 Publication Order Number: CAT5171/D CAT5171 VDD A SCL I2C Interface and Control SDA AD0 Power On Midscale W B GND Figure 1. Functional Block Diagram Table 1. ORDERING INFORMATION Part Number Resistance CAT5171TBI−50GT3 50 kW CAT5171TBI−00GT3 100 kW Temperature Range Package Shipping† −40C to 85C SOT−23−8 (Pb-Free) 3000/Tape & Reel 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com. Table 2. PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 W 2 VDD Positive Power Supply 3 GND Digital Ground 4 SCL Serial Clock Input 5 SDA Serial Data Input 6 AD0 I2C Address bit 0 input 7 B Bottom Terminal of resistive element 8 A Top Terminal of resistive element Resistor’s Wiper Terminal Table 3. ABSOLUTE MAXIMUM RATINGS (Note 2) Rating VDD to GND Value Unit −0.3 to 6.5 V VA, VB, VW to GND VDD IMAX 20 mA 0 to 6.5 V −40 to +85 C 150 C −65 to +150 C 300 C Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. http://onsemi.com 2 CAT5171 Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions VDD = 2.7 V to 5.5 V; VA = VDD; VB = 0 V; –40C < TA < +85C; unless otherwise noted. Test Conditions Symbol Min Typ (Note 3) Max Unit Resistor Differential Nonlinearity (Note 4) RWB, VA = no connection R−DNL −1 0.1 +1 LSB Resistor Integral Nonlinearity (Note 4) 0.4 +2 LSB Parameter DC CHARACTERISTICS — RHEOSTAT MODE RWB, VA = no connection R−INL −2 Nominal Resistor Tolerance (Note 5) TA = 25C nRAB −20 Resistance Temperature Coefficient VAB = VDD, Wiper = no connection nRAB/nT VDD = 5 V, IW = 3 mA RW Wiper Resistance +20 100 VDD = 3 V, IW = 3 mA % ppm/C 50 120 100 250 W DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE N Resolution 8 Bits LSB Differential Nonlinearity (Note 6) DNL −1 0.1 +1 Integral Nonlinearity (Note 6) INL −1 0.4 +1 100 LSB Voltage Divider Temperature Coefficient Code = 0x80 nVW/nT ppm/C Full-Scale Error Code = 0xFF VWFSE −3 −1 0 LSB Zero-Scale Error Code = 0x00 VWZSE 0 1 3 LSB VA,B,W GND VDD V RESISTOR TERMINALS Voltage Range (Note 7) Capacitance (Note 8) A, B f = 1 MHz, measured to GND, Code = 0 x 80 CA,B 45 pF Capacitance (Note 8) W f = 1 MHz, measured to GND, Code = 0 x 80 CW 60 pF VA = VB = VDD/2 ICM 1 nA Input Logic High VDD = 5 V VIH Input Logic Low VDD = 5 V VIL Input Logic High VDD = 3 V VIH VDD = 3 V VIL 0.3VDD V VIN = 0 V or 5 V IIL 1 mA 5.5 V Common-Mode Leakage (Note 8) DIGITAL INPUTS Input Logic Low Input Current 0.7 x VDD V 0.3VDD 0.7 x VDD V V POWER SUPPLIES VDD RANGE Power Supply Range Supply Current Power Dissipation (Note 8) Power Supply Sensitivity 2.7 VIH = 5 V or VIL = 0 V IDD 2 mA VIH = 5 V or VIL = 0 V, VDD = 5 V PDISS 0.3 0.2 mW nVDD = +5 V 10%, Code = Midscale PSS 0.05 %/% DYNAMIC CHARACTERISTICS (Notes 8 and 10) Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (50 kW/100 kW) RAB = 50 kW / 100 kW, Code = 0x80 BW 100/40 kHz VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kW THDW 0.05 % VA = 5 V, VB = 0 V, 1 LSB error band tS 2 ms 3. Typical specifications represent average readings at +25C and VDD = 5 V. 4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 5. VAB = VDD, Wiper (VW) = no connect. 6. INL and DNL are measured at VW with the digital potentiometer configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 7. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 8. Guaranteed by design and not subject to production test. 9. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 10. All dynamic characteristics use VDD = 5 V. http://onsemi.com 3 CAT5171 Table 5. CAPACITANCE TA = 25C, f = 1.0 MHz, VDD = 5 V Test Symbol CI/O (Note 11) Input/Output Capacitance (SDA, SCL) Conditions Max Units VI/O = 0V 8 pF Max Units Table 6. POWER UP TIMING (Notes 11 and 12) Parameter Symbol tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Max Units Wiper Response Time After Power Supply Stable 50 ms Wiper Response Time: SCL falling edge after last bit of wiper position data byte to wiper change 20 ms Max Units 400 kHz 11. This parameter is tested initially and after a design or process change that affects the parameter. 12. tPUR and t PUW are delays required from the time VCC is stable until the specified operation can be initiated. Table 7. DIGITAL POTENTIOMETER TIMING Symbol tWRPO tWR Parameter Min Table 8. A.C. CHARACTERISTICS VDD = +2.7 V to +5.5 V, −40C to +85C unless otherwise specified. Parameter Symbol Min Typ fSCL Clock Frequency tHIGH Clock High Period 600 ns tLOW Clock Low Period 1300 ns tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:DAT Data in Setup Time 100 ns tHD:DAT Data in Hold Time 0 ns tSU:STO Stop Condition Setup Time 600 ns Time the bus must be free before a new transmission can start 1300 ns tBUF tR SDA and SCL Rise Time 300 ns tF SDA and SCL Fall Time 300 ns tDH Data Out Hold Time 100 ns TI Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA SCL Low to SDA Data Out and ACK Out 1 ms http://onsemi.com 4 CAT5171 TYPICAL CHARACTERISTICS 0.03 0.1 0.02 0 DNL ERROR (LSB) ERROR (LSB) 0.01 0 −0.01 −0.02 −0.1 INL −0.2 −0.3 −0.03 −0.4 −0.04 −0.05 0 32 64 96 128 160 192 224 −0.5 256 0 32 64 96 128 160 192 TAP TAP Figure 2. Differential Non−Linearity, VDD = 5.6 V Figure 3. Integral Non−Linearity, VDD = 5.6 V 120 6 100 5 224 256 5.6 V VDD = 2.6 V 4.0 V Vw (V) 60 3.3 V 3 40 3.3 V 2 20 0 5.0 V 4 5.6 V 4.0 V 0 50 100 VDD = 2.6 V 1 150 200 0 250 0 52 104 156 TAP TAP Figure 4. Wiper Resistance at Room Temperature Figure 5. Wiper Voltage 400 350 T = 90C 300 ISB (nA) Rw (W) 80 T = −45C 250 T = 25C 200 150 100 2 3 4 5 VDD (V) Figure 6. Standby Current http://onsemi.com 5 6 208 260 CAT5171 TYPICAL CHARACTERISTICS 102.15 0.4 102.10 102.05 0.2 D (%) R (kW) 102.00 101.95 101.90 0 101.85 101.80 −0.2 −50 −20 10 40 70 101.75 −50 100 −20 10 40 70 TEMPERATURE (C) TEMPERATURE (C) Figure 7. Change in End−to−End Resistance Figure 8. End−to−End Resistance vs. Temperature 0 100 30 −6 25 VDD = 5 V PSRR (dB) A (dB) −12 VDD = 3 V −18 −24 −30 −36 20 VDD = 5 V 15 VDD = 3 V 10 5 1 10 100 1000 0 1 10 100 f (KHz) f (KHz) Figure 9. Gain vs. Bandwidth (Tap 0x80) Figure 10. PSRR http://onsemi.com 6 1000 CAT5171 BASIC OPERATION stable, the wiper may be repositioned via the I2C compatible interface. The CAT5171 is a 256-position digitally controlled potentiometer. When power is first applied, the wiper assumes a mid-scale position. Once the power supply is PROGRAMMING: VARIABLE RESISTOR Rheostat Mode and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 100 kW and the A terminal is open circuited, the following output resistance RWB will be set for the indicated Wiper register codes: The resistance between terminals A and B, RAB, has a nominal value of 50 kW or 100 kW and has 256 contact points accessed by the wiper terminal, plus the B terminal contact. Data in the 8-bit Wiper register is decoded to select one of these 256 possible settings. The wiper’s first connection is at the B terminal, corresponding to control position 0x00. Ideally this would present a 0 W between the Wiper and B, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the RON of the FET switch connecting the wiper output with its respective contact point. In CAT5171 this ‘contact’ resistance is typically 50 W. Thus a connection setting of 0x00 yields a minimum resistance of 50 W between terminals W and B. For a 100 kW device, the second connection, or the first tap point, corresponds to 441 W (RWB = RAB/256 + RW = 390.6 + 50 W) for data 0x01. The third connection is the next tap point, is 831 W (2 x 390.6 + 50 W) for data 0x02, and so on. Figure 11 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. Table 9. CODES AND CORRESPONDING RWB RESISTANCE FOR RAB = 100 kW, VDD = 5 V RWB (W) Output State 255 99,559 Full Scale (RAB – 1 LSB + RW) 128 50,050 Midscale 1 441 1 LSB 0 50 Zero Scale (Wiper Contact Resistance) Be aware that in the zero-scale position, the wiper resistance of 50 W is still present. Current flow between W and B in this condition should be limited to a maximum pulsed current of no more than 20 mA. Failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. Similar to the mechanical potentiometer, the resistance of the digital POT between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is A RS RS Wiper Register and Decoder D (Dec.) R WA(D) + 256 * D R AB ) R W 256 (eq. 2) For RAB = 100 kW and the B terminal open circuited, the following output resistance RWA will be set for the indicated Wiper register codes. RS W Table 10. CODES AND CORRESPONDING RWA RESISTANCE FOR RAB = 100 kW, VDD = 5 V RS B Figure 11. CAT5171 Equivalent Digital POT Circuit The equation for determining the digitally programmed output resistance between W and B is R WB + D R AB ) R W 256 (eq. 1) D (Dec.) RWA (W) Output State 255 441 Full Scale 128 50,050 Midscale 1 99,659 1 LSB 0 100,050 Zero Scale Typical device to device resistance matching is lot dependent and may vary by up to 20%. where D is the decimal equivalent of the binary code loaded in the 8-bit Wiper register, RAB is the end-to-end resistance, http://onsemi.com 7 CAT5171 ESD Protection Power-up Sequence Digital Input Because ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 12), it is recommended that VDD/GND be powered before applying any voltage to terminals A, B, and W. The ideal power−up sequence is: GND, VDD, digital inputs, and then VA/B/W. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND. LOGIC GND Power Supply Bypassing Good design practice employs compact, minimum lead length layout design. Leads should be as direct as possible. It is also recommended to bypass the power supplies with quality low ESR Ceramic chip capacitors of 0.01 mF to 0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. As a further precaution digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. W, A, B Potentiometer GND VDD Figure 12. ESD Protection Networks VDD C3 10 mF Terminal Voltage Operating Range The CAT5171 VDD and GND power supply define the limits for proper 3-terminal digital potentiometer operation. Signals or potentials applied to terminals A, B or the wiper must remain inside the span of VDD and GND. Signals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes. + C1 0.1 mF CAT5171 GND Figure 14. Power Supply Bypassing VDD W, A, B CAT5171 LOGIC GND Figure 13. http://onsemi.com 8 CAT5171 I2C BUS PROTOCOL The following defines the features of the I2C bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. is hard-wired to the AD0 pin to establish the device’s address. After the Master sends a START condition and the slave address byte, the CAT5171 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. Acknowledge The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5171 will be considered a slave device in all applications. After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5171 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5171 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5171 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. START Condition The START condition precedes all commands to the device, and is defined as a high to low transition of SDA when SCL is high. The CAT5171 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A low to high transition of SDA when SCL is high determines the STOP condition. All operations must end with a STOP condition. Write Operation In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the wiper register. The CAT5171 acknowledges once more and the Master generates the STOP condition. Device Addressing The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The six most significant bits of the 8-bit slave address are fixed as 010110 for the CAT5171. The next bit (AD0) is the device least significant address bit and defines which device the Master is accessing. Up to two devices may be individually addressed by the system. Typically, +5 V (VDD) or ground tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH SDA OUT Figure 15. Bus Timing Diagram http://onsemi.com 9 tBUF CAT5171 SDA SCL START CONDITION STOP CONDITION Figure 16. Start/Stop Condition SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 17. Acknowledge Condition http://onsemi.com 10 CAT5171 INSTRUCTION AND REGISTER DESCRIPTION Slave Address Byte power-up, the wiper is set to midscale and may be repositioned anytime after the power has become stable. The first byte sent to the CAT5171 from the master/processor is called the Slave Address Byte. The most significant six bits of the slave address are a device type identifier. For the CAT5171, these bits are fixed at 010110. The next bit, AD0, is the first bit of the internal slave address and must match the physical device address which is defined by the state of the AD0 input pin for the CAT5171 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The AD0 input can be actively driven by CMOS input signals or tied to the supply voltage or ground. The next bit, R/W, indicates whether this command corresponds to a Write or Read instruction. To write into the Wiper control register, R/W bit is set to a logic low; while a read from the wiper register is done with the bit high. Instructions Write and Read instructions are respectively three and two bytes in length. The basic sequence of the two instructions is illustrated in Table 11 and 12. In write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is a don’t care. The second MSB, RS, is the midscale reset. A logic high on this bit moves the wiper to the center tap. The third MSB, SD, is a shutdown bit. A logic high causes an open circuit at terminal A, and short the wiper terminal W to terminal B. The “shutdown” operation does not change the contents of the wiper register. When the shutdown bit, SD, goes back to a logic low, the previous wiper position is restored. Also during shutdown, new settings can be programmed. As soon as the device is returned from shutdown, the wiper position is set according to the wiper register value. Wiper Control The CAT5171 contains one 8-bit Wiper Control Register (WCR). The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR may be written by the host via Write instruction. The Wiper Control Register is a volatile register that loses its contents when the CAT5171 is powered-down. Upon Two CAT5171 on a Single Bus When needed, it is possible to connect two CAT5171 potentiometers on the same I2C bus and be able to address each one independently. Each device can be set to a unique address by using the AD0 input pin. One device AD0 pin is connected to ground, and the other device AD0 pin is tied to the supply voltage. Table 11. Write S 0 1 0 1 1 0 AD0 W A X RS Slave Address Byte SD X X X X X A D7 D6 D5 Instruction Byte D4 D3 D2 D1 D0 D2 D1 D0 A P Data Byte SDA 0 1 S T A R T 0 1 1 0 AD0 X R/W RS SD D6 D7 X X X X X A C K D5 D4 D3 A S C T K O P A C K Instruction Byte Slave Address Byte Data Byte Table 12. READ S 0 1 0 1 1 0 AD0 R A D7 D6 D5 Slave Address Byte SDA S T A R T 0 1 0 1 1 0 D4 D3 D2 D1 D0 D2 D1 D0 A P N A C K S T O P Data Byte D7 AD0 R/W D6 D5 D4 D3 A C K Data Byte Slave Address Byte Legend W = Write (bit is 0 for Write instruction) RS = When the bit is 1, the wiper position is moved to mid-scale 0x80 SD = Shut Down: 0: normal operation 1: wiper is parked at B terminal and terminal A is open circuit. X = Don’t Care S = Start P = Stop A = Acknowledge AD0 = Address bit 0, needed when using two potentiometers on the same I2C bus. D = Data bit R = Read (bit is 1 for Read instruction) http://onsemi.com 11 CAT5171 PACKAGE DIMENSIONS SOT−23, 8 Lead CASE 527AK ISSUE A E1 e SYMBOL MIN A 0.90 A1 0.00 A2 0.90 A3 0.60 0.80 b 0.28 0.38 c 0.08 0.22 E b 1.45 0.15 1.10 1.30 2.90 BSC E 2.80 BSC E1 1.60 BSC 0.65 BSC L TOP VIEW MAX D e PIN #1 IDENTIFICATION NOM 0.45 0.30 L1 0.60 0.60 REF L2 0.25 REF θ 0° 8° D A2 A q A3 c L1 A1 SIDE VIEW L L2 END VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-178. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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