Maxim DS1822Z Econo 1-wire digital thermometer Datasheet

DS1822
Econo 1-Wire Digital
Thermometer
www.maxim-ic.com
PIN ASSIGNMENT
FEATURES
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ƒ
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DALLAS
1822
NC
1
NC
2
VDD
3
DQ
4
1 2 3
DS1822
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Unique 1-Wire interface requires only one
port pin for communication.
Each device has a unique 64-bit serial code
stored in an on-board ROM.
Multidrop capability simplifies distributed
temperature-sensing applications.
Requires no external components.
Can be powered from data line. Power supply
range is 3.0V to 5.5V.
Measures temperatures from -55°C to +125°C
(-67°F to +257°F).
±2.0°C accuracy from -10°C to +85°C.
Thermometer resolution is user-selectable
from 9 to 12 bits.
Converts temperature to 12-bit digital word in
750ms (max.)
User-definable nonvolatile (NV) alarm
settings.
Alarm search command identifies and
addresses devices whose temperature is
outside of programmed limits (temperature
alarm condition).
Software compatible with the DS18B20.
Applications include thermostatic controls,
industrial systems, consumer products,
thermometers, or any thermally sensitive
system.
8
NC
7
NC
6
NC
5
GND
8-Pin 150mil SO
(DS1822Z)
GND
DQ
VDD
ƒ
®
1 2
3
(BOTTOM VIEW)
TO-92
(DS1822)
PIN DESCRIPTION
GND
DQ
VDD
NC
- Ground
- Data In/Out
- Power Supply Voltage
- No Connect
DESCRIPTION
The DS1822 digital thermometer provides 9- to 12-bit centigrade temperature measurements and has an
alarm function with NV user-programmable upper and lower trigger points. The DS1822 communicates
over a 1-Wire bus that by definition requires only one data line (and ground) for communication with a
central microprocessor. It has an operating temperature range of –55°C to +125°C and is accurate to
±2.0°C over the range of –10°C to +85°C. In addition, the DS1822 can derive power directly from the
data line (“parasite power”), eliminating the need for an external power supply.
Each DS1822 has a unique 64-bit serial code, which allows multiple DS1822s to function on the 1-Wire
bus; thus, it is simple to use one microprocessor to control many DS1822s distributed over a large area.
Applications that can benefit from this feature include HVAC environmental controls, temperature
monitoring systems inside buildings, equipment or machinery, and process monitoring and control
systems.
1-Wire is a registered trademark of Dallas Semiconductor.
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101107
DS1822
ORDER INFORMATION
ORDERING
NUMBER
DS1822
DS1822/T&R
DS1822+
DS1822+T&R
PACKAGE
MARKING
1822
1822
1822 (See Note)
1822 (See Note)
DESCRIPTION
DS1822 in 3-pin TO92
DS1822 in 3-pin TO92, 2000 Piece Tape-and-Reel
DS1822 in Lead-Free 3-pin TO92
DS1822 in Lead-Free 3-pin TO92, 2000 Piece Tape-andReel
DS1822Z
DS1822
DS1822 in 150 mil 8-pin SO
DS1822Z/T&R
DS1822
DS1822 in 150 mil 8-pin SO, 2500 Piece Tape-and-Reel
DS1822Z+
DS1822 (See Note)
DS1822 in Lead-Free 150 mil 8-pin SO
DS1822Z+T&R
DS1822 (See Note)
DS1822 in Lead-Free 150 mil 8-pin SO, 2500 Piece
Tape-and-Reel
Note: A “+” symbol will also be marked on the package.
DETAILED PIN DESCRIPTIONS Table 1
8-PIN SO*
5
4
TO-92 SYMBOL DESCRIPTION
1
GND
Ground.
2
DQ
Data Input/Output pin. Open-drain 1-Wire interface pin. Also
provides power to the device when used in parasite power mode
(see “Parasite Power” section).
3
3
VDD
Optional VDD pin. VDD must be grounded for operation in
parasite power mode.
*All pins not specified in this table are “No Connect” pins.
OVERVIEW
Figure 1 shows a block diagram of the DS1822, and pin descriptions are given in Table 1. The 64-bit
ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte temperature
register that stores the digital output from the temperature sensor. In addition, the scratchpad provides
access to the 1-byte upper and lower alarm trigger registers (TH and TL), and the 1-byte configuration
register. The configuration register allows the user to set the resolution of the temperature-to-digital
conversion to 9, 10, 11, or 12 bits. The TH, TL and configuration registers are NV (EEPROM), so they will
retain data when the device is powered down.
The DS1822 uses Dallas’ exclusive 1-Wire bus protocol that implements bus communication using one
control signal. The control line requires a weak pullup resistor since all devices are linked to the bus via a
3-state or open-drain port (the DQ pin in the case of the DS1822). In this bus system, the microprocessor
(the master device) identifies and addresses devices on the bus using each device’s unique 64-bit code.
Because each device has a unique code, the number of devices that can be addressed on one bus is
virtually unlimited. The 1-Wire bus protocol, including detailed explanations of the commands and “time
slots,” is covered in the 1-WIRE BUS SYSTEM section of this data sheet.
Another feature of the DS1822 is the ability to operate without an external power supply. Power is instead
supplied through the 1-Wire pullup resistor via the DQ pin when the bus is high. The high bus signal also
charges an internal capacitor (CPP), which then supplies power to the device when the bus is low. This
method of deriving power from the 1-Wire bus is referred to as “parasite power.” As an alternative, the
DS1822 may also be powered by an external supply on VDD.
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DS1822
DS1822 BLOCK DIAGRAM Figure 1
VPU
PARASITE POWER
CIRCUIT
4.7K
MEMORY CONTROL
LOGIC
DS1822
DQ
TEMPERATURE SENSOR
INTERNAL VDD
GND
CPP
64-BIT ROM
AND
1-wire PORT
SCRATCHPAD
ALARM HIGH TRIGGER (TH)
REGISTER (EEPROM)
ALARM LOW TRIGGER (TL)
REGISTER (EEPROM)
VDD
CONFIGURATION REGISTER
(EEPROM)
POWER
SUPPLY
SENSE
8-BIT CRC GENERATOR
3 of 21
DS1822
OPERATION—MEASURING TEMPERATURE
The core functionality of the DS1822 is its direct-to-digital temperature sensor. The resolution of the
temperature sensor is user-configurable to 9, 10, 11, or 12 bits, corresponding to increments of 0.5°C,
0.25°C, 0.125°C, and 0.0625°C, respectively. The default resolution at power-up is 12 bit. The DS1822
powers-up in a low-power idle state; to initiate a temperature measurement and A-to-D conversion, the
master must issue a Convert T [44h] command. Following the conversion, the resulting thermal data is
stored in the 2-byte temperature register in the scratchpad memory and the DS1822 returns to its idle
state. If the DS1822 is powered by an external supply, the master can issue “read-time slots” (see the 1WIRE BUS SYSTEM section) after the Convert T command and the DS1822 will respond by
transmitting 0 while the temperature conversion is in progress and 1 when the conversion is done. If the
DS1822 is powered with parasite power, this notification technique cannot be used since the bus must be
pulled high by a strong pullup during the entire temperature conversion. The bus requirements for parasite
power are explained in detail in the POWERING THE DS1822 section of this data sheet.
The DS1822 output temperature data is calibrated in degrees centigrade; for Fahrenheit applications, a
lookup table or conversion routine must be used. The temperature data is stored as a 16-bit sign-extended
two’s complement number in the temperature register (see Figure 2). The sign bits (S) indicate if the
temperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. If the
DS1822 is configured for 12-bit resolution, all bits in the temperature register will contain valid data. For
11-bit resolution, bit 0 is undefined. For 10-bit resolution, bits 1 and 0 are undefined, and for 9-bit
resolution bits 2, 1 and 0 are undefined. Table 2 gives examples of digital output data and the
corresponding temperature reading for 12-bit resolution conversions.
TEMPERATURE REGISTER FORMAT Figure 2
bit 7
LS Byte
MS Byte
3
bit 6
2
bit 5
1
2
2
2
bit 15
bit 14
bit 13
S
S
S
bit 4
bit 3
0
-1
2
bit 12
2
bit 11
S
S
bit 2
-2
2
bit 10
2
6
TEMPERATURE/DATA RELATIONSHIP Table 2
TEMPERATURE
+125°C
+85°C*
+25.0625°C
+10.125°C
+0.5°C
0°C
-0.5°C
-10.125°C
-25.0625°C
-55°C
DIGITAL OUTPUT DIGITAL OUTPUT
(Binary)
(Hex)
0000 0111 1101 0000
07D0h
0000 0101 0101 0000
0550h
0000 0001 1001 0001
0191h
0000 0000 1010 0010
00A2h
0000 0000 0000 1000
0008h
0000 0000 0000 0000
0000h
1111 1111 1111 1000
FFF8h
1111 1111 0101 1110
FF5Eh
1111 1110 0110 1111
FE6Fh
1111 1100 1001 0000
FC90h
*The power on reset value of the temperature register is +85°C
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bit 1
-3
2
bit 9
2
5
bit 0
2-4
bit 8
24
DS1822
OPERATION—ALARM SIGNALING
After the DS1822 performs a temperature conversion, the temperature value is compared to the userdefined two’s complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure 3).
The sign bit (S) indicates if the value is positive or negative: for positive numbers S = 0 and for negative
numbers S = 1. The TH and TL registers are NV (EEPROM) so they will retain data when the device is
powered down. TH and TL can be accessed through bytes 2 and 3 of the scratchpad as explained in the
MEMORY section of this data sheet.
TH AND TL REGISTER FORMAT Figure 3
bit 7
S
bit 6
2
6
bit 5
2
5
bit 4
bit 3
4
3
2
2
bit 2
2
2
bit 1
2
1
bit 0
20
Only bits 11 through 4 of the temperature register are used in the TH and TL comparison since TH and TL
are 8-bit registers. If the measured temperature is lower than or equal to TL or higher than or equal to TH,
an alarm condition exists and an alarm flag is set inside the DS1822. This flag is updated after every
temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the
next temperature conversion.
The master device can check the alarm flag status of all DS1822s on the bus by issuing an Alarm Search
[ECh] command. Any DS1822s with a set alarm flag will respond to the command, so the master can
determine exactly which DS1822s have experienced an alarm condition. If an alarm condition exists and
the TH or TL settings have changed, another temperature conversion should be done to validate the alarm
condition.
POWERING THE DS1822
The DS1822 can be powered by an external supply on the VDD pin, or it can operate in “parasite power”
mode, which allows the DS1822 to function without a local external supply. Parasite power is very useful
for applications that require remote temperature sensing or that are very space constrained. Figure 1
shows the DS1822’s parasite-power control circuitry, which “steals” power from the 1-Wire bus via the
DQ pin when the bus is high. The stolen charge powers the DS1822 while the bus is high, and some of
the charge is stored on the parasite power capacitor (CPP) to provide power when the bus is low. When the
DS1822 is used in parasite power mode, the VDD pin must be connected to ground.
In parasite power mode, the 1-Wire bus and CPP can provide sufficient current to the DS1822 for most
operations as long as the specified timing and voltage requirements are met (refer to the DC
ELECTRICAL CHARACTERISTICS and the AC ELECTRICAL CHARACTERISTICS sections of this
data sheet). However, when the DS1822 is performing temperature conversions or copying data from the
scratchpad memory to EEPROM, the operating current can be as high as 1.5mA. This current can cause
an unacceptable voltage drop across the weak 1-Wire pullup resistor and is more current than can be
supplied by CPP. To assure that the DS1822 has sufficient supply current, it is necessary to provide a
strong pullup on the 1-Wire bus whenever temperature conversions are taking place or data is being
copied from the scratchpad to EEPROM. This can be accomplished by using a MOSFET to pull the bus
directly to the rail as shown in Figure 4. The 1-Wire bus must be switched to the strong pullup within
10μs (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus must be
held high by the pullup for the duration of the conversion (tconv) or data transfer (twr = 10ms). No other
activity can take place on the 1-Wire bus while the pullup is enabled.
The DS1822 can also be powered by the conventional method of connecting an external power supply to
the VDD pin, as shown in Figure 5. The advantage of this method is that the MOSFET pullup is not
required, and the 1-Wire bus is free to carry other traffic during the temperature conversion time.
5 of 21
DS1822
The use of parasite power is not recommended for temperatures above 100°C since the DS1822 may not
be able to sustain communications due to the higher leakage currents that can exist at these temperatures.
For applications in which such temperatures are likely, it is strongly recommended that the DS1822 be
powered by an external power supply.
In some situations the bus master may not know whether the DS1822s on the bus are parasite powered or
powered by external supplies. The master needs this information to determine if the strong bus pullup
should be used during temperature conversions. To get this information, the master can issue a Skip ROM
[CCh] command followed by a Read Power Supply [B4h] command followed by a “read-time slot”.
During the read time slot, parasite powered DS1822s will pull the bus low, and externally powered
DS1822s will let the bus remain high. If the bus is pulled low, the master knows that it must supply the
strong pullup on the 1-Wire bus during temperature conversions.
SUPPLYING THE PARASITE-POWERED DS1822 DURING TEMPERATURE
CONVERSIONS Figure 4
VPU
DS1822
Microprocessor
GND DQ VDD
VPU
4.7k
To Other
1-Wire Devices
1-Wire Bus
POWERING THE DS1822 WITH AN EXTERNAL SUPPLY Figure 5
DS1822
VPU
Microprocessor
VDD (External Supply)
GND DQ VDD
4.7k
To Other
1-Wire Devices
1-Wire Bus
64-BIT LASERED ROM CODE
Each DS1822 contains a unique 64–bit code (see Figure 6) stored in ROM. The least significant 8 bits of
the ROM code contain the DS1822’s 1-Wire family code: 22h. The next 48 bits contain a unique serial
number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated from
the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in the CRC
GENERATION section. The 64-bit ROM code and associated ROM function control logic allow the
DS1822 to operate as a 1-Wire device using the protocol detailed in the 1-WIRE BUS SYSTEM section
of this data sheet.
64-BIT LASERED ROM CODE Figure 6
8-BIT CRC
MSB
48-BIT SERIAL NUMBER
LSB
MSB
LSB
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8-BIT FAMILY CODE (22h)
MSB
LSB
DS1822
MEMORY
The DS1822’s memory is organized as shown in Figure 7. The memory consists of an SRAM scratchpad
with NV EEPROM storage for the high and low alarm trigger registers (TH and TL) and configuration
register. Note that if the DS1822 alarm function is not used, the TH and TL registers can serve as generalpurpose memory. All memory commands are described in detail in the DS1822 FUNCTION
COMMANDS section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Byte 4
contains the configuration register data, which is explained in detail in the CONFIGURATION
REGISTER section of this data sheet. Bytes 5, 6, and 7 are reserved for internal use by the device and
cannot be overwritten.
Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0
through 7 of the scratchpad. The DS1822 generates this CRC using the method described in the CRC
GENERATION section.
Data is written to bytes 2, 3, and 4 of the scratchpad using the Write Scratchpad [4Eh] command; the data
must be transmitted to the DS1822 starting with the least significant bit of byte 2. To verify data integrity,
the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is written. When
reading the scratchpad, data is transferred over the 1-Wire bus starting with the least significant bit of
byte 0. To transfer the TH, TL and configuration data from the scratchpad to EEPROM, the master must
issue the Copy Scratchpad [48h] command.
Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM
data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM to
2
the scratchpad at any time using the Recall E [B8h] command. The master can issue read time slots
following the Recall E2 command and the DS1822 will indicate the status of the recall by transmitting 0
while the recall is in progress and 1 when the recall is done.
DS1822 MEMORY MAP Figure 7
SCRATCHPAD (Power-up State)
byte 0 Temperature LSB (50h)
byte 1 Temperature MSB (05h)
(85°C)
EEPROM
byte 2 TH Register or User Byte 1*
TH Register or User Byte 1
byte 3 TL Register or User Byte 2*
TL Register or User Byte 2
byte 4 Configuration Register*
Configuration Register
byte 5 Reserved (FFh)
byte 6 Reserved
byte 7 Reserved (10h)
byte 8 CRC*
*Power-up state depends on value(s) stored
in EEPROM
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DS1822
CONFIGURATION REGISTER
Byte 4 of the scratchpad memory contains the configuration register, which is organized as
illustrated in Figure 8. The user can set the conversion resolution of the DS1822 using the R0 and R1
bits in this register as shown in Table 3. The power-up default of these bits is R0 = 1 and R1 = 1 (12-bit
resolution). Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits 0–4
in the configuration register are reserved for internal use by the device and cannot be overwritten.
CONFIGURATION REGISTER Figure 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
R1
R0
1
1
1
1
1
THERMOMETER RESOLUTION CONFIGURATION Table 3
R1
0
0
1
1
R0
0
1
0
1
Resolution
9-bit
10-bit
11-bit
12-bit
Max Conversion Time
93.75ms
(tCONV/8)
187.5ms
(tCONV/4)
375ms
(tCONV/2)
750ms
(tCONV)
CRC GENERATION
CRC bytes are provided as part of the DS1822’s 64-bit ROM code and in the 9th byte of the scratchpad
memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in the
most significant byte of the ROM. The scratchpad CRC is calculated from the data stored in the
scratchpad, and therefore it changes when the data in the scratchpad changes. The CRCs provide the bus
master with a method of data validation when data is read from the DS1822. To verify that data has been
read correctly, the bus master must recalculate the CRC from the received data and then compare this
value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for scratchpad reads). If
the calculated CRC matches the read CRC, the data has been received error free. The comparison of CRC
values and the decision to continue with an operation are determined entirely by the bus master. There is
no circuitry inside the DS1822 that prevents a command sequence from proceeding if the DS1822 CRC
(ROM or scratchpad) does not match the value generated by the bus master.
The equivalent polynomial function of the CRC (ROM or scratchpad) is:
CRC = X8 + X5 + X4 + 1
The bus master can recalculate the CRC and compare it to the CRC values from the DS1822 using the
polynomial generator shown in Figure 9. This circuit consists of a shift register and XOR gates, and the
shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the least
significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After
shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the
polynomial generator will contain the recalculated CRC. Next, the 8-bit ROM code or scratchpad CRC
from the DS1822 must be shifted into the circuit. At this point, if the recalculated CRC was correct, the
shift register will contain all 0s. Additional information about the Dallas 1-Wire cyclic redundancy check
8 of 21
DS1822
is available in Application Note 27 entitled Understanding and Using Cyclic Redundancy Checks with
Dallas Semiconductor Touch Memory Products.
CRC GENERATOR Figure 9
INPUT
XOR
XOR
XOR
(MSB)
(LSB)
1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS1822 is
always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”
system; the system is “multidrop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the
data line via an open drain or 3-state port. This allows each device to “release” the data line when the
device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the
DS1822 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 10.
The 1-Wire bus requires an external pullup resistor of approximately 5 kΩ; thus, the idle state for the 1Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480μs,
all components on the bus will be reset.
HARDWARE CONFIGURATION Figure 10
VPU
DS1822 1-WIRE PORT
4.7k
RX
1-wire Bus
DQ
Pin
RX
5μA
Typ.
TX
100Ω
MOSFET
TX
RX = RECEIVE
TX = TRANSMIT
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DS1822
TRANSACTION SEQUENCE
The transaction sequence for accessing the DS1822 is as follows:
Step 1. Initialization
Step 2. ROM Command (followed by any required data exchange)
Step 3. DS1822 Function Command (followed by any required data exchange)
It is very important to follow this sequence every time the DS1822 is accessed, as the DS1822 will not
respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search
ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM commands, the
master must return to Step 1 in the sequence.
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that slave devices (such as the DS1822) are on the
bus and are ready to operate. Timing for the reset and presence pulses is detailed in the
1-WIRE SIGNALING section.
ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM command. These commands
operate on the unique 64–bit ROM codes of each slave device and allow the master to single out a
specific device if many are present on the 1-Wire bus. These commands also allow the master to
determine how many and what types of devices are present on the bus or if any device has experienced an
alarm condition. There are five ROM commands, and each command is 8 bits long. The master device
must issue an appropriate ROM command before issuing a DS1822 function command. A flowchart for
operation of the ROM commands is shown in Figure 11.
SEARCH ROM [F0h]
When a system is initially powered up, the master must identify the ROM codes of all slave devices on
the bus, which allows the master to determine the number of slaves and their device types. The master
learns the ROM codes through a process of elimination that requires the master to perform a Search ROM
cycle (i.e., Search ROM command followed by data exchange) as many times as necessary to identify all
of the slave devices. If there is only one slave on the bus, the simpler Read ROM command (see below)
can be used in place of the Search ROM process. For a detailed explanation of the Search ROM
procedure, refer to the iButton Book of Standards at www.ibutton.com/ibuttons/standard.pdf. After every
Search ROM cycle, the bus master must return to Step 1 (Initialization) in the transaction sequence.
READ ROM [33h]
This command can only be used when there is one slave on the bus. It allows the bus master to read the
slave’s 64-bit ROM code without using the Search ROM procedure. If this command is used when there
is more than one slave present on the bus, a data collision will occur when all the slaves attempt to
respond at the same time.
MATCH ROM [55h]
The match ROM command followed by a 64-bit ROM code sequence allows the bus master to address a
specific slave device on a multidrop or single-drop bus. Only the slave that exactly matches the 64-bit
ROM code sequence will respond to the function command issued by the master; all other slaves on the
bus will wait for a reset pulse.
10 of 21
DS1822
SKIP ROM [CCh]
The master can use this command to address all devices on the bus simultaneously without sending out
any ROM code information. For example, the master can make all DS1822s on the bus perform
simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [44h]
command.
Note that the Read Scratchpad [BEh] command can follow the Skip ROM command only if there is a
single slave device on the bus. In this case time is saved by allowing the master to read from the slave
without sending the device’s 64-bit ROM code. A Skip ROM command followed by a Read Scratchpad
command will cause a data collision on the bus if there is more than one slave since multiple devices will
attempt to transmit data simultaneously.
ALARM SEARCH [ECh]
The operation of this command is identical to the operation of the Search ROM command except that
only slaves with a set alarm flag will respond. This command allows the master device to determine if
any DS1822s experienced an alarm condition during the most recent temperature conversion. After every
Alarm Search cycle (i.e., Alarm Search command followed by data exchange), the bus master must return
to Step 1 (Initialization) in the transaction sequence. Refer to the OPERATION—ALARM SIGNALING
section for an explanation of alarm flag operation.
DS1822 FUNCTION COMMANDS
After the bus master has used a ROM command to address the DS1822 with which it wishes to
communicate, the master can issue one of the DS1822 function commands. These commands allow the
master to write to and read from the DS1822’s scratchpad memory, initiate temperature conversions and
determine the power supply mode. The DS1822 function commands, which are described below, are
summarized in Table 4 and illustrated by the flowchart in Figure 12.
CONVERT T [44h]
This command initiates a single temperature conversion. Following the conversion, the resulting thermal
data is stored in the 2-byte temperature register in the scratchpad memory and the DS1822 returns to its
low-power idle state. If the device is being used in parasite power mode, within 10μs (max) after this
command is issued the master must enable a strong pullup on the 1-Wire bus for the duration of the
conversion (tconv) as described in the POWERING THE DS1822 section. If the DS1822 is powered by an
external supply, the master can issue read time slots after the Convert T command and the DS1822 will
respond by transmitting 0 while the temperature conversion is in progress and 1 when the conversion is
done. In parasite power mode this notification technique cannot be used since the bus is pulled high by
the strong pullup during the conversion.
WRITE SCRATCHPAD [4Eh]
This command allows the master to write three bytes of data to the DS1822’s scratchpad. The first data
byte is written into the TH register (byte 2 of the scratchpad), the second byte is written into the TL
register (byte 3), and the third byte is written into the configuration register (byte 4). Data must be
transmitted least significant bit first. All three bytes MUST be written before the master issues a reset, or
the data may be corrupted.
READ SCRATCHPAD [BEh]
This command allows the master to read the contents of the scratchpad. The data transfer starts with the
least significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8–CRC) is read.
The master may issue a reset to terminate reading at any time if only part of the scratchpad data is needed.
COPY SCRATCHPAD [48h]
This command copies the contents of the scratchpad TH, TL and configuration registers (bytes 2, 3, and 4)
to EEPROM. If the device is being used in parasite power mode, within 10μs (max) after this command is
11 of 21
DS1822
issued the master must enable a strong pullup on the 1-Wire bus for at least 10ms as described in the
POWERING THE DS1822 section.
RECALL E2 [B8h]
This command recalls the alarm trigger values (TH and TL) and configuration data from EEPROM and
places the data in bytes 2, 3, and 4, respectively, in the scratchpad memory. The master device can issue
read time slots following the Recall E2 command and the DS1822 will indicate the status of the recall by
transmitting 0 while the recall is in progress and 1 when the recall is done. The recall operation happens
automatically at power-up, so valid data is available in the scratchpad as soon as power is applied to the
device.
READ POWER SUPPLY [B4h]
The master device issues this command followed by a read time slot to determine if any DS1822s on the
bus are using parasite power. During the read time slot, parasite powered DS1822s will pull the bus low,
and externally powered DS1822s will let the bus remain high. Refer to the POWERING THE DS1822
section for usage information for this command.
DS1822 FUNCTION COMMAND SET Table 4
1-Wire Bus Activity
Description
Protocol
After Command is Issued
TEMPERATURE CONVERSION COMMANDS
Convert T
Initiates temperature
44h
DS1822 transmits conversion
conversion.
status to master (not applicable
for parasite-powered DS1822s).
MEMORY COMMANDS
Read Scratchpad Reads the entire scratchpad
BEh
DS1822 transmits up to 9 data
including the CRC byte.
bytes to master.
Write Scratchpad Writes data into scratchpad
4Eh
Master transmits 3 data bytes to
bytes 2, 3, and 4 (TH, TL,
DS1822.
and configuration registers).
Copy Scratchpad Copies TH, TL, and
48h
None
configuration register data
from the scratchpad to
EEPROM.
2
Recalls TH, TL, and
B8h
DS1822 transmits recall status to
Recall E
configuration register data
master.
from EEPROM to the
scratchpad.
Read Power
Signals DS1822 power
B4h
DS1822 transmits supply status
Supply
supply mode to the master.
to master.
Command
Notes
1
2
3
1
NOTES:
1. For parasite-powered DS1822s, the master must enable a strong pullup on the 1-Wire bus during
temperature conversions and copies from the scratchpad to EEPROM. No other bus activity may take
place during this time.
2.
The master can interrupt the transmission of data at any time by issuing a reset.
3.
All three bytes must be written before a reset is issued.
12 of 21
DS1822
ROM COMMANDS FLOW CHART Figure 11
Initialization
Sequence
MASTER TX
RESET PULSE
DS1822 TX
PRESENCE
PULSE
MASTER TX ROM
COMMAND
33h
READ ROM
COMMAND
Y
N
55h
MATCH ROM
COMMAND
F0h
SEARCH ROM
COMMAND
N
Y
Y
N
ECh
ALARM SEARCH
COMMAND
CCh
SKIP ROM
COMMAND
N
Y
Y
MASTER TX
BIT 0
DS1822 TX BIT 0
DS1822 TX BIT 0
DS1822 TX BIT 0
DS1822 TX BIT 0
MASTER TX BIT 0
MASTER TX BIT 0
BIT 0
MATCH?
DEVICE(S)
WITH ALARM
FLAG SET?
DS1822 TX
FAMILY CODE
1 BYTE
N
BIT 0
MATCH?
DS1822 TX
SERIAL NUMBER
6 BYTES
N
Y
Y
Y
DS1822 TX BIT 1
DS1822 TX
CRC BYTE
MASTER TX
BIT 1
DS1822 TX BIT 1
MASTER TX BIT 1
N
N
BIT 1
MATCH?
BIT 1
MATCH?
Y
Y
DS1822 TX BIT 63
MASTER TX
BIT 63
DS1822 TX BIT 63
MASTER TX BIT 63
N
BIT 63
MATCH?
Y
N
BIT 63
MATCH?
Y
MASTER TX
FUNCTION
COMMAND
(FIGURE 12)
13 of 21
N
N
DS1822
DS1822 FUNCTION COMMANDS FLOW CHART Figure 12
44h
CONVERT
TEMPERATURE
?
MASTER TX
FUNCTION
COMMAND
48h
COPY
SCRATCHPAD
?
N
Y
Y
N
PARASITE
POWER
?
DS1822 BEGINS
CONVERSION
Y
N
DATA COPIED FROM
SCRATCHPAD TO EEPROM
B4h
READ
POWER SUPPLY
?
PARASITE
POWERED
?
N
MASTER DISABLES
STRONG PULLUP
Y
MASTER
RX “0s”
MASTER
RX “1s”
N
B8h
RECALL E2
?
MASTER
RX “1s”
BEh
READ
SCRATCHPAD
?
N
Y
Y
N
COPY IN
PROGRESS
?
MASTER DISABLES
STRONG PULLUP
MASTER
RX “0s”
Y
MASTER ENABLES
STRONG PULL-UP ON DQ
N
Y
N
PARASITE
POWER
?
MASTER ENABLES
STRONG PULLUP ON DQ
DS1822 CONVERTS
TEMPERATURE
DEVICE
CONVERTING
TEMPERATURE
?
N
N
Y
Y
MASTER TX TH BYTE
TO SCRATCHPAD
MASTER RX DATA BYTE
FROM SCRATCHPAD
Y
MASTER BEGINS DATA
2
RECALL FROM E PROM
4Eh
WRITE
SCRATCHPAD
?
MASTER TX TL BYTE
TO SCRATCHPAD
MASTER
RX “1s”
MASTER
RX “0s”
MASTER
TX RESET
?
DEVICE
BUSY RECALLING
DATA
?
N
N
N
Y
MASTER
RX “0s”
Y
MASTER
RX “1s”
HAVE 8 BYTES
BEEN READ
?
Y
MASTER RX SCRATCHPAD
CRC BYTE
RETURN TO INITIALIZATION
SEQUENCE (FIGURE 11) FOR
NEXT TRANSACTION
14 of 21
MASTER TX CONFIG. BYTE
TO SCRATCHPAD
DS1822
1-WIRE SIGNALING
The DS1822 uses a strict 1-Wire communication protocol to insure data integrity. Several signal types are
defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these
signals, with the exception of the presence pulse, are initiated by the bus master.
INITIALIZATION PROCEDURE: RESET AND PRESENCE PULSES
All communication with the DS1822 begins with an initialization sequence that consists of a reset pulse
from the master followed by a presence pulse from the DS1822. This is illustrated in Figure 13. When the
DS1822 sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus
and ready to operate.
During the initialization sequence the bus master transmits (TX) the reset pulse by pulling the 1-Wire bus
low for a minimum of 480μs. The bus master then releases the bus and goes into receive mode (RX).
When the bus is released, the 5k pullup resistor pulls the 1-Wire bus high. When the DS1822 detects this
rising edge, it waits 15μs to 60μs and then transmits a presence pulse by pulling the 1-Wire bus low for
60μs to 240μs.
INITIALIZATION TIMING Figure 13
MASTER TX RESET PULSE
MASTER RX
480μs minimum
DS1822 TX
presence pulse
60-240μs
480μs minimum
VPU
DS1822
waits 15-60μs
1-WIRE BUS
GND
LINE TYPE LEGEND
Bus master pulling low
DS1822 pulling low
Resistor pullup
READ/WRITE TIME SLOTS
The bus master writes data to the DS1822 during write time slots and reads data from the DS1822 during
read time slots. One bit of data is transmitted over the 1-Wire bus per time slot.
WRITE TIME SLOTS
There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master
uses a Write 1 time slot to write a logic 1 to the DS1822 and a Write 0 time slot to write a logic 0 to the
DS1822. All write time slots must be a minimum of 60μs in duration with a minimum of a 1μs recovery
time between individual write slots. Both types of write time slots are initiated by the master pulling the
1-Wire bus low (see Figure 14).
To generate a Write 1 time slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wire
bus within 15μs. When the bus is released, the 5k pullup resistor will pull the bus high. To generate a
Write 0 time slot, after pulling the 1-Wire bus low, the bus master must continue to hold the bus low for
the duration of the time slot (at least 60μs).
15 of 21
DS1822
The DS1822 samples the 1-Wire bus during a window that lasts from 15μs to 60μs after the master
initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the DS1822.
If the line is low, a 0 is written to the DS1822.
READ/WRITE TIME SLOT TIMING DIAGRAM Figure 14
START
OF SLOT
START
OF SLOT
MASTER WRITE “0” SLOT
MASTER WRITE “1” SLOT
1μs < TREC < ∞
60μs < TX “0” < 120μs
> 1μs
VPU
1-WIRE BUS
GND
DS1822 Samples
MIN
15μs
TYP
DS1822 Samples
MAX
15μs
MIN
15μs
30μs
MASTER READ “0” SLOT
TYP
MAX
15μs
30μs
MASTER READ “1” SLOT
1μs < TREC < ∞
VPU
1-WIRE BUS
GND
> 1 μs
Master samples
Master samples
> 1μs
15μs
45μs
15μs
LINE TYPE LEGEND
Bus master pulling low
DS1822 pulling low
Resistor pullup
READ TIME SLOTS
The DS1822 can only transmit data to the master when the master issues read time slots. Therefore, the
master must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power
Supply [B4h] command, so that the DS1822 can provide the requested data. In addition, the master can
generate read time slots after issuing Convert T [44h] or Recall E2 [B8h] commands to find out the status
of the operation as explained in the DS1822 FUNCTION COMMAND section.
All read time slots must be a minimum of 60μs in duration with a minimum of a 1μs recovery time
between slots. A read time slot is initiated by the master device pulling the 1-Wire bus low for a
minimum of 1μs and then releasing the bus (see Figure 14). After the master initiates the read time slot,
the DS1822 will begin transmitting a 1 or 0 on bus. The DS1822 transmits a 1 by leaving the bus high
and transmits a 0 by pulling the bus low. When transmitting a 0, the DS1822 will release the bus by the
end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output
16 of 21
DS1822
data from the DS1822 is valid for 15μs after the falling edge that initiated the read time slot. Therefore,
the master must release the bus and then sample the bus state within 15μs from the start of the slot.
Figure 15 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15μs for a read time slot.
Figure 16 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by locating the master sample time during read time slots towards the end of the 15μs period.
DETAILED MASTER READ 1 TIMING Figure 15
VPU
VIH of Master
1-WIRE BUS
GND
TINT > 1μs
TRC
Master samples
15μs
RECOMMENDED MASTER READ 1 TIMING Figure 16
VPU
VIH of Master
1-WIRE BUS
GND
Master samples
TINT = TRC =
small small
15 μs
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
RELATED APPLICATION NOTES
The following Application Notes can be applied to the DS1822. These notes can be obtained from the
Dallas Semiconductor “Application Note Book,” via the Dallas website at http://www.dalsemi.com/, or
through our faxback service at (214) 450–0441.
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor
Touch Memory Product
Application Note 55: Extending the Contact Range of Touch Memories
Application Note 74: Reading and Writing Touch Memories via Serial Interfaces
Application Note 104: Minimalist Temperature Control Demo
Application Note 106: Complex MicroLANs
Application Note 108: MicroLAN—In the Long Run
Application Note 162: Interfacing the DS18X20/DS1822 1-Wire Temperature Sensor in a
Microcontroller Environment
Sample 1-Wire subroutines that can be used in conjunction with AN74 can be downloaded from the
Dallas website or anonymous FTP Site.
17 of 21
DS1822
DS1822 OPERATION EXAMPLE 1
In this example there are multiple DS1822s on the bus and they are using parasite power. The bus master
initiates a temperature conversion in a specific DS1822 and then reads its scratchpad and recalculates the
CRC to verify the data.
MASTER MODE
TX
RX
TX
TX
TX
TX
TX
RX
TX
TX
TX
RX
DATA (LSB FIRST)
Reset
Presence
55h
64-bit ROM code
44h
DQ line held high by
strong pullup
Reset
Presence
55h
64-bit ROM code
BEh
9 data bytes
COMMENTS
Master issues reset pulse.
DS1822s respond with presence pulse.
Master issues Match ROM command.
Master sends DS1822 ROM code.
Master issues Convert T command.
Master applies strong pullup to DQ for the duration of the
conversion (tconv).
Master issues reset pulse.
DS1822s respond with presence pulse.
Master issues Match ROM command.
Master sends DS1822 ROM code.
Master issues Read Scratchpad command.
Master reads entire scratchpad including CRC. The master
then recalculates the CRC of the first eight data bytes from the
scratchpad and compares the calculated CRC with the read
CRC (byte 9). If they match, the master continues; if not, the
read operation is repeated.
DS1822 OPERATION EXAMPLE 2
In this example there is only one DS1822 on the bus and it is using parasite power. The master writes to
the TH, TL, and configuration registers in the DS1822 scratchpad and then reads the scratchpad and
recalculates the CRC to verify the data. The master then copies the scratchpad contents to EEPROM.
MASTER MODE
TX
RX
TX
TX
TX
TX
RX
TX
TX
RX
DATA (LSB FIRST)
Reset
Presence
CCh
4Eh
3 data bytes
Reset
Presence
CCh
BEh
9 data bytes
TX
RX
TX
TX
TX
Reset
Presence
CCh
48h
DQ line held high by
strong pullup
COMMENTS
Master issues reset pulse.
DS1822 responds with presence pulse.
Master issues Skip ROM command.
Master issues Write Scratchpad command.
Master sends three data bytes to scratchpad (TH, TL, and config).
Master issues reset pulse.
DS1822 responds with presence pulse.
Master issues Skip ROM command.
Master issues Read Scratchpad command.
Master reads entire scratchpad including CRC. The master then
recalculates the CRC of the first eight data bytes from the
scratchpad and compares the calculated CRC with the read CRC
(byte 9). If they match, the master continues; if not, the read
operation is repeated.
Master issues reset pulse.
DS1822 responds with presence pulse.
Master issues Skip ROM command.
Master issues Copy Scratchpad command.
Master applies strong pullup to DQ for at least 10ms while copy
operation is in progress.
18 of 21
DS1822
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Storage Temperature Range
Solder Dip Temperature
Reflow Oven Temperature
-0.5V to +6.0V
-55°C to +125°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A Specification
+220°C
*These are stress ratings only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Pullup Supply
Voltage
Thermometer Error
Input Logic Low
Input Logic High
Sink Current
Standby Current
Active Current
DQ Input Current
Drift
SYMBOL
VDD
VPU
tERR
VIL
VIH
CONDITION
Local Power
Parasite Power
Local Power
-10°C to
+85°C
-55°C to
+125°C
(-55°C to +125°C; VDD = 3.0V to 5.5V)
MIN
+3.0
+3.0
+3.0
TYP
MAX
+5.5
+5.5
VDD
±2
UNITS NOTES
V
1
V
1, 2
°C
3
V
V
1, 4, 5
1, 6
mA
nA
mA
µA
°C
1
7, 8
9
10
11
±3
Local Power
-0.3
+2.2
Parasite Power
+3.0
IL
VI/O=0.4V
4.0
IDDS
IDD
IDQ
VDD=5V
+0.8
The lower of
5.5
or
VDD + 0.3
750
1
5
±0.2
1000
1.5
NOTES:
1.
2.
All voltages are referenced to ground.
The Pullup Supply Voltage specification assumes that the pullup device is ideal, and therefore the
high level of the pullup is equal to VPU. In order to meet the VIH spec of the DS1822, the actual
supply rail for the strong pullup transistor must include margin for the voltage drop across the
transistor when it is turned on; thus: VPU_ACTUAL = VPU_IDEAL + VTRANSISTOR.
3. See typical performance curve in Figure 17.
4. Logic low voltages are specified at a sink current of 4mA.
5. To guarantee a presence pulse under low voltage parasite power conditions, VILMAX may have to be
reduced to as low as 0.5V.
6. Logic high voltages are specified at a source current of 1mA.
7. Standby current specified up to +70°C. Standby current typically is 3μA at +125°C.
8. To minimize IDDS, DQ should be within the following ranges: GND ≤ DQ ≤ GND + 0.3V or VDD 0.3V ≤ DQ ≤ VDD.
9. Active current refers to supply current during active temperature conversions or EEPROM writes.
10. DQ line is high (high-Z state).
11. Drift data is based on a 1000 hour stress test at +125°C with VDD = 5.5V.
19 of 21
DS1822
AC ELECTRICAL CHARACTERISTICS: NV MEMORY
(-55°C to +100°C; VDD = 3.0V to 5.5V)
PARAMETER
NV Write Cycle Time
EEPROM Writes
EEPROM Data Retention
SYMBOL
twr
NEEWR
tEEDR
CONDITION
MIN
-55°C to +55°C
-55°C to +55°C
50k
10
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Temperature Conversion
Time
SYMBOL
tCONV
Time to Strong Pullup On
tSPON
Time Slot
Recovery Time
Write 0 Low Time
Write 1 Low Time
Read Data Valid
Reset Time High
Reset Time Low
Presence Detect High
Presence Detect Low
Capacitance
tSLOT
tREC
rLOW0
tLOW1
tRDV
tRSTH
tRSTL
tPDHIGH
tPDLOW
CIN/OUT
TYP
2
MAX
10
UNITS
ms
writes
years
(-55°C to +125°C; VDD = 3.0V to 5.5V)
CONDITION MIN TYP MAX
9-bit resolution
93.75
10-bit resolution
187.5
11-bit resolution
375
12-bit resolution
750
Start Convert T
10
Command Issued
60
120
1
60
120
1
15
15
480
480
15
60
60
240
25
UNITS
ms
ms
ms
ms
µs
NOTES
1
1
1
1
µs
µs
µs
µs
µs
µs
µs
µs
µs
pF
1
1
1
1
1
1
1,2
1
1
NOTES:
1.
2.
Refer to timing diagrams in Figure 18.
Under parasite power, if tRSTL > 960μs, a power on reset may occur.
TYPICAL PERFORMANCE CURVE Figure 17
DS1822 Typical Performance Curve
0.8
Thermometer Error (°C)
0.6
+3s Error
0.4
0.2
0
Mean Error
-0.2
-0.4
-0.6
-3s Error
-0.8
-1
-1.2
-10
0
10
20
30
40
Temperature (°C)
20 of 21
50
60
70
80
DS1822
TIMING DIAGRAMS Figure 18
21 of 21