a
FEATURES
8-Bit Dual Transmit DAC
125 MSPS Update Rate
Excellent SFDR to Nyquist @ 5 MHz Output = 66 dBc
Excellent Gain and Offset Matching: 0.1%
Fully Independent or Single Resistor Gain Control
Dual Port or Interleaved Data
On-Chip 1.2 V Reference
Single 5 V or 3 V Supply Operation
Power Dissipation: 380 mW @ 5 V
Power-Down Mode: 50 mW @ 5 V
48-Lead LQFP
APPLICATIONS
Communications
Basestations
Digital Synthesis
Quadrature Modulation
3D Ultrasound
PRODUCT DESCRIPTION
The AD9709 is a dual-port, high-speed, two-channel, 8-bit
CMOS DAC. It integrates two high-quality 8-bit TxDAC+
cores, a voltage reference, and digital interface circuitry into a
small 48-lead LQFP package. The AD9709 offers exceptional
ac and dc performance while supporting update rates up to
125 MSPS.
The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of
two double-buffered latches as well as control logic. Separate
write inputs allow data to be written to the two DAC ports
independent of one another. Separate clocks control the update
rate of the DACs.
A mode control pin allows the AD9709 to interface to two separate data ports, or to a single interleaved high-speed data port.
In interleaving mode, the input data stream is demuxed into
its original I and Q data and then latched. The I and Q data
is then converted by the two DACs and updated at half the
input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be
set independently using two external resistors, or IOUTFS for
both DACs can be set using a single external resistor.
8-Bit, 125 MSPS
Dual TxDAC+® D/A Converter
AD9709*
FUNCTIONAL BLOCK DIAGRAM
DVDD
DCOM
WRT2
ACOM
“1”
LATCH
PORT1
WRT1
AVDD
DIGITAL
INTERFACE
“1”
DAC
MODE
IOUTA1
IOUTB1
REFERENCE
REFIO
FSADJ1
FSADJ2
GAINCTRL
BIAS
GENERATOR
SLEEP
“2”
DAC
IOUTA2
AD9709
“2”
LATCH
PORT2
CLK1
IOUTB2
CLK2
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output thus supporting single-ended
or differential applications. Both DACs can be simultaneously
updated and provide a nominal full-scale current of 20 mA.
The full-scale currents between each DAC are matched to
within 0.1%.
The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.0 V to 5.0 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9709 is a member of a pin-compatible family of dual
TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
2. Dual 8-Bit, 125 MSPS DACs: A pair of high-performance
DACs optimized for low-distortion performance provide for
flexible transmission of I and Q information.
3. Matching: Gain matching is typically 0.1% of full-scale, and
offset error is better than 0.02%.
4. Low Power: Complete CMOS Dual DAC function operates
on 380 mW from a 3.0 V to 5.0 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low-power idle periods.
5. On-Chip Voltage Reference: The AD9709 includes a 1.20 V
temperature-compensated bandgap voltage reference.
TxDAC+ is a registered trademark of Analog Devices, Inc.
*Patent pending.
6. Dual 8-Bit Inputs: The AD9709 features a flexible dual-port
interface allowing dual or interleaved input data.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD9709–SPECIFICATIONS
DC SPECIFICATIONS (T
MIN
to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
Min
RESOLUTION
Typ
Max
8
Unit
Bits
1
DC ACCURACY
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Gain Match
TA = 25°C
TMIN to TMAX
TMIN to TMAX
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth
–0.5
–0.5
± 0.1
± 0.1
+0.5
+0.5
LSB
LSB
–0.02
–2
–5
± 0.25
±1
+0.02
+2
+5
% of FSR
% of FSR
% of FSR
+0.3
+1.6
+0.14
20.0
+1.25
% of FSR
% of FSR
dB
mA
V
kΩ
pF
1.26
V
nA
1.25
1
0.5
V
MΩ
MHz
0
± 50
± 100
± 50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
–0.3
–1.6
–0.14
2.0
–1.0
100
5
1.14
OPERATING RANGE
1.20
100
0.1
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)4
Digital Supply Current (IDVDD)5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio7—AVDD
Power Supply Rejection Ratio7—DVDD
± 0.1
3
2.7
5
5
71
5
–0.4
–0.025
+0.4
+0.025
V
V
mA
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
–40
+85
°C
8
380
420
450
5.5
5.5
75
7
15
12
410
450
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I OUTFS, is 32 times the IREF current.
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.
5
Measured at fCLOCK = 100 MSPS and f OUT = 1 MHz.
6
Measured as unbuffered voltage output with I OUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and f OUT = 40 MHz.
7
± 10% power supply variation.
Specifications subject to change without notice.
–2–
REV. 0
AD9709
(TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, Differential Transformer-Coupled Output,
DYNAMIC SPECIFICATIONS 50 ⍀ Doubly Terminated, unless otherwise noted)
Parameter
Min
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (90% to 10%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
Max
125
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 100 MSPS; fOUT = 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
fCLOCK = 65 MSPS; fOUT = 1.00 MHz
fCLOCK = 65 MSPS; fOUT = 2.51 MHz
fCLOCK = 65 MSPS; fOUT = 5.02 MHz
fCLOCK = 65 MSPS; fOUT = 14.02 MHz
fCLOCK = 65 MSPS; fOUT = 25 MHz
fCLOCK = 125 MSPS; fOUT = 25 MHz
fCLOCK = 125 MSPS; fOUT = 40 MHz
Signal to Noise and Distortion Ratio
fCLOCK = 50 MHz; fOUT = 1 MHz
Total Harmonic Distortion
fCLOCK = 100 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 2.00 MHz
fCLOCK = 125 MSPS; fOUT = 4.00 MHz
fCLOCK = 125 MSPS; fOUT = 10.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLOCK = 65 MSPS; fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
Channel Isolation
fCLOCK = 125 MSPS; fOUT = 10 MHz
fCLOCK = 125 MSPS; fOUT = 40 MHz
63
–3–
Unit
35
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
68
62
56
50
68
68
66
60
50
63
55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
50
dB
–67
–63
–63
–63
NOTES
1
Measured single-ended into 50 Ω load.
Specifications subject to change without notice.
REV. 0
Typ
–63
dBc
dBc
dBc
dBc
58
51
46
41
dBc
dBc
dBc
dBc
85
77
dBc
dBc
AD9709–SPECIFICATIONS
DIGITAL SPECIFICATIONS (T
MIN
to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = 5 V
Logic “1” @ DVDD = 3
Logic “0” Voltage @ DVDD = 5 V
Logic “0” @ DVDD = 3
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW, tCPW)
Min
Typ
3.5
2.1
5
3
0
Max
Unit
V
V
V
V
µA
µA
pF
ns
ns
ns
1.3
0.9
+10
+10
0
–10
–10
5
2.0
1.5
3.5
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD
DVDD
ACOM
AVDD
MODE, CLK1, CLK2, WRT1, WRT2
Digital Inputs
IOUTA1/IOUTA2, IOUTB1/IOUTB2
REFIO, FSADJ1, FSADJ2
GAINCTRL, SLEEP
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With
Respect to
Min
Max
Unit
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
+6.5
+6.5
+0.3
+6.5
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
+150
300
V
V
V
V
V
V
V
V
V
°C
°C
°C
–65
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
ORDERING GUIDE
tS
Model
Temperature
Range
Package
Description
AD9709AST
–40°C to +85°C
Thin Plastic Quad ST-48
Flatpack (LQFP)
Evaluation Board
AD9709-EB
Package
Option
tH
DATA IN
(WRT2) (WRT1 / IQWRT)
t LPW
(CLK2) (CLK1/ IQCLK)
t CPW
IOUTA
OR
IOUTB
THERMAL CHARACTERISTICS
Thermal Resistance
t PD
Figure 1. Timing Diagram for Dual and Interleaved Modes
48-Lead LQFP
θJA = 91°C/W
See Dynamic and Digital sections for timing specifications.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9709 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD9709
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1–8
9–14, 31–36
15, 21
16, 22
17
18
19
20
23–30
37
38
39, 40
41
42
43
44
45, 46
47
48
PORT1
NC
DCOM1, DCOM2
DVDD1, DVDD2
WRT1/IQWRT
CLK1/IQCLK
CLK2/IQRESET
WRT2/IQSEL
PORT2
SLEEP
ACOM
IOUTA2, IOUTB2
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1, IOUTA1
AVDD
MODE
Data Bits DB7–P1 to DB0–P1
No Connection
Digital Common
Digital Supply Voltage
Input Write Signal for PORT 1 (IQWRT in Interleaving Mode)
Clock Input for DAC1 (IQCLK in Interleaving Mode)
Clock Input for DAC2 (IQRESET in Interleaving Mode)
Input Write Signal for PORT 2 (IQSEL in Interleaving Mode)
Data Bits DB7–P2 to DB0–P2
Power-Down Control Input
Analog Common
“PORT 2” Differential DAC Current Outputs
Full-Scale Current Output Adjust for DAC2
Master/Slave Resistor Control Mode
Reference Input/Output
Full-Scale Current Output Adjust for DAC1
“PORT 1” Differential DAC Current Outputs
Analog Supply Voltage
Mode Select (1 = Dual Port, 0 = Interleaved)
ACOM
SLEEP
IOUTB2
IOUTA2
GAIN CTRL
FSADJ2
REFIO
IOUTB1
FSADJ1
AVDD
IOUTA1
MODE
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
DB7-P1(MSB)
1
DB6-P1
2
DB5-P1
3
34 NC
DB4-P1
4
33 NC
DB3-P1
5
DB2-P1
6
DB1-P1
7
DB0-P1
8
29 DB1-P2
NC
9
28 DB2-P2
NC 10
27 DB3-P2
NC 11
26 DB4-P2
36 NC
PIN 1
IDENTIFIER
35 NC
32 NC
AD9709
31 NC
DUAL 8-BIT DAC
48-PIN LQFP
30 DB0-P2
25 DB5-P2
NC 12
REV. 0
DB6-P2
DB7-P2 (MSB)
DVDD2
DCOM2
WRT/IQSEL
CLK1/IQCLK
–5–
CLK2/IQRESET
DVDD1
DCOM1
WRT1/IQWRT
NC = NO CONNECT
NC
NC
13 14 15 16 17 18 19 20 21 22 23 24
AD9709
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full-scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full-scale, associated with a 1 LSB change in digital input code.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected when
all inputs are set to 1s.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
5V
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It
is expressed as a percentage or in decibels (dB).
CLK1/
IQCLK
CLK2/
IQRESET
SLEEP
AVDD
CLK
DIVIDER
FSADJ1
RSET1
2k⍀
PMOS
CURRENT
SOURCE
ARRAY
REFIO
0.1F
DAC1
LATCH
AD9709
MINI CIRCUITS
T1-1T
IOUTA1
SEGMENTED
SWITCHES
FOR DAC1
LSB
SWITCH
50⍀
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
IOUTB1
50⍀
IOUTA2
PMOS
CURRENT
SOURCE
ARRAY
FSADJ2
RSET2
2k⍀
DAC2
LATCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
1.2V REF
IOUTB2
MODE
MULTIPLEXING LOGIC
DVDD
WRT1/
IQWRT
CHANNEL 1 LATCH
DCOM ACOM
DB0-DB7
GAINCTRL
5V
CHANNEL 2 LATCH
DB0-DB7
WRT2/
IQSEL
50⍀
DVDD
DCOM
RETIMED CLOCK OUTPUT
LECROY 9210
PULSE
GENERATOR
DIGITAL
DATA
*AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS
ON FALLING EDGE OF 50% DUTY CYCLE CLOCK
TEKTRONIX
AWG-2021
w/OPTION 4
Figure 2. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent
GAINCTRL Resistors on FSADJ1 and FSADJ2
–6–
REV. 0
AD9709
Typical Characterization Curves
(AVDD = 5 V, DVDD = 3.3 V, IOUTFS = 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = 25ⴗC, SFDR up to Nyquist, unless
otherwise noted)
75
75
fCLK = 25MSPS
70
75
70
70
0dBFS
65
fCLK = 5MSPS
60
fCLK = 65MSPS
55
SFDR – dBc
65
SFDR – dBc
SFDR – dBc
0 dBFS
–6 dBFS
60
–12 dBFS
55
65
–6dBFS
60
55
fCLK = 125MSPS
–12dBFS
50
50
50
45
45
0.1
1
10
0
100
0.5
1
1.5
fOUT – MHz
fOUT – MHz
Figure 3. SFDR vs. fOUT @ 0 dBFS
45
2.5
Figure 4. SFDR vs. fOUT @ 5 MSPS
70
SFDR – dBc
–6dBFS
–6dBFS
60
–12dBFS
55
55
SFDR – dBc
65
65
8
6
fOUT – MHz
10
12
IOUTFS = 20mA
0dBFS
0dBFS
60
4
2
75
70
70
0
Figure 5. SFDR vs. fOUT @ 25 MSPS
75
75
SFDR – dBc
2
65
60
IOUTFS = 10mA
55
IOUTFS = 5mA
–12dBFS
50
45
45
0
5
10
50
50
15
20
fOUT – MHz
30
25
35
Figure 6. SFDR vs. fOUT @ 65 MSPS
0
10
20
40
30
fOUT – MHz
60
50
45
70
Figure 7. SFDR vs. fOUT @ 125 MSPS
0
70
70
25MSPS/2.27MHz
55
65MSPS/5.91MHz
50
60
55
10MSPS/2.0MHz
65MSPS/13.0MHz
45
40
–25 –22 –19 –16 –13 –10 –7
AOUT – dBFS
3.3/3.4MHz
@25MSPS
45
–4
–1
2
16.9/18.1Mz
@125MSPS
8.8/9.8MHz
@65MSPS
25MSPS/5.0MHz
Figure 9. Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
REV. 0
55
50
125MSPS/11.37MHz
40
–25
35
60
125MSPS/5.0MHz
50
45
30
65
SFDR – dBc
10MSPS/0.91MHz
SFDR – dBc
SFDR – dBc
65
60
25
0.965/1.035MHz
@7MSPS
5MSPS/1.0MHz
65
15
20
fOUT – MHz
75
70
5MSPS /0.46MHz
10
Figure 8. SFDR vs. fOUT and IOUTFS
@ 65 MSPS and 0 dBFS
75
75
5
–20
–15
–10
AOUT – dBFS
–5
0
Figure 10. Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/5
–7–
40
–25
–20
–10
–15
AOUT – dBFS
–5
0
Figure 11. Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9709
0.06
70
0.07
0.04
0.06
0.02
0.05
65
55
IOUTFS = 20mA
0
DNL – LSBs
INL – LSBs
SINAD – dBc
60
–0.02
–0.04
0.04
0.03
0.02
50
–0.06
IOUTFS = 5mA
45
0.01
–0.08
0
–0.1
–0.01
IOUTFS = 10mA
40
0
20
40
60
80 100
fCLK – MSPS
120
140
0
Figure 12. SINAD vs. fCLOCK and IOUTFS
@ fOUT = 5 MHz and 0 dBFS
32
64
96
0
128 160 192 224 256
CODE
Figure 13. Typical INL
75
50
100
150
CODE
200
250
Figure 14. Typical DNL
0
1.0
0.05
–10
GAIN ERROR
fOUT = 25MHz
60
fOUT = 40MHz
55
fOUT = 60MHz
OFFSET ERROR
0.0
0.00
–0.5
–0.03
50
AMPLITUDE – dBm
65
–20
0.5
0.03
GAIN ERROR – % FS
fOUT = 10MHz
OFFSET ERROR – % FS
SFDR – dBc
70
–30
–40
–50
–60
–70
–80
–90
45
–50
–30
–10 10
30
50
TEMPERATURE – ⴗC
70
90
0
0
–10
–10
–20
–20
–30
–40
–50
–60
60
Figure 18. Dual-Tone SFDR @
fCLK = 125 MSPS
10
50
40
30
20
FREQUENCY – MHz
60
Figure 17. Single-Tone SFDR @
fCLK = 125 MSPS
–60
–80
20
30
40
50
FREQUENCY – MHz
0
–50
–80
10
–1.0
80 5
–40
–70
0
0
20
40
60
TEMPERATURE – ⴗC
–30
–70
–90
–20
Figure 16. Gain and Offset Error vs.
Temperature @ fCLK = 125 MSPS
AMPLITUDE – dBm
AMPLITUDE – dBm
Figure 15. SFDR vs. Temperature @
fCLK = 125 MSPS, 0 dBFS
–0.05
–40
–100
–90
0
10
50
20
30
40
FREQUENCY – MHz
60
Figure 19. Four-Tone SFDR @
fCLK = 125 MSPS
–8–
REV. 0
AD9709
FUNCTIONAL DESCRIPTION
REFERENCE OPERATION
Figure 20 shows a simplified block diagram of the AD9709.
The AD9709 consists of two DACs, each one with its own
independent digital control logic and full-scale output current
control. Each DAC contains a PMOS current source array
capable of providing up to 20 mA of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The three lower bits consist of
seven equal current sources whose value is 1/8th of an MSB
current source. Implementing the lower bits with current sources,
instead of an R-2R ladder, enhances the dynamic performance
for multitone or low-amplitude signals and helps maintain the
DACs high-output impedance (i.e., >100 kΩ).
The AD9709 contains an internal 1.20 V bandgap reference.
This can be easily overridden by an external reference with no
effect on performance. REFIO serves as either an input or output
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1 µF capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier
with an input bias current of less than 100 nA should be used.
An example of the use of the internal reference is shown in
Figure 21.
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This
new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the
differential current switches.
GAINCTRL MODE
The analog and digital sections of the AD9709 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3 V to 5.5 V range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.20 V bandgap voltage
reference and two reference control amplifiers.
The AD9709 allows the gain of each channel to be set independently by connecting one RSET resistor to FSADJ1 and another
RSET resistor to FSADJ2. To add flexibility and reduce system
cost, a single RSET resistor can be used to set the gain of both
channels simultaneously.
When GAINCTRL is low (i.e., connected to AGND), the independent channel gain control mode using two resistors is enabled.
In this mode, individual RSET resistors should be connected to
FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., connected
to AVDD), the master/slave channel gain control mode using one
resistor is enabled. In this mode, a single RSET resistor is connected to FSADJ1 and the resistor on FSADJ2 can be removed.
The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from 2 mA to
20 mA via an external resistor, RSET, connected to the Full-Scale
Adjust (FSADJ) pin. The external resistor, in combination with
both the reference control amplifier and voltage reference VREFIO,
sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The fullscale current, IOUTFS, is 32 × IREF.
5V
CLK1/
IQCLK
An external reference can be applied to REFIO as shown in
Figure 22. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 µF
compensation capacitor is not required since the internal reference is overridden, and the relatively high-input impedance of
REFIO minimizes any loading of the external reference.
CLK2/
IQRESET
AVDD
SLEEP
CLK
DIVIDER
FSADJ1
RSET1
2k⍀
IREF1
PMOS
CURRENT
SOURCE
ARRAY
REFIO
0.1F
DAC1
LATCH
VDIFF = VOUTA – VOUTB
AD9709
VOUT1A
IOUTA1
SEGMENTED
SWITCHES
FOR DAC1
LSB
SWITCH
VOUT1B
IOUTB1
VOUT2A
IOUTA2
PMOS
CURRENT
SOURCE
ARRAY
FSADJ2
RSET2
2k⍀
IREF2
DAC2
LATCH
SEGMENTED
SWITCHES
FOR DAC2
LSB
SWITCH
1.2V REF
IOUTB2
DVDD
MULTIPLEXING LOGIC
ACOM
CHANNEL 1 LATCH
CHANNEL 2 LATCH
DCOM
GAINCTRL WRT1/
IQWRT
DB0-DB7
DB0-DB7
DIGITAL DATA INPUTS
WRT2/ MODE
IQSEL
Figure 20. Simplified Block Diagram
REV. 0
–9–
5V
VOUT2B
RL2B
50⍀
RL2A
50⍀
RL1B
50⍀
RL1A
50⍀
AD9709
REFERENCE CONTROL AMPLIFIER
Both of the DACs in the AD9709 contain a control amplifier
that is used to regulate the full-scale output current, IOUTFS. The
control amplifier is configured as a V-I converter as shown in
Figure 21, so that its current output, IREF, is determined by the
ratio of the VREFIO and an external resistor, RSET, as stated in
Equation 4. IREF is copied to the segmented current sources with
the proper scale factor to set IOUTFS as stated in Equation 3.
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
AVDD
GAINCTRL
AD9709
+1.2V
REF
0.1F
IREF
CURRENT
SOURCE
ARRAY
FSADJ
2k⍀
+1.2V
REF
IREF
AD9709
2k⍀
CURRENT
SOURCE
ARRAY
ACOM
Figure 22. External Reference Configuration
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 µA
and 625 µA. The wide adjustment range of IOUTFS provides
several benefits. The first relates directly to the power dissipation of the AD9709, which is proportional to IOUTFS (refer to the
Power Dissipation section). The second relates to the 20 dB
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier
is approximately 500 kHz and can be used for low frequency,
small signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9709 provide complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current
output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023)
while IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of both
the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/256) × IOUTFS
(1)
IOUTB = (255 – DAC CODE)/256 × IOUTFS
(2)
where DAC CODE = 0 to 255 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage, VREFIO
and external resistor RSET. It can be expressed as:
IOUTFS = 32 × IREF
(3)
where
IREF = VREFIO /RSET
(7)
(8)
These last two equations highlight some of the advantages of
operating the AD9709 differentially. First, the differential
operation will help cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion and dc
offsets. Second, the differential code dependent current and
subsequent voltage, VDIFF, is twice the value of the single-ended
voltage output (i.e., VOUTA or VOUTB), thus providing twice the
signal power to the load.
REFERENCE
SECTION
FSADJ
(6)
VDIFF = {(2 × DAC CODE – 255)/256} ×
(32 × RLOAD/RSET) × VREFIO
AVDD
REFIO
EXTERNAL
REFERENCE
VOUTB = IOUTB × RLOAD
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
Figure 21. Internal Reference Configuration
AVDD
(5)
VDIFF = (IOUTA – IOUTB) × RLOAD
ACOM
GAINCTRL
VOUTA = IOUTA × RLOAD
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
REFERENCE
SECTION
REFIO
ADDITIONAL
EXTERNAL
LOAD
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω
or 75 Ω cable. The single-ended voltage output appearing at the
IOUTA and IOUTB nodes is simply :
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9709
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown
in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA and
IOUTB, may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load
resistor, RLOAD, as described in the DAC Transfer Function
section by Equations 5 through 8. The differential voltage, VDIFF,
existing between VOUTA and VOUTB can also be converted to a
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9709 is optimum
and specified using a differential transformer coupled output in
which the voltage swing at IOUTA and IOUTB is limited to ± 0.5 V.
If a single-ended unipolar output is desirable, IOUTA should be
selected.
The distortion and noise performance of the AD9709 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
dynamic common-mode distortion mechanisms, digital feedthrough and noise.
(4)
–10–
REV. 0
AD9709
Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are complementary,
they become additive when processed differentially. A properly selected transformer will allow the AD9709 to provide the
required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground
via an I-V op amp configuration will result in the optimum dc
linearity. Note the INL/DNL specifications for the AD9709 are
measured with IOUTA maintained at a virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9709.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS =
2 mA. The optimum distortion performance for a single-ended
or differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V. Applications
requiring the AD9709’s output (i.e., VOUTA and/or VOUTB) to
extend its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely
affect the AD9709’s linearity performance and subsequently
degrade its distortion performance.
DAC TIMING
The AD9709 can operate in two timing modes, dual and interleaved, which are described below. The block diagram in Figure
25 represents the latch architecture in the interleaved timing mode.
DUAL PORT MODE TIMING
When the mode pin is at Logic 1, the AD9709 operates in dual
port mode. The AD9709 functions as two distinct DACs. Each
DAC has its own completely independent digital input and control lines.
The AD9709 features a double buffered data path. Data enters
the device through the channel input latches. This data is then
transferred to the DAC latch in each signal path. Once the data
is loaded into the DAC latch, the analog output will settle to its
new value.
For general consideration, the WRT lines control the channel
input latches and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. Should the rising edge of CLK
occur after the rising edge of WRT, a 2 ns minimum delay should
be maintained from rising edge of WRT to rising edge of CLK.
tS
DATA IN
WRT1/WRT2
t CPW
IOUTA
OR
IOUTB
t PD
Figure 23. Dual Mode Timing
The AD9709’s digital inputs consists of two independent channels. For the dual port mode, each DAC has its own dedicated
8-bit data port, WRT line and CLK line. In the interleaved
timing mode, the function of the digital control pins changes
as described below under the Interleaved Mode Timing section.
The 8-bit parallel data inputs follow straight binary coding
where DB7 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
REV. 0
t LPW
CLK1/CLK2
DIGITAL INPUTS
The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge, or every other rising edge of the clock,
depending on whether dual or interleaved mode is being used.
The DAC outputs are designed to support a clock rate as high
as 125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input
data transitions on the falling edge of a 50% duty cycle clock.
tH
Timing specifications for dual port mode are given in Figures 23
and 24.
DATAIN
D1
D2
D3
D4
D5
WRT1/WRT2
CLK1/CLK2
IOUTA
OR
IOUTB
xx
D1
D2
D3
D4
Figure 24. Dual Mode Timing
INTERLEAVED MODE TIMING
When the mode pin is at Logic 0, the AD9709 operates in interleaved mode. WRT1 now functions as IQWRT and CLK1
functions as IQCLK. WRT2 functions as IQSEL and CLK2
functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic
level of IQSEL will steer the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). Note: For
proper operation, IQSEL should only change state when IQWRT
and IQCLK are low.
–11–
AD9709
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the interleaved mode IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be used
to synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
PORT 1
INPUT
LATCH
INTERLEAVED
DATA IN, PORT 1
DAC1
LATCH
DAC1
DEINTERLEAVED
DATA OUT
PORT 2
INPUT
LATCH
IQWRT
IQSEL
IQCLK
IQRESET
DAC2
LATCH
DAC2
ⴜ2
Figure 25. Latch Structure in Interleaved Mode
Timing specifications for interleaved mode are given in Figures
26 and 27.
tS
tH
VTHRESHOLD = DVDD/2 (± 20%)
The internal digital circuitry of the AD9709 is capable of operating over a digital supply range of 3 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high-level voltage of the
TTL drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically
ensure proper compatibility with most TTL logic families. Figure 28 shows the equivalent digital input circuit for the data and
clock inputs. The sleep mode input is similar with the exception
that it contains an active pull-down circuit, thus ensuring that
the AD9709 remains enabled if this input is left disconnected.
Since the AD9709 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9709
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9709 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a lowvalue resistor network (i.e., 20 Ω to 100 Ω) between the AD9709
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high-data update
rates, stripline techniques with proper impedance and termination resistors should be considered to maintain “clean” digital
inputs.
DATA IN
IQSEL
t H*
IQWRT
t LPW
IQCLK
The external clock driver circuitry should provide the AD9709
with a low-jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed
waveform. Thus, the clock input should be driven by the fastest
logic family suitable for the application.
t PD
IOUTA
OR
IOUTB
The digital inputs are CMOS-compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDD) or
*APPLIES TO FALLING EDGE OF IQCLK /IQWRT AND IQSEL ONLY
Figure 26. Interleaved Mode Timing
DVDD
INTERLEAVED
DATA
xx
D1
D2
D3
D4
D5
DIGITAL
INPUT
IQSEL
IQWRT
Figure 28. Equivalent Digital Input
IQCLK
IQRESET
DAC OUTPUT
PORT 1
DAC OUTPUT
PORT 2
xx
xx
D1
D2
Figure 27. Interleaved Mode Timing
D3
D4
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the
effective clock duty cycle and, subsequently, cut into the required
data setup and hold times.
–12–
REV. 0
AD9709
the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the optimum high-frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling,
a bipolar output, signal gain and/or level shifting, within the
bandwidth of the chosen op amp.
60
50
SINAD – dBc
40
30
20
80
10
70
–3
0
–2
–1
1
2
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE – ns
3
60
4
IAVDD – mA
0
–4
Figure 29. SINAD vs. Clock Placement @ fOUT = 20 MHz
INPUT CLOCK AND DATA TIMING RELATIONSHIP
50
40
30
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9709 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock/data placement.
20
10
0
5
20
25
0.4
0.5
Figure 30. IAVDD vs. IOUTFS
35
SLEEP MODE OPERATION
30
The AD9709 has a power down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 3.0 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level 1 to the SLEEP pin. The SLEEP pin logic threshold
is equal to 0.5 × AVDD. This digital input also contains an
active pull-down circuit that ensures the AD9709 remains
enabled if this input is left disconnected. The AD9709 takes
less than 50 ns to power down and approximately 5 µs to
power back up.
125MSPS
25
IDVDD – mA
100MSPS
20
65MSPS
15
10
25MSPS
5
0
POWER DISSIPATION
The power dissipation, PD, of the AD9709 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output IOUTFS,
(3) the update rate fCLOCK, (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS as shown in
Figure 30 and is insensitive to fCLOCK.
5MSPS
0
0.1
0.2
0.3
RATIO – fOUT /fCLK
Figure 31. IDVDD vs. Ratio @ DVDD = 5 V
18
16
125MSPS
14
100MSPS
IDVDD – mA
12
Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 31 and 32
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
10
65MSPS
8
6
25MSPS
4
5MSPS
2
APPLYING THE AD9709
Output Configurations
0
The following sections illustrate some typical output configurations for the AD9709. Unless otherwise noted, it is assumed
that IOUTFS is set to a nominal 20 mA. For applications requiring
REV. 0
15
10
IOUTFS – mA
0
0.1
0.2
0.3
RATIO – fOUT /fCLK
0.4
Figure 32. IDVDD vs. Ratio @ DVDD = 3 V
–13–
0.5
AD9709
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, RLOAD, referred to ACOM. This configuration
may be more suitable for a single-supply system requiring a dccoupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This configuration
provides the best dc linearity since IOUTA or IOUTB is maintained at
a virtual ground. Note that IOUTA provides slightly better performance than IOUTB.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 33. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios may also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
AD9709
OPTIONAL
RDIFF
The differential circuit shown in Figure 35 provides the necessary
level-shifting required in a single supply system. In this case,
AVDD which is the positive analog supply for both the AD9709
and the op amp is also used to level-shift the differential output
of the AD9709 to midsupply (i.e., AVDD/2). The AD8041 is a
suitable op amp for this application.
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 36 shows the AD9709 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated 50 Ω cable since the nominal full-scale current, IOUTFS, of
20 mA flows through the equivalent RLOAD of 25 Ω. In this case,
RLOAD represents the equivalent load resistance seen by IOUTA or
IOUTB. The unused output (IOUTA or IOUTB) can be connected to
ACOM directly or via a matching RLOAD. Different values of
IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output configuration is suggested.
MINI-CIRCUITS
T1-1T
IOUTA
some additional signal gain. The op amp must operate off of a
dual supply since its output is approximately ± 1.0 V. A highspeed amplifier capable of preserving the differential performance
of the AD9709 while meeting other system level objectives (i.e.,
cost, power) should be selected. The op amp’s differential gain,
its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit.
RLOAD
500⍀
IOUTB
AD9709
225⍀
IOUTA
Figure 33. Differential Output Using a Transformer
AD8047
225⍀
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically
around ACOM and should be maintained with the specified
output compliance range of the AD9709. A differential resistor,
RDIFF, may be inserted in applications where the output of the
transformer is connected to the load, RLOAD , via a passive
reconstruction filter or cable. RDIFF is determined by the
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately
half the signal power will be dissipated across RDIFF.
IOUTB
COPT
500⍀
25⍀
25⍀
Figure 34. DC Differential Coupling Using an Op Amp
500⍀
AD9709
225⍀
IOUTA
AD8041
225⍀
IOUTB
COPT
1k⍀
AVDD
DIFFERENTIAL COUPLING USING AN OP AMP
25⍀
An op amp can also be used to perform a differential to singleended conversion as shown in Figure 34. The AD9709 is
configured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is converted
to a single-ended signal via the differential op amp configuration.
An optional capacitor can be installed across IOUTA and IOUTB,
forming a real pole in a low-pass filter. The addition of this
capacitor also enhances the op amps distortion performance by
preventing the DACs high-slewing output from overloading the
op amp’s input.
25⍀
500⍀
Figure 35. Single Supply DC Differential Coupled Circuit
AD9709
IOUTA
50⍀
IOUTB
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide
–14–
Figure 36. 0 V to 0.5 V Unbuffered Voltage Output
REV. 0
AD9709
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 37 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9709 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in
the Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slewing capabilities. U1 provides a negative
unipolar output voltage and its full-scale output voltage is simply
the product of RFB and IOUTFS. The full-scale output should be
set within U1’s voltage output swing capabilities by scaling IOUTFS
and/or RFB. An improvement in ac distortion performance may
result with a reduced IOUTFS since the signal current U1 will be
required to sink will be subsequently reduced.
RFB
200⍀
AD9709
VOUT = IOUTFS ⴛ RFB
IOUTB
200⍀
Figure 37. Unipolar Buffered Voltage Output
90
PSRR – dB
85
Proper grounding and decoupling should be a primary objective
in any high-speed, high-resolution system. The AD9709 features separate analog and digital supply and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, AVDD, the analog supply, should be
decoupled to ACOM, the analog common, as close to the chip
as physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close to the chip as physically possible.
80
75
70
0.2
Note that the units in Figure 38 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal current sources, and therefore the
output current. The voltage noise on AVDD, therefore, will be
added in a nonlinear manner to the desired IOUT. PSRR is very
code dependent, thus producing mixing effects which can
modulate low-frequency power supply noise to higher frequencies. Worst case PSRR for either one of the differential DAC
outputs will occur when the full-scale current is directed towards that output. As a result, the PSRR measurement in Figure 38 represents a worst-case condition in which the digital
inputs remain static and the full-scale output current of 20 mA is
directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and for simplicity sake (i.e., ignore harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the dc’s full-scale
current, IOUTFS, one must determine the PSRR in dB using
Figure 38 at 250 kHz. To calculate the PSRR for a given RLOAD,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 38 by the scaling factor 20 × Log
(RLOAD ). For instance, if RLOAD is the PSRR is reduced by
34 dB (i.e., PSRR of the DAC at 250 kHz which is 85 dB in
Figure 38 becomes 51 dB VOUT/VIN).
IOUTA
U1
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, IOUTFS. AC noise on the DC supplies
is common in applications where the power distribution is generated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs. frequency of the AD9709 AVDD
supply over this frequency range is shown in Figure 38.
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY – MHz
0.9
1.0
FERRITE
BEADS
1.1
TTL/CMOS
LOGIC
CIRCUITS
Figure 38. AVDD Power Supply Rejection Ratio
CERAMIC
AVDD
100F
10F–22F
0.1F
ACOM
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
TANTALUM
Many applications seek high-speed and high-performance
under less than ideal operating conditions. In these application
circuits, the implementation and construction of the printed
circuit board is as important as the circuit design. Proper RF
techniques must be used for device selection, placement and
routing as well as power supply bypassing and grounding to
ensure optimum performance.
+5V
POWER SUPPLY
Figure 39. Differential LC Filter for Single 5 V and 3 V
Applications
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
REV. 0
ELECTROLYTIC
For those applications that require a single 5 V or 3 V supply for
both the analog and digital supplies, a clean analog supply may
be generated using the circuit shown in Figure 39. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low-ESR
type electrolytic and tantalum capacitors.
–15–
AD9709
APPLICATIONS
Using the AD9709 for Quadrature Amplitude Modulation
implementation and complexity of the analog filter, which can
be a significant contributor to mismatches in gain and phase
between the two baseband channels. A quadrature mixer modulates the I and Q components with the in-phase and quadrature
carrier frequency and then sums the two outputs to provide the
QAM signal.
QAM is one of the most widely used digital modulation schemes
in digital communications systems. This modulation technique
can be found in FDM as well as spread spectrum (i.e., CDMA)
based systems. A QAM signal is a carrier frequency that is
modulated in both amplitude (i.e., AM modulation) and phase
(i.e., PM modulation). It can be generated by independently
modulating two carriers of identical frequency but with a 90°
phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90° phase
shift with respect to the I component. The I and Q components
are then summed to provide a QAM signal at the specified carrier frequency.
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 41 helps improve
upon the matching between the I and Q channels, as well as
showing a path for up-conversion using the AD8346 quadrature
modulator. The AD9709 provides both I and Q DACs as well as
a common reference that will improve the gain matching and
stability. RCAL can be used to compensate for any mismatch in
gain between the two channels. The mismatch may be attributed
to the mismatch between RSET1 and RSET2, effective load resistance of each channel, and/or the voltage offset of the control
amplifier in each DAC. The differential voltage outputs of both
DACs in the AD9709 are fed into the respective differential
inputs of the AD8346 via matching networks.
8
DAC
DSP
OR
ASIC
0
CARRIER
FREQUENCY
Σ
90
TO
MIXER
8
DAC
NYQUIST
FILTERS
I and Q digital data can be fed into the AD9709 in two different
ways. In dual port mode, The digital I information drives one
input port, while the digital Q information drives the other input
port. If no interpolation filter precedes the DAC, the symbol
rate will be the rate at which the system clock drives the CLK
and WRT pins on the AD9709. In interleaved mode, the digital
input stream at Port I contains the I and the Q information in
alternating digital words. Using IQSEL and IQRESET, the
AD9709 can be synchronized to the I and Q data stream. The
internal timing of the AD9709 routes the selected I and Q data
to the correct DAC output. In interleaved mode, if no interpolation filter precedes the AD9709, the symbol rate will be
half that of the system clock driving the digital datastream and
the IQWRT and IQCLK pins on the AD9709.
QUADRATURE
MODULATOR
Figure 40. Typical Analog QAM Architecture
A common and traditional implementation of a QAM modulator is shown in Figure 40. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components. Each component is then typically
applied to a Nyquist filter before being applied to a quadrature
mixer. The matching Nyquist filters shape and limit each components spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate
or possibly a multiple of it if an interpolating filter precedes
the DAC. The use of an interpolating filter typically eases the
ROHDE &
SCHWARZ
FSEA30B
AVDD
0.1F
DVDD
DCOM
RL
IOUTA
TEKTRONICS
AWG2021
W/OPTION 4
PORT I
IQWRT
IQCLK
D
I
G
I
T
A
L
“I”
DAC
LATCH
PORT Q
“I”
DAC
RL
LA
RA
RL
RA
RB
BBIP
VOUT
BBIN
RL
LOIP
PHASE
SPLITTER
RL
QOUTA
“Q”
DAC
LATCH
“Q”
DAC
FSADJQ
RSET
3.9k⍀
RL
RA
RL
LA
CA
QOUTB
FSADJI
VPBF
CB RB
AD9709
IQSEL
SLEEP MODE
LA
CA
IOUTB
I
N
T
E
R
F
A
C
E
SPECTRUM
ANALYZER
AVDD
ACOM
LA
RA
RB
LOIN
BBQP
CB RB CFILTER
RL
ROHDE &
SCHWARZ
AD8346
BBQN
SIGNAL
GENERATOR
VDIFF = 1.82V p-p
REFIO
RSET
3.9k⍀
DIFFERENTIAL
0.1F RLC FILTER
AVDD
NOTE: DACs Full-Scale OUTPUT CURRENT = IOUTFS
RA, RB AND RL ARE THIN FILM RESISTOR NETWORKSWITH
0.1% MATCHING, 1% ACCURACY.
AVAILABLE FROM OHMTEK ORNXXXXD SERIES.
NOTE:
RL = 200⍀
RA = 2500⍀
RB = 500⍀
RP = 200⍀
CA = 280pF
CB = 45pF
LA = 10H
IOUTFS = 11mA
AVDD = 5.0V
VCM = 1.2V
AD976x
RL
RB
RA
AD8346
VMOD
0 TO IOUTFS
VDAC
Figure 41. Baseband QAM Implementation Using an AD9709 and AD8346
–16–
REV. 0
AD9709
CDMA
–30
Carrier Division Multiple Access, or CDMA, is an air transmit/
receive scheme where the signal in the transmit path is modulated
with a pseudorandom digital code (sometimes referred to as the
spreading code). The effect of this is to spread the transmitted
signal across a wide spectrum. Similar to a DMT waveform, a
CDMA waveform containing multiple subscribers can be characterized as having a high peak to average ratio (i.e., crest factor),
thus demanding highly linear components in the transmit signal
path. The bandwidth of the spectrum is defined by the CDMA
standard being used, and in operation is implemented by using
a spreading code with particular characteristics.
–40
–50
–60
dBm
–70
–90
–100
–110
–130
Figure 43 shows an example of the AD9709 used in a W-CDMA
transmitter application using the AD6122 CDMA 3 V IF subsystem. The AD6122 has functions, such as external gain
control and low-distortion characteristics, needed for the
superior Adjacent Channel Power (ACP) requirements of
W-CDMA.
634⍀
(“I DAC”)
U1
500⍀
IOUTA
DAC
DAC
LATCH
INPUT
LATCHES
50⍀
WRT2
RSET2
1.9k⍀
U2
QOUTA
DAC
DAC
LATCH
FSADJ2
RCAL
220⍀
QOUTB
(“Q DAC”)
REFIO
SLEEP
ACOM
500⍀
AD6122
IIPP
IIPN
50⍀
500⍀
INPUT
LATCHES
500⍀
500⍀
IOUTB
WRT1
Q DATA
INPUT
LOIPP
500⍀ LOIPN
ⴜ2
500⍀
IIQP
500⍀
IIQN
PHASE
SPLITTER
MODOPP
MODOPN
50⍀
50⍀
TEMPERATURE
COMPENSATION
DCOM
CLK2
REFIN
0.1F
GAIN
CONTROL
VGAIN
GAIN
CONTROL
SCALE
FACTOR
TXOPP
TXOPN
Figure 43. CDMA Transmit Application Using AD9709 and AD6122
REV. 0
SPAN 30MHz
AD9709
FSADJ1
I DATA
INPUT
3MHz
FREQUENCY
3V
CLK1
RSET1
2k⍀
CENTER 2.4GHz
cu1
cu1
C0
C2
Figure 42. CDMA Signal, 8 M Chips Sampled at 65 MSPS,
Recreated at 2.4 GHz, Adjacent Channel Power > 54 dBm
Figure 42 shows the AD9709/AD8346 application circuit of
Figure 41 reconstructing a wideband, or W-CDMA test vector
with a bandwith of 8 MHz, centered at 2.4 GHz and being
sampled at 62.5 MHz. The IF frequency at the DAC output
is 15.625 MHz. ACPR for the given test vector is measured
at greater than 54 dB.
AVDD
c11
1
c11
–120
Distortion in the transmit path can lead to power being transmitted out of the defined band. The ratio of power transmitted
in-band to out-of-band is often referred to as Adjacent Channel
Power (ACP). This is a regulatory issue due to the possibility
of interference with other signals being transmitted by air.
Regulatory bodies define a spectral mask outside of the transmit
band, and the ACP must fall under this mask. If distortion in
the transmit path causes the ACP to be above the spectral mask,
then filtering, or different component selection is needed to
meet the mask requirements.
DVDD
–80
–17–
VCC
VCC
AD9709
various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single and differential outputs. The digital inputs can be used in dual port or
interleaved mode, and are designed to be driven from various
word generators, with the on-board option to add a resistor
network for proper load termination. When operating the
AD9709, best performance is obtained when running the Digital
Supply (DVDD) at 3 V and the Analog Supply (AVDD) at 5 V.
EVALUATION BOARD
General Description
The AD9709-EB is an evaluation board for the AD9709 8-bit
dual D/A converter. Careful attention to layout and circuit
design, combined with a prototyping area, allow the user to
easily and effectively evaluate the AD9709 in any application
where high resolution, high speed conversion is required. This
board allows the user flexibility to operate the AD9709 in
POWER DECOUPLING AND INPUT CLOCKS
RED
TP10
B1
B3
L1
DVDDIN
DVDD
BEAD
BAN-JACK
B2
BAN-JACK
BLK
TP38
TP43
BLK
AVDD
BEAD
BAN-JACK
BLK
TP39
DVDD
L2
AVDDIN
1
C9
BLK
10F
TP37
2 25V
RED
TP11
1
C10
10F
BLK
TP40
2 25V
B4
BAN-JACK
DGND
BLK
TP41
BLK
TP42
TP44
BLK
1 C7
1 C8
2 0.1F
2 0.01F
AGND
JP9
3
A B
DCLKIN2
JP6
JP16
2
1
DVDD
WHT
TP29
WRT1IN S1
IQWRT
2
1
DCLKIN1
JP2
4
DGND;3,4,5
WHT
TP30
CLK1IN S2
IQCLK
JP5
A 2B
1
I
DGND;3,4,5
WHT
TP31
CLK2IN S3
RESET
I
WHT
TP32
1
DGND;3,4,5
1
2
1
R1
50⍀
2
1
R2
50⍀
2
R3
50⍀
1
2
I
U1
Q
Q
K
CLR
15
3
5
11
13
CLK
2
DVDD
C
JP3
A2 B
J
1
3
10
PRE
3
JP1
C
JP4
A 2B
1
DGND;3,4,5
WRT2IN S4
IQSEL
3
A B
6
12
PRE
J
9
Q
U2
CLK
7
Q
K
CLR
TSSOP112
14
DGND;8
DVDD;16
TSSOP112
DGND;8
DVDD;16
A B
DVDD
1
3
2
JP7
/2 CLOCK DIVIDER
3
C
WRT1
R4
50⍀
CLK1
CLK2
WHT
TP33
WRT2
SLEEP
SLEEP
1
2
R13
50⍀
RP16
R1
22⍀
RCOM
1
2
INP1
R2
22⍀
3
INP2
R3
22⍀
4
INP3
R4
22⍀
5
INP4
R5
22⍀
6
INP5
R6
22⍀
7
INP6
R7
22⍀
8
INP7
R8
22⍀
9
R9
22⍀
RP9
R1
22⍀
RCOM
10
1
INP8
2
R2
22⍀
3
R3
22⍀
4
R4
22⍀
5
R5
22⍀
6
R6
22⍀
7
R7
22⍀
8
INP9 INP10 INP11 INP12 INP13 INP14
R8
22⍀
9
R1
22⍀
1
2
R2
22⍀
3
R3
22⍀
4
R4
22⍀
5
R5
22⍀
6
R6
22⍀
7
R7
22⍀
8
R8
22⍀
9
R9
22⍀
10
INCK1
RP10
RCOM
R9
22⍀
RP15
R1
22⍀
RCOM
10
1
INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30
2
R2
22⍀
3
R3
22⍀
4
R4
22⍀
5
R5
22⍀
6
R6
22⍀
7
INP31 INP32 INP33 INP34 INP35 INP36
R7
22⍀
8
R8
22⍀
9
R9
22⍀
10
INCK2
Figure 44. Power Decoupling and Clocks on AD9709 Evaluation Board
–18–
REV. 0
AD9709
DIGITAL INPUT SIGNAL CONDITIONING
RP3
R9
RCOM R1
22⍀
2
P1
P1
1
4
P1
P1
3
6
P1
P1
5
8
P1
P1
7
10
P1
P1
9
12
P1
P1 11
14
P1
P1 13
16
P1
P1 15
18
P1
P1 17
20
P1
P1 19
22
P1
P1 21
24
P1
P1 23
26
P1
P1 25
28
P1
P1
30
P1
P1 29
32
P1
P1
34
P1
P1 33
36
P1
P1 35
38
P1
P1 37
40
P1
P1
27
INP2
INP3
INP4
INP5
INP6
INP7
INP8
INP9
INP10
INP11
INP12
INP13
INP14
DVDD
RP5, 10⍀
1
16
14
2
12
4
10
6
16
8
14
2
12
DUTP2
15
DUTP3
DUTP4
13
DUTP5
DUTP6
11
DUTP7
DUTP8
9
DUTP9
DUTP10
15
DUTP11
RP6, 10⍀
4
RP6, 10⍀
5
DUTP1
RP6, 10⍀
RP6, 10⍀
3
DUTP12
13
DUTP13
RP6, 10⍀
DUTP14
11
6
31
RP6, 10⍀
INCK1
8
DCLKIN1
9
39
RP4
R9
RCOM R1
22⍀
1
2
P2
P2
1
4
P2
P2
3
6
P2
P2
5
8
P2
P2
7
10
P2
P2
9
12
P2
P2 11
14
P2
P2 13
16
P2
P2 15
18
P2
P2 17
20
P2
P2 19
22
P2
P2 21
24
P2
P2 23
26
P2
P2 25
28
P2
P2
30
P2
P2 29
32
P2
P2
34
P2
P2 33
36
P2
P2 35
38
P2
P2 37
40
P2
P2
27
INP23
INP24
INP25
INP26
INP27
INP28
INP29
INP30
INP31
INP32
INP33
INP34
INP35
INP36
1
16
RP7, 10⍀
3
14
RP7, 10⍀
5
12
RP7, 10⍀
7
10
RP8, 10⍀
1
16
RP8, 10⍀
3
14
RP8, 10⍀
5
12
R9
22⍀
2 3 4 5 6 7 8 9 10
DVDD
RP7, 10⍀
RP14
RP2
RCOM R1
1
RP12
RCOM R1
2 3 4 5 6 7 8 9 10
1
2 3 4 5 6 7 8 9 10
DUTP25
DUTP26
13
DUTP27
DUTP28
11
DUTP29
DUTP30
9
DUTP31
RP8, 10⍀
2
DUTP32
15
DUTP33
RP8, 10⍀
4
DUTP34
13
DUTP35
RP8, 10⍀
6
2 3 4 5 6 7 8 9 10
DUTP24
15
RP7, 10⍀
8
1
DUTP23
RP7, 10⍀
6
R9
DVDD
RP7, 10⍀
4
RCOM R1
33⍀
RP7, 10⍀
2
R9
33⍀
DUTP36
11
31
39
INCK2
RP8, 10⍀
8
DCLKIN2
9
SPARES
RP5, 10⍀
7
10
RP8, 10⍀
7
10
Figure 45. Digital Input Signal Conditioning
REV. 0
2 3 4 5 6 7 8 9 10
1
DVDD
RP5, 10⍀
RP6, 10⍀
1
2 3 4 5 6 7 8 9 10
1
R9
33⍀
RP5, 10⍀
RP5, 10⍀
7
RCOM R1
RP5, 10⍀
RP5, 10⍀
5
R9
33⍀
2 3 4 5 6 7 8 9 10
1
RP11
RCOM R1
RP5, 10⍀
RP5, 10⍀
3
R9
22⍀
2 3 4 5 6 7 8 9 10
1
INP1
RP13
RP1
RCOM R1
–19–
AD9709
DUT AND ANALOG OUTPUT SIGNAL CONDITIONING
BL1
TP34
WHT
ACOM
DVDD
1
C1
2 VAL
1
C2
2 0.01F
NC = 5
3
C3
2 0.1F
1
AVDD
2
2
R11
VAL
3
A B
1:1
6
T1
JP8
MODE 48
2
DB12P1
AVDD 47
3
DB11P1
IA1 46
1
DUTP2
DUTP3
DUTP4
1
DB13P1MSB
DUTP1
4
DB10P1
2
BL2
3
A B
1
2
C4 2
10pF 1
5
DB9P1
FSADJ1 44
DUTP6
6
DB8P1
REFIO 43
DUTP7
7
DB7P1
GAINCTRL 42
2
R6
50⍀
C5 2
10pF 1
TP45
WHT
R9
1.92k⍀
1
C16
22nF
8
DB6P1
FSADJ2 41
C17
22nF
2
1
R10
1.92k⍀
DUTP9
9
DB5P1
IA2 40
10
DB4P1
IB2 39
DUTP11
11
DB3P1
ACOM 38
DUTP12
12
DB2P1
SLEEP 37
SLEEP
DUTP13
13
DB1P1
DB0P2 36
DUTP36
DUTP14
14
DB0P1
DB1P2 35
DUTP35
U2
2
1
DUTP10
WRT1
1
R5
50⍀
IB1 45
DUTP5
DUTP8
S6
OUT1
AGND;3,4,5
1
MODE
DVDD
4
JP15
1
15
DCOM1
DB2P2 34
DUTP34
16
DVDD1
DB3P2 33
DUTP33
17
WRT1
DB4P2 32
DUTP32
CLK1
18
CLK1
DB5P2 31
DUTP31
CLK2
19
CLK2
DB6P2 30
DUTP30
WRT2
20
WRT2
DB7P2 29
DUTP29
21
DCOM2
DB8P2 28
DUTP28
22
DVDD2
DB9P2 27
DUTP27
DUTP23
23
DB13P2MSB
DB10P2 26
DUTP26
DUTP24
24
DB12P2
DB11P2 25
DUTP25
C15 2
10pF 1
1
C6 2
10pF 1
1
2
1
R7
50⍀
2
R8
50⍀
2
R15
256⍀
1
REFIO
2
TP36
WHT
R14
256⍀
1
1
2
2
C14
0.1F
JP10
2
WHT
TP46
BL3
TP35
WHT
3
R12
VAL
2
NC = 5
4
1:1
1
S11
OUT2
AGND;3,4,5
6
T2
BL4
AVDD
1
C11
2 1F
1
C12
2 0.01F
1
C13
2 0.1F
Figure 46. AD9709 and Output Signal Conditioning
–20–
REV. 0
AD9709
Figure 47. Assembly, Top Side
REV. 0
–21–
AD9709
Figure 48. Assembly, Bottom Side
–22–
REV. 0
AD9709
Figure 49. Layer 1, Top Side
REV. 0
–23–
AD9709
Figure 50. Layer 2, Ground Plane
–24–
REV. 0
AD9709
Figure 51. Layer 3, Power Plane
REV. 0
–25–
AD9709
Figure 52. Layer 4, Bottom Side
–26–
REV. 0
AD9709
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
0ⴗ
MIN
12
25
13
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
24
C3701–8–5/00 (rev. 0) 00606
48-Lead Thin Plastic Quad Flatpack (LQFP)
(ST-48)
0.011 (0.27)
0.006 (0.17)
0.057 (1.45)
0.053 (1.35)
7ⴗ
0ⴗ
PRINTED IN U.S.A.
0.006 (0.15) SEATING
0.002 (0.05) PLANE
REV. 0
–27–