EL5170, EL5370 ® Data Sheet September 14, 2010 100MHz Differential Twisted-Pair Drivers Features The EL5170 and EL5370 are single and triple high bandwidth amplifiers with a fixed gain of 2. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The inputs signal can be in either single-ended or differential form but the outputs are always in differential form. • Fully differential inputs and outputs The output common mode level for each channel is set by the associated VREF pin, which have a -3dB bandwidth of over 70MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL5170 and EL5370 are specified for operation over the full -40°C to +85°C temperature range. Pinouts IN+ 1 IN- 3 REF 4 • Differential input range ±2.3V typ. • 100MHz 3dB bandwidth at fixed gain of 2 • 1100V/µs slew rate • Single 5V or dual ±5V supplies • 50mA maximum output current • Low power - 7.4mA per channel • Pb-free available (RoHS compliant) Applications • Twisted-pair drivers • Differential line drivers • VGA over twisted-pairs EL5370 (24 LD QSOP) TOP VIEW EL5170 (8 LD SOIC, MSOP) TOP VIEW EN 2 FN7309.8 EN 1 8 OUT+ + - INP1 2 7 VS6 VS+ 5 OUT- + - • Single ended to differential amplification 24 OUT1 22 NC REF1 4 21 VSP NC 5 20 VSN INN2 7 REF2 8 19 NC + - NC 9 INP3 10 INN3 11 REF3 12 • Transmission of analog signals in a noisy environment 23 OUT1B INN1 3 INP2 6 1 • ADSL/HDSL drivers 18 OUT2 17 OUT2B 16 NC + - 15 OUT3 14 OUT3B 13 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2003, 2004, 2006, 2007, 2010. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5170, EL5370 Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # EL5170IS 5170IS 5170IS 8 Ld SOIC (150 mil) M8.15E EL5170IS-T7* 5170IS 5170IS 8 Ld SOIC (150 mil) M8.15E EL5170ISZ (Note) 5170ISZ 5170ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E EL5170ISZ-T7* (Note) 5170ISZ 5170ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E EL5170ISZ-T13* (Note) 5170ISZ 5170ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E EL5170IY-T7* g g 8 Ld MSOP (3.0mm) M8.118A EL5170IYZ (Note) BAAVA BAAVA 8 Ld MSOP (3.0mm) (Pb-free) M8.118A EL5170IYZ-T7* (Note) BAAVA BAAVA 8 Ld MSOP (3.0mm) (Pb-free) M8.118A EL5170IYZ-T13* (Note) BAAVA BAAVA 8 Ld MSOP (3.0mm) (Pb-free) M8.118A EL5370IU EL5370IU EL5370IU 24 Ld QSOP (150 mil) MDP0040 EL5370IUZ (Note) EL5370IUZ EL5370IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5370IUZ-T7* (Note) EL5370IUZ EL5370IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5370IUZ-T13* (Note) EL5370IUZ EL5370IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7309.8 September 14, 2010 EL5170, EL5370 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . 1V/µs Input Voltage (IN+, IN- to VS+, VS-). . . . . . VS- - 0.3V to VS+ + 0.3V Differential Input Voltage (IN+ to IN-) . . . . . . . . . . . . . . . . . . . . ±4.8V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C Recommended Operating Temperature . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, AV = 2, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth 100 MHz BW ± 0.1dB Bandwidth 12 MHz SR Slew Rate VOUT = 2VP-P, 20% to 80% 1100 V/µs tSTL Settling Time to 0.1% VOUT = 2VP-P 20 ns tOVR Output Overdrive Recovery time 40 ns 800 VREFBW (-3dB) VREF -3dB Bandwidth AV =1, CLD = 2.7pF 70 MHz VREFSR+ VREF Slew Rate - Rise VOUT = 2VP-P, 20% to 80% 125 V/µs VREFSR- VREF Slew Rate - Fall VOUT = 2VP-P, 20% to 80% 65 V/µs VN Input Voltage Noise f = 10kHz 28 nV/√Hz HD2 Second Harmonic Distortion VOUT = 2VP-P, 1MHz -79 dBc HD2 Second Harmonic Distortion VOUT = 2VP-P, 10MHz -65 dBc HD3 Third Harmonic Distortion VOUT = 2VP-P, 1MHz -62 dBc HD3 Third Harmonic Distortion VOUT = 2VP-P, 10MHz -43 dBc dG Differential Gain at 3.58MHz RLD = 300Ω, AV = 2 0.14 % dθ Differential Phase at 3.58MHz RLD = 300Ω, AV = 2 0.38 ° eS Channel Separation - For EL5370 only at f = 1MHz 85 dB INPUT CHARACTERISTICS VOS Input Referred Offset Voltage IIN Input Bias Current (VIN, VINB) IREF Input Bias Current at REF Pin Gain Gain Accuracy RIN Differential Input Resistance CIN Differential Input Capacitance DMIR Differential Mode Input Range CMIR+ Common Mode Positive Input Range at VIN+, VIN- CMIR- Common Mode Negative Input Range at VIN+, VIN- VREFIN Reference Input Voltage Range - Positive ±6 ±25 mV -10 -6 -2 µA VREF = +3.2V 0.5 1.25 3 µA VREF = -3.2V -1 0 +1 µA 1.98 2 2.02 V VIN = ±1V Reference Input Voltage Range - Negative 3 300 kΩ 1 pF ±2.1 ±2.3 V 3.2 3.4 V -4.5 VIN+ = VIN- = 0V 3.4 -4.2 3.8 -3.3 V V -3 V FN7309.8 September 14, 2010 EL5170, EL5370 Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, AV = 2, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS VREFOS Output Offset Relative to VREF CMRR Input Common Mode Rejection Ratio MIN TYP MAX UNIT -140 60 +140 mV VIN = ±2.5V 65 84 dB RLD = 200Ω 3.3 3.6 V OUTPUT CHARACTERISTICS VOUT Positive Output Voltage Swing Negative Output Voltage Swing IOUT(Max) -3.3 Maximum Output Current V RL = 10Ω (EL5170) ±50 ±80 mA RL = 10Ω (EL5370) ±70 ±85 mA 60 mΩ Output Impedance ROUT -3 SUPPLY VSUPPLY Supply Operating Range IS(ON) Power Supply Current - Per Channel IS(OFF)+ Positive Power Supply Current - Disabled IS(OFF)- Negative Power Supply Current - Disabled IS(OFF)+ Positive Power Supply Current - Disabled IS(OFF)- Negative Power Supply Current - Disabled PSRR Power Supply Rejection Ratio VS+ to VS- 4.75 11 V 6 7.4 8.4 mA 60 80 100 µA -150 -120 -90 µA 0.5 2 5 µA -150 -120 -90 µA VS from ±4.5V to ±5.5V (EL5170) 70 83 dB VS from ±4.5V to ±5.5V (EL5370) 65 83 dB EN pin tied to 4.8V (EL5170) EN pin tied to 4.8V (EL5370) ENABLE tEN Enable Time 200 ns tDS Disable Time 1 µs VIH EN Pin Voltage for Power-Up VIL EN Pin Voltage for Shutdown IIH-EN EN Pin Input Current High - Per Channel At VEN = 5V IIL-EN EN Pin Input Current Low - Per Channel At VEN = 0V VS+ -1.5 VS+ -0.5 V 40 -6 V 50 -3 µA µA Pin Descriptions EL5170 EL5370 1 PIN NAME PIN FUNCTION IN+ Non-inverting input EN Enable 3 IN- Inverting input 4 REF Reference input, sets common-mode output voltage 5 OUT- Inverting output 6 VS+ Positive supply 7 VS- Negative supply 8 OUT+ Non-inverting output 2, 6, 10 INP1, INP2, INP3 Non-inverting inputs 3, 7, 11 INN1, INN2, INN3 Inverting inputs 4, 8, 12 REF1, REF2, REF3 14, 17, 23 OUT3B, OUT2B, OUT1B 2 1 4 Reference input, sets common-mode output voltage Inverting outputs FN7309.8 September 14, 2010 EL5170, EL5370 Pin Descriptions (Continued) EL5170 EL5370 PIN NAME PIN FUNCTION 21 VSP Positive supply 20 VSN Negative supply 15, 18, 24 OUT3, OUT2, OUT1 5, 9, 13, 16, 19, 22 NC Non-inverting outputs No connects; grounded for best crosstalk performance Typical Performance Curves CLD = 1pF, VODP-P = 200mV 10 9 9 8 8 7 7 6 VOP-P = 200mV 5 4 3 GAIN (dB) GAIN (dB) VS = ±5V, AV = 2, RLD = 200Ω, CLD = 1pF 10 5 4 RLD = 200Ω 2 1 0 100k 1M 10M 100M 0 100k 1G VS = ±5V, RLD = 200Ω, VODP-P = 200mV 2 GAIN (dB) 7 6 VREF = 1VP-P -4 -5 2 1 100k 0 -1 -3 CLD = 0pF VREF = 200mVP-P 1 -2 CLD = 20pF 4 3 1G 3 CLD = 40pF 5 100M 4 CLD = 75pF 8 10M FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE vs RLD 11 9 1M FREQUENCY (Hz) FIGURE 1. FREQUENCY RESPONSE 10 RLD = 100Ω 1 VOP-P = 1V FREQUENCY (Hz) GAIN (dB) RLD = 500Ω 6 3 VOP-P = 2V 2 RLD = 1kΩ 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE vs CLD 5 -6 1M 10M 100M FREQUENCY (Hz) FIGURE 4. FREQUENCY RESPONSE vs VREF FN7309.8 September 14, 2010 EL5170, EL5370 Typical Performance Curves (Continued) 100Ω VINCM + - VODM VOCM 100Ω -10 COMMON MODE REJECTION (dB) 0 -10 -20 PSRR (dB) -30 -40 -50 PSRR- -60 -70 PSRR+ -80 -90 100k 1M 10M -20 -30 -40 -50 VOCM/VINCM -60 -70 VODM/VINCM -80 -90 100k 100M 1M FREQUENCY (Hz) 10M 100M FREQUENCY (Hz) FIGURE 5. POWER SUPPLY REJECTION RATIO vs FREQUENCY FIGURE 6. COMMON MODE REJECTION vs FREQUENCY 100Ω VIN + - RT VCM VODM R 100Ω 1000 -10 VOLTAGE NOISE (nV/√Hz) BALANCE ERROR (dB) 0 -20 -30 -40 -50 -60 100k VOCM/VODM 1M 10M 100 10 10 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 8. INPUT VOLTAGE NOISE vs FREQUENCY FIGURE 7. DIFFERENTIAL MODE OUTPUT BALANCE ERROR vs FREQUENCY RLD = 200Ω 110 -50 -60 -70 105 CH2 <=> CH1 CH3 <=> CH2 100 CH2 <=> CH3 BW (MHz) CHANNEL ISOLATION (dB) -40 CH1<=> CH2 -80 90 -90 CH3 <=> CH1 85 -100 -110 100k 95 CH1 <=> CH3 1M 10M 100M FREQUENCY (Hz) FIGURE 9. CHANNEL ISOLATION vs FREQUENCY 6 80 4 5 6 7 8 9 10 11 12 VS (V) FIGURE 10. BANDWIDTH vs SUPPLY VOLTAGE FN7309.8 September 14, 2010 EL5170, EL5370 Typical Performance Curves (Continued) 7.78 -30 VS = ±5V, RLD = 200Ω, VOP-P = 2V 7.76 DISTORTION (dB) 7.72 IS (mA) HD3 -40 IS+ 7.74 7.70 IS- 7.68 7.66 7.64 7.62 -50 -60 HD2 -70 -80 7.60 7.58 4 5 6 8 7 9 10 11 -90 0M 2M FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE 0.5V/DIV 4M 6M 8M 10M 12M 14M 16M 18M 20M FREQUENCY (Hz) VS (V) FIGURE 12. HARMONIC DISTORTION vs FREQUENCY 500mV/DIV 40ns/DIV FIGURE 13. VCOM TRANSIENT RESPONSE 20ns/DIV FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE 100mV/DIV 20ns/DIV FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE 7 FIGURE 16. DISABLED RESPONSE FN7309.8 September 14, 2010 EL5170, EL5370 Typical Performance Curves (Continued) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 1.2 1.0 870mW 0.8 QSOP24 θJA = +115°C/W 625mW 0.6 SO8 θJA = +160°C/W 0.4 486mW MSOP8 θJA = +206°C/W 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 17. ENABLED RESPONSE POWER DISSIPATION (W) 1.4 FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.136W 1.0 909mW 0.8 QSOP24 θJA = +88°C/W SO8 θJA = +110°C/W 870mW 0.6 MSOP8/10 θJA = +115°C/W 0.4 0.2 0 0 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Simplified Schematic 200Ω VS+ R1 IN+ R3 R2 IN- FBP R4 R7 R8 FBN VB1 OUT+ RCD REF RCD OUT- VB2 CC R9 R10 CC R5 R6 VS- 400Ω 8 200Ω FN7309.8 September 14, 2010 EL5170, EL5370 Description of Operation and Application Information Product Description The EL5170 and EL5370 are wide bandwidth, low power and single/differential ended to differential output amplifiers. They have a fixed gain of 2. The EL5170 is a single channel differential amplifier. The EL5370 is a triple channel differential amplifier. The EL5170 and EL5370 have a -3dB bandwidth of 100MHz while driving a 200Ω differential load. The EL5170 and EL5370 are available with a power-down feature to reduce the power while the amplifiers are disabled. Input, Output and Supply Voltage Range The EL5170 and EL5370 have been designed to operate with a single supply voltage of 5V to 10V or split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.5V to 3.4V for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.8V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to become distorted. The output of the EL5170 and EL5370 can swing from -3.3V to 3.6V at 200Ω differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. Differential and Common Mode Gain Settings As shown in the “Simplified Schematic” on page 8, since the feedback resistors RF and the gain resistor are integrated with 200Ω and 400Ω, the EL5170 and EL5370 have a fixed gain of 2. The common mode gain is always one. Driving Capacitive Loads and Cables The EL5170 and EL5370 can drive 75pF differential capacitor in parallel with 200Ω differential load with less than 3.5dB of peaking. If less peaking is desired in applications, a small series resistor (usually between 5Ω to 50Ω) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier’s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. 120µA for IS- typically, thereby effectively eliminating the power consumption. The amplifier’s power-down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above VS+ -0.5V. Output Drive Capability The EL5170 and EL5370 have internal short circuit protection. Its typical short circuit current is ±80mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±60mA. This limit is set by the design of the internal metal interconnect. Power Dissipation With the high output drive capability of the EL5170 and EL5370 it is possible to exceed the +125°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1: T JMAX – T AMAX PD MAX = --------------------------------------------Θ JA Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or as expressed in Equation 2: ΔV O⎞ ⎛ PD = i × ⎜ V S × I SMAX + V S × ------------⎟ R LD ⎠ ⎝ (EQ. 2) Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current per channel ΔVO = Maximum differential output voltage of the application Disable/Power-Down RLD = Differential load resistance The EL5170 and EL5370 can be disabled and their outputs placed in a high impedance state. The turn-off time is about 1µs and the turn-on time is about 200ns. When disabled, the amplifier’s supply current is reduced to 2µA for IS+ and ILOAD = Load current 9 (EQ. 1) i = Number of channels FN7309.8 September 14, 2010 EL5170, EL5370 By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier’s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Typical Applications 0Ω 50 IN+ VFB 50Ω EL5170/ EL5370 VIN 50 IN- ZO = 100Ω EL5172/ EL5372 VINB 50Ω VOUT VREF FIGURE 20. TWISTED PAIR DRIVER 0Ω 50Ω VIN VIN 50Ω COAX IN+ VOUT + EL5170/EL5370 50Ω IN- VOUTB VREF 50Ω COAX 50Ω VFB VIN EL5172/EL5372 VINB VOUT VREF 50Ω FIGURE 21. DUAL COAXIAL CABLE DRIVER 10 FN7309.8 September 14, 2010 EL5170, EL5370 10V 10k VIN 10k 50Ω IN+ TWISTED PAIR EL5170/EL5370 100Ω VOUT IN- ZO = 100Ω VREF 10k 50Ω 10k FIGURE 22. SINGLE SUPPLY TWISTED PAIR DRIVER 50Ω IN+ A TWISTED PAIR EL5172/ EL5372 A EL5172 B 50 EL5170/EL5370 INVREF 50Ω ZO = 100Ω 50 B FIGURE 23. DUAL SIGNAL TRANSMISSION CIRCUIT 11 FN7309.8 September 14, 2010 EL5170, EL5370 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 12 FN7309.8 September 14, 2010 EL5170, EL5370 Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 3.0±0.1 8 A 0.25 CAB 3.0±0.1 4.9±0.15 DETAIL "X" 1.10 Max PIN# 1 ID B SIDE VIEW 2 1 0.18 ± 0.05 2 0.65 BSC TOP VIEW 0.95 BSC 0.86±0.09 H GAUGE PLANE C 0.25 SEATING PLANE 0.33 +0.07/ -0.08 0.08 C A B 0.10 ± 0.05 3°±3° 0.10 C 0.55 ± 0.15 DETAIL "X" SIDE VIEW 1 5.80 NOTES: 4.40 3.00 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.25mm max per side are not included. 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. 6. This replaces existing drawing # MDP0043 MSOP 8L. 0.65 0.40 1.40 TYPICAL RECOMMENDED LAND PATTERN 13 FN7309.8 September 14, 2010 EL5170, EL5370 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN7309.8 September 14, 2010