10 MHz, 20 V/μs, G = 1, 2, 4, 8 i CMOS® Programmable Gain Instrumentation Amplifier AD8251 FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR Small package: 10-lead MSOP Programmable gains: 1, 2, 4, 8 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 98 dB (minimum), G = 8 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.8 μV/°C (maximum), G = 8 Excellent ac performance Fast settling time: 785 ns to 0.001% (maximum) High slew rate: 20 V/μs (minimum) Low distortion: −110 dB THD at 1 kHz,10 V swing High CMRR over frequency: 80 dB to 50 kHz (minimum) Low noise: 18 nV/√Hz, G = 10 (maximum) Low power: 4 mA 2 4 7 OUT +IN 10 8 3 9 +VS –VS REF 06287-001 AD8251 Figure 1. 25 20 Data acquisition Biomedical analysis Test and measurement G=8 15 GAIN (dB) G=4 GENERAL DESCRIPTION The AD8251 user interface consists of a parallel port that allows users to set the gain in one of two different ways (see Figure 1 for the functional block diagram). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use transparent gain mode where the state of logic levels at the gain port determines the gain. A0 5 LOGIC –IN 1 APPLICATIONS 10 G=2 5 G=1 0 –5 06287-002 The AD8251 is an instrumentation amplifier with digitally programmable gains that has GΩ input impedance, low output noise, and low distortion, making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (ADCs). It has high bandwidth of 10 MHz, low THD of −110 dB, and fast settling time of 785 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C, respectively, for G = 8. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB at G = 1 from dc to 50 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8251 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. A1 6 –10 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 2. Gain vs. Frequency Table 1. Instrumentation and Difference Amplifiers by Category High Performance AD82201 AD8221 AD8222 AD82241 1 Low Cost AD6231 AD85531 High Voltage AD628 AD629 Mil Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 Digital Gain AD82311 AD8250 AD85551 AD85561 AD85571 Rail-to-rail output. The AD8251 is available in a 10-lead MSOP package and is specified over the −40°C to +85°C temperature range, making it an excellent solution for applications where size and packing density are important considerations. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD8251 TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Regulation and Bypassing ................................ 18 Applications....................................................................................... 1 Input Bias Current Return Path ............................................... 18 General Description ......................................................................... 1 Input Protection ......................................................................... 18 Functional Block Diagram .............................................................. 1 Reference Terminal .................................................................... 19 Revision History ............................................................................... 2 Common-Mode Input Voltage Range ..................................... 19 Specifications..................................................................................... 3 Layout .......................................................................................... 19 Timing Diagram ........................................................................... 5 RF Interference ........................................................................... 19 Absolute Maximum Ratings............................................................ 6 Driving an Analog-to-Digital Converter ................................ 20 Maximum Power Dissipation ..................................................... 6 Applications..................................................................................... 21 ESD Caution.................................................................................. 6 Differential Output .................................................................... 21 Pin Configuration and Function Descriptions............................. 7 Setting Gains with a Microcontroller ...................................... 21 Typical Performance Characteristics ............................................. 8 Data Acquisition......................................................................... 22 Theory of Operation ...................................................................... 16 Outline Dimensions ....................................................................... 23 Gain Selection ............................................................................. 16 Ordering Guide .......................................................................... 23 REVISION HISTORY 5/07—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8251 SPECIFICATIONS +VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance G=1 G=2 G=4 G=8 CMRR to 50 kHz G=1 G=2 G=4 G=8 NOISE Voltage Noise, 1 kHz, RTI G=1 G=2 G=4 G=8 0.1 Hz to 10 Hz, RTI G=1 G=2 G=4 G=8 Current Noise, 1 kHz Current Noise, 0.1 Hz to 10 Hz VOLTAGE OFFSET Offset RTI VOS Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR) INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G=2 G=4 G=8 Settling Time 0.01% G=1 G=2 G=4 G=8 Conditions Min Typ 80 86 92 98 94 104 105 105 Max Unit +IN = −IN = −10 V to +10 V dB dB dB dB +IN = −IN = −10 V to +10 V 80 84 86 86 dB dB dB dB 40 27 22 18 nV/√Hz nV/√Hz nV/√Hz nV/√Hz 2.5 2.5 1.8 1.2 μV p-p μV p-p μV p-p μV p-p pA/√Hz pA p-p ±200 + 600/G ±260 + 900/G ±1.2 + 5/G ±6 + 20/G μV μV μV/°C μV/V 30 40 400 30 30 160 nA nA pA/°C nA nA pA/°C 5 60 G = 1, 2, 4, 8 T = −40°C to +85°C T = −40°C to +85°C VS = ±5 V to ±15 V 5 T = −40°C to +85°C T = −40°C to +85°C 5 T = −40°C to +85°C T = −40°C to +85°C 10 10 8 2.5 MHz MHz MHz MHz ΔOUT = 10 V step 615 460 460 625 Rev. 0 | Page 3 of 24 ns ns ns ns AD8251 Parameter Settling Time 0.001% G=1 G=2 G=4 G=8 Slew Rate G=1 G=2 G=4 G=8 Total Harmonic Distortion + Noise GAIN Gain Range Gain Error G=1 G = 2, 4, 8 Gain Nonlinearity G=1 G=2 G=4 G=8 Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output DIGITAL LOGIC Digital Ground Voltage, DGND Digital Input Voltage Low Digital Input Voltage High Digital Input Current Gain Switching Time 1 tSU tHD t WR -LOW t WR -HIGH Conditions ΔOUT = 10 V step Min Typ Max Unit 785 700 700 770 ns ns ns ns 20 30 30 30 −110 f = 1 kHz, RL = 10 kΩ, ±10V, G = 1, 10 Hz to 22 kHz bandpass filter G = 1, 2, 4, 8 OUT = ±10 V V/μs V/μs V/μs V/μs dB 1 OUT = −10 V to +10 V RL = 10 kΩ, 2 kΩ, 600 Ω RL = 10 kΩ, 2 kΩ, 600 Ω RL = 10 kΩ, 2 kΩ, 600 Ω RL = 10 kΩ, 2 kΩ, 600 Ω All gains 3 8 V/V 0.03 0.04 % % 9 12 12 15 10 ppm ppm ppm ppm ppm/°C GΩ||pF GΩ||pF V V 1||2pF 1||2pF VS = ±5 V to ±15 V T = −40°C to +85°C −VS + 1.5 −VS + 1.6 +VS − 1.5 +VS − 1.7 T = −40°C to +85°C −13.5 −13.5 +13.5 +13.5 37 20 +IN, −IN, REF = 0 1 +VS −VS 1 ± 0.0001 Referred to GND Referred to GND Referred to GND −VS + 4.25 DGND 2.8 0 +VS − 2.7 2.1 +VS 1 325 See Figure 3 timing diagram Rev. 0 | Page 4 of 24 20 10 20 40 V V mA kΩ μA V V/V V V V μA ns ns ns ns ns AD8251 Parameter POWER SUPPLY Operating Range Quiescent Current, +IS Quiescent Current, −IS Over Temperature TEMPERATURE RANGE Specified Performance 1 Conditions Min Typ Max Unit 4.1 3.7 ±15 4.5 4.5 4.5 V mA mA mA +85 °C ±5 T = −40°C to +85°C −40 Add time for the output to slew and settle to calculate the total time for a gain change. TIMING DIAGRAM tWR-HIGH tWR-LOW WR tSU tHD 06287-003 A0, A1 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Rev. 0 | Page 5 of 24 AD8251 ABSOLUTE MAXIMUM RATINGS package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). Table 3. Rating ±17 V See Figure 4 Indefinite1 ±VS ±VS ±VS –65°C to +125°C –40°C to +85°C 300°C 140°C 112°C/W 140°C The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power) ⎛V V PD = (VS × I S ) + ⎜ S × OUT ⎜ 2 RL ⎝ ⎞ VOUT 2 ⎟– ⎟ RL ⎠ In single-supply operation with RL referenced to −VS, the worst case is VOUT = VS/2. Assumes the load is referenced to midsupply. 2 Temperature for specified performance is −40°C to +85°C. For performance to +125°C, see the Typical Performance Characteristics section. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8251 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8251. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θJA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board. 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 –40 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION TJ = TA + (PD × θ JA ) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the Rev. 0 | Page 6 of 24 06287-004 1 MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Power Dissipation Output Short-Circuit Current Common-Mode Input Voltage Differential Input Voltage Digital Logic Inputs Storage Temperature Range Operating Temperature Range2 Lead Temperature (Soldering 10 sec) Junction Temperature θJA (4-Layer JEDEC Standard Board) Package Glass Transition Temperature AD8251 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 DGND 2 AD8251 10 +IN 9 REF 8 +VS TOP VIEW A0 4 (Not to Scale) 7 OUT A1 5 6 WR 06287-005 –VS 3 Figure 5. 10-Lead MSOP (RM-10) Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic −IN DGND −VS A0 A1 WR OUT +VS REF +IN Description Inverting Input Terminal. True differential input. Digital Ground. Negative Supply Terminal. Gain Setting Pin (LSB). Gain Setting Pin (MSB). Write Enable. Output Terminal. Positive Supply Terminal. Reference Voltage Terminal. Noninverting Input Terminal. True differential input. Rev. 0 | Page 7 of 24 AD8251 TYPICAL PERFORMANCE CHARACTERISTICS TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. 2700 800 2400 700 NUMBER OF UNITS 1800 1500 1200 900 500 400 300 200 600 100 06287-006 300 0 600 –120 –90 –60 –30 0 30 60 90 0 120 06287-009 NUMBER OF UNITS 2100 –30 –20 –10 0 10 20 30 INPUT OFFSET CURRENT (nA) CMRR (µV/V) Figure 9. Typical Distribution of Input Offset Current Figure 6. Typical Distribution of CMRR, G = 1 90 500 80 300 200 0 06287-007 100 –200 –100 0 100 60 50 G=1 40 30 G=2 20 G=4 G=8 10 0 200 1 10 INPUT OFFSET VOLTAGE, VOSI , RTI (µV) 100 1k 06287-010 NOISE (nV/√Hz) NUMBER OF UNITS 70 400 10k 100k FREQUENCY (Hz) Figure 7. Typical Distribution of Offset Voltage, VOSI Figure 10. Voltage Spectral Density Noise vs. Frequency 600 400 0 –30 –20 –10 0 10 20 2µV/DIV 1s/DIV 30 INPUT BIAS CURRENT (nA) Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Figure 8. Typical Distribution of Input Bias Current Rev. 0 | Page 8 of 24 06287-011 200 06287-008 NUMBER OF UNITS 800 AD8251 150 130 G=4 PSRR (dB) 110 90 G=2 G=1 70 G=8 50 06287-016 06287-012 30 1s/DIV 1.25µV/DIV 10 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 8 Figure 15. Positive PSRR vs. Frequency, RTI 150 18 16 130 14 G=4 PSRR (dB) 10 8 6 G=8 90 70 G=1 50 4 G=2 1 10 100 1k 10k 06287-017 06287-013 2 0 30 10 10 100k 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Current Noise Spectral Density vs. Frequency Figure 16. Negative PSRR vs. Frequency, RTI 20 INPUT BIAS CURRENT (nA) 15 IB+ 10 5 IB– 0 IOS 140pA/DIV 1s/DIV –10 –60 06287-019 –5 06287-014 NOISE (pA/√Hz) 110 12 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (ºC) Figure 14. 0.1 Hz to 10 Hz Current Noise Figure 17. Input Bias Current and Offset Current vs. Temperature Rev. 0 | Page 9 of 24 AD8251 140 25 G=4 VS = ±15V VIN = 200m Vp-p RLOAD = 2kΩ G=8 20 G=8 120 15 G=2 GAIN (dB) CMRR (dB) G=4 100 80 10 G=2 5 G=1 G=1 0 60 40 10 100 1k 10k 100k 06287-023 06287-020 –5 –10 1k 1M 10k 100k FREQUENCY (Hz) 1M 100M 10M FREQUENCY (Hz) Figure 18. CMRR vs. Frequency Figure 21. Gain vs. Frequency 140 40 30 NONLINEARITY (10ppm/DIV) 120 100 G=4 G=2 80 G=1 60 100 1k 10k 100k 10 0 –10 –20 –30 06287-021 40 10 20 –40 –10 1M 06287-024 CMRR (dB) G=8 –8 –6 –4 2 4 6 8 10 40 15 30 NONLINEARITY (10ppm/DIV) 10 5 0 –5 –10 –30 –10 10 30 50 70 90 110 20 10 0 –10 –20 –40 –10 130 06287-025 –30 06287-022 ΔCMRR (µV/V) 0 Figure 22. Gain Nonlinearity, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω Figure 19. CMRR vs. Frequency, 1 kΩ Source Imbalance –15 –50 –2 OUTPUT VOLTAGE (V) FREQUENCY (Hz) –8 –6 –4 –2 0 2 4 6 8 OUTPUT VOLTAGE (V) TEMPERATURE (°C) Figure 23. Gain Nonlinearity, G = 2, RL = 10 kΩ, 2 kΩ, 600 Ω Figure 20. CMRR vs. Temperature, G = 1 Rev. 0 | Page 10 of 24 10 40 16 30 12 COMMON-MODE VOLTAGE (V) 20 10 0 –10 –20 –8 –6 –4 –2 0 2 4 6 8 VS ±15V 8 –4V, +4V 4 –4 –4V, –3.9V –12 –8 –1 INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES NONLINEARITY (10ppm/DIV) 30 20 10 0 –10 –20 06287-027 –30 –2 0 2 4 6 8 –40°C +1 +125°C 4 6 8 12 16 14 +VS 10 +4V, +2V CURRENT (mA) –4V, –2V –4 +85°C 10 +14V, +7V VS = ±5V 0 +25°C Figure 28. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 kΩ +4V, –2V 0V, –3.9V 5 FAULT CONDITION (OVER DRIVEN INPUT) G=8 FAULT CONDITION (OVER DRIVEN INPUT) G=8 +IN 0 –IN –5 –8 –12 –16 –16 –14.2V, –7.1V +14V, –7V 0V, –13.5V –12 –8 –4 0 4 8 12 –10 06287-028 COMMON-MODE VOLTAGE (V) –4V, +2.2V –40°C +2 8 4 16 12 15 0V, ±15V 0V, +3.85V 8 SUPPLY VOLTAGE (±VS) 0V, +13.5V –14.2V, +7.1V +13V, –13.5V 4 +125°C +25°C –2 –VS 10 Figure 25. Gain Nonlinearity, G = 8, RL = 10 kΩ, 2 kΩ, 600 Ω 12 0 +85°C OUTPUT VOLTAGE (V) 16 –4 06287-029 0V, –13.5V –13V, –13.1V Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 8 +VS –4 +4V, –4V OUTPUT VOLTAGE (V) 40 –6 0V, –3.9V –8 –16 –16 10 Figure 24. Gain Nonlinearity, G = 4, RL = 10 kΩ, 2 kΩ, 600 Ω –8 +4V, +3.9V VS = ±5V 0 OUTPUT VOLTAGE (V) –40 –10 0V, +4V 06287-030 –40 –10 +13V, +13V –12 06287-026 –30 0V, +13.5V –13V, +13.5V –15 –16 16 OUTPUT VOLTAGE (V) –VS –12 –8 –4 0 4 8 12 06287-031 NONLINEARITY (10ppm/DIV) AD8251 16 DIFFERENTIAL INPUT VOLTAGE (V) Figure 26. Input Common-Mode Voltage Range vs. Output Voltage, G = 1 Rev. 0 | Page 11 of 24 Figure 29. Fault Current Draw vs. Input Voltage, G = 8, RL = 10 kΩ AD8251 +VS OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +125°C –0.8 –1.0 –40°C +25°C +25°C –40°C +1.0 +0.8 +0.6 +85°C +0.4 +125°C 06287-032 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +85°C –0.6 +0.2 –VS +85°C –0.4 –0.4 4 6 8 10 12 14 +125°C –0.8 –1.2 +25°C –40°C –1.6 –2.0 +2.0 –40°C +1.6 +25°C +1.2 +0.8 +0.4 –VS 16 +85°C 4 +125°C 06287-035 +VS –0.2 6 8 SUPPLY VOLTAGE (±VS) 10 12 16 14 OUTPUT CURRENT (mA) Figure 30. Output Voltage Swing vs. Supply Voltage, G = 8, RL = 2 kΩ Figure 33. Output Voltage Swing vs. Output Current +VS NO LOAD +125°C +85°C –0.4 47pF 100pF –0.6 –0.8 –1.0 –40°C +25°C –40°C +1.0 +0.8 +0.4 +25°C +125°C +85°C +0.2 –VS 4 6 8 10 12 14 20mV/DIV 2µs/DIV 16 06287-036 +0.6 06287-033 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –0.2 SUPPLY VOLTAGE (±VS) Figure 31. Output Voltage Swing vs. Supply Voltage, G = 8, RL = 10 kΩ Figure 34. Small Signal Pulse Response for Various Capacitive Loads 15 +25°C +85°C –40°C +125°C 5V/DIV 5 0 585ns TO 0.01% 723ns TO 0.001% –5 0.002%/DIV –10 –40°C +85°C +25°C –15 100 1k 2µs/DIV 06287-037 +125°C 06287-034 OUTPUT VOLTAGE SWING (V) 10 10k LOAD RESISTANCE (Ω) Figure 32. Output Voltage Swing vs. Load Resistance Figure 35. Large Signal Pulse Response and Settling Time, G = 1, RL = 10 kΩ Rev. 0 | Page 12 of 24 AD8251 5V/DIV 400ns TO 0.01% 600ns TO 0.001% 25mV/DIV 2µs/DIV 06287-041 2µs/DIV 06287-038 0.002%/DIV Figure 39. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF Figure 36. Large Signal Pulse Response and Settling Time, G = 2, RL = 10 kΩ 5V/DIV 376ns TO 0.01% 640ns TO 0.001% 25mV/DIV 2µs/DIV 06287-042 2µs/DIV 06287-039 0.002%/DIV Figure 40. Small Signal Response, G = 2, RL = 2 kΩ, CL = 100 pF Figure 37. Large Signal Pulse Response and Settling Time, G = 4, RL = 10 kΩ 5V/DIV 364ns TO 0.01% 522ns TO 0.001% 25mV/DIV Figure 38. Large Signal Pulse Response and Settling Time, G = 8, RL = 10 kΩ 2µs/DIV Figure 41. Small Signal Response, G = 4, RL = 2 kΩ, CL = 100 pF Rev. 0 | Page 13 of 24 06287-043 2µs/DIV 06287-040 0.002%/DIV AD8251 1200 1000 TIME (ns) 800 SETTLED TO 0.001% 600 400 0 06287-047 2µs/DIV 200 06287-044 25mV/DIV SETTLED TO 0.01% 2 4 6 8 10 12 14 16 18 20 STEP SIZE (V) Figure 42. Small Signal Response, G = 8, RL = 2 kΩ, CL = 100 pF 1200 1200 1000 1000 SETTLED TO 0.001% 600 800 TIME (ns) 800 TIME (ns) Figure 45. Settling Time vs. Step Size, G = 4, RL = 10 kΩ SETTLED TO 0.01% SETTLED TO 0.001% 600 400 400 200 200 2 4 6 8 10 12 14 16 18 0 20 06287-048 0 06287-045 SETTLED TO 0.01% 2 4 6 STEP SIZE (V) 8 10 12 14 16 18 20 STEP SIZE (V) Figure 43. Settling Time vs. Step Size, G = 1, RL = 10 kΩ Figure 46. Settling Time vs. Step Size, G = 8, RL = 10 kΩ 1200 –50 –55 –60 1000 –65 –70 THD + N (dB) SETTLED TO 0.001% 600 400 SETTLED TO 0.01% –75 –80 –85 G=8 –90 G=4 –95 –100 –105 200 2 4 6 8 10 12 14 16 18 –115 –120 10 20 STEP SIZE (V) G=1 100 1k 06287-049 0 –110 06287-046 TIME (ns) 800 G=2 10k 100k FREQUENCY (Hz) Figure 44. Settling Time vs. Step Size, G = 2, RL = 10 kΩ Figure 47. Total Harmonic Distortion vs. Frequency, 10 Hz to 22 kHz Band-Pass Filter, 2 kΩ Load Rev. 0 | Page 14 of 24 1M AD8251 –50 –55 –60 –65 –75 –80 G=8 G=4 –85 G=2 –90 –95 –100 –105 –110 G=1 06287-050 THD + N (dB) –70 –115 –120 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 48. Total Harmonic Distortion vs. Frequency, 10 Hz to 500 kHz Band-Pass Filter, 2 kΩ Load Rev. 0 | Page 15 of 24 AD8251 THEORY OF OPERATION +VS +VS A0 A1 2.2kΩ +VS –IN –VS –VS 2.2kΩ 10kΩ A1 10kΩ –VS +VS DIGITAL GAIN CONTROL OUT A3 –VS +VS +VS 10kΩ A2 REF 2.2kΩ +VS –VS –VS +VS 2.2kΩ DGND WR –VS 06287-061 +IN 10kΩ –VS Figure 49. Simplified Schematic Transparent Gain Mode The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 50 shows an example of this gain setting method, referred to throughout the data sheet as transparent gain mode. Tie WR to the negative supply to engage transparent gain mode. In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. Table 5 is the truth table for transparent gain mode, and Figure 50 shows the AD8251 configured in transparent gain mode. All internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow THD. Laser trimmed resistors allow for a maximum gain error of less than 0.03% for G = 1 and minimum CMRR of 98 dB for G = 8. A pinout optimized for high CMRR over frequency enables the AD8251 to offer a guaranteed minimum CMRR over frequency of 80 dB at 50 kHz (G = 1). The balanced input reduces the parasitics that, in the past, had adversely affected CMRR performance. GAIN SELECTION +15V 10μF 0.1µF WR A1 A0 +IN REF –IN DGND Rev. 0 | Page 16 of 24 +5V G=8 AD8251 10μF This section shows users how to configure the AD8251 for basic operation. Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. Refer to the specifications table (Table 2) for the permissible voltage range of DGND. The gain of the AD8251 can be set using two methods. –15V +5V DGND 0.1µF –15V NOTE: 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −VS. THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 8. 06287-051 The AD8251 is a monolithic instrumentation amplifier based on the classic, three op amp topology, as shown in Figure 49. It is fabricated on the Analog Devices, Inc. proprietary iCMOS process that provides precision, linear performance, and a robust digital interface. A parallel interface allows users to digitally program gains of 1, 2, 4, and 8. Gain control is achieved by switching resistors in an internal, precision, resistor array (as shown in Figure 49). Although the AD8251 has a voltage feedback topology, gain bandwidth product increases for gains of 1, 2, and 4 because each gain has its own frequency compensation. This results in maximum bandwidth at higher gains. Figure 50. Transparent Gain Mode, A0 and A1 = High, G = 8 AD8251 Table 5. Truth Table Logic Levels for Transparent Gain Mode Table 6. Truth Table Logic Levels for Latched Gain Mode WR A1 A0 Gain WR A1 A0 Gain −VS −VS −VS −VS Low Low High High Low High Low High 1 2 4 8 High to Low High to Low High to Low High to Low Low to Low Low to High High to High Low Low High High X1 X1 X1 Low High Low High X1 X1 X1 Change to 1 Change to 2 Change to 4 Change to 8 No Change No Change No Change Latched Gain Mode Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8251 can be set using WR as a latch, allowing other devices to share A0 and A1. Figure 51 shows a schematic using this method, known as latched gain mode. The AD8251 is in this mode when WR is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 are read on the downward edge of the WR signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table listing in Table 6 for more on these gain changes. +15V WR 10μF 0.1µF A1 A1 A0 +IN +5V 0V +5V 0V WR + A0 G = PREVIOUS STATE +5V 0V G=8 AD8251 REF – –IN DGND –15V NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8. X = don’t care. On power-up, the AD8251 defaults to a gain of 1 when in latched gain mode. In contrast, if the AD8251 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 on power-up. Timing for Latched Gain Mode In latched gain mode, logic levels at A0 and A1 have to be held for a minimum setup time, tSU, before the downward edge of WR latches in the gain. Similarly, they must be held for a minimum hold time of tHD after the downward edge of WR to ensure that the gain is latched in correctly. After tHD, A0 and A1 may change logic levels but the gain does not change (until the next downward edge of WR). The minimum duration that WR can be held high is t WR-HIGH, and t WR-LOW is the minimum duration that WR can be held low. Digital timing specifications are listed in Table 2. The time required for a gain change is dominated by the settling time of the amplifier. A timing diagram is shown in Figure 52. When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8251. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board. DGND 0.1µF 06287-052 10μF 1 Figure 51. Latched Gain Mode, G = 8 tWR-HIGH tWR-LOW WR tSU tHD 06287-053 A0, A1 Figure 52. Timing Diagram for Latched Gain Mode Rev. 0 | Page 17 of 24 AD8251 INCORRECT POWER SUPPLY REGULATION AND BYPASSING The AD8251 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier. –VS –VS TRANSFORMER TRANSFORMER +VS +VS 10µF AD8251 A0 AD8251 REF VOUT AD8251 –VS REF –IN –VS THERMOCOUPLE DGND THERMOCOUPLE +VS 10µF –VS +VS C 06287-054 0.1µF REF 10MΩ LOAD DGND REF C 1 fHIGH-PASS = 2πRC AD8251 Figure 53. Supply Decoupling, REF, and Output Referred to Ground C REF INPUT BIAS CURRENT RETURN PATH The AD8251 input bias current must have a return path to its local analog ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created (see Figure 54). R AD8251 C REF R –VS –VS CAPACITIVELY COUPLED CAPACITIVELY COUPLED 06287-055 +IN AD8251 REF +VS 0.1µF +VS AD8251 Place a 0.1 μF capacitor close to each supply pin. A 10 μF tantalum capacitor can be used farther away from the part (see Figure 53) and, in most cases, it can be shared by other precision integrated circuits. WR A1 CORRECT +VS Figure 54. Creating an IBIAS Path INPUT PROTECTION All terminals of the AD8251 are protected against ESD. Note that 2.2 kΩ series resistors precede the ESD diodes as shown in Figure 49. They limit current into the diodes and allow for dc overload conditions 13 V above the positive supply and 13 V below the negative supply. An external resistor should be used in series with each of the inputs to limit current for voltages greater than 13 V beyond either supply rail. In either scenario, the AD8251 safely handles a continuous 6 mA current at room temperature. For applications where the AD8251 encounters extreme overload voltages, external series resistors and low leakage diode clamps such as BAV199Ls, FJH1100s, or SP720s should be used. Rev. 0 | Page 18 of 24 AD8251 REFERENCE TERMINAL Coupling Noise The reference terminal, REF, is at one end of a 10 kΩ resistor (see Figure 49). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8251 can interface with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +VS or −VS by more than 0.5 V. To prevent coupling noise onto the AD8251, follow these guidelines: For best performance, especially in cases where the output is not measured with respect to the REF terminal, source impedance to the REF terminal should be kept low because parasitic resistance can adversely affect CMRR and gain accuracy. INCORRECT • Do not run digital lines under the device. • Run the analog ground plane under the AD8251. • Shield fast switching signals with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. • Avoid crossover of digital and analog signals. • Connect digital and analog ground at one point only (typically under the ADC). • Power supply lines should use large traces to ensure a low impedance path. Decoupling is necessary; follow the guidelines listed in the Power Supply Regulation and Bypassing section. CORRECT Common-Mode Rejection AD8251 AD8251 The AD8251 has high CMRR over frequency, giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical in amps whose CMRR falls off around 200 Hz. They often need common-mode filters at the inputs to compensate for this shortcoming. The AD8251 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering. VREF VREF + – 06287-056 OP1177 Figure 55. Driving the Reference Pin COMMON-MODE INPUT VOLTAGE RANGE The three op amp architecture of the AD8251 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8251 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 26 and Figure 27 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. LAYOUT Grounding In mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. Designing with the AD8251 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PC board can cause an error. Therefore, use separate analog and digital ground planes. Only at one point, star ground, should analog and digital ground meet. The output voltage of the AD8251 develops with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground. Careful board layout maximizes system performance. To maintain high CMRR over frequency, lay out the input traces symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input pins and traces. Source resistance and capacitance should be placed as close to the inputs as possible. Should a trace cross the inputs (from another layer), it should be routed perpendicular to the input traces. RF INTERFERENCE RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, RC network placed at the input of the instrumentation amplifier, as shown in Figure 56. The filter limits the input signal bandwidth according to the following relationship: FilterFreq DIFF = FilterFreq CM = where CD ≥ 10 CC. Rev. 0 | Page 19 of 24 1 2 π R( 2C D + C C ) 1 2 π RC C AD8251 +15V 10µF CC R +IN VOUT AD8251 CD R REF –IN CC –15V 06287-057 10µF 0.1µF +15V Figure 56. RFI Suppression Values of R and CC should be chosen to minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at negative input degrades the CMRR of the AD8251. By using a value of CD that is 10 times larger than the value of CC, the effect of the mismatch is reduced and performance is improved. 10μF 0.1µF WR +12V A1 A0 +IN REF AD7612 1nF +5V –IN DRIVING AN ANALOG-TO-DIGITAL CONVERTER 0.1μF 0.1μF 49.9Ω AD8251 –12V ADR435 An instrumentation amplifier is often used in front of an analog-to-digital converter to provide CMRR. Usually, instrumentation amplifiers require a buffer to drive an ADC. However, the low output noise, low distortion, and low settle time of the AD8251 make it an excellent ADC driver. DGND 10μF Rev. 0 | Page 20 of 24 DGND 0.1µF 06287-058 0.1µF In this example, a 1 nF capacitor and a 49.9 Ω resistor create an antialiasing filter for the AD7612. The 1 nF capacitor also serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 49.9 Ω series resistor reduces the burden of the 1 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7612. Selecting too small a resistor improves the correlation between the voltage at the output of the AD8251 and the voltage at the input of the AD7612 but may destabilize the AD8251. A trade-off must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability. –15V Figure 57. Driving an ADC AD8251 APPLICATIONS When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC. DIFFERENTIAL OUTPUT In certain applications, it is necessary to create a differential signal. High resolution analog-to-digital converters often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference. SETTING GAINS WITH A MICROCONTROLLER +15V 10μF Figure 59 shows how to configure the AD8251 to output a differential signal. An op amp, the AD817, is used in an inverting topology to create a differential voltage. VREF sets the output midpoint according to the equation shown in the figure. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers. 0.1µF WR A1 A0 +IN MICROCONTROLLER + AD8251 REF – –IN DGND DGND 0.1µF 06287-059 10μF –15V Figure 58. Programming Gain Using a Microcontroller +12V 0.1μF AMPLITUDE WR +5V A1 A0 +IN AMPLITUDE + VOUTA = VIN + VREF 2 AD8251 VIN G=1 – 0.1μF REF DGND – –12V 4.99kΩ 10μF TIME 4.99kΩ –12V +12V +2.5V 0V –2.5V 10pF + AD817 0.1µF –12V +12V 0.1µF 10μF DGND VOUTB = –VIN + VREF 2 Figure 59. Differential Output with Level Shift Rev. 0 | Page 21 of 24 VREF 0V AMPLITUDE +2.5V 0V –2.5V TIME 06287-060 –5V AD8251 –70 DATA ACQUISITION –80 The AD8251 makes an excellent instrumentation amplifier for use in data acquisition systems. Its wide bandwidth, low distortion, low settling time, and low noise enable it to condition signals in front of a variety of 16-bit ADCs. –90 AMPLITUDE (dB) –100 Figure 61 shows a schematic of the AD825x data acquisition demonstration board. The quick slew rate of the AD8251 allows it to condition rapidly changing signals from the multiplexed inputs. An FPGA controls the AD7612, AD8251, and ADG1209. In addition, mechanical switches and jumpers allow users to pin strap the gains when in transparent gain mode. –110 –120 –130 –140 –150 06287-062 –160 –170 –180 This system achieved −106 dB of THD at 1 kHz and a signal-tonoise ratio of 91 dB during testing, as shown in Figure 60. 0 5 10 15 20 25 30 35 40 45 FREQUENCY (kHz) Figure 60. FFT of the AD825x DAQ Demo Board Using the AD8251 1 kHz Signal JMP +12V + +12V 0.1µF 10µF +CH2 +CH3 +CH4 –CH4 –CH3 –CH2 –CH1 806Ω 806Ω 806Ω 806Ω 806Ω 806Ω 806Ω +5V VDD 2kΩ 10µF 2 EN 4 S1A DGND DGND JMP +5V DGND 5 S2A 2kΩ 2 6 S3A ALTERA EPF6010ATC144-3 DGND 6 0Ω 7 S4A ADG1209 0Ω 9 11 S3B 0Ω CC +IN 8 10 S4B 0Ω CD –IN CC 15 12 S2B 13 –VS 10 1 + A1 4 A0 AD8251 VREF – +VS –VS 9 3 1 7 VOUT +IN 0Ω 49.9Ω AD7612 1nF C4 0.1µF C3 0.1µF 3 DGND ADR435 8 A0 S1B A1 VSS 16 5 WR +12V –12V JMP 0.1µF –12V +5V 2kΩ DGND JMP +5V R8 2kΩ 06287-067 +CH1 JMP –12V GND 14 806Ω + DGND Figure 61. Schematic of ADG1209, AD8251, and AD7612 in the AD825x DAQ Demo Board Rev. 0 | Page 22 of 24 50 AD8251 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.23 0.08 0.80 0.60 0.40 8° 0° COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 62. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD8251ARMZ 1 AD8251ARMZ-RL1 AD8251ARMZ-R71 AD8251-EVALZ1 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 Package Option RM-10 RM-10 RM-10 Branding H0T H0T H0T AD8251 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06287-0-5/07(0) Rev. 0 | Page 24 of 24