Earphone Interface Bridge Flash MCU BH45F0031 Revision: V1.01 Date: April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description.......................................................................................... 7 Block Diagram................................................................................................... 7 Pin Assignment................................................................................................. 8 Pin Description................................................................................................. 8 Absolute Maximum Ratings............................................................................. 9 D.C. Characteristics........................................................................................ 10 Operating Voltage Characteristics.......................................................................................... 10 Standby Current Characteristics............................................................................................ 10 Operating Current Characteristics...........................................................................................11 A.C. Characteristics........................................................................................ 12 High Speed Internal Oscillator – HIRC – Frequency Accuracy.............................................. 12 Low Speed Internal Oscillator Characteristics – LIRC........................................................... 12 Operating Frequency Characteristic Curves.......................................................................... 13 System Start Up Time Characteristics................................................................................... 13 Input/Output Characteristics......................................................................... 14 Memory Characteristics................................................................................. 14 LVD & LVR Electrical Characteristics........................................................... 15 Sine Wave Generator Electrical Characteristics.......................................... 15 Over Voltage Protection Electrical Characteristics..................................... 16 Power-on Reset Characteristics.................................................................... 16 System Architecture....................................................................................... 17 Clocking and Pipelining.......................................................................................................... 17 Program Counter.................................................................................................................... 18 Stack...................................................................................................................................... 19 Arithmetic and Logic Unit – ALU............................................................................................ 19 Flash Program Memory.................................................................................. 20 Structure................................................................................................................................. 20 Special Vectors...................................................................................................................... 20 Look-up Table ........................................................................................................................ 20 Table Program Example......................................................................................................... 21 In Circuit Programming – ICP................................................................................................ 22 On-Chip Debug Support – OCDS.......................................................................................... 23 RAM Data Memory.......................................................................................... 24 Structure................................................................................................................................. 24 General Purpose Data Memory............................................................................................. 24 Special Purpose Data Memory.............................................................................................. 24 Rev. 1.01 2 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Special Function Register Description......................................................... 26 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 26 Memory Pointers – MP0, MP1............................................................................................... 26 Accumulator – ACC ............................................................................................................... 27 Program Counter Low Register – PCL .................................................................................. 27 Look-up Table Registers – TBLP, TBLH ................................................................................ 27 Status Register – STATUS .................................................................................................... 27 Oscillators....................................................................................................... 29 Oscillator Overview ............................................................................................................... 29 System Clock Configurations................................................................................................. 29 Internal RC Oscillator – HIRC ............................................................................................... 30 Internal 32kHz Oscillator – LIRC............................................................................................ 30 Supplementary Oscillator....................................................................................................... 30 Operating Modes and System Clocks.......................................................... 31 System Clocks....................................................................................................................... 31 System Operation Modes....................................................................................................... 32 Control Registers................................................................................................................... 33 Operating Mode Switching..................................................................................................... 35 Standby Current Considerations............................................................................................ 39 Wake-up................................................................................................................................. 39 Watchdog Timer.............................................................................................. 40 Watchdog Timer Clock Source............................................................................................... 40 Watchdog Timer Control Register.......................................................................................... 40 Watchdog Timer Operation.................................................................................................... 41 Reset and Initialisation .................................................................................. 42 Reset Functions..................................................................................................................... 42 Reset Initial Conditions ......................................................................................................... 44 Input/Output Ports ......................................................................................... 46 Pull-high Resistors................................................................................................................. 46 Port A Wake-up...................................................................................................................... 46 I/O Port Control Registers...................................................................................................... 47 Pin-shared Functions............................................................................................................. 47 I/O Pin Structures................................................................................................................... 49 Programming Considerations ................................................................................................ 49 Timer Modules – TM....................................................................................... 50 Introduction............................................................................................................................ 50 TM Operation......................................................................................................................... 50 TM Clock Source.................................................................................................................... 50 TM Interrupts.......................................................................................................................... 51 TM External Pins.................................................................................................................... 51 TM Input/Output Pin Selection............................................................................................... 51 Programming Considerations................................................................................................. 52 Rev. 1.01 3 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Compact Type TM – CTM............................................................................... 53 Compact Type TM Operation................................................................................................. 53 Compact Type TM Register Description................................................................................ 53 Compact Type TM Operating Modes..................................................................................... 57 Standard Type TM – STM............................................................................... 63 Standard TM Operation.......................................................................................................... 63 Standard Type TM Register Description................................................................................ 64 Standard Type TM Operation Modes..................................................................................... 68 Over Voltage Protection – OVP...................................................................... 78 Over Voltage Protection Operation........................................................................................ 78 Over Voltage Protection Control Registers............................................................................ 78 Offset Calibration................................................................................................................... 80 Sine Wave Generator...................................................................................... 81 Sine Wave Generator Operation............................................................................................ 81 Sine Wave Output Control Registers..................................................................................... 82 Sine Wave Output Function Operation.................................................................................. 84 Sine Wave Generation Timing............................................................................................... 85 Interrupts......................................................................................................... 86 Interrupt Registers.................................................................................................................. 86 Interrupt Operation................................................................................................................. 90 External Interrupt.................................................................................................................... 91 OVP Interrupt......................................................................................................................... 92 LVD Interrupt.......................................................................................................................... 92 ASW Interrupt......................................................................................................................... 92 Multi-function Interrupts.......................................................................................................... 92 Time Base Interrupts.............................................................................................................. 93 Timer Module Interrupts......................................................................................................... 94 Interrupt Wake-up Function.................................................................................................... 94 Programming Considerations................................................................................................. 95 Low Voltage Detector – LVD.......................................................................... 96 LVD Register.......................................................................................................................... 96 LVD Operation........................................................................................................................ 97 Application Circuits........................................................................................ 98 Instruction Set............................................................................................... 100 Introduction.......................................................................................................................... 100 Instruction Timing................................................................................................................. 100 Moving and Transferring Data.............................................................................................. 100 Arithmetic Operations........................................................................................................... 100 Logical and Rotate Operation.............................................................................................. 101 Branches and Control Transfer............................................................................................ 101 Bit Operations...................................................................................................................... 101 Table Read Operations........................................................................................................ 101 Other Operations.................................................................................................................. 101 Rev. 1.01 4 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Instruction Set Summary............................................................................. 102 Table Conventions................................................................................................................ 102 Instruction Definition.................................................................................... 104 Package Information.....................................................................................113 8-pin SOP (150mil) Outline Dimensions...............................................................................114 16-pin NSOP (150mil) Outline Dimensions...........................................................................115 Rev. 1.01 5 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Features CPU Features • Operating Voltage ♦♦ fSYS=4MHz: 2.2V~5.5V ♦♦ fSYS=8MHz: 2.2V~5.5V ♦♦ fSYS=12MHz: 2.7V~5.5V • Up to 0.33μs instruction cycle with 12MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillators: ♦♦ High Speed Internal RC – HIRC ♦♦ Internal 32kHz RC – LIRC • Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components • Multi-mode operation: FAST, SLOW, IDLE and SLEEP • All instructions executed in 1~2 instruction cycles • Table read instructions • 63 powerful instructions • 4-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 1K×16 • RAM Data Memory: 128×8 • Watchdog Timer function • Up to 6 bidirectional I/O lines • Single pin-shared external interrupt • Multiple Timer Modules for time measure, capture input, compare match output, PWM output or single pulse output function • Dual Time-Base functions for generation of fixed time interrupt signals • Over Voltage Protection Function • Sine Wave Output Function • Low Voltage Reset function – LVR • Low Voltage Detect function – LVD • Package type: 8-pin SOP/16-pin NSOP Rev. 1.01 6 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU General Description The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller, which is designed for smart mobile phone headset interface applications that directly transmit data and communicate with the microcontroller using their audio earphone interface. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory. The device includes all the circuitry required to generate audio frequency digital data to enable it to be transmitted using the smartphone audio earphone interface to externally connected hardware. Other features include extremely flexible Timer Modules which provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset, Low Voltage Detector and an over voltage protection function coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of internal high and low oscillator functions are provided which require no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. The inclusion of Time-Base functions, flexible I/O programming features, along with the unique earphone data transmission interface as well as a range of other features ensure the device is well adapted for use in audio frequency data communication applications such as home health care products as well as many others. Block Diagram Flash Programming Circuitry (ICP/OCDS) Flash Program Memory I/O Rev. 1.01 Reset Circuit Low Voltage Detect Watchdog Timer Low Voltage Reset RAM Data Memory 8-bit RISC MCU Core Interrupt Controller Internal RC Oscillators Time Bases OVP Timer Modules 7 Sine Wave Generator April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Pin Assignment VDD 1 8 VSS PA5/STCK 2 7 PA0/Lin/ICPDA PA4/INT/OVPVR 3 6 PA3/MIC2/STPI 4 5 PA1/Rin PA2/MIC1/STP/ICPCK BH45F0031 8 SOP-A VDD PA5/STCK 1 16 VSS 2 15 PA0/Lin/ICPDA PA4/INT/OVPVR 3 14 PA3/MIC2/STPI NC 4 13 PA1/Rin PA2/MIC1/STP/ICPCK 5 12 NC NC 6 11 7 10 OCDSCK 8 9 NC NC NC OCDSDA BH45F0031/BH45V0031 16 NSOP-A Note: 1. If the pin-shared pin functions have multiple outputs, the desired pin-shared function is determined by the corresponding software control bits. 2. The OCDSDA and OCDSCK pins are supplied as dedicated OCDS pins and as such only available for the BH45V0031 device which is the OCDS EV chip for the BH45F0031 device. Pin Description With the exception of the power pins, all pins on the device can be referenced by their port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these port pins are also shared with other function such as the Sine Wave input pins, Over Voltage Protection relvant input pins, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name PA0/Lin/ICPDA PA1/Rin PA2/MIC1/STP/ ICPCK PA3/MIC2/STPI Rev. 1.01 Function OPT I/T O/T PA0 PAWU PAPU PAS0 ST CMOS Description General purpose I/O. Register enabled pull-up and wake-up. Lin PAS0 AN — ICPDA — ST CMOS ICP address/data PA1 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. Rin PAS0 AN — PA2 PAWU PAPU PAS0 ST CMOS MIC1 PAS0 AN — STP PAS0 — CMOS ICPCK — ST — PA3 PAWU PAPU PAS0 ST CMOS MIC2 PAS0 AN — Microphone 2 input STPI PAS0 IFS ST — STM input 8 Audio Left channel input Audio Right channel input General purpose I/O. Register enabled pull-up and wake-up. Microphone 1 input STM output ICP clock General purpose I/O. Register enabled pull-up and wake-up. April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Pin Name PA4/INT/OVPVR PA5/STCK VDD VSS Function OPT I/T O/T PA4 PAWU PAPU PAS1 Description ST CMOS INT PAS1 INTEG INTC0 ST — External interrupt input OVPVR PAS1 AN — OVP DAC reference voltage input PA5 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. STCK — ST — STM clock input VDD — PWR — Positive power supply VSS — PWR — Negative power supply, ground OCDSCK OCDSCK — ST — OCDS clock, for EV chip only OCDSDA OCDSDA — ST CMOS Legend: I/T: Input type; OPT: Optional by register option; ST: Schmitt Trigger input; CMOS: CMOS output; OCDS address/data, for EV chip only O/T: Output type; PWR: Power; AN: Analog signal Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.01 9 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU D.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency, pin load conditions, temperature and program instruction type, etc., can all exert an influence on the measured values. Operating Voltage Characteristics Ta= -40°C~85°C Symbol Parameter Operating voltage – HIRC VDD Operating voltage – LIRC Test Conditions Min. Typ. Max. fSYS=fHIRC=4MHz 2.2 — 5.5 VDD — — Conditions fSYS=fHIRC=8MHz 2.2 — 5.5 fSYS=fHIRC=12MHz 2.7 — 5.5 fSYS=fLIRC=32kHz 2.2 — 5.5 Unit V V Standby Current Characteristics Ta=25°C Symbol Standby Mode Test Conditions VDD Conditions 2.2V SLEEP Mode 3V WDT on 5V 2.2V IDLE0 Mode 3V fSUB on 5V 2.2V 3V ISTB fSUB on, fSYS=4MHz 5V 2.2V IDLE1 Mode – HIRC 3V fSUB on, fSYS=8MHz 5V 2.7V 3V fSUB on, fSYS=12MHz 5V Min. Typ. Max. — TBD TBD Max. 85°C Unit TBD — 1.5 5 TBD — 3 10 TBD TBD — TBD TBD — 3 5 TBD — 5 10 TBD — TBD TBD TBD — 0.18 0.25 TBD — 0.4 0.6 TBD TBD — TBD TBD — 0.36 0.5 TBD — 0.6 0.8 TBD — TBD TBD TBD — 0.54 0.75 TBD — 0.8 1.2 TBD μA μA mA mA mA Notes: When using the characteristic table data, the following notes should be taken into consideration: • Any digital inputs are setup in a non-floating condition. • All measurements are taken under conditions of no load and with all peripherals in an off state. • There are no DC current paths. • All Standby Current values are taken after a HALT instruction execution thus stopping all instruction execution. Rev. 1.01 10 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Operating Current Characteristics Ta=25°C Symbol Operating Mode Test Conditions Min. Typ. Max. — TBD TBD — 10 20 — 30 50 — TBD TBD — 0.4 0.6 5V — 0.8 1.2 2.2V — TBD TBD VDD Conditions 2.2V SLOW Mode – LIRC 3V fSYS=32kHz 5V 2.2V 3V IDD FAST Mode – HIRC 3V fSYS=4MHz fSYS=8MHz 5V 2.7V 3V fSYS=12MHz 5V — 0.8 1.2 — 1.6 2.4 — TBD TBD — 1.2 1.8 — 2.4 3.6 Unit μA mA mA mA Notes: When using the characteristic table data, the following notes should be taken into consideration: • Any digital inputs are setup in a non-floating condition. • All measurements are taken under conditions of no load and with all peripherals in an off state. • There are no DC current paths. • All Operating Current values are measured using a continuous NOP instruction program loop. Rev. 1.01 11 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU A.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency and temperature etc., can all exert an influence on the measured values. High Speed Internal Oscillator – HIRC – Frequency Accuracy During the program writing operation the writer will trim the HIRC oscillator at a user selected HIRC frequency and user selected voltage of either 3V or 5V. 4/8/12MHz Symbol Parameter 4MHz Writer Trimmed HIRC Frequency 8MHz Writer Trimmed HIRC Frequency fHIRC 12MHz Writer Trimmed HIRC Frequency Test Conditions VDD Temp. 3V/5V 2.2V~5.5V 3V/5V 2.2V~5.5V 5V 2.7V~5.5V Min Typ Max Ta=25°C -1.0% 4 +1.0% Ta= -40°C ~ 85°C -2.0% 4 +2.0% Ta=25°C -2.5% 4 +2.5% Ta= -40°C ~ 85°C -3.0% 4 +3.0% Ta=25°C -1.0% 8 +1.0% Ta= -40°C ~ 85°C -2.0% 8 +2.0% Ta=25°C -2.5% 8 +2.5% Ta= -40°C ~ 85°C -3.0% 8 +3.0% Ta=25°C -1.0% 12 +1.0% Ta= -40°C ~ 85°C -2.0% 12 +2.0% Ta=25°C -2.5% 12 +2.5% Ta= -40°C ~ 85°C -3.0% 12 +3.0% Unit MHz MHz MHz Notes: 1. The 3V/5V values for VDD are provided as these are the two selectable fixed voltages at which the HIRC frequency is trimmed by the writer. 2. The row below the 3V/5V trim voltage row is provided to show the values for the full VDD range operating voltage. It is recommended that the trim voltage is fixed at 3V for application voltage ranges from 2.2V to 3.6V and fixed at 5V for application voltage ranges from 3.3V to 5.5V. 3. The minimum and maximum tolerance values provided in the table are only for the frequency at which the writer trims the HIRC oscillator. After trimming at this chosen specific frequency any change in HIRC oscillator frequency using the oscillator register control bits by the application program will give a frequency tolerance to within ±20%. Low Speed Internal Oscillator Characteristics – LIRC Ta=25°C, unless otherwise specified Symbol fLIRC Rev. 1.01 Parameter LIRC Frequency Test Conditions VDD Temp. 2.2V~5.5V Ta= -40°C ~ 85°C 12 Min. Typ. Max. Unit 8 32 50 kHz April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Operating Frequency Characteristic Curves System Operating Frequency 12MHz 8MHz 4MHz ~ ~ ~ ~ ~ ~ 2.2V 2.7V 5.5V Operating Voltage System Start Up Time Characteristics Ta= -40°C~85°C Symbol tSST Min. Typ. Max. Unit System Start-up Time Wake-up from condition where fSYS is off Parameter fSYS=fH ~ fH/64, fH=fHIRC — 16 — tHIRC fSYS=fSUB=fLIRC — 2 — tLIRC System Start-up Time Wake-up from condition where fSYS is on fSYS=fH ~ fH/64, fH=fHIRC — 2 — tH fSYS=fSUB=fLIRC — 2 — tSUB fHIRC off → on — 16 — tHIRC 25 50 100 ms System Speed Switch Time FAST to SLOW Mode or SLOW to FAST Mode tRSTD tSRESET Test Conditions System Reset Delay Time Reset Source from Power-on Reset or LVR Hardware Reset — System Reset Delay Time WDTC software Reset — System Reset Delay Time Reset source from WDT Overflow — 8.3 16.7 33.3 ms Minimum Software Reset Width to Reset — 40 90 360 μs Notes: 1.For the System Start-up time values, whether fSYS is on or off depends upon the mode type and the chosen fSYS system oscillator. Details are provided in the System Operating Modes section. 2. The time units, shown by the symbols tHIRC, are the inverse of the corresponding frequency values as provided in the frequency tables. For example tHIRC=1/fHIRC, tSYS=1/fSYS etc. 3. If the LIRC is used as the system clock and if it is off when in the SLEEP Mode, then an additional LIRC start up time, tSTART, as provided in the LIRC frequency table, must be added to the tSST time in the table above. 4. The System Speed Switch Time is effectively the time taken for the newly activated oscillator to start up. Rev. 1.01 13 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Input/Output Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions 5V VIL Input Low Voltage for I/O Ports VIH Input High Voltage for I/O Ports IOL Sink Current for I/O Ports IOH Source Current for I/O Ports RPH Pull-High Resistance for I/O Ports (Note) ILEAK Input Leakage Current tTPI STPI Input Pin Minimum Pulse Width — tTCK STCK Input Pin Minimum Pulse Width — tINT External Interrupt Minimum Pulse Width — — — 5V 3V 3V 3V 3V 1.5 — 0.2VDD V 5.0 VDD 15.5 31 — 31 62 — -3.5 -7.0 — -7.2 -14.5 — 20 60 100 10 30 50 — — ±1 — — ±1 — 0.3 — — μs — 0.3 — — μs — 0.3 — — μs VIN=VDD or VIN=VSS 5V — 0 — — 5V 0 Unit — VOH=0.9VDD 5V Max. 3.5 VOL=0.1VDD 5V Typ. 0.8VDD — — Min. V mA mA kΩ μA Note: The RPH internal pull high resistance value is calculated by connecting to ground and enabling the input pin with a pull-high resistor and then measuring the input sink current at the specified supply voltage level. Dividing the voltage by this measured current provides the RPH value. Memory Characteristics Ta= -40°C~85°C Symbol VRW Parameter VDD for Read / Write Test Conditions Min. Typ. Max. Unit — VDDmin — VDDmax V VDD Conditions — Program Flash Memory tDEW Erase / Write Cycle Time — — 2.2 2.5 2.8 ms IDDPGM Programming / Erase Current on VDD — — — — 5.0 mA EP Cell Endurance — — 100K — — E/W tRETD ROM Data Retention Time — Ta=25°C — 40 — Year — MCU in SLEEP mode 1.0 — — V RAM Data Memory VDR Rev. 1.01 RAM Data Retention Voltage 14 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU LVD & LVR Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions VDD VDD Operating Voltage — VLVR Low Voltage Reset Voltage — VLVD Low Voltage Detection Voltage — Conditions — LVR enable, voltage select 2.1V Min. Typ. Max. Unit 1.9 — 5.5 V -5% 2.1 +5% V ENLVD=1, VLVD=2.0V 2.0 V ENLVD=1, VLVD=2.2V 2.2 V ENLVD=1, VLVD=2.4V 2.4 V ENLVD=1, VLVD=2.7V 2.7 -5% ENLVD=1, VLVD=3.0V 3.0 +5% V V ENLVD=1, VLVD=3.3V 3.3 V ENLVD=1, VLVD=3.6V 3.6 V ENLVD=1, VLVD=4.0V 4.0 V tLVR Minimum Low Voltage Width to Reset — — 120 600 850 μs tLVD Minimum Low Voltage Width to Interrupt — — 60 150 320 μs tLVDS LVDO Stable Time — For LVR enable, LVD off→on — — 15 μs — For LVR disable, LVD off→on — — 150 μs Sine Wave Generator Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit V VDD Operating Mode — — 2.2 — 5.5 VAUDLI AUDLI Input Voltage — — 2.2 — 5.5 V fASWCLK Input Frequency Range — — 0.4 — 12 MHz IDAC0 Additional Current for DAC0 Enable 3V — — — 1.2 mA 5V — — — 2 mA 3V — — — 3 mA 5V — — — 5 mA IDAC1 Rev. 1.01 Additional Current for DAC1 Enable 15 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Over Voltage Protection Electrical Characteristics Ta=25°C Symbol Parameter IOVP OVP Operating Current VOS Input Offset Voltage VHYS VCM DNL INL Hysteresis Test Conditions Min. Typ. Max. Unit — — 350 μA — 280 400 μA With calibration -4 — 4 mV With calibration -4 — 4 mV 3V — 10 40 60 mV 5V — 10 40 60 mV V VDD Conditions 3V OVPEN=1, DAC VREF=2.5V 5V OVPEN=1, DAC VREF=2.5V 3V 5V 3V — VSS — VDD - 1.4 5V — VSS — VDD - 1.4 V Common Mode Voltage Range Differential Non-linearity Integral Non-linearity 3V DAC VREF=VDD — — ±1.5 LSB 5V DAC VREF=VDD — — ±1.0 LSB 3V DAC VREF=VDD — — ±2.0 LSB 5V DAC VREF=VDD — — ±1.5 LSB Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms VDD tPOR RRPOR VPOR Rev. 1.01 16 Time April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fSYS (System Clock) Phase Clock T1 Phase Clock T2 Phase Clock T3 Phase Clock T4 Program Counter Pipelining PC PC+1 PC+2 Fetch Inst. (PC) Execute Inst. (PC-1) Fetch Inst. (PC+1) Execute Inst. (PC) Fetch Inst. (PC+2) Execute Inst. (PC+1) System Clocking and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.01 17 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU 1 MOV A,[12H] 2 CALL DELAY 3 CPL [12H] 4 : 5 : 6 DELAY: NOP Fetch Inst. 1 Execute Inst. 1 Fetch Inst. 2 Execute Inst. 2 Fetch Inst. 3 Flush Pipeline Fetch Inst. 6 Execute Inst. 6 Fetch Inst. 7 Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register PC9~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly. However, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.01 18 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. Program Counter Top of Stack Stack Pointer Stack Level 1 Stack Level 2 Stack Level 3 Bottom of Stack Program Memory Stack Level 4 If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement: INCA, INC, DECA, DEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.01 19 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 1K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 000H Reset 004H Interrupt Vectors 020H 3FFH 16 bits Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRDC[m]" or "TABRDL[m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. Rev. 1.01 20 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Last page or present page PC9~PC8 Program Memory Address PC High Byte TBLP Register Data 16 bits Register TBLH User Selected Register High Byte Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "300H" which refers to the start address of the last page within the 1K Program Memory of the microcontroller. The table pointer low byte register is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "306H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the "TABRDC [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRDC [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "306H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "305H" transferred to ; tempreg2 and TBLH in this example the data "1AH" is ; transferred to tempreg1 and data "0FH" to register tempreg2 : : org 300h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : Rev. 1.01 21 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, a means of programming the microcontroller in-circuit has provided using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Flash MCU to Writer Programming Pin correspondence table is as follows: Writer Pins MCU Programming Pins ICPDA PA0 Programming serial data/address Pin Description ICPCK PA2 Programming clock VDD VDD Power supply VSS VSS Ground The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the ICPDA and ICPCK pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Writer Connector Signals MCU Programming Pins Writer_VDD VDD ICPDA PA0 ICPCK PA2 Writer_VSS VSS * * To other Circuit Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. Rev. 1.01 22 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU On-Chip Debug Support – OCDS An EV chip exists for the purposes of device emulation. This EV chip device also provides an "OnChip Debug" function to debug the device during the development process. The EV chip and the actual MCU device are almost functionally compatible except for the "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document. Rev. 1.01 e-Link Pins EV Chip Pins OCDSDA OCDSDA On-chip debug support data/address input/output OCDSCK OCDSCK On-chip debug support clock input VDD VDD Power supply VSS VSS Ground 23 Pin Description April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Categorized into two types, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. Structure The Data Memory is a volatile area of 8-bit wide RAM internal memory which only includes one bank, namely Bank 0. It is subdivided into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The start address of the Data Memory for the device is the address 00H. Special Purpose Data Memory General Purpose Data Memory Available Bank Address Capacity Address 0 0: 00H~7FH 128×8 0: 80H~FFH Data Memory Summary 00H Special Purpose Data Memory 7FH 80H General Purpose Data Memory FFH Bank 0 Data Memory Structure General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Rev. 1.01 24 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Bank0 IAR0 MP0 IAR1 MP1 Unused ACC PCL TBLP TBLH Unused STATUS SCC HIRCC LVDC Unused RSTFC Unused MFI0 MFI1 Unused PA PAC PAPU PAWU IFS WDTC Unused TBC INTEG INTC0 INTC1 CTMC0 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH Bank0 CTMC1 CTMDL CTMDH CTMAL CTMAH Unused PAS0 PAS1 STMC0 STMC1 STMDL STMDH STMAL STMAH Unused OVPC0 OVPC1 OVPDA Unused ASWTMR ASWC0 ASWC1 ASWDAC0 ASWDAC1 VDRC INTC2 Unused 7FH : Unused, read as “00” Special Purpose Data Memory Rev. 1.01 25 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections， however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h ; setup size of block mov block, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp0, a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.01 26 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicate the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. Rev. 1.01 27 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x" unknown Rev. 1.01 Bit 7~6 Unimplemented, read as "0" Bit 5 TO: Watchdog Time-Out Flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power Down Flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow Flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero Flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry Flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. 28 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through application programs and relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Fully integrated internal oscillators require no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the registers. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device have the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Internal High Speed RC HIRC 4/8/12MHz Internal Low Speed RC LIRC 32kHz System Clock Configurations There are two methods of generating the system clock, a high speed oscillator and a low speed oscillator. The high speed oscillator is the internal 4/8/12MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2 ~ CKS0 bits in the SCC register and as the system clock can be dynamically selected. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a nooscillator selection for either the high or low speed oscillator. fH High Speed Oscillator HIRCEN fH/2 fH/4 fH/8 HIRC IDLE0 SLEEP Prescaler fSYS fH/16 fH/32 fH/64 FHS fSUB Low Speed Oscillator CKS2~CKS0 LIRC fSUB IDLE2 SLEEP FSS fLIRC System Clock Configurations Rev. 1.01 29 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 4/8/12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Supplementary Oscillator The low speed oscillator, in addition to providing a system clock source is also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Rev. 1.01 30 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As both high and low speed clock sources are provided the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced from an HIRC oscillator. The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected then it can be sourced by the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There is one additional internal clock for the peripheral circuits, the Time Base clock, fTBC. fTBC is sourced from the LIRC oscillator. The fTBC clock is used as a source for the Time Base interrupt functions. fH fH /2 High Speed Oscillator HIRCEN fH /4 fH /8 HIRC IDLE0 SLEEP Prescaler fSYS fH /16 fH /32 fH /64 Low Speed Oscillator LIRC CKS2~ CKS0 fLIRC fSUB IDLE2 SLEEP fSUB fSYS/4 fTB f TBC Prescaler 0 Time Base 0 TB0 [2:0] fSYS/4 fTB f TBC Prescaler 1 Time Base 1 TB1 [1:0] fLIRC f LIRC WDT LVR Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillator can be stopped to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit. Rev. 1.01 31 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the FAST Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power. Register Setting Operation CPU Mode FHIDEN FSIDEN CKS2~CKS0 fSYS FAST On x x 000~110 fH~fH/64 SLOW On x x 111 fSUB IDLE0 Off 0 1 IDLE1 Off 1 1 IDLE2 Off 1 0 SLEEP Off 0 0 000~110 Off 111 On xxx On 000~110 On 111 Off xxx Off fH fSUB On fLIRC On On On On Off On On On On On On Off On Off Off On/Off (1) On (2) "x" don’t care Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fLIRC clock is switched on as the WDT function is still enabled in the SLEEP mode. FAST Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from the HIRC oscillator. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from the LIRC oscillator. In the SLOW mode, the fH clock can be switched off by configuring the relevant register. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. However the fLIRC clock can still continue to operate as the WDT function is always enabled. IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. Rev. 1.01 32 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Control Registers The registers, SCC and HIRCC, are used to control the system clock and the corresponding oscillator configurations. Bit Register Name 7 6 5 4 3 2 1 0 SCC CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN System Operating Mode Control Registers List SCC Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN R/W R/W R/W R/W — — — R/W R/W POR 0 0 0 — — — 0 0 Bit 7~5 CKS2~CKS0: System Clock Selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4~2 Unimplemented, read as "0" Bit 1 FHIDEN: High Frequency Oscillator Control when CPU is Switched Off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. Bit 0 FSIDEN: Low Frequency Oscillator Control when CPU is Switched Off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled. 33 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU HIRCC Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name — — — — HIRC1 HIRC0 HIRCF HIRCEN R/W — — — — R/W R/W R R/W POR — — — — 0 0 0 1 Bit 7~4 Unimplemented, read as "0" Bit 3~2 HIRC1~HIRC0: HIRC Frequency Selection 00: 4 MHz 01: 8 MHz 10: 12 MHz 11: 4 MHz When the HIRC oscillator is enabled or the HIRC frequency selection is changed by application program, the clock frequency will automatically be changed after the HIRCF flag is set to 1. Bit 1 HIRCF: HIRC Oscillator Stable Flag 0: HIRC unstable 1: HIRC stable This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection is changed by application program, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable. Bit 0 HIRCEN: HIRC Oscillator Enable Control 0: Disable 1: Enable 34 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the FAST Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the FAST/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. FAST fSYS=fH~fH/64 fH on CPU run fSYS on fSUB on SLOW fSYS=fSUB fSUB on CPU run fSYS on fH on/off SLEEP HALT instruction executed CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off IDLE0 HALT instruction executed CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on IDLE2 HALT instruction executed CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off Rev. 1.01 35 IDLE1 HALT instruction executed CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU FAST Mode to SLOW Mode Switching When running in the FAST Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to "111" in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. FAST Mode CKS2~CKS0 = 111 SLOW Mode FHIDEN=0, FSIDEN=0 HALT instruction is executed SLEEP Mode FHIDEN=0, FSIDEN=1 HALT instruction is executed IDLE0 Mode FHIDEN=1, FSIDEN=1 HALT instruction is executed IDLE1 Mode FHIDEN=1, FSIDEN=0 HALT instruction is executed IDLE2 Mode Rev. 1.01 36 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU SLOW Mode to FAST Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the FAST mode from fSUB, the CKS2~CKS0 bits should be set to "000" ~"110" and then the system clock will respectively be switched to fH ~ fH/64. However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the FAST mode from the SLOW Mode. This is monitored using the HIRCF bit in the HIRCC register. The time duration required for the high speed system oscillator stabilization is specified in the System Start Up Time Characteristics. SLOW Mode CKS2~CKS0 = 000~110 FAST Mode FHIDEN=0, FSIDEN=0 HALT instruction is executed SLEEP Mode FHIDEN=0, FSIDEN=1 HALT instruction is executed IDLE0 Mode FHIDEN=1, FSIDEN=1 HALT instruction is executed IDLE1 Mode FHIDEN=1, FSIDEN=0 HALT instruction is executed IDLE2 Mode Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "0". In this mode all the clocks and functions will be switched off except the WDT function. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting. Rev. 1.01 37 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be on but the fSUB clock will be off and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting. Rev. 1.01 38 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled.In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the "HALT" instruction, the PDF flag will be set to 1. The PDF flag will be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.01 39 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fLIRC, which is in turn supplied by the LIRC oscillator. The LIRC internal oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary with VDD, temperature and process variations.The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the WDT enable and MCU reset operation. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT Function Software Control 10101: Disable 01010: Enable Others: Reset MCU When these bits are changed by the environmental noise or software setting to reset the microcontroller, the reset operation will be activated after a delay time, tSRESET, and the WRF bit in the RSTFC register will be set high. Bit 2~0 WS2~WS0: WDT Time-out Period Selection 000: 28/fLIRC 001: 29/fLIRC 010: 210/fLIRC 011: 211/fLIRC 100: 212/fLIRC 101: 213/fLIRC 110: 214/fLIRC 111: 215/fLIRC These three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — LVRF — WRF R/W — — — — — R/W — R/W POR — — — — — x — 0 "x" unknown Rev. 1.01 Bit 7~3 Unimplemented, read as "0" Bit 2 LVRF: LVR Function Reset Flag Described elsewhere Bit 1 Unimplemented, read as "0" 40 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU WRF: WDT Control Register Software Reset Flag 0: Not occur 1: Occurred This bit is set high by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to zero by the application program. Bit 0 Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to offer the enable/reset control of the Watchdog Timer. The WDT function will be enabled if the WE4~WE0 bits are equal to 10101B or 01010B. If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device after a delay time, tSRESET. After power on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B or 01010B Enable Any other values Reset MCU Watchdog Timer Function Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time out period is when the 215 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 division ratio, and a minimum timeout of 8ms for the 28 division ration. WDTC Register Reset MCU WE4~WE0 bits CLR “HALT”Instruction “CLR WDT”Instruction LIRC fLIRC 8-stage Divider fLIRC/28 WS2~WS0 WDT Prescaler 8-to-1 MUX WDT Time-out Watchdog Timer Rev. 1.01 41 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring internally. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. VDD Power-on Reset tRSTD SST Time-out Power-On Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will also be set high. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the LVD & LVR Electrical Characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The LVR has a fixed voltage value of 2.1V and will reset the device after a delay time, tSRESET. Note that the LVR function will be automatically disabled when the device enters the power down mode. LVR tRSTD + tSST Internal Reset Low Voltage Reset Timing Chart Rev. 1.01 42 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU • RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — LVRF — WRF R/W — — — — — R/W — R/W POR — — — — — x — 0 "x" unknown Bit 7~3 Unimplemented, read as "0" Bit 2 LVRF: LVR Function Reset Flag 0: Not occur 1: Occurred This bit is set high when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to zero by the application program. Bit 1 Unimplemented, read as "0" Bit 0 WRF: WDT Control register software reset flag Described elsewhere Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as LVR reset except that the Watchdog time-out flag TO will be set high. WDT Time-out tRSTD + tSST Internal Reset WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the System Start Up Time Characteristics for tSST details. WDT Time-out tSST Internal Reset WDT Time-out Reset during Sleep or IDLE Mode Timing Chart Rev. 1.01 43 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset Reset Conditions u u LVR reset during FAST or SLOW Mode operation 1 u WDT time-out reset during FAST or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT, Time Bases Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Register Name Rev. 1.01 Reset (Power On) LVR Reset WDT Time-out (Normal Operation) (Normal Operation) WDT Time-out (IDLE/SLEEP) IAR0 xxxx xxxx xxxx xxxx xxxx xxxx MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu IAR1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TBLH xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu STATUS - - 00 xxxx - - uu uuuu - - 1u uuuu - - 11 u u u u SCC 000- - - 00 000- - - 00 000- - - 00 uuu- - - uu HIRCC - - - - 0001 - - - - 0001 - - - - 0001 - - - - uuuu LVDC - - 00 - 000 - - 00 - 000 - - 00 - 000 - - uu - uuu - - - - - u- u RSTFC - - - - - x- 0 - - - - - x- 0 - - - - - x- 0 MFI0 - - 00 - - 00 --00 --00 --00 --00 - - uu - - uu MFI1 - - 00 - - 00 --00 --00 --00 --00 - - uu - - uu PA - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PAC - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PAPU - - 00 0000 - - 00 0000 - - 00 0000 - - uu uuuu PAWU - - 00 0000 - - 00 0000 - - 00 0000 - - uu uuuu 44 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Register Name Reset (Power On) LVR Reset WDT Time-out (Normal Operation) (Normal Operation) WDT Time-out (IDLE/SLEEP) IFS ---- ---0 ---- ---0 ---- ---0 WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 ---- ---u uuuu uuuu TBC 0 0 11 - 111 0 0 11 - 111 0 0 11 - 111 uuuu - uuu INTEG - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu INTC0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 u u u u u u uu CTMC0 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMDH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu uuuu uuuu CTMAL 0000 0000 0000 0000 0000 0000 CTMAH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu PAS0 0000 0000 0000 0000 0000 0000 uuuu uuuu PAS1 - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu STMC0 0000 0000 0000 0000 0000 0000 uuuu uuuu STMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu uuuu uuuu STMAL 0000 0000 0000 0000 0000 0000 STMAH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu OVPC0 - - 00 - 000 - - 00 - 000 - - 00 -000 - - uu - uuu OVPC1 0001 0000 0001 0000 0001 0000 uuuu uuuu OVPDA 0000 0000 0000 0000 0000 0000 uuuu uuuu ASWTMR 0000 0000 0000 0000 0000 0000 uuuu uuuu ASWC0 - - - - - 000 - - - - - 000 - - - - - 000 - - - - - uuu ASWC1 - 111 1111 - 111 1111 - 111 1111 -uuu uuuu ASWDAC0 - - - - - 000 - - - - - 000 - - - - - 000 - - - - - uuu ASWDAC1 - - - 0 0000 - - - 0 0000 - - - 0 0000 - - - u uuuu VDRC - - - - - 000 - - - - - 000 - - - - - 000 - - - - - uuu INTC2 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u Note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented Rev. 1.01 45 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Input/Output Ports The microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port name PA. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PA — — PA5 PA4 PA3 PA2 PA1 PA0 PAC — — PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU — — PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU — — PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 "—" unimplemented I/O Logic Function Registers List Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU, and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high resistors cannot be enabled. PAPU Register Bit 7 6 5 4 3 2 1 0 Name — — PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 PAPU5~PAPU0: I/O Port A bit 5~bit 0 Pull-high Function Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Rev. 1.01 46 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the MCU enters the Power down mode. PAWU Register Bit 7 6 5 4 3 2 1 0 Name — — PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 PAWU5~PAWU0: Port A bit 5~bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name — — PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 Unimplemented, read as "0" Bit 5~0 PAC5~PAC0: I/O Port A bit 5~bit 0 input/output control bit 0: Output 1: Input Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. The device includes Port A output function Selection register "n", labeled as PASn, and Input Function Selection register, labeled as IFS, which can select the desired functions of the multi-function pin-shared pins. Rev. 1.01 47 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU The most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. To select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register. After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 — — — — — — PAS11 PAS10 IFS — — — — — — — STPIPS Pin-shared Function Selection Registers List • PAS0 Register Bit 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAS07~PAS06: PA3 Pin-Shared Function Selection 00: PA3/STPI 01: MIC2 (ASWO) 10: PA3/STPI 11: PA3/STPI Bit 5~4 PAS05~PAS04: PA2 Pin-Shared Function Selection 00: PA2 01: MIC1 (ASWO) 10: PA2 11: STP Bit 3~2 PAS03~PAS02: PA1 Pin-Shared Function Selection 00: PA1 01: Rin (AUDLI) 10: PA1 11: PA1 Bit 1~0 PAS01~PAS00: PA0 Pin-Shared Function Selection 00: PA0 01: Lin (AUDLI) 10: PA0 11: PA0 • PAS1 Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name — — — — — — PAS11 PAS10 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PAS11~PAS10: PA4 Pin-Shared Function Selection 00: PA4/INT 01: PA4/INT 10: OVPVR 11: PA4/INT 48 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU • IFS Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — STPIPS R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as "0" Bit 0 STPIPS: STPI Input Source Pin Selection 0: PA3 1: Internally connected to OVPINT I/O Pin Structures The accompanying diagram illustrates the internal structures of the I/O logic function. As the exact logical construction of the I/O pin will differ from this diagram, it is supplied as a guide only to assist with the functional understanding of the logic function I/O pins. The wide range of pin-shared structures does not permit all types to be shown. VDD Control Bit Data Bus Write Control Register Chip Reset Read Control Register Q D Weak Pull-up CK Q S I/O pin Data Bit D Write Data Register Pull-high Register Select Q CK Q S Read Data Register System Wake-up M U X wake-up Select PA only Logic Function Input/Output Structure Programming Considerations Within the user program, one of the things first to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control register PAC is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.01 49 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Standard Type TM sections. Introduction The device contains two TMs and each individual TM can be categorised as a certain type, namely Compact Type TM or Standard Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact and Standard Type TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table. TM Function CTM STM Timer/Counter √ √ Input Capture — √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output PWM Alignment PWM Adjustment Period & Duty — 1 Edge Edge Duty or Period Duty or Period TM Function Summary CTM STM 10-bit CTM 10-bit STM TM Name/Type Reference TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. When the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTCK2~xTCK0 bits in the xTM control registers, where the "x" stands for the C or S type. The clock source can be a ratio of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCK pin. The xTCK pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. Rev. 1.01 50 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU TM Interrupts The Compact or Standard type TM has two internal interrupt, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins In this device, the Compact Type TM input pin CTCK is unbonded, the input signal of CTM is the ASWEdge signal from the Sine Wave Generator. The Standard Type TM has two TM input pins, with the label STCK and STPI respectively. The STM input pin, STCK, is essentially a clock source for the STM and is selected using the STCK2~STCK0 bits in the STMC0 register. This external TM input pin allows an external clock source to drive the internal TM. The STCK or ASWEdge signal can be chosen to have either a rising or falling active edge. The STCK pin is also used as the external trigger input pin in single pulse output mode for the STM. The other STM input pin, STPI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the STIO1~STIO0 bits in the STMC1 register. There is another capture input, STCK, for STM capture input mode, which can be used as the external trigger input source except the STPI pin. The Compact Type TM has no ouput pin, while the Standar Type STM has one output pin, STP. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external STP output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. STM Input Output STCK, STPI STP TM External Pins TM Input/Output Pin Selection Selecting to have a TM input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. STCK CCR capture input STPI STM CCR output STP STM Function Pin Control Block Diagram Rev. 1.01 51 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA register, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA register are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA low byte registers, namely the xTMAL registers, using the following access procedures. Accessing the CCRA low byte registers without following these access procedures will result in unpredictable values. xTM Counter Register (Read only) xTMDL xTMDH 8-bit Buffer xTMAL xTMAH xTM CCRA Register (Read/Write) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA ♦♦ Step 1. Write data to Low Byte xTMAL ––Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMAH ––Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA Rev. 1.01 ♦♦ Step 1. Read data from the High Byte xTMDH, xTMAH ––Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMDL, xTMAL ––This step reads data from the 8-bit buffer. 52 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Compact Type TM – CTM The Compact Type TM contains three operating modes, which are Compare Match Output, Timer/ Event Counter and PWM Output modes. The Compact Type TM input pin, CTCK and output pins, CTP and CTPB, are unbonded, the input signal of CTM is the ASWEdge signal sourced from the Sine Wave Generator. CCRP fSYS/4 fSYS fH/16 fH/64 fSUB fSUB ASWEdge 000 001 010 011 100 101 110 111 Comparator P Match 3-bit Comparator P CTMPF Interrupt CTOC b7~b9 Counter Clear 10-bit Count-up Counter CTON CTPAU CTCCLR b0~b9 Comparator A Match 10-bit Comparator A Output Control Polarity Control CTM1, CTM0 CTIO1, CTIO0 CTPOL 0 1 To other function CTMAF Interrupt CTCK2~CTCK0 CCRA Compact Type TM Block Diagram Compact Type TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 3-bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the CTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including the ASWEdge signal and can also control an output. All operating setup conditions are selected using relevant internal registers. Compact Type TM Register Description Overall operation of the Compact Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as three CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 CTMC0 CTPAU CTCK2 CTCK1 CTCK0 CTON CTRP2 CTRP1 CTRP0 CTMC1 CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR CTMDL D7 D6 D5 D4 D3 D2 D1 D0 CTMDH — — — — — — D9 D8 CTMAL D7 D6 D5 D4 D3 D2 D1 D0 CTMAH — — — — — — D9 D8 10-Bit Compact Type TM Register List Rev. 1.01 53 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU CTMC0 Register Bit 7 6 5 4 3 2 1 0 Name CTPAU CTCK2 CTCK1 CTCK0 CTON CTRP2 CTRP1 CTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Bit 6~4 Bit 3 Bit 2~0 Rev. 1.01 CTPAU: CTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. CTCK2~CTCK0: Select CTM Counter Clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: ASWEdge rising edge clock 111: ASWEdge falling edge clock These three bits are used to select the clock source for the CTM. The ASWEdge clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. CTON: CTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the CTM. Setting the bit high enables the counter to run, clearing the bit disables the CTM. Clearing this bit to zero will stop the counter from counting and turn off the CTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the CTM is in the Compare Match Output Mode or the PWM Output Mode then the CTM output will be reset to its initial condition, as specified by the CTOC bit, when the CTON bit changes from low to high. CTRP2~CTRP0: CTM CCRP 3-bit Register, Compared with the CTM Counter bit 9~bit 7 Comparator P Match Period 000: 1024 CTM clocks 001: 128 CTM clocks 010: 256 CTM clocks 011: 384 CTM clocks 100: 512 CTM clocks 101: 640 CTM clocks 110: 768 CTM clocks 111: 896 CTM clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTCCLR bit is set to zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. 54 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU CTMC1 Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 CTM1~CTM0: Select CTM Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the CTM. To ensure reliable operation the CTM should be switched off before any changes are made to the CTM1 and CTM0 bits. In the Timer/Counter Mode, the CTM output pin state is undefined. Bit 5~4 CTIO1~CTIO0: Select CTP Output Function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/counter Mode Unused These two bits are used to determine how the CTM output changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTM is running. In the Compare Match Output Mode, the CTIO1 and CTIO0 bits determine how the CTM output changes state when a compare match occurs from the Comparator A. The CTM output can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTM output should be setup using the CTOC bit in the CTMC1 register. Note that the output level requested by the CTIO1 and CTIO0 bits must be different from the initial value setup using the CTOC bit otherwise no change will occur on the CTM output when a compare match occurs. After the CTM output changes state it can be reset to its initial level by changing the level of the CTON bit from low to high. In the PWM Output Mode, the CTIO1 and CTIO0 bits determine how the CTM output changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CTIO1 and CTIO0 bits only after the CTM has been switched off. Unpredictable PWM outputs will occur if the CTIO1 and CTIO0 bits are changed when The CTM is running. 55 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Bit 3 CTOC: CTM Output Control Bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the CTM output. Its operation depends upon whether CTM is being used in the Compare Match Output Mode or in the PWM Output Mode. It has no effect if the CTM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTM output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM signal is active high or active low. Bit 2 CTPOL: CTM Output Polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the CTP output. When the bit is set high the CTM output will be inverted and not inverted when the bit is zero. It has no effect if the CTM is in the Timer/Counter Mode. Bit 1 CTDPX: CTM PWM Period/Duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 CTCCLR: Select CTM Counter Clear Condition 0: CTM Comparatror P match 1: CTM Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact type TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTCCLR bit is not used in the PWM Output Mode. CTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CTM Counter Low Byte Register bit 7 ~ bit 0 CTM 10-bit Counter bit 7 ~ bit 0 CTMDH Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTM Counter High Byte Register bit 1 ~ bit 0 CTM 10-bit Counter bit 9 ~ bit 8 56 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU CTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CTM CCRA Low Byte Register bit 7 ~ bit 0 CTM 10-bit CCRA bit 7 ~ bit 0 CTMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTM CCRA High Byte Register bit 1 ~ bit 0 CTM 10-bit CCRA bit 9 ~ bit 8 Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and CTM0 bits in the CTMC1 register. Compare Match Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the CTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both CTMAF and CTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the CTCCLR bit in the CTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the CTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTCCLR is high no CTMPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTM output pin will change state. The CTM output pin condition however only changes state when a CTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The CTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the CTM output pin. The way in which the CTM output pin changes state are determined by the condition of the CTIO1 and CTIO0 bits in the CTMC1 register. The CTM output pin can be selected using the CTIO1 and CTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTM output pin, which is setup after the CTON bit changes from low to high, is setup using the CTOC bit. Note that if the CTIO1 and CTIO0 bits are zero then no pin change will take place. Rev. 1.01 57 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter overflow Counter Value 0x3FF CTCCLR = 0; CTM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP=0 CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time CTON CTPAU CTPOL CCRP Int. flag CTMPF CCRA Int. flag CTMAF CTM O/P Pin Output pin set to initial Level Low if CTOC=0 Output not affected by CTMAF flag. Remains High until reset by CTON bit Output Toggle with CTMAF flag Here CTIO [1:0] = 11 Toggle Output select Note CTIO [1:0] = 10 Active High Output select Output Inverts when CTPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – CTCCLR=0 Note: 1. With CTCCLR=0, a Comparator P match will clear the counter 2. The CTM output pin controlled only by the CTMAF flag 3. The output pin reset to initial state by a CTON bit rising edge Rev. 1.01 58 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value CTCCLR = 1; CTM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time CTON CTPAU CTPOL No CTMAF flag generated on CCRA overflow CCRA Int. flag CTMAF CCRP Int. flag CTMPF CTM O/P Pin CTMPF not generated Output pin set to initial Level Low if CTOC=0 Output does not change Output not affected by CTMAF flag. Remains High until reset by CTON bit Output Toggle with CTMAF flag Here CTIO [1:0] = 11 Toggle Output select Note CTIO [1:0] = 10 Active High Output select Output Inverts when CTPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – CTCCLR=1 Note: 1. With CTCCLR=1, a Comparator A match will clear the counter 2. The CTM output pin controlled only by the CTMAF flag 3. The output pin reset to initial state by a CTON bit rising edge 4. The CTMPF flags is not generated when CTCCLR=1 Rev. 1.01 59 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTM output is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. PWM Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 10 respectively. The PWM function within the CTM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTM output, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the CTCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The CTOC bit In the CTMC1 register is used to select the required polarity of the PWM waveform while the two CTIO1 and CTIO0 bits are used to enable the PWM output or to force the CTM output to a fixed high or low level. The CTPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit CTM, PWM Output Mode, Edge-aligned Mode, CTDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=4MHz, CTM clock source is fSYS/4, CCRP =100b and CCRA =128, The CTM PWM output frequency=(fSYS/4)/512=fSYS/2048=1.9531 kHz, Duty=128/512=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit CTM, PWM Output Mode, Edge-aligned Mode, CTDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the CTM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.01 60 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value CTDPX = 0; CTM [1:0] = 10 Counter cleared by CCRP Counter Reset when CTON returns high CCRP Pause Resume Counter Stop if CTON bit low CCRA Time CTON CTPAU CTPOL CCRA Int. flag CTMAF CCRP Int. flag CTMPF CTM O/P Pin (CTOC=1) CTM O/P Pin (CTOC=0) PWM resumes Output controlled by operation other pin-shared function Output Inverts when CTPOL = 1 PWM Period set by CCRP PWM Duty Cycle set by CCRA PWM Output Mode – CTDPX=0 Note: 1. Here CTDPX=0 – Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when CTIO [1:0]=00 or 01 4. The CTCCLR bit has no influence on PWM operation. Rev. 1.01 61 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value CTDPX = 1; CTM [1:0] = 10 Counter cleared by CCRA Counter Reset when CTON returns high CCRA Pause Resume Counter Stop if CTON bit low CCRP Time CTON CTPAU CTPOL CCRP Int. flag CTMPF CCRA Int. flag CTMAF CTM O/P Pin (CTOC=1) CTM O/P Pin (CTOC=0) PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin-shared function Output Inverts when CTPOL = 1 PWM Period set by CCRA PWM Output Mode – CTDPX=1 Note: 1. Here CTDPX=1 – Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTIO [1:0]=00 or 01 4. The CTCCLR bit has no influence on PWM operation. Rev. 1.01 62 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with external input pin and can drive one external output pins. CCRP fSYS/4 fSYS fH/16 fH/64 fSUB fSUB STCK 000 001 010 011 100 101 110 111 3-bit Comparator P Comparator P Match STMPF Interrupt STOC b7~b9 10-bit Count-up Counter STON STPAU STCK2~STCK0 Counter Clear 0 1 STCCLR b0~b9 10-bit Comparator A Output Control Polarity Control Pin Control STM1, STM0 STIO1, STIO0 STPOL PAS0 Comparator A Match STP STMAF Interrupt STIO1, STIO0 Edge Detector CCRA Pin Control STPI STPIPS,PAS0 Standard Type TM Block Diagram Standard TM Operation The size of Standard TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3-bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10-bit and therefore compares all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the STON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a STM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.01 63 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes and the 3-bit CCRP value. Bit Register Name 7 6 5 4 3 2 1 0 STMC0 STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0 STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D7 D6 D5 D4 D3 D2 D1 D0 STMDH — — — — — — D9 D8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH — — — — — — D9 D8 10-bit Standard TM Registers List STMC0 Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 STPAU: STM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 STCK2~STCK0: Select STM Counter Clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the STM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3 STON: STM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the STM. Setting the bit high enables the counter to run while clearing the bit disables the STM. Clearing this bit to zero will stop the counter from counting and turn off the STM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the STM is in the Compare Match Output Mode then the STM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. 64 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Bit 2~0 STRP2~STRP0: STM CCRP 3-bit Register, Compared with the STM Counter bit 9~bit 7 Comparator P Match Period 000: 1024 STM clocks 001: 128 STM clocks 010: 256 STM clocks 011: 384 STM clocks 100: 512 STM clocks 101: 640 STM clocks 110: 768 STM clocks 111: 896 STM clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTCCLR bit is set to zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. STMC1 Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM. To ensure reliable operation the STM should be switched off before any changes are made to the STM1 and STM0 bits. In the Timer/Counter Mode, the STM output pin control will be disabled. Bit 5~4 STIO1~STIO0: Select STM Function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of STPI 01: Input capture at falling edge of STPI 10: Input capture at rising/falling edge of STPI 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the STM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the STM is running. 65 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU In the Compare Match Output Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the STM output pin should be setup using the STOC bit in the STMC1 register. Note that the output level requested by the STIO1 and STIO0 bits must be different from the initial value setup using the STOC bit otherwise no change will occur on the STM output pin when a compare match occurs. After the STM output pin changes state, it can be reset to its initial level by changing the level of the STON bit from low to high. In the PWM Output Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the STIO1 and STIO0 bits only after the STM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the STM is running. Rev. 1.01 Bit 3 STOC: STM STP Output Control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM Output Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/ Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM Output Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2 STPOL: STM STP Output Polarity Control 0: Non-inverted 1: Inverted This bit controls the polarity of the STP output pin. When the bit is set high the STM output pin will be inverted and not inverted when the bit is zero. It has no effect if the STM is in the Timer/Counter Mode. Bit 1 STDPX: STM PWM Duty/Period Control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 STCCLR: STM Counter Clear Condition Selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. 66 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter Low Byte Register bit 7 ~ bit 0 STM 10-bit Counter bit 7 ~ bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 STM Counter High Byte Register bit 1 ~ bit 0 STM 10-bit Counter bit 9 ~ bit 8 STMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STM CCRA Low Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 7 ~ bit 0 STMAH Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 STM CCRA High Byte Register bit 1 ~ bit 0 STM 10-bit Counter bit 9 ~ bit 8 67 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Standard Type TM Operation Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the STM output pin, will change state. The STM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the STM output pin. The way in which the STM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place. Rev. 1.01 68 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU STCCLR = 0; STM [1:0] = 00 Counter overflow Counter Value CCRP > 0 Counter cleared by CCRP value CCRP=0 0x3FF CCRP > 0 Counter Restart Resume CCRP Stop Pause CCRA Time STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin Output pin set to initial Level Low if STOC=0 Output not affected by STMAF flag. Remains High until reset by STON bit Output Toggle with STMAF flag Here STIO [1:0] = 11 Toggle Output select Note STIO [1:0] = 10 Active High Output select Output Inverts when STPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – STCCLR=0 Note: 1. With STCCLR=0 a Comparator P match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to itsinitial state by a STON bit rising edge Rev. 1.01 69 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time STON STPAU STPOL No STMAF flag generated on CCRA overflow CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin Output does not change STMPF not generated Output pin set to initial Level Low if STOC=0 Output Toggle with STMAF flag Here STIO [1:0] = 11 Toggle Output select Output not affected by STMAF flag. Remains High until reset by STON bit Note STIO [1:0] = 10 Active High Output select Output Inverts when STPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – STCCLR=1 Note: 1. With STCCLR=1 a Comparator A match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to its initial state by a STON bit rising edge 4. A STMPF flag is not generated when STCCLR=1 Rev. 1.01 70 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=4MHz, TM clock source is fSYS/4, CCRP =100b and CCRA=128, The STM PWM output frequency=(fSYS/4)/512=fSYS /2048=1.9531 kHz, duty=128/512=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.01 71 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value STDPX = 0; STM [1:0] = 10 Counter cleared by CCRP Counter Reset when STON returns high CCRP Pause Resume Counter Stop if STON bit low CCRA Time STON STPAU STPOL CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when STPOL = 1 PWM Period set by CCRP PWM Output Mode – STDPX=0 Note: 1. Here STDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STIO [1:0]=00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.01 72 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value STDPX = 1; STM [1:0] = 10 Counter cleared by CCRA Counter Reset when STON returns high CCRA Pause Resume Counter Stop if STON bit low CCRP Time STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM resumes operation Output controlled by Output Inverts other pin-shared function when STPOL = 1 PWM Period set by CCRA PWM Duty Cycle set by CCRP PWM Output Mode – STDPX=1 Note: 1. Here STDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when STIO [1:0]=00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.01 73 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Output Mode, the STON bit can also be made to automatically change from low to high using the STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from ComparatorA. However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Output Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. S/W Command SET“STON” or STCK Pin Transition CCRA Leading Edge CCRA Trailing Edge STON bit 0→1 STON bit 1→0 S/W Command CLR“STON” or CCRA Compare Match STP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.01 74 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value STM [1:0] = 10 ; STIO [1:0] = 11 Counter stopped by CCRA Counter Reset when STON returns high CCRA Pause Counter Stops by software Resume CCRP Time STON Software Trigger Cleared by CCRA match Auto. set by STCK pin STCK pin Software Trigger Software Trigger Software Software Trigger Clear STCK pin Trigger STPAU STPOL CCRP Int. Flag STMPF No CCRP Interrupts generated CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) Output Inverts when STPOL = 1 Pulse Width set by CCRA Single Pulse Output Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the STCK pin or by setting the STON bit high 4. A STCK pin active edge will automatically set the STON bit high. 5. In the Single Pulse Output Mode, STIO [1:0] must be set to "11" and can not be changed. Rev. 1.01 75 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STPI pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPI pin the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPI pin, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.01 76 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Counter Value STM [1:0] = 01 Counter cleared by CCRP Counter Stop Counter Reset CCRP YY Pause Resume XX Time STON STPAU Active edge Active edge Active edge STM capture pin STPI CCRA Int. Flag STMAF CCRP Int. Flag STMPF CCRA Value STIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. STM [1:0]=01 and active edge set by the STIO [1:0] bits 2. A STM Capture input pin active edge transfers the counter value to CCRA 3. STCCLR bit not used 4. No output function – STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.01 77 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Over Voltage Protection – OVP The device includes an over voltage protection function which provides a protection mechanism for applications. To prevent the operating voltage from exceeding a specific level, the voltage on the OVP pin is compared with a reference voltage generated by an 8-bit D/A converter. When an over voltage event occurs, an OVP interrupt will be generated if the corresponding interrupt control is enabled. OVPVRS M U X OVPVR VDD OVPDA[7:0] 8-bit DAC OVPCHY S1 S2 CMP + S0 OVPI OVPO OVPDEB[1:0] - Debounce OVPINT fSYS OVPEN Note: The OVP signal comes from the AUDOVP and the OVPINT is connected to STPI. Over Voltage Protection Circuit Over Voltage Protection Operation The voltage input signal OVPI is supplied on the OVP pin and then connected to one input of the comparator. A D/A converter is used to generate a reference voltage. The comparator compares the reference voltage with the input voltage to produce the OVPO signal. Over Voltage Protection Control Registers Overall operation of the over voltage protection is controlled using several registers. One register is used to provide the reference voltages for the over voltage protection circuit. The remaining two registers are control registers which are used to control the OVP function, D/A converter reference voltage selection, comparator de-bounce time, comparator hysteresis function together with the comparator input offset calibration. Bit Register Name 7 6 5 4 3 2 1 0 OVPC0 — — OVPEN OVPCHY — OVPVRS OVPDEB1 OVPDEB0 OVPC1 OVPO OVPCOF4 OVPCOF3 OVPCOF2 OVPCOF1 OVPCOF0 OVPDA D7 D4 D3 D2 D1 D0 OVPCOFM OVPCRS D6 D5 OVP Control Register List OVPC0 Register Rev. 1.01 Bit 7 6 5 4 3 Name — — OVPEN OVPCHY — 2 1 0 OVPVRS OVPDEB1 OVPDEB0 R/W — — R/W R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 OVPEN: OVP function control bit 0: Disable 1: Enable If the OVPEN bit is cleared to 0, the over voltage protection function is disabled and no power will be consumed. This results in the comparator and D/A converter of OVP all being switched off. 78 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU OVPCHY: OVP comparator hysteresis function control bit 0: Disable 1: Enable Bit 4 Bit 3 Unimplemented, read as "0" Bit 2 OVPVRS: OVP DAC reference voltage selection bit 0: DAC reference voltage comes from VDD 1: DAC reference voltage comes from OVPVR If the DAC reference voltage is selected to come from the OVPVR pin, it is required to properly configure the corresponding pin-shared control bit to choose the right pin function. Bit 1~0 OVPDEB1~OVPDEB0: OVP comparator debounce time control bits 00: No debounce 01: (7~8) × 1/fSYS 10: (15~16) × 1/fSYS 11: (31~32) × 1/fSYS OVPC1 Register Bit 7 6 5 4 3 2 1 0 Name OVPO OVPCOFM OVPCRS OVPCOF4 OVPCOF3 OVPCOF2 OVPCOF1 OVPCOF0 R/W R R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 1 0 0 0 0 Bit 7 OVPO: OVP comparator ouptut bit 0: Positive input voltage < negative input voltage 1: Positive input voltage > negative input voltage Bit 6 OVPCOFM: OVP comparator normal operation or input offset voltage calibration mode selection 0: Normal operation 1: Input offset voltage calibration mode Bit 5 OVPCRS: OVP comparator input offset voltage calibration reference selection bit 0: Input reference voltage comes from negative input 1: Input reference voltage comes from positive input Bit 4~0 OVPCOF4 ~ OVPCOF0: OVP comparator input offset voltage calibration control bits OVPDA Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.01 OVP DAC output voltage control bits DAC VOUT=(DAC reference voltage/256) × D[7:0] 79 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Offset Calibration The OVPCOFM bit in the OVPC1 register is used to select the OVP comparator operating mode, normal operation or offset calibration mode. If set the bit high, the comparator will enter the offset voltage calibration mode. It is need to note that before offset calibration, the hysteresis voltage should be zero by set OVPCHY=0 and because the OVP pin are pin-shared with I/O, it should be configured as comparator input first. Comparator Calibration Procedure Step 1: Set OVPCOFM=1, OVPCRS=1, the OVP is now in the comparator calibration mode, S0 and S2 on. To make sure VOS as minimize as possible after calibration, the input reference voltage in calibration should be the same as input DC operating voltage in normal mode operation. Step 2: Set OVPCOF [4:0] =00000 then read OVPO bit. Step 3: Let OVPCOF[4:0]=OVPCOF[4:0]+1 then read the OVPO bit status; if OVPO is changed, record the OVPCOF[4:0] data as VOS1. Step 4: Set OVPCOF [4:0] =11111 then read the OVPO bit status. Step 5: Let OVPCOF[4:0]=OVPCOF[4:0]-1 then read the OVPO bit status; if OVPO data is changed, record the OVPCOF[4:0] data as VOS2. Step 6: Restore VOS=(VOS1 + VOS2)/2 to the OVPCOF[4:0] bits. The calibration is finished. If (VOS1 + VOS2)/2 is not integral, discard the decimal. Residue VOS=VOUT - VIN Rev. 1.01 80 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Sine Wave Generator The device contains a function which can generate an approximate sinusoidal waveform for transmission to the earphone audio interface on smartphones. These simulated sinusoidal waveforms are used to represent data through which the application MCU can transmit data in sinusoidal format to smartphones for processing. Sine Wave Generator Operation Using this function data can be transmitted from the MCU to the smartphone using simulated audio frequency sine waves. The Sine Wave Generator is composed of an 8-bit counter/divider, a 5-bit up/down counter and two D/A converters. By clamping the peak output of the counter to a certain level an approximate to a sine wave can be generated digitally. The AUDLI input and ASWO output signals are sourced from the MIC1, MIC2, Rin or Lin pins, seleted by the pin-shared function register PAS0. More detail information is contained in the "Pin-shared Function Selection" Section. AUDLI ASWEN ASWEN ASWCLK 8-bit Counter A* 5-bit U/D Counter ASWEN D* S1 E* ASWEdge Function ASWDAC0S[2:0] B* Logic C* clamping 1CH 0FH 03H 00H VDD ASWDAC0EN M U X VDRSW0 5-bit D/A0 ASWTMR[7:0] 1k ASWSW0 2k ASWSW1 4k ASWSW2 8k ASWSW3 16k ASWSW4 32k ASWSW5 32k ASWSW6 20k 20k AUDOVP (to OVPI input) VDRSW1 VDRSW2 Vss ASWO ASWDAC1EN ASWDAC1D[4:0] 5-bit D/A1 ASWINT (to CTM clock input) Sine Wave Generator Circuit The ASWCLK clock input drives an 8-bit counter whose overflow signal creates a divided clock. This divided clock then drives a 5-bit up/down counter whose output which generates an approximate triangle waveform. The Logic Clamping circuit sets a limit on the triangle waveform, clamping it to a certain value and thus allowing the original triangle wave to be closer to the shape of a sinusoidal waveform. Here the maximum value for up-counting is 01CH while the minimum value for down-counting is 03H. An output signal from the 5-bit up/down counter is also used to control the up/down function of the counter. Rev. 1.01 81 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Sine Wave Output Control Registers Register Name ASWTMR Bit 7 6 5 ASWTMR7 ASWTMR6 ASWTMR5 4 3 2 1 0 ASWTMR4 ASWTMR3 ASWTMR2 ASWTMR1 ASWTMR0 ASWC0 — — — — — ASWC1 — ASWSW6 ASWSW5 ASWSW4 ASWSW3 ASWDAC0 — — — — — ASWDAC1 — — — VDRC — — — ASWDAC1EN ASWDAC0EN ASWSW2 ASWSW1 ASWEN ASWSW0 ASWDAC0S2 ASWDAC0S1 ASWDAC0S0 ASWDAC1D4 ASWDAC1D3 ASWDAC1D2 ASWDAC1D1 ASWDAC1D0 — — VDRSW2 VDRSW1 VDRSW0 Sine Wave Output Control Registers ASWTMR Register Bit Name 7 6 5 4 3 2 1 0 ASWTMR7 ASWTMR6 ASWTMR5 ASWTMR4 ASWTMR3 ASWTMR2 ASWTMR1 ASWTMR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 ASWTMR[7:0]: 8-bit counter preload register bit 7 ~ bit 0 This register is used to store the 8-bit counter preload value. When the counter is disabled, the preload value will be immediately loaded into the 8-bit counter. If the counter is enabled, the preload value will be loaded into the counter when the sine wave is completely output. ASWC0 Register Rev. 1.01 Bit 7 6 5 4 3 Name — — — — — 2 1 0 ASWDAC1EN ASWDAC0EN ASWEN R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as "0" Bit 2 ASWDAC1EN: DAC1 enable or disable control 0: Disable 1: Enable When the DAC1 is disabled by setting this bit low, the DAC1 output will be floating. Bit 1 ASWDAC0EN: DAC0 enable or disable control 0: Disable 1: Enable When the DAC0 is disabled by setting this bit low, the DAC0 output will be floating. Bit 0 ASWEN: Sine Wave 8-bit Counter enable or disable control 0: Disable 1: Enable When the 8-bit counter is disabled by setting this bit low, the counter value will keeping counting until the sine wave is completely output. Then the counter value will be 0FH. 82 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU ASWC1 Register Bit 7 Name — 6 5 4 3 2 1 0 ASWSW6 ASWSW5 ASWSW4 ASWSW3 ASWSW2 ASWSW1 ASWSW0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 1 1 1 1 1 1 1 Bit 7 Unimplemented, read as "0" Bit 6 ASWSW6: 32kΩ series-resistor SW control bit 0: Off 1: On Bit 5 ASWSW5: 32kΩ series-resistor SW control bit 0: Off 1: On Bit 4 ASWSW4: 16kΩ series-resistor SW control bit 0: Off 1: On Bit 3 ASWSW3: 8kΩ series-resistor SW control bit 0: Off 1: On Bit 2 ASWSW2: 4kΩ series-resistor SW control bit 0: Off 1: On Bit 1 ASWSW1: 2kΩ series-resistor SW control bit 0: Off 1: On Bit 0 ASWSW0: 1kΩ series-resistor SW control bit 0: Off 1: On ASWDAC0 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — ASWDAC0S2 ASWDAC0S1 ASWDAC0S0 R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 1 0 Bit 7~3 Unimplemented, read as "0" Bit 2~0 ASWDAC0S[2:0]: DAC0 output control code selection 000: Logic Clamping Output 001: Digital Value 1CH 010: Digital Value 0FH 011: Digital Value 03H 1xx: Digital Value 00H ASWDAC1 Register Rev. 1.01 Bit 7 6 5 Name — — — ASWDAC1D4 ASWDAC1D3 ASWDAC1D2 ASWDAC1D1 ASWDAC1D0 4 3 2 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as "0" Bit 4~0 ASWDAC1D[4:0]: DAC1 output control code 83 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU VDRC Register Bit 7 6 5 4 3 Name — — — — — 2 1 0 VDRSW2 VDRSW1 VDRSW0 R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as "0" Bit 2 VDRSW2: SW control bit 0: Off 1: On Bit 1 VDRSW1: 20kΩ resistor SW control bit 0: Off 1: On Bit 0 VDRSW0: 20kΩ resistor SW control bit 0: Off 1: On Sine Wave Output Function Operation • The ASWTMR register is used to preset the new frequency value to be changed in the next period. • ASWO waveform frequency: fASWO=fASWCLK/((256-ASWTMR)×64). • The ASWCLK can be sourced from the system clock HIRC or other clock sources, with a frequency range of 400kHz~12MHz. Note that the ASWCLK clock will be stopped if its clock source is also stopped when the CPU is off after the "HALT" instruction executed. • ASWEdge function: When the 5-bit up/down counter counts up, and reaches the value of 0FH, the ASWEdge function will output an edge signal. • Logic clamping function: The 5-bit up/down counter has a maximum value of 1FH and a minimum value of 00H, by using the logic clamping function, the values will become to 1CH and 03H respectively. • When the VDRSW2 bit is 1, AUDOVP is connected to ASWO. Rev. 1.01 84 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Sine Wave Generation Timing ASWCLK ASWEN 1 0 A 15 31 0 0 31 0 15 31 0 31 0 15 15 1CH B 0FH 03H ASWTMR=254 ASWTMR=255 ASWTMR=255 ASWTMR=254 ASWTMR 1CH C 0FH 03H D td為8 ASWCLK E T0 T1 t12 T2 t23 T3 t34 T4 Sine Wave Generation Timing Timing Description • Set up the ASWTMR value and set ASWDAC0S[2:0] to 00H, choose the DAC0 input as the logic gate path. • When the ASWEN bit is low, the preload value in the ASWTMR register will be loaded into the 8-bit counter directly. • When the ASWEN bit is high, the 5-bit up/down counter will start counting from an initial value of 0FH. • If the frequency switch is not required, when the E point signal generates an edge, the ASWTMR switch S1 will be on, and will re-load a value to the 8-bit counter. • I������������������������������������������������������������������������������������������� f the frequency switch is required, when an ASWEdge ��������������������������������������� function������������������������������� is generated, it can be implemented by writting a new value to the ASWTMR register before the next ASWEdge function occurs. Note that during this writing time the ASWTMR switch S1 action is forbidden. For example, when an ASWEdge function is generated at the T2 point in the timing diagram, setting up a new ASWTMR value during the t23 period will switch the frequency at the T3 point. • T������������������������������������������������������������������������������������������������ he C point is the waveform output of logic gate. When the 5-bit counter count-up value is greater than 1CH, the output will remain at a value of 1CH. When the count-down value is less than 03H, the output will remain at a value of 03H which will be output to the 5-bit D/A converter 0. • To stop the output waveforms, the ASWEN bit needs to be cleared, and the frequency output needs to be stopped when the next E point generates an edge. For example, in the timing diagram above, clearing the ASWEN bit to zero during the t34 period will stop the frequency output on point C at T4. During the t34 period, if the ASWEN bit is set high, waveforms will be continuously output and check if it is required to stop to output waveforms when the ASWEN bit becomes low. Rev. 1.01 85 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupt functions. The external interrupts are generated by the action of the external INT pin, while the internal interrupts are generated by various internal functions such as the Timer Modules, Time Base, Over Voltage Protection, Sine Wave Function and Low Voltage Detector. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory. The registers fall into three categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupts trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Global Enable Bit Request Flag Notes EMI — — INT Pin INTE INTF — Multi-function MFnE MFnF n=0~1 Time Base TBnE TBnF n=0~1 OVP OVPE OVPF — ASW ASWE ASWF — — LVD CTM STM LVDE LVDF CTMAE CTMAF CTMPE CTMPF STMAE STMAF STMPE STMPF — — Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — — — INTS1 INTS0 INTC0 — TB1F TB0F INTF TB1E TB0E INTE EMI INTC1 LVDF OVPF MF1F MF0F LVDE OVPE MF1E MF0E INTC2 — — — ASWF — — — ASWE MFI0 — — STMAF STMPF — — STMAE STMPE MFI1 — — CTMAF CTMPF — — CTMAE CTMPE Interrupt Register List Rev. 1.01 86 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — INTS1 INTS0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 INTS1~INTS0: Interrupt Edge Control for INT Pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INTC0 Register Rev. 1.01 Bit 7 6 5 4 3 2 1 Name — TB1F TB0F INTF TB1E TB0E INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TB1F: Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5 TB0F: Time Base 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4 INTF: External Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 TB1E: Time Base 1 Interrupt Enable 0: Disable 1: Enable Bit 2 TB0E: Time Base 0 Interrupt Enable 0: Disable 1: Enable Bit 1 INTE: External Interrupt Enable 0: Disable 1: Enable Bit 0 EMI: Global Interrupt Enable 0: Disable 1: Enable 87 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU INTC1 Register Bit 7 6 5 4 3 2 1 0 Name LVDF OVPF MF1F MF0F LVDE OVPE MF1E MF0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7 LVDF: LVD Interrupt Request Flag 0: No request 1: Interrupt request Bit 6 OVPF: OVP Interrupt Request Flag 0: No request 1: Interrupt request Bit 5 MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 4 MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request Bit 3 LVDE: LVD Interrupt Enable 0: Disable 1: Enable Bit 2 OVPE: OVP Interrupt Enable 0: Disable 1: Enable Bit 1 MF1E: Multi-function Interrupt 1 Control 0: Disable 1: Enable Bit 0 MF0E: Multi-function Interrupt 0 Control 0: Disable 1: Enable INTC2 Register Bit Rev. 1.01 7 6 5 4 3 Name — — — ASWF — — — ASWE R/W — — — R/W — — — R/W POR — — — 0 — — — 0 Bit 7~5 Unimplemented, read as "0" Bit 4 ASWF: Sine Wave Interrupt Request Flag 0: No request 1: Interrupt request Bit 3~1 Unimplemented, read as "0" Bit 0 ASWE: Sine Wave Interrupt Enable 0: Disable 1: Enable 88 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — STMAF STMPF — — STMAE STMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 2 1 0 Bit 7~6 Unimplemented, read as "0" Bit 5 STMAF: STM CCRA Comparator Interrupt Request Flag 0: No request 1: Interrupt request Bit 4 STMPF: STM CCRP Comparator Interrupt Request Flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 STMAE: STM CCRA Comparator Interrupt Enable 0: Disable 1: Enable Bit 0 STMPE: STM CCRP Comparator Interrupt Enable 0: Disable 1: Enable MFI1 Register Bit Rev. 1.01 7 6 5 4 3 Name — — CTMAF CTMPF — — CTMAE CTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 CTMAF: CTM CCRA Comparator Interrupt Request Flag 0: No request 1: Interrupt request Bit 4 CTMPF: CTM CCRP Comparator Interrupt Request Flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 CTMAE: CTM CCRA Comparator Interrupt Enable 0: Disable 1: Enable Bit 0 CTMPE: CTM CCRP Comparator Interrupt Enable 0: Disable 1: Enable 89 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match or A/D conversion completion etc., the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.01 90 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU xxF Legend Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR xxE Enable Bits Interrupt Name Request Flags Enable Bits EMI auto disabled in ISR Interrupt Name Request Flags Enable Bits Master Enable Vector INT Pin INTF INTE EMI 04H Time Base 0 TB0F TB0E EMI 08H Time Base 1 TB1F TB1E EMI 0CH STM P STMPF STMPE STM A STMAF STMAE M. Funct. 0 MF0F MF0E EMI 10H CTM P CTMPF CTMPE M. Funct. 1 MF1F MF1E EMI 14H CTM A CTMAF CTMAE OVP OVPF OVPE EMI 18H LVD LVDF LVDE EMI 1CH ASW ASWF ASWE EMI 20H Interrupts contained within Multi-Function Interrupts Priority High Low Interrupt Structure External Interrupt The external interrupts are controlled by signal transitions on the pin INT. An external interrupt request will take place when the external interrupt request flag, INTF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pins if the external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Rev. 1.01 91 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU OVP Interrupt The OVP Interrupt is controlled by detecting the input voltage. An OVP Interrupt request will take place when the OVP Interrupt request flag, OVPF, is set, which occurs when a high voltage is detected. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and OVP Interrupt enable bit, OVPE, must first be set. When the interrupt is enabled, the stack is not full and a large voltage is detected, a subroutine call to the OVP Interrupt vector, will take place. When the interrupt is serviced, the OVP Interrupt flag, OVPF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. LVD Interrupt An LVD Interrupt request will take place when the LVD Interrupt request flag, LVDF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Low Voltage Interrupt enable bit, LVDE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take place. When the interrupt is serviced, the LVD Interrupt flag, LVDF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. ASW Interrupt An ASW Interrupt request will take place when the ASW Interrupt request flag, ASWF, is set, which occurs when the ASWEdge function generates an edge signal. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Sine Wave Interrupt enable bit, ASWE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the ASW Interrupt vector, will take place. When the interrupt is serviced, the ASW Interrupt flag, ASWF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Multi-function Interrupts Within this device there are two Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts will not be automatically reset and must be manually reset by the application program. Rev. 1.01 92 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TBnF will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fTB, originates from the internal clock source fTBC or fSYS/4 and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC registers to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the TBCK bit in the TBC register. TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 — TB02 TB01 TB00 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 1 1 — 1 1 1 Bit 7 TBON: Time Base 0 and Time Base 1 Control 0: Disable 1: Enable Bit 6 TBCK: Select fTB clock 0: fTBC 1: fSYS/4 Bit 5~4 TB11~TB10: Select Time Base 1 Time-out Period 00: 212/fTB 01: 213/fTB 10: 214/fTB 11: 215/fTB Bit 3 Unimplemented, read as "0" Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period 000: 28/fTB 001: 29/fTB 010: 210/fTB 011: 211/fTB 100: 212/fTB 101: 213/fTB 110: 214/fTB 111: 215/fTB TB02 ~ TB00 fSYS/4 LIRC fTBC M U X ÷ 28 ~ 215 Time Base 0 Interrupt ÷ 212 ~ 215 Time Base 1 Interrupt fTB TBCK Bit TB11 ~ TB10 Time Base Interrupt Rev. 1.01 93 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Timer Module Interrupts Each of the Compact Type TM and Standard Type TM has two interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For the Compact Type TM and Standard Type TM, each has two interrupt request flags of xTMPF, xTMAF and two enable bits of xTMPE, xTMAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltage may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.01 94 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.01 95 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Low Voltage Detector – LVD The device has a Low Voltage Detector function, also known as LVD. This enables the device to monitor the power supply voltage, VDD, and provides a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The ENLVD bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Rev. 1.01 Bit 7 6 5 4 3 2 1 0 Name — — LVDO ENLVD — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 LVDO: LVD Output Flag 0: No Low Voltage Detected 1: Low Voltage Detected Bit 4 ENLVD: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as "0" Bit 2~0 VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V 96 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device enters the SLEEP mode, the low voltage detector will be disabled even if the ENLVD bit is set high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. VDD VLVD LVDEN LVDO tLVDS LVD Operation The Low Voltage Detector also has its own interrupt, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. In this case, the LVDF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVDF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.01 97 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Application Circuits VDD 60kΩ 0.1µF 60kΩ L VDD R SDA MIC1 SCL MCU VSS MIC2 BH45F0031 Earphone Jack Type L R MIC GND Non-international Standard 4-conductor Contact Pin Structure L R MIC GND International Standard 4-conductor Contact Pin Structure Earphone Jack Insert Detection • MCU enters the SLEEP Mode ♦♦ The MIC1/MIC2 pins are setup to have I/O functions and to output low. ♦♦ The R pin is setup as an input with pull-high resistor and wake-up functions both enabled. • When the Phone Jack does not detect an insertion, the R pin will be in a high state. • When an earphone is plugged into the Phone Jack, the R pin will change to a low state. The device can then be woken up using the circuit formed by the R pin, MIC1/MIC2 pin and GND pin. Rev. 1.01 98 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU MIC/GND Automatic Pin Switching − Earphone Jack Type Discrimination As the figure shows, earphone jacks are classified as two types. It is therefore required to discriminate the MIC pin position. • After the device has been woken up ♦♦ Configure the OVP MUX Input Path to come from the MIC2 pin and setup a proper voltage for the D/A converter. ♦♦ Set the MIC1 pin low. ♦♦ Delay for a certain time, such as 1.5s, wait until the iPhone or other cellphone automatic detection has completed. ♦♦ Check the OVP comparator output flag • If the comparator output flag is high, it indicates that the MIC1 pin is connected to GND and therefore the MIC2 pin is configured as an MIC pin. Setup the D/A converter voltage to 1/2VDD for normal operation after the automatic detection process has completed. • If the comparator output flag is low, this indicates that the MIC and GND position configurations have failed. Setup the OVP MUX input path to come from the MIC1 pin and set the MIC2 pin low, then repeat Step 1. • Check the comparator output flag: ♦♦ If the comparator output flag is high, the MIC1 pin is configured as an MIC pin and the MIC2 pin as GND. ♦♦ If the comparator output flag is low, repeat the above procedures to re-initiate a detection operation. Start the Earphone Interface Communication • After the “Earphone Jack Insert Detection” and “MIC/GND Automatic Pin Switching” operations have completed, the earphone interface communication can be initiated. • The BH45F0031 device outputs a sine wave earphone interface signal through the MIC pin and receives the earphone interface signal on the L pin. • Use the internal OVP to convert the received earphone interface signal to a digital signal and process these digital signals using the internal CTM and application program. • The Sine Wave Generator generates a Sine Wave on either the MIC1 or MIC2 pin. When the MIC pin is connected to a cellphone, the VPP and VDC voltages on this pin can be amplified by adjusting the Sine Wave Generator output voltage. The adjustment operation can be implemented by configuring the internal divider resistance and the D/A converter. Rev. 1.01 99 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.01 100 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.01 101 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] Logical AND Data Memory to ACC OR A,[m] Logical OR Data Memory to ACC XOR A,[m] Logical XOR Data Memory to ACC ANDM A,[m] Logical AND ACC to Data Memory ORM A,[m] Logical OR ACC to Data Memory XORM A,[m] Logical XOR ACC to Data Memory AND A,x Logical AND immediate Data to ACC OR A,x Logical OR immediate Data to ACC XOR A,x Logical XOR immediate Data to ACC CPL [m] Complement Data Memory CPLA [m] Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.01 102 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read Operation TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.01 103 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.01 Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z 104 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CALL addr Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Rev. 1.01 Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z 105 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z DAA [m] Description Operation Operation Affected flag(s) Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z HALT Description Operation Operation Affected flag(s) Rev. 1.01 106 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z JMP addr Description Operation Affected flag(s) OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) Rev. 1.01 Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None 107 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) RLC [m] Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) Rev. 1.01 Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None 108 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) SBC A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) Rev. 1.01 Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None 109 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SDZA [m] Description Operation Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) Rev. 1.01 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C 110 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SUB A,x Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) Rev. 1.01 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None 111 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU TABRD [m] Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev. 1.01 Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z 112 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.01 113 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU 8-pin SOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — 0.020 C 0.012 — C’ — 0.193 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol A Rev. 1.01 Dimensions in mm Min. Nom. Max. — 6 BSC — B — 3.9 BSC — C 0.31 — 0.51 C’ — 4.9 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 114 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU 16-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — 0.020 C 0.012 — C' — 0.390 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° ― 8° Symbol Rev. 1.01 Dimensions in mm Min. Nom. Max. — A — 6.000 BSC B — 3.900 BSC — C 0.31 — 0.51 C' — 9.900 BSC — D — — 1.75 E — 1.270 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° ― 8° 115 April 11, 2017 BH45F0031 Earphone Interface Bridge Flash MCU Copyright© 2017 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw/en/home. Rev. 1.01 116 April 11, 2017