A8502 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver Description Features and Benefits • AEC-Q100 qualified • Wide input voltage range of 5 to 40 V for start/stop, cold crank and load dump requirements • Fully integrated LED current sinks and boost converter with 60 V DMOS • Sync function to synchronize boost converter switching frequency up to 2.3 MHz, allowing operation above the AM band • Excellent input voltage transient response • Single resistor primary OVP minimizes VOUT leakage • Internal secondary OVP for redundant protection • LED current of 120 mA per channel • Drives up to 12 series LEDs in 2 parallel strings • 0.7% to 0.8% LED to LED matching accuracy • PWM and analog dimming inputs • 5000:1 PWM dimming at 200 Hz • Provides driver for optional external PMOS input disconnect switch • Extensive protection against: ▫ Shorted boost switch or inductor ▫ Shorted FSET or ISET resistor ▫ Shorted output ▫ Open or shorted LED pin ▫ Open boost Schottky ▫ Overtemperature (OTP) The A8502 is a multi-output white LED driver for small-size LCD backlighting. It integrates a current-mode boost converter with internal power switch and two current sinks. The boost converter can drive up to 24 LEDs, 12 LEDs per string, at 120 mA. The LED sinks can be paralleled together to achieve even higher LED currents, up to 240 mA. The A8502 can operate with a single power supply, from 5 to 40 V, which allows the part to withstand load dump conditions encountered in automotive systems. If required, the A8502 can drive an external P-FET to disconnect the input supply from the system in the event of a fault. The A8502 provides protection against output short and overvoltage, open or shorted diode, open or shorted LED pin, shorted boost switch or inductor, shorted FSET or ISET resistor, and IC overtemperature. A dual level cycle-by-cycle current limit function provides soft start and protects the internal current switch against high current overloads. The A8502 has a synchronization pin that allows PWM switching frequencies to be synchronized in the range of 580 kHz to 2.3 MHz. The high switching frequency allows the A8502 to operate above the AM radio band. Continued on the next page… Package: 16-pin TSSOP with exposed thermal pad (suffix LP) Applications: LCD backlighting or LED lighting for: ▫ Automotive infotainment ▫ Automotive cluster ▫ Automotive center stack Not to scale Typical Application Circuit VIN 10 to 14 V CIN 4.7 μF 50 V RSC 0.033 Ω RADJ 249 Ω Q1 RC 20 Ω CC 22 nF GATE VSENSE VIN VDD VC CVDD 0.1 μF 100 kΩ D1 2 A / 60 V L1 10 μH OVP COUT 4.7 μF 50 V A8502 PAD RFSET 10 kΩ ROVP 137 kΩ SW FAULT PWM/EN APWM ISET RISET 8.25 kΩ VOUT FSET/SYNC AGND LED1 LED2 COMP PGND CP 120 pF RZ 120 Ω CZ 0.47 μF Figure 1. Application with VIN to ground short protection, using optional P-MOSFET sensing A8502-DS, Rev. 3 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Description (continued) The A8502 is provided in a 16-pin TSSOP package (suffix LP) with an exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin lead frame plating. Selection Guide Part Number Packing* A8502KLPTR-T 4000 pieces per 13-in. reel *Contact Allegro™ for additional packing options Absolute Maximum Ratings* Characteristic Symbol Notes LEDx Pins OVP Pin Rating Unit –0.3 to 55 V –0.3 to 60 V VSENSE and GATE pins should not exceed VIN by more than 0.4 V –0.3 to 40 V Continuous –0.6 to 62 V –1.0 V ¯Ā¯Ū¯L̄¯T̄ ¯ Pin F̄ -0.3 to 40 V ISET, FSET, APWM, COMP Pins –0.3 to 5.5 V VIN, VSENSE, GATE Pins SW Pin t < 50 ns All Other Pins –0.3 to 7 V –40 to 125 ºC TJ(max) 150 ºC Tstg –55 to 150 ºC Operating Ambient Temperature TA Maximum Junction Temperature Storage Temperature Range K *Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. Table of Contents Specifications Pin-out Diagram and Terminal List Characteristic Performance Functional Description Enabling the IC Powering up: LED pin short-to-ground check Soft start function Frequency selection Sync LED current setting and LED dimming PWM dimming APWM pin Analog dimming 2 3 8 11 11 11 13 13 14 15 15 16 18 LED short detect Overvoltage protection Boost switch overcurrent protection Input overcurrent protection and disconnect switch Setting the current sense resistor Input UVLO VDD Shutdown Fault protection during operation Application Information Design Example for Boost Configuration Design Example for SEPIC Configuration Package Outline Drawing 18 18 21 22 23 23 23 24 24 26 26 30 34 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol RθJA Package Thermal Resistance Test Conditions* Value Unit 2 48.5 ºC/W On 4-layer PCB based on JEDEC standard 34 ºC/W On 2-layer PCB, 3 in. *Additional thermal information available on the Allegro website VDD 1 16 LED2 PGND 2 15 LED1 14 AGND OVP 3 Pin-out Diagram SW 4 GATE 5 VSENSE 6 PAD 13 ISET 12 FSET/SYNC 11 PWM/EN VIN 7 10 APWM FAULT 8 9 COMP Terminal List Table Number Name Function 1 VDD Output of internal LDO; connect a 0.1 μF decoupling capacitor between this pin and ground. 2 PGND 3 OVP Overvoltage Condition (OVP) sense; connect the ROVP resistor from VOUT to this pin to adjust the overvoltage protection. 4 SW The drain of the internal DMOS switch of the boost converter. 5 GATE 6 VSENSE 7 VIN Power ground for internal DMOS device. Output gate driver pin for external P-channel FET control. Connect this pin to the negative sense side of the current sense resistor RSC. The threshold voltage is measured as VIN – VSENSE . There is also a fixed current sink to allow for trip threshold adjustment. Input power to the A8502 as well as the positive input used for current sense resistor. 8 ¯Ā¯Ū¯L̄¯T̄ ¯ F̄ Indicates a fault condition. Connect a 100 kΩ resistor between this pin and the required logic level voltage. The pin is an open drain type configuration that will be pulled low when a fault occurs. 9 COMP Output of the error amplifier and compensation node. Connect a series RZ-CZ network from this pin to ground for control loop compensation. 10 APWM Analog trimming option for dimming. Applying a digital PWM signal to this pin adjusts the internal ISET current. 11 PWM/EN PWM dimming pin, used to control the LED intensity by using pulse width modulation. Also used to enable the A8502. 12 FSET/SYNC Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching frequency. This pin can also be used to synchronize two or more A8502s in the system. The maximum synchronization frequency is 2.3 MHz. 13 ISET 14 AGND LED signal ground. 15 LED1 Connect the cathode of the LED string to this pin. 16 LED2 Connect the cathode of the LED sring to this pin. – PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad. Connect the RISET resistor between this pin and ground to set the 100% LED current. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Functional Block Diagram VDD SW Internal VCC Regulator UVLO VIN VREF 1.235 V Ref Internal VCC AGND ∑ FSET/SYNC Fault + – Oscillator Diode Open Driver Circuit + Sense COMP – + Current Sense ISS – Internal Soft Start + PGND – VSENSE Thermal Shutdown Input Current Sense Amplifier IADJ Fault + PMOS Driver PWM/EN OVP Sense GOFF Fault Enable – GATE OVP VREF Open/Short LED Detect PWM 100 kΩ VREF ISS LED1 LED Driver APWM LED2 ISET Internal VCC ISET AGND Fault FAULT PAD PGND AGND Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 ELECTRICAL CHARACTERISTICS1,2 Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit 5 – 40 V Input Voltage Specifications Operating Input Voltage Range3 VIN UVLO Start Threshold VUVLOrise VIN rising − – 4.35 V UVLO Stop Threshold VUVLOfall VIN falling − – 3.90 V UVLO Hysteresis2 VUVLOHYS 300 450 600 mV Input Currents IQ PWM/EN = VIH ; SW = 2 MHz, no load − 5.5 10 mA IQSLEEP VIN = 16 V, VPWMEN = VFSETSYNC = 0 V − 2.0 10.0 μA Input Quiescent Current Input Sleep Supply Current Input Logic Levels (PWM/EN and APWM) Input Logic Level-Low VIL VIN throughout operating input voltage range – – 400 mV Input Logic Level-High VIH VIN throughout operating input voltage range 1.5 – – V PWM/EN Pin Open Drain Pull-down Resistor RPWMEN PWM/EN = 5 V 60 100 140 kΩ APWM Pull-down Resistor RAPWM PWM/EN = VIH 60 100 140 kΩ fAPWM VIH = 2 V, VIL = 0 V 20 − 1000 kHz 44 48 52 dB 750 990 1220 μA/V − –350 − μA APWM APWM Frequency2 Error Amplifier Open Loop Voltage Gain Transconductance AVOL gm ΔICOMP = ±10 μA Source Current IEA(SRC) VCOMP = 1.5 V Sink Current IEA(SINK) VCOMP = 1.5 V − 350 − μA COMP Pin Pull-down Resistance RCOMP ¯ĀŪ¯L̄¯T̄ ¯ =0 F̄ − 2000 − Ω VOVP(th) OVP connected to VOUT 7.7 8.1 8.5 V 188 199 210 μA − 0.1 1 μA 53 55 58 V ISW = 0.750 A, VIN = 16 V 75 300 600 mΩ VSW = 16 V, PWM/EN = VIL − 0.1 1 μA 3.0 3.5 4.2 A − 7.00 − A Overvoltage Protection Overvoltage Threshold OVP Sense Current IOVPH OVP Leakage Current IOVPLKG Secondary Overvoltage Protection VOVP(sec) ROVP = 40.2 kΩ, VIN = 16 V, PWM/EN = VIL Boost Switch Switch On-Resistance RSW Switch Leakage Current ISWLKG Switch Current Limit ISW(LIM) Secondary Switch Current Limit2 ISW(LIM2) Higher than ISW(LIM)(max) for all conditions, device latches when detected Soft Start Boost Current Limit ISWSS(LIM) Initial soft start current for boost switch − 700 − mA Minimum Switch On-Time tSWONTIME 60 85 111 ns Minimum Switch Off-Time tSWOFFTIME 30 47 68 ns Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit 1.8 2 2.2 MHz Oscillator Frequency RFSET = 10 kΩ Oscillator Frequency fSW RFSET = 20 kΩ 0.9 1 1.1 MHz RFSET = 35.6 kΩ 520 580 640 kHz FSET/SYNC Pin Voltage VFSET − 1.00 − V FSET Frequency Range fFSET 580 − 2500 kHz fSWSYNC 580 − 2300 kHz Synchronization Input Minimum Off-Time tPWSYNCOFF 150 − − ns Synchronization Input Minimum On-Time tPWSYNCON 150 − − ns RFSET = 10 kΩ Synchronization Synchronized PWM Frequency V SYNC(H) FSET/SYNC pin, high level − − 0.4 V V SYNC(L) FSET/SYNC pin, low level 2.0 − − V LEDx Accuracy ErrLED ISET = 120 μA − − 2 % LEDx Matching ΔLEDx ISET = 120 μA − − 1 % SYNC Input Logic Voltage LED Current Sinks LEDx Regulation Voltage VLED VLED1 = VLED2 , ISET = 120 μA 620 720 820 mV ISET to ILEDx Current Gain AISET ISET = 120 μA 960 980 1000 A/A ISET Pin Voltage VISET 0.988 1.003 1.018 V Allowable ISET Current ISET 40 − 120 μA 4.6 5.1 5.6 V VLED Short Detect VLEDSC While LED sinks are in regulation, sensed from LEDx pin to ground Soft Start LEDx Current ILEDSS Current through each enabled LEDx pin during soft start − 3.2 − mA Maximum PWM Dimming Until Off-Time2 tPWML Measured while PWM/EN = low, during dimming control and internal references are powered-on (exceeding tPWML results in shutdown) − 32,750 − fSW cycles Minimum PWM On-Time tPWMH First cycle when powering-up device − 0.75 2 μs − 0.5 1 μs − 360 500 ns PWM High to LED-On Delay tdPWM(on) Time between PWM enable and LED current reaching 90% of maximum PWM Low to LED-Off Delay tdPWM(off) Time between PWM enable going low and LED current reaching 10% of maximum Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit − −104 − μA GATE Pin GATE Pin Sink Current IGSINK VGS = VIN Gate Fault Shutdown Greater than 2X Current2 tGFAULT2 − − 3 μs Gate Fault Shutdown Greater than 1–2X Current tGFAULT1 − 10,000 − fSW cycles − –6.7 − V 18.8 20.3 21.8 μA Gate Voltage VGS Gate to source voltage measured when gate is on VSENSE Pin VSENSE Pin Sink Current IADJ VSENSE Trip Point VSENSEtrip1 Measured between VIN and VSENSE, RADJ = 0 Ω 94 104 114 mV VSENSE 2X Trip2 VSENSEtrip2 2X VSENSEtrip , instantaneous shutdown, RADJ = 0 Ω – 180 – mV VFAULT IFAULT = 1 mA − − 0.5 V IFAULTLKG VFAULT = 5 V − − 1 μA − 165 − ºC − 20 − ºC ¯Ā¯Ū¯L̄ ¯T̄ ¯ Pin F̄ ¯ĀŪ¯L̄¯T̄ ¯ Pull-Down Voltage F̄ ¯ĀŪ¯L̄¯T̄ ¯ Pin Leakage Current F̄ Thermal Protection (TSD) Thermal Shutdown Threshold2 TSD Thermal Shutdown Hysteresis2 TSDHYS Temperature rising 1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2Ensured by design and characterization, not production tested. 3Minimum V = 5 V is only required at startup. After startup is completed, the IC is able to function down to V = 4 V. IN IN Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Characteristic Performance TA = TJ VUVLOrise (V) 10 9 8 7 6 5 4 3 2 1 0 -50 -40 -30 -20 -10 0 VIN UVLO Start Threshold Voltage versus Ambient Temperature 10 20 30 40 50 60 70 80 90 100 110 120 130 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) Switching Frequency versus Ambient Temperature VIN UVLO Stop Threshold Voltage versus Ambient Temperature 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 -50 -40 -30 -20 -10 0 VUVLOfall (V) Temperature (°C) 10 20 30 40 50 60 70 80 90 100 110 120 130 3.70 3.69 3.68 3.67 3.66 3.65 3.64 3.63 3.62 3.61 3.60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) Temperature (°C) OVP Pin Sense Current versus Ambient Temperature OVP Pin Overvoltage Threshold versus Ambient Temperature 210 208 206 204 202 200 198 196 194 192 190 -50 -40 -30 -20 -10 0 8.4 8.3 VOVP(th) (V) IOVPH (μA) fSW (MHz) IQSLEEP (μA) VIN Input Sleep Mode Current versus Ambient Temperature 8.2 8.1 8.0 7.9 7.8 7.7 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) 7.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver ILED (mA) 118.2 LED to LED Matching Accuracy -50 -40 -30 -20 -10 0 0.3 0.1 -0.1 -0.3 -0.5 10 20 30 40 50 60 70 80 90 100 110 120 130 -50 -40 -30 -20 -10 0 Temperature (°C) LED Current versus Ambient Temperature ISET = 120 μA Input Disconnect Switch Gate to Source Voltage -6.3 118.0 -6.4 117.8 -6.5 117.6 117.4 117.0 3.0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) 117.2 versus Ambient Temperature -6.6 -6.7 -6.8 -50 -40 -30 -20 -10 0 -6.9 10 20 30 40 50 60 70 80 90 100 110 120 130 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) Temperature (°C) LED Current Setpoint Accuracy versus Ambient Temperature VSENSE Pin Sink Current versus Ambient Temperature 20.8 20.7 2.5 20.6 2.0 IADJ (μA) ErrLED (%) versus Ambient Temperature 0.5 $LEDx (%) 1000 995 990 985 980 975 970 965 960 ISET to LED Current Gain versus Ambient Temperature ISET = 120 μA VGS (V) AISET A8502 1.5 1.0 20.5 20.4 20.3 20.2 0.5 20.1 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) 20.0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Temperature (°C) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Efficiency for Various LED Configura ons ILED = 80 mA, LED Vf ≈ 3.2 V Efficiency (%) 100 95 90 2 strings, 6 series LEDs each 85 2 strings, 7 series LEDs each 2 strings, 8 series LEDs each 80 75 70 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0 Input Voltage, VIN (V) Efficiency for Various LED Configura ons ILED = 100 mA, LED Vf ≈ 3.2 V Efficiency (%) 100 95 90 85 2 strings, 6 series LEDs each 80 2 strings, 7 series LEDs each 75 2 strings, 8 series LEDs each 70 65 60 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0 Input Voltage, VIN (V) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A8502 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver Functional Description The A8502 incorporates a current-mode boost controller with internal DMOS switch, and two LED current sinks. It can be used to drive two LED strings of up to 12 white LEDs in series, with current up to 120 mA per string. For optimal efficiency, the output of the boost stage is adaptively adjusted to the minimum voltage required to power both LED strings. This is expressed by the following equation: VOUT = max ( VLED1 , VLED2 ) + VREG (1) where VLEDx is the voltage drop across LED strings 1 and 2, and VREG is the regulation voltage of the LED current sinks (typically 0.72 V at the maximum LED current). Enabling the IC The IC turns on when a logic high signal is applied on the PWM/EN pin with a minimum duration of tPWMH for the first clock cycle, and the input voltage present on the VIN pin is greater than the 4.35 V necessary to clear the UVLO (VUVLOrise ) threshold. The power-up sequence is shown in figure 2. Before the LEDs are enabled, the A8502 driver goes through a system check to determine if there are any possible fault conditions that might prevent the system from functioning correctly. Also, if the FSET/SYNC pin is pulled low, the IC will not power-up. More information on the FSET/SYNC pin can be found in the Sync section of this datasheet. VDD C1 FSET/SYNC C2 ISET C3 PWM/EN C4 t Figure 2. Power-up diagram; shows VDD (ch1, 2 V/div.), FSET/SYNC (ch2, 1 V/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 2 V/div.) pins, time = 200 μs/div. GATE = VIN – 4.5 V GATE C1 LEDx Powering up: LED pin short-to-ground check The VIN pin has a UVLO function that prevents the A8502 from powering-up until the UVLO threshold is reached. After the VIN pin goes above UVLO, and a high signal is present on the PWM/EN pin, the IC proceeds to power-up. As shown in figure 3, at this point the A8502 enables the disconnect switch and checks if any LEDx pins are shorted to ground and/or are not used. The LED detect phase starts when the GATE voltage of the disconnect switch is equal to VIN – 4.5 V. After the voltage threshold on the LEDx pins exceeds 120 mV, a delay of between 3000 and 4000 clock cycles is used to determine the status of the pins. Thus, the LED detection duration varies with the switching LED detection period C2 ISET C3 C4 PWM/EN t Figure 3. Power-up diagram; shows the relationship of an LEDx pin with respect to the gate voltage of the disconnect switch (if used) during the LED detect phase, as well as the duration of the LED detect phase for a switching frequency of 2 MHz; shows GATE (ch1, 5 V/div.), LED (ch2, 500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 μs/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 frequency, as shown in the following table: Switching Frequency (MHz) Detection Time (ms) 2 1.5 to 2 1 3 to 4 0.800 3.75 to 5 0.600 5 to 6.7 LED1 LED detection period C1 C2 LED2 C3 ISET The LED pin detection voltage thresholds are as follows: LED Pin Voltage LED Pin Status Action <70 mV Short-to-ground Power-up is halted 150 mV Not used LED removed from operation 325 mV LED pin in use None All unused pins should be connected with a 1.54 kΩ resistor to ground, as shown in figure 5. The unused pin, with the pull-down resistor, will be taken out of regulation at this point and will not contribute to the boost regulation loop. C4 PWM/EN t 4B. Example with LED2 pin not being used; the detect voltage is about 150 mV; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 μs/div. Short removed Pin shorted LED1 LED detection period C1 LED1 C1 LED2 C2 LED2 C2 ISET C3 C4 ISET C3 PWM/EN t 4A. An LED detect occurring when both LED pins are selected to be used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 μs/div. C4 PWM/EN t 4C. Example with one LED shorted to ground. The IC will not proceed with power-up until the shorted LED pin is released, at which point the LED is checked to see if it is being used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 1 ms/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 If a LEDx pin is shorted to ground the A8502 will not proceed with soft start until the short is removed from the LEDx pin. This prevents the A8502 from powering-up and putting an uncontrolled amount of current through the LEDs. Soft start function During soft start the LEDx pins are set to sink (ILEDSS) and the boost switch current is reduced to the ISWSS(LIM) level to limit the inrush current generated by charging the output capacitors. When the converter senses that there is enough voltage on the LEDx pins the converter proceeds to increase the LED current to the preset regulation current and the boost switch current limit is switched to the ISW(LIM) level to allow the A8502 to deliver the necessary output power to the LEDs. This is shown in figure 6. Frequency selection The switching frequency on the boost regulator is set by the resistor connected to the FSET/SYNC pin. The switching frequency can be can be anywhere from 580 kHz to 2.3 MHz. Figure 7 shows the typical switching frequencies, in MHz, for given resistor values, in kΩ. Inrush current caused by enabling the disconnect switch (when used) Operation during ISWSS(lim) C1 IOUT C2 IIN Normal operation ISW(lim) C3 VOUT C4 PWM/EN t Figure 6. Startup diagram showing the input current, output voltage, and output current; shows IOUT (ch1, 200 mA/div.), IIN (ch2, 1 A/div.), VOUT (ch3, 20 V/div.), and PWM/EN (ch4, 5 V/div.), time = 1 ms/div. In case during operation a fault occurs that will increase the switching frequency, the FSET/SYNC pin is clamped to a maximum switching frequency of no more than 3.5 MHz. If the FSET/SYNC pin is shorted to GND the part will shut down. For more details see the Fault Mode table later in this datasheet. A8502 fSW (MHz) A8502 LED1 GND LED2 LED1 GND LED2 1.54 kΩ 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 30.0 32.5 35.0 Resistance for RSET (kΩ) Figure 5. Channel select setup: (left) using only channel LED1, (right) using both channels. Figure 7. Typical Switching Frequency versus value of RFSET resistor. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Sync The A8502 can also be synchronized using an external clock on the FSET/SYNC pin. Figure 8 shows the correspondence of a sync signal and the FSET/SYNC pin, and figure 9 shows the result when a sync signal is detected: the LED current does not show any variation while the frequency changeover occurs. At power-up if the FSET/SYNC pin is held low, the IC will not power-up. Only when the FSET/SYNC pin is tri-stated to allow the pin to rise, to about 1 V, or when a synchronization clock is detected, will the A8502 try to power-up. The basic requirement of the sync signal is 150 ns minimum ontime and 150 ns minimum off time, as indicated by the specifications for tPWSYNCON and tPWSYNCOFF . Figure 10 shows the timing for a synchronization clock into the A8502 at 2.2 MHz. Thus any pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to synchronize the IC. VOUT C1 IOUT C2 C3 FSET/SYNC SW node C4 t Figure 8. Diagram showing a synchronized FSET/SYNC pin and switch node; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 2 μs/div. The SYNC pulse duty cycle ranges for selected switching frequencies are: VOUT SYNC Pulse Frequency (MHz) Duty Cycle Range (%) C1 2.2 33 to 66 C2 2 30 to 70 1 15 to 85 0.800 12 to 88 0.600 9 to 91 If during operation a sync clock is lost, the IC will revert to the preset switching frequency that is set by the resistor RFSET. During this period the IC will stop switching for a maximum period of about 7 μs to allow the sync detection circuitry to switch over to the externally preset switching frequency. If the clock is held low for more than 7 μs, the A8502 will shut down. In this shutdown mode the IC will stop switching, the input disconnect switch is open, and the LEDs will stop sinking current. To shutdown the IC into low power mode, the user must disable the IC using the PWM pin, by keeping the pin low for a period of 32,750 clock cycles. If the FSET/SYNC pin is released at any time after 7 μs, the A8502 will proceed to soft start. IOUT C3 FSET/SYNC 2 MHz operation 1 MHz operation SW node C4 t Figure 9. Transition of the SW waveform when the SYNC pulse is detected. The A8502 switching at 2 MHz, applied SYNC pulse at 1 MHz; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 5 μs/div. t PWSYNCON 154 ns 150 ns 150 ns t PWSYNCOFF T = 454 ns Figure 10. SYNC pulse on and off time requirements. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 VOUT COMP LED current setting and LED dimming The maximum LED current can be up to 120 mA per channel, and is set through the ISET pin. To set the ILED current, connect a resistor, RISET, between this pin and ground, according to the following formula: RISET = (1.003 × 980) / ILED (2) where ILED is in A and RISET is in Ω. This sets the maximum current through the LEDs, referred to as the 100% current. Standard RISET values, at gain equals 980, are as follows: Standard Closest RISET Resistor Value (kΩ) LED current per LED, ILED (mA) 8.25 120 9.76 100 12.1 80 15.0 65 PWM dimming The LED current can be reduced from the 100% current level by PWM dimming using the PWM/EN pin. When the PWM/EN pin is pulled high, the A8502 turns on and all enabled LEDs sink 100% current. When PWM/EN is pulled low, the boost converter and LED sinks are turned off. The compensation (COMP) pin is floated, and critical internal circuits are kept active. The typical PWM dimming frequencies fall between 200 Hz and 1 kHz. Figures 11A to 11D provide examples of PWM switching behavior. C2 C1 C3 PWM C4 ILED t Figure 11B. Typical PWM diagram showing VOUT, ILED, and COMP pin as well as the PWM signal. PWM dimming frequency is 500 Hz at 1% duty cycle ; shows VOUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 μs/div. PWM C1 ILED C2 t Figure 11C. Delay from rising edge of PWM signal to LED current; shows PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div. VOUT PWM COMP C1 C2 C1 C3 PWM ILED C2 C4 ILED t Figure 11A. Typical PWM diagram showing VOUT, ILED, and COMP pin as well as the PWM signal. PWM dimming frequency is 500 Hz at 50% duty cycle; shows VOUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 μs/div. t Figure 11D. Delay from falling edge of PWM signal to LED current turn off; shows PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Another important feature of the A8502 is the PWM signal to LED current delay. This delay is typically less than 500 ns, which allows greater accuracy at low PWM dimming duty cycles, as shown in figure 12. APWM pin The APWM pin is used in conjunction with the ISET pin (see figure 13). This is a digital signal pin that internally adjusts the ISET current. When this pin is not used it should be tied to ground. The typical input signal frequency is between 20 kHz and 1 MHz. The duty cycle of this signal is inversely proportional to the percentage of current that is delivered to the LEDs (figure 14). To use this pin for a trim function, the user should set the maximum output current to a value higher than the required current by at least 5%. The LED ISET current is then trimmed down to the appropriate value. Another consideration that also is important is the limitation of the user APWM signal duty cycle. In some cases it might be preferable to set the maximum ISET current to be 25% to 50% higher, thus allowing the APWM signal to have duty cycles that are between 25% and 50%. 10 150 Worst-case 6 IOUT (mA) ErrLED (%) 8 Typical 4 2 100 0 0.1 1 10 0 100 0 PWM Duty Cycle, D (%) 60 80 100 Figure 14. Output current versus duty cycle; 200 kHz APWM signal. A8502 ISET Current Mirror Current Adjust LED Driver ErrLED (%) PWM 40 –15 APWM RISET 20 PWM Duty Cycle, D (%) Figure 12. Percentage Error of the LED current versus PWM duty cycle (at 200 Hz PWM frequency). ISET 50 –10 –5 0 0 20 40 60 80 100 PWM Duty Cycle, D (%) Figure 13. Simplified block diagram of the APWM and ISET circuit. Figure 15. Percentage Error of the LED current versus PWM duty cycle; 200 kHz APWM signal. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 As an example, a system that delivers a full LED current of 120 mA per LED would deliver 90 mA of current per LED when an APWM signal is applied with a duty cycle of 25% (figures 16 and 17). function it is recommended to use frequency ranges between 50 and 500 kHz for best accuracy. The frequency range must be considered only if the user is not using this function as a closed loop trim function. Another limitation is that the propagation delay between this APWM signal and IOUT takes several milliseconds to change the actual LED current. This effect is shown in figures 16-18. Although the APWM dimming function has a wide frequency range, if this function is used strictly as an analog dimming ILED ILED C1 C1 APWM APWM C2 C2 C3 C3 PWM/EN PWM/EN t t Figure 17. Diagram showing the transition of LED current from 90 mA to 120 mA, when a 25% duty cycle signal is removed from the APWM pin. PWM = 1; shows ILED (ch1, 50 mA/div.), APWM (ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 500 μs/div. Figure 16. Diagram showing the transition of LED current from 120 mA to 90 mA, when a 25% duty cycle signal is applied to the APWM pin; PWM = 1; shows ILED (ch1, 50 mA/div.), APWM (ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 500 μs/div. C1 IOUT APWM C2 C3 PWM/EN t Figure 18. Transition of output current level when a 50% duty cycle signal is applied to the APWM pin, in conjunction with a 50% duty cycle PWM dimming being applied to the PWM pin; shows IOUT (ch1, 100 mA/div.), APWM (ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 1 ms/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Analog dimming The A8502 can also be dimmed by using an external DAC or another voltage source applied either directly to the ground side of the RISET resistor or through an external resistor to the ISET pin (see figure 19). The limit of this type of dimming depends on the range of the ISET pin. In the case of the A8502 the limit is 40 to 125 μA. The advantage of this circuit is that the DAC voltage can be higher or lower, thus adjusting the LED current to a higher or lower value of the preset LED current set by the RISET resistor: • For a single resistor (panel A of figure 18), the ISET current is controlled by the following formula: VISET – VDAC ISET = (3) RISET LED short detect Both LEDx pins are capable of handling the maximum VOUT that the converter can deliver, thus providing protection from the LEDx pin to VOUT in the event of a connector short. where VISET is the ISET pin voltage and VDAC is the DAC output voltage. When the DAC voltage is 0 V the LED current will be at its maximum. To keep the internal gain amplifier stable, the user should not decrease the current through the RISET resistor to less than 40 μA • For a dual-resistor configuration (panel B of figure 19), the ISET current is controlled by the following formula: VISET VDAC – VISET – ISET = (4) RISET R1 DAC R ISET VDAC ▫ VDAC = 1.003 V; the output is strictly controlled by RISET ▫ VDAC > 1.003 V; the LED current is reduced ▫ VDAC < 1.003 V; the LED current is increased An LEDx pin that has a voltage exceeding VLEDSC will be removed from operation (see figure 20). This is to prevent the IC from dissipating too much power by having a large voltage present on an LEDx pin. While the IC is being PWM-dimmed, the IC rechecks the disabled LED every time the PWM signal goes high, to prevent false tripping of an LED short event. This also allows some self-correction if an intermittent LED pin short to VOUT is present. Overvoltage protection The A8502 has overvoltage protection (OVP) and open Schottky diode (D1 in figure 1) protection. The OVP protection has a A8502 ISET GND GND IOUT C1 LED1 (A) DAC R1 A8502 VDAC GND ISET R ISET C2 GND (B) Figure 19. Simplified diagrams of voltage control of ILED: typical applications using a DAC to control ILED using a single resistor (upper), and dual resistors (lower). PWM/EN C3 t Figure 20. Example of the disabling of an LED string when the LED pin voltage is increased above 4.6 V; shows IOUT (ch1, 200 mA/div.), LED1 (ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 10 μs/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 default level of 8.1 V and can be increased up to 53 V by connecting resistor ROVP between the OVP pin and VOUT . When the current into the OVP pin exceeds 199 μA (typical), the OVP comparator goes low and the boost stops switching. The following equation can be used to determine the resistance for setting the OVP level: where: ROVP = ( VOUTovp – VOVP(th) ) / IOVPH (5) VOUTovp is the target overvoltage level, ROVP is the value of the external resistor, in Ω, VOVP(th) is the pin OVP trip point found in the Electrical Characteristics table, and IOVPH is the current into the OVP pin. There are several possibilities for why an OVP condition would be encountered during operation, the two most common being: a Output disconnect event detected disconnected output, and an open LED string. Examples of these are provided in figures 21 and 22. Figure 21 illustrates when the output of the A8502 is disconnected from load during normal operation. The output voltage instantly increases up to OVP voltage level and then the boost stops switching to prevent damage to the IC. If the output is drained off, eventually the boost might start switching for a short duration until the OVP threshold is hit again. Figure 22 displays a typical OVP event caused by an open LED string. After the OVP condition is detected, the boost stops switching, and the open LED string is removed from operation. Afterwards VOUT is allowed to fall, and eventually the boost will resume switching and the A8502 will resume normal operation. A8502 also has built-in secondary overvoltage protection to protect the internal switch in the event of an open diode condition. Open Schottky diode detection is implemented by detecting overvoltage on the SW pin of the device. If voltage on the SW LED string open condition detected VOUT VOUT SW node C2 SW node C2 C3 C3 PWM C1 PWM C1 ILED C4 ILED C4 t Figure 21. OVP protection in an output disconnect event; shows VOUT (ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and ILED (ch4, 200 mA/div.), time = 1 ms/div. t Figure 22. OVP protection in an open LED string event; shows VOUT (ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and ILED (ch4, 200 mA/div.), time = 500 μs/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 pin exceeds the device safe operating voltage rating, the A8502 disables and remains latched. To clear this fault, the IC must be shut down either by using the PWM/EN signal or by going below the UVLO threshold on the VIN pin. Figure 23 illustrates this. As soon as the switch node voltage (SW) exceeds 60 V, the IC shuts down. Due to small delays in the detection circuit, as well Open diode condition detected as there being no load present, the switch node voltage will rise above the trip point voltage. Figure 24 illustrates when the A8502 is being enabled during an open diode condition. The IC goes through all of its initial LED detection and then tries to enable the boost, at which point the open diode is detected. PWM C1 SW node C2 VOUT IOUT C3 C4 t Figure 23. OVP protection in an open Schottky diode event, while the IC is in normal operation; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), VOUT (ch3, 20 V/div.), and IOUT (ch4, 200 mA/div.), time = 1 μs/div. Open diode condition detected PWM C1 SW node C2 VOUT C3 IOUT C4 t Figure 24. OVP protection when the IC is enabled during an open diode condition; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), VOUT (ch3, 10 V/div.), and IOUT (ch4, 200 mA/div.), time = 500 μs/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Boost switch overcurrent protection The boost switch is protected with cycle-by-cycle current limiting set at a minimum of 3.0 A. There is also a secondary current limit that is sensed on the boost switch. When detected this current limit immediately shuts down the A8502. The level of this cur- rent limit is set above the cycle-by-cycle current limit to protect the switch from destructive currents when the boost inductor is shorted. Various boost switch overcurrent conditions are shown in figures 25 through 27. SW node C1 C1 SW node C2 IL IL VOUT VOUT C2 PWM/EN C3 C4 PWM/EN C3 C4 t t Figure 25. Normal operation of the switch node (SW); inductor current (IL) and output voltage (VOUT) for 9 series LEDs in each of 2 strings configuration; shows SW node (ch1, 20 V/div.), inductor current, IL (ch2, 1 A/div.), VOUT (ch3, 10 V/div.), and PWM/EN (ch4, 5 V/div.), time = 2 μs/div. Figure 26. Cycle-by-cycle current limiting; inductor current (yellow trace, IL), note reduction in output voltage as compared to normal operation with the same configuration (figure 23); shows SW node (ch1, 20 V/div.), inductor current, IL (ch2, 1 A/div.), VOUT (ch3, 10 V/div.), and PWM/EN (ch4, 5 V/div.), time = 2 μs/div. PWM/EN C1 FAULT C2 SW node C3 IL C4 t Figure 27. Secondary boost switch current limit; when this limit is hit, the ¯ĀŪ¯L̄¯T̄ ¯ A8502 immediately shuts down; shows PWM/EN (ch1, 5 V/div.), F̄ (ch2, 5 V/div.), SW node (ch3, 50 V/div.), and inductor current, IL (ch4, 2 A/div.), time = 100 ns/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Input overcurrent protection and disconnect switch The primary function of the input disconnect switch is to protect the system and the device from catastrophic input currents during a fault condition. The external circuit implementing the disconnect is shown in figure 28. If the input disconnect switch is not used, the VSENSE pin must be tied to VIN and the GATE pin must be left open. C1 When selecting the external PMOS, check for the following parameters: FAULT IIN (3) IIN limited to 3 A (1) Initial fault detected C2 • Drain-source breakdown voltage V(BR)DSS > –40 V (2) Disconnect switch goes into a linear mode • Gate threshold voltage (make sure it is fully conducting at VGS = -4 V, and cut-off at –1 V) • RDS(on): Make sure the on-resistance is rated at VGS = -4.5 V or similar, not at -10 V; derate it for higher temperature The input disconnect switch has two modes of operation: GATE C4 PWM/EN t • 1X mode When the input current is between one and two times the preset current limit value, the disconnect switch enters a constant-current mode for a maximum duration of 10,000 cycles or 5 ms at 2 MHz. During this time, the Fault flag is set immediately and the disconnect switch goes into a linear mode of operation, in which the input current will be limited to a value approximate to the 1X current trip point level (figure 29). If the fault corrects itself before the expiration of the timer, the Fault flag will be removed and normal operation will resume. The user can also during this time decide whether to shut down the A8502. To immediately shut down the device, pull the FSET/ SYNC pin low for more than 7 μs. After the FSET/SYNC pin has been low for a period longer than 7 μs, the IC will stop switching, the input disconnect switch will open, and the LEDx pins will stop sinking current. The A8502 can be powered-down into low power mode. To do so, disable the IC by keeping the PWM/EN pin low for a period of 32,750 clock cycles. To keep the discon- (4) After 12.5 ms, disconnect switch shuts down C3 Figure 29. Showing typical wave forms for a 3-A, 1X current limit under a ¯ĀŪ¯L̄¯T̄ ¯ (ch1, 5 V/div.), IIN (ch2, 2 A/ fault condition; shows fSW = 800 kHz, F̄ div.), GATE (ch3, 5 V/div.), and PWM/EN (ch4, 5 V/div.), time = 5 ms/div. FAULT C1 C2 Fault flag set at 1X trip point A8502 shuts down at 2X trip point GATE IIN C3 VIN RSC Q1 C4 To L1 RC t CC RADJ GATE VSENSE VIN PWM/EN A8502 Figure 30. 2X mode, secondary overcurrent fault condition. IIN is the input current through the switch. The Fault flag is set at the 1X current limit, and when the 2X current limit is reached the A8502 disables the gate of the ¯ĀŪ¯L̄¯T̄ ¯ (ch1, 5 V/div.), GATE (ch2, disconnect switch (GATE); shows F̄ 10 V/div.), IIN (ch3, 2 A/div.), and PWM/EN (ch4, 5 V/div.), time = 5 μs/div. Figure 28. Typical circuit showing the implementation of the input disconnect feature. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 A8502 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver nect switch stable while the disconnect switch is in 1X mode, use a 22 nF capacitor for CC and a 20 Ω resistor for RC. • 2X current limit If the input current level goes above 2X of the preset current limit threshold, the A8502 will shut down in less than 3 μs regardless of user input (figure 30). This is a latched condition. The Fault flag is also set to indicate a fault. This feature is meant to prevent catastrophic failure in the system due to inductor short to ground, switch pin short to ground, or output short to ground. Setting the current sense resistor The typical threshold for the current sense circuit is 104 mV, when RADJ is 0 Ω. This voltage can be trimmed by the RADJ resistor. The typical 1X trip point should be set at about 3 A, which coincides with the cycle-by-cycle current limit minimum threshold. For example, given 3 A of input current, and the calculated maximum value of the sense resistor, RSC = 0.033 Ω. The RSC chosen is 0.03 Ω, a standard. VIN IOUT C1 C2 VDD C3 PWM/EN C4 t Figure 31. Shutdown showing a falling input voltage (VIN); shows VIN (ch1, 2 V/div.), IOUT (ch2, 200 mA/div.), VDD (ch3, 5 V/div.), and PWM/EN (ch4, 2 V/div.), time = 5 ms/div. Also: RADJ = (VSENSETRIP – VADJ ) / IADJ (6) The trip point voltage is calculated as: VADJ = 3.0 A × 0.03 Ω = 0.090 V GATE C1 RADJ = (0.104 – 0.09 V) / (20.3 μA) = 731 Ω IOUT C2 Input UVLO When VIN and VSENSE rise above the VUVLOrise threshold, the A8502 is enabled. A8502 is disabled when VIN falls below the VUVLOfall threshold for more than 50 μs. This small delay is used to avoid shutting down because of momentary glitches in the input power supply. When VIN falls below 4.35 V, the IC will shut down (see figure 31). VDD The VDD pin provides regulated bias supply for internal circuits. Connect the capacitor CVDD with a value of 0.1 μF or greater to this pin. The internal LDO can deliver no more than 2 mA of current with a typical VDD of about 3.5 V, enabling this pin to serve ¯T̄ ¯ pin. as the pull-up voltage for the F̄¯Ā¯Ū¯L̄ VDD C3 PWM/EN C4 t Figure 32. Shutdown using the enable function, showing the 16 ms delay between the PWM/EN signal and when the VDD and GATE of the disconnect switch turns off; shows GATE (ch1, 10 V/div.), IOUT (ch2, 200 mA/div.), VDD (ch3, 5 V/div.), and PWM/EN (ch4, 2 V/div.), time = 5 ms/div. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Shutdown If the PWM/EN pin is pulled low for more than tPWML (32,750 clock cycles), the device enters shutdown mode and clears all internal fault registers. As an example, at a 2 MHz clock frequency, it will take approximately 16.3 ms to shut down the IC into the low power mode (figure 32). When the A8502 is shut down, the IC will disable all current sources and wait until the PWM/EN signal goes high to re-enable the IC. If faster shut down is required, the FSET/SYNC pin can be used. response to a triggered fault condition is summarized in the Fault Mode table. Fault protection during operation The A8502 constantly monitors the state of the system to determine if any fault conditions occur during normal operation. The • Some of these faults will not be protected if the input disconnect switch is not being used. An example of this is VOUT short to ground. The possible fault conditions that the device can detect are: Open LED pin, LED pin shorted to ground, shorted inductor, VOUT short to ground, SW pin shorted to ground, ISET pin shorted to ground, and input disconnect switch source shorted to ground. Note the following: • Some of the protection features might not be active during startup, to prevent false triggering of fault conditions. Fault Mode Table Fault Name Type Active Fault Flag Set Primary switch overcurrent protection (cycle-by-cycle current limit) Auto-restart Always No This fault condition is triggered by the cycle-bycycle current limit, ISW(LIM). Secondary switch current limit Input disconnect current limit Secondary OVP Latched Latched Latched Always Always Always Boost Disconnect switch Sink driver Off for a single cycle On On Yes When the current through the boost switch exceeds secondary current SW limit (ISW(LIM2)) the device immediately shuts down the disconnect switch, LED drivers, and boost. The Fault flag is set. To reenable the device, the PWM/EN pin must be pulled low for 32,750 clock cycles. Off Off Off Yes The device is immediately shut off if the voltage across the input sense resistor is 2X the preset current value. The Fault flag is set. If the input current limit is between 1X and 2X, the Fault flag is set but the IC will continue to operate normally for tGFAULT1 or until it is shut down. To re-enable the device the PWM/EN pin must be pulled low for 32,750 clock cycles. Off Off Off Yes Secondary overvoltage protection is used for open diode detection. When diode D1 opens, the SW pin voltage will increase until VOVP(SEC) is reached. This fault latches the IC. The input disconnect switch is disabled as well as the LED drivers, and the Fault flag is set. To re-enable the part the PWM pin must be pulled low for 32,750 clock cycles. Off Off Off Description Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Fault Mode Table (continued) Fault Name LED Pin Short Protection LED Pin open ISET Short Protection FSET/SYNC Short Protection Overvoltage Protection Type Auto-restart Auto-restart Auto-restart Auto-restart Auto-restart Active Startup Normal Operation Always Always Always Fault Flag Set Description Boost Disconnect Switch Sink driver Off On Off No This fault prevents the device from starting-up if either of the LEDx pins are shorted. The device stops soft-start from starting while either of the LEDx pins are determined to be shorted. After the short is removed, soft-start is allowed to start. No When an LEDx pin is open the device will determine which LED pin is open by increasing the output voltage until OVP is reached. Any LED string not in regulation will be turned off. The device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. On On Off for open pins. On for all others. No This fault occurs when the ISET current goes above 150% of the maximum current. The boost will stop switching, the disconnect switch will turn off, and the IC will disable the LED sinks until the fault is removed. When the fault is removed the IC will try to to regulate to the preset LED current. Off On Off Yes Fault occurs when the FSET/SYNC current goes above 150% of maximum current, about 180 μA. The boost will stop switching, the disconnect switch will turn off, and the IC will disable the LED sinks until the fault is removed. When the fault is removed the IC will try to restart with soft-start. Off Off Off No Fault occurs when OVP pin exceeds VOVP(th) threshold. The A8502 will immediately stop switching to try to reduce the output voltage. If the output voltage decreases then the A8502 will restart switching to regulate the output voltage. Stop during OVP event. On On On On Off for shorted pins. On for all others. LED Short Protection Auto-restart Always No Fault occurs when the LED pin voltage exceeds VLEDSC. When the LED short protection is detected the LED string that is above the threshold will be removed from operation. Overtemperature Protection Auto-restart Always No Fault occurs when the die temperature exceeds the overtemperature threshold, 165°C. Off Off Off VIN UVLO Auto-restart Always No Fault occurs when VIN drops below VUVLO , 3.90 V maximum. This fault resets all latched faults. Off Off Off Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Application Information Design Example for Boost Configuration This section provides a method for selecting component values when designing an application using the A8502. The resulting design is diagrammed in figure 33. Then the OVP resistor is: Assumptions: For the purposes of this example, the following are given as the application requirements: where both IOVPH and VOVP(th) are taken from the Electrical Characteristics table. • VBAT: 10 to 14 V Chose a value of resistor that is higher value than the calculated ROVP . In this case a value of 137 kΩ was selected. Below is the actual value of the minimum OVP trip level with the selected resistor: • Quantity of LED channels, #CHANNELS : 2 • Quantity of series LEDs per channel, #SERIESLEDS : 10 • LED current per channel, ILED : 120 mA ROVP = (VOUT(OVP) – VOVP(th) ) / IOVPH (9) = (34.72 V – 8.1 V) / 199 μA = 133.77 kΩ VOUT(OVP) = 137 (kΩ) × 199 (μA )+ 8.1 (V) = 35.36 V • LED Vf at 120 mA: 3.2 V Step 3b At this point a quick check must be done to determine if • fSW : 2 MHz the conversion ratio is acceptable for the selected frequency. • TA(max): 65°C Dmaxofboost = 1 – tSWOFFTIME × fSW • PWM dimming frequency: 200 Hz, 1% duty cycle (10) = 1 – 68 (ns) × 2 (MHz) = 86.4% Procedure: The procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. where the minimum off-time (tSWOFFTIME) is found in the Electrical Characteristics table. Step 1 Connect LEDs to pins LED1 and LED2. The Theoretical Maximum VOUT is then calculated as: Step 2 Determining the LED current setting resistor RISET: RISET = (VISET × AISET) / ILED (7) VOUT(max) = = (1.003 (V) × 980) / 120 (mA) = 8.19 kΩ = Choose a 8.25 kΩ resistor. Step 3 Determining the OVP resistor. The OVP resistor is connected between the OVP pin and the output voltage of the converter. on the LED requirements. The regulation voltage, VLED , of the A8502 is 720 mV. A constant term, 2 V, is added to give margin to the design due to noise and output voltage ripple. = 10 × 3.2 (V) + 0.720 (V) + 2 (V) = 34.72 V 1 – Dmaxofboost – Vd (11) 10 (V) – 0.4 (V) = 73.13 V 1 – 0.864 where Vd is the diode forward voltage. Step 3a The first step is determining the maximum voltage based VOUT(OVP) = #SERIESLEDS × Vf + VLED + 2 (V) VIN(min) (8) The Theoretical Maximum VOUT value must be greater than the value VOUT(OVP) . If this is not the case, the switching frequency of the boost converter must be reduced to meet the maximum duty cycle requirements. Step 4 Selecting the inductor. The inductor must be chosen such that it can handle the necessary input current. In most applications, due to stringent EMI requirements, the system must operate in continuous conduction mode throughout the whole input voltage range. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Step 4a Determining the duty cycle, calculated as follows: D(max) = 1 – Step 4d Double-check to make sure the ½ current ripple is less than IIN(min): VIN(min) (12) VOUT(OVP) + Vd Step 4e This step is used to verify that there is sufficient slope Step 4b Determining the maximum and minimum input current to the system. The minimum input current will dictate the inductor value. The maximum current rating will dictate the current rating of the inductor. First, the maximum input current, given: = 2 (13) ILED 0.120 (A) = 0.240 A then: IIN(max) = = VIN(min) compensation for the inductor chosen. The slope compensation value is determined by the following formula: 3.6 fSW Slope Compensation = = 3.6 A /μs (19) 2 10 6 Next insert the inductor value used in the design: ΔILused = VOUT(OVP) IOUT (14) H = 35.36 (V) 240 (mA) = 0.94 A 10 (V) 0.90 Required Slope (min) = Next, calculate minimum input current, as follows: = VOUT(OVP) IOUT VIN(max) H VIN(min) D(max) Lused fSW (20) 10 (V) 0.72 = 0.36 A 10 (μH) 2.0 (MHz) Calculate the minimum required slope: where η is efficiency. IIN(min) = (18) 0.67 A > 0.19 A A good inductor value to use would be 10 μH. 10 (V) =1– = 72.04% 35.36 (V) + 0.4 (V) IOUT = #CHANNELS IIN(min) > 1/2 ΔIL ΔILused 1 10 –6 1 (1 – D(max)) (21) fSW (15) 35.36 (V) 240 (mA) = 0.67 A 14 (V) 0.90 = 0.36 (A) 1 10 –6 1 (1 – 0.72) 2.0 (MHz) = 2.57 A/μs If the minimum required slope is greater than the calculated slope compensation, the inductor value must be increased. A good approximation of efficiency, η , can be taken from the efficiency curves located in the datasheet. A value of 90% is a good starting approximation. Note: The slope compensation value is in A/μs, and 1×10 –6 is a constant multiplier. Step 4c Determining the inductor value. To ensure that the induc- Step 4f Determining the inductor current rating. The inductor tor operates in continuous conduction mode, the value of the inductor must be set such that the ½ inductor ripple current is not greater than the average minimum input current. As a first pass assume Iripple to be 40% of the maximum inductor current: ΔIL = IIN(max) × Iripple (16) = 0.94 (A) × 0.40 = 0.376 A = VIN(min) ΔIL fSW (17) D(max) 10 (V) 0.376 (A) 2 (MHz) 0.72 = 9.57 μH L(min) = IIN(max) + 1/2 ΔILused (22) = 0.94 (A) + 0.36 (A) / 2 = 1.12 A Step 5 Determining the resistor value for a particular switching then: L= current rating must be greater than the IIN(max) value plus half of the ripple current ΔIL, calculated as follows: frequency. Use the RFSET values shown in figure 7. For example, a 10 kΩ resistor will result in a 2 MHz switching frequency. Step 6 Choosing the proper switching diode. The switching diode must be chosen for three characteristics when it is used in LED lighting circuitry. The most obvious two are: current rating of the diode and reverse voltage rating. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 The reverse voltage rating should be such that during operation condition, the voltage rating of the device is larger than the maximum output voltage. In this case it is VOUT(OVP). ICOUTrms = IOUT The peak current through the diode is calculated as: Idp = IIN(max) + 1/2 ΔILused Step 7 Choosing the output capacitors. The output capacitors must be chosen such that they can provide filtering for both the boost converter and for the PWM dimming function. The biggest factors that contribute to the size of the output capacitor are: PWM dimming frequency and PWM duty cycle. Another major contributor is leakage current, ILK . This current is the combination of the OVP leakage current as well as the reverse current of the switching diode. In this design the PWM dimming frequency is 200 Hz and the minimum duty cycle is 1%. Typically, the voltage variation on the output, VCOUT , during PWM dimming must be less than 250 mV, so that no audible hum can be heard. The capacitance can be calculated as follows: 1 – D(min) fPWM(dimming) = 200 (μA) ∆ILused IIN(max) × 12 1 – D(max) D(max) + (23) = 0.94 (A) + 0.36 (A) / 2 = 1.12 A The third major component in deciding the switching diode is the reverse current, IR , characteristic of the diode. This characteristic is especially important when PWM dimming is implemented. During PWM off-time the boost converter is not switching. This results in a slow bleeding off of the output voltage, due to leakage currents. IR can be a large contributor, especially at high temperatures. On the diode that was selected in this design, the current varies between 1 and 100 μA. COUT = ILK The rms current through the capacitor is given by: (24) VCOUT 1 – 0.01 = 3.96 μF 200 (Hz) 0.250 (V) A capacitor larger than 3.96 μF should be selected due to degradation of capacitance at high voltages on the capacitor. A ceramic 4.7 μF 50 V capacitor is a good choice to fulfill this requirement. Corresponding capacitors include: (25) 0.36 (A) 0.94 (A) × 12 = 0.39 A 1 – 0.72 0.72 + = 0.240 (A) The output capacitor must have a current rating of at least 390 mA. The capacitor selected in this design was a 4.7 μF 50 V capacitor with a 3 A current rating. Step 8 Selecting input capacitor. The input capacitor must be selected such that it provides a good filtering of the input voltage waveform. A good estimation rule is to set the input voltage ripple, ΔVIN , to be 1% of the minimum input voltage. The minimum input capacitor requirements are as follows: CIN = = ∆ILused 8 8 (26) fSW ∆VIN 0.36 (A) 2 (MHz) 0.1 (V) = 0.23 μF The rms current through the capacitor is given by: CINrms = IOUT × ∆ILused IIN(max) (1 – D)× 12 0.36 (A) 0.240 (A) × 0.94 (A) = 0.095 A = (1 – 0.72)× 12 (27) A good ceramic input capacitor with ratings of 2.2 μF 50 V or 4.7 μF 50 V will suffice for this application. Corresponding capacitors include: Vendor Value Part number Vendor Value Part number Murata 4.7 μF 50 V GRM32ER71H475KA88L Murata 4.7 μF 50 V GRM32ER71H475KA88L Murata 2.2 μF 50 V GRM31CR71H225KA88L Murata 2.2 μF 50 V GRM31CR71H225KA88L Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 The trip point voltage must be: Step 9 Choosing the input disconnect switch components. Set the input disconnect 1X current limit to 3 A by choosing a sense VADJ = 3.0 (A) × 0.033 (Ω) = 0.099 (V), therefore resistor. The calculated maximum value of the sense resistor is: RSC(max) = VSENSEtrip / 3.0 (A) RADJ = (VSENSEtrip – VADJ ) / IADJ (typ) (28) = (0.104 (V) – 0.099 (V)) / 20.3 (μA) = 246.31 Ω = 0.104 (V) / 3.0 (A) = 0.035 Ω The RSC chosen is 0.033 Ω, a standard. VIN 10 to 14 V CIN 4.7 μF A value of 249 Ω was chosen for this design. RSC 0.033 Ω RADJ 249 Ω Q1 RC 20 Ω D1 2 A / 60 V L1 10 μH CC 22 nF GATE VSENSE VIN VDD VC CVDD 0.1 μF 100 kΩ OVP COUT 4.7 μF A8502 PAD RFSET 10 kΩ VOUT ROVP 137 kΩ SW FAULT PWM/EN APWM ISET RISET 8.25 kΩ (29) FSET/SYNC AGND LED1 10 LEDs each string LED2 COMP PGND CP 120 pF RZ 150 Ω CZ 0.47 μF Figure 33. The schematic diagram showing calculated values from the design example above. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Design Example for SEPIC Configuration This section provides a method for selecting component values when designing an application using the A8502 in SEPIC (Single-Ended Primary-Inductor Converter) circuit. SEPIC topology has the advantage that it can generate a positive output voltage either higher or lower than the input voltage. The resulting design is diagrammed in figure 34. Assumptions: For the purposes of this example, the following are given as the application requirements: Step 3a The first step is determining the maximum voltage based on the LED requirements. The regulation voltage, VLED , of the A8502 is 720 mV. A constant term, 2 V, is added to give margin to the design due to noise and output voltage ripple. VOUT(OVP) = #SERIESLEDS × Vf + VLED + 2 (V) (31) = 4 × 3.2 (V) + 0.720 (V) + 2 (V) = 15.9 V Then the OVP resistor is: ROVP = (VOUT(OVP) – VOVP(th) ) / IOVPH (32) = (15.9 (V) – 8.1 (V)) / 0.199 (mA) = 39.196 kΩ • VBAT: 6 to 14 V ( VIN(min): 5 V and VIN(max): 16 V ) • Quantity of LED channels, #CHANNELS : 2 where both IOVPH and VOVP(th) are taken from the Electrical Characteristics table. • Quantity of series LEDs per channel, #SERIESLEDS : 4 • LED current per channel, ILED : 120 mA In this case a value of 39.2 kΩ was selected. Below is the actual value of the minimum OVP trip level with the selected resistor: • LED Vf at 120 mA: ≈ 3.3 V • fSW : 2 MHz VOUT(OVP) = 39.2 (kΩ) × 0.199 (mA) + 8.1 (V) = 15.9 V • TA(max): 65°C Step 3b At this point a quick check must be done to determine if • PWM dimming frequency: 200 Hz, 1% duty cycle the conversion ratio is acceptable for the selected frequency. Procedure: The procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. Step 1 Connect LEDs to pins LED1 and LED2. Note: if only one LED channel is needed, the unused LEDx pin should be pulled to ground using a 1.5 kΩ resistor. Alternatively, short the LED1 and LED2 pins together, and half the LED current, to 60 mA per channel. Dmax = 1 – tSWOFFTIME × fSW = 1 – 68 (ns) × 2 (MHz) = 86.4% where the minimum off-time (tSWOFFTIME) is found in the Electrical Characteristics table. The Theoretical Maximum VOUT is then calculated as: VOUT(max) = VIN(min) Step 2 Determining the LED current setting resistor RISET: RISET = (VISET × AISET) / ILED (30) (33) = 5 (V) Dmax 1 – Dmax – Vd (34) 0.86 – 0.4 (V) = 30.3 V 1 – 0.86 = (1.003 (V) × 980) / 120 mA = 8.19 kΩ Choose a 8.25 kΩ resistor 1% resistor (or 16.2 kΩ if ILED is 60mA/channel). Step 3 Determining the OVP resistor. The OVP resistor is connected between the OVP pin and the output voltage of the converter. where Vd is the diode forward voltage. The Theoretical Maximum VOUT value must be greater than the value VOUT(OVP) . If this is not the case, the switching frequency of the boost converter must be reduced to meet the maximum duty cycle requirements. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Step 4 Selecting the inductor. The inductor must be chosen such that it can handle the necessary input current. In most applications, due to stringent EMI requirements, the system must operate in continuous conduction mode throughout the whole input voltage range. D(max) = = VIN(min) + VOUT(OVP) + Vd (35) to the system. The minimum input current will dictate the inductor value. The maximum current rating will dictate the current rating of the inductor. First, the maximum input current, given: = 2 L= = Step 4b Determining the maximum and minimum input current ILED (39) then: 15.9 (V) + 0.4 (V) = 76.5% 5 (V) + 15.9 (V) + 0.4 (V) IOUT = #CHANNELS ΔIL = IIN(max) × Iripple = 0.848 × 0.30 = 0.254 A Step 4a Determining the duty cycle, calculated as follows: VOUT(OVP) + Vd inductor must be set such that the ½ inductor ripple current is not greater than the average minimum input current. As a first pass assume Iripple to be 30% of the maximum inductor current: (36) 0.120 (A) = 0.240 A VIN(min) ΔIL fSW (40) D(max) 5 (V) 0.254 (A) 2 (MHz) 0.765 = 7.53 μH Step 4d Double-check to make sure the ½ current ripple is less than IIN(min): IIN(min) > 1/2 ΔIL (41) 0.265 A > 0.127 A A good inductor value to use would be 10 μH. Step 4e Next insert the inductor value used in the design to deter- then: mine the actual inductor ripple current: IIN(max) = = VOUT(OVP) IOUT VIN(min) (37) H ΔILused = 15.9 (V) 0.24 (A) = 0.848 A 5 (V) 0.90 = where η is efficiency. = VOUT(OVP) IOUT VIN(max) H 15.9 (V) 16 (V) (42) 0.765 5 (V) = 0.191 A 10 (μH) 2.0 (MHz) Step 4f Determining the inductor current rating. The inductor Next, calculate minimum input current, as follows: IIN(min) = VIN(min) D(max) Lused fSW (38) 0.24 (A) = 0.265 A 0.90 A good approximation of efficiency, η , can be taken from the efficiency curves located in the datasheet. A value of 90% is a good starting approximation. Step 4c Determining the inductor value. To ensure that the induc- tor operates in continuous conduction mode, the value of the current rating must be greater than the IIN(max) value plus half of the ripple current ΔIL, calculated as follows: L(min) = IIN(max) + 1/2 ΔILused (43) = 0.848 (A) + 0.096 (A) = 0.944 A Step 5 Determining the resistor value for a particular switching frequency. Use the RFSET values shown in figure 7. For example, a 10 kΩ resistor will result in a 2 MHz switching frequency. Step 6 Choosing the proper switching diode. The switching diode must be chosen for three characteristics when it is used in LED lighting circuitry. The most obvious two are: current rating of the diode and reverse voltage rating. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 31 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 The reverse breakdown voltage rating for the output diode in a SEPIC circuit should be: VBD > VOUT(OVP)(max) + VIN(max) (44) > 15.9 (V) + 16 (V) = 31.9 V because the maximum output voltage in this case is VOUT(OVP). The peak current through the diode is calculated as: Idp = IIN(max) + 1/2 ΔILused (45) = 0.848 (A) + 0.096 (A) = 0.944 A The third major component in deciding the switching diode is the reverse current, IR , characteristic of the diode. This characteristic is especially important when PWM dimming is implemented. During PWM off-time the boost converter is not switching. This results in a slow bleeding off of the output voltage, due to leakage currents. IR can be a large contributor, especially at high temperatures. On the diode that was selected in this design, the current varies between 1 and 100 μA. It is often advantageous to pick a diode with a much higher breakdown voltage, just to reduce the reverse current. Therefore for this example, pick a diode rated for a VBD of 60 V, instead of just 40 V. Step 7 Choosing the output capacitors. The output capacitors must be chosen such that they can provide filtering for both the boost converter and for the PWM dimming function. The biggest factors that contribute to the size of the output capacitor are: PWM dimming frequency and PWM duty cycle. Another major contributor is leakage current, ILK . This current is the combination of the OVP leakage current as well as the reverse current of the switching diode. In this design the PWM dimming frequency is 200 Hz and the minimum duty cycle is 1%. Typically, the voltage variation on the output, VCOUT , during PWM dimming must be less than 250 mV, so that no audible hum can be heard. The capacitance can be calculated as follows: COUT = ILK 1 – D(min) fPWM(dimming) = 200 (μA) VCOUT 1 – 0.01 = 3.96 μF 200 (Hz) 0.250 (V) (46) A capacitor larger than 3.96 μF should be selected due to degradation of capacitance at high voltages on the capacitor. Select a 4.7 μF capacitor for this application. The rms current through the capacitor is given by: ICOUTrms = IOUT D(max) 1 – D(max) = 0.240 (A) (47) 0.765 = 0.433 A 1 – 0.765 The output capacitor must have a ripple current rating of at least 500 mA. The capacitor selected for this design is a 4.7 μF 50 V capacitor with a 1.5 A current rating. Step 8 Selecting input capacitor. The input capacitor must be selected such that it provides a good filtering of the input voltage waveform. A estimation rule is to set the input voltage ripple, ΔVIN , to be 1% of the minimum input voltage. The minimum input capacitor requirements are as follows: CIN = = ∆ILused 8 8 fSW ∆VIN 0.191 (A) = 0.24 μF 2 (MHz) 0.05 (V) (48) The rms current through the capacitor is given by: CINrms = = ∆ILused 12 0.191 (A) 12 (49) = 0.055 A A good ceramic input capacitor with a rating of 2.2 μF 25 V will suffice for this application. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 32 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 The rms current requirement of the coupling capacitor is given by: Step 9 Selecting coupling capacitor CSW. The minimum capaci- tance of CSW is related to the maximum voltage ripple allowed 1 – D(max) D(max) ICSWrms = IIN across it: CSW = IOUT DMAX fSW = 0.848 (A) (50) ∆VSW 0.24 (A) 0.765 = = 0.92 μF 0.1 (V) 2 (MHz) (51) 1 – 0.765 = 0.47 A 0.765 The voltage rating of the coupling capacitor must be greater than VIN(max), or 16 V in this case. A ceramic capacitor rated for 2.2 μF 25V will suffice for this application. L2 10 μH VIN RSC 6 to 14 V 0.033 Ω CIN 2.2 μF RADJ 249 Ω Q1 RC 20 Ω CC 22 nF VC CVDD 0.1 μF 100 kΩ CSW 2.2 μF L1 10 μH GATE VSENSE VIN VDD RISET 8.25 kΩ RFSET 10 kΩ OVP PAD LED1 AGND COUT 4.7 μF 39.2 kΩ A8502 FSET/SYNC VOUT ROVP SW FAULT PWM/EN APWM ISET D1 2 A / 60 V LED2 COMP PGND CP 120 pF RZ 150 Ω CZ 0.47 μF Figure 34. Typical application showing SEPIC configuration, designed according to the application example. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 33 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Package LP, 16-Pin TSSOP with Exposed Thermal Pad 0.45 5.00±0.10 16 0.65 16 8º 0º 0.20 0.09 1.70 B 3 NOM 4.40±0.10 3.00 6.40±0.20 6.10 0.60 ±0.15 A 1 1.00 REF 2 3 NOM 0.25 BSC Branded Face 16X SEATING PLANE 0.10 C 0.30 0.19 C 3.00 C PCB Layout Reference View For Reference Only; not for tooling use (reference MO-153 ABT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 1.20 MAX 0.65 BSC 1 2 SEATING PLANE GAUGE PLANE 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 34 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver A8502 Revision History Revision Revision Date Rev. 3 January 16, 2012 Description of Revision Update Features list and gm Copyright ©2011-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 35