TI1 BQ294702DSGT Overvoltage protection for 2-series to 4-series cell li-ion batteries with external delay capacitor Datasheet

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bq2947
SLUSB15F – SEPTEMBER 2012 – REVISED JANUARY 2017
bq2947 Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries
with External Delay Capacitor
1 Features
3 Description
•
•
•
The bq2947 family is an overvoltage monitor and
protector for Li-Ion battery pack systems. Each cell is
monitored independently for an overvoltage condition.
1
•
•
•
•
•
2-, 3-, and 4-Series Cell Overvoltage Protection
External Capacitor-Programmed Delay Timer
Factory Programmed OVP Threshold (Threshold
Range 3.85 V to 4.6 V)
Output Options: Active High or Open Drain Active
Low
High-Accuracy Overvoltage Protection: ±10 mV
Low Power Consumption ICC ≈ 1 µA
(VCELL(ALL) < VPROTECT)
Low Leakage Current Per Cell Input < 100 nA
Small Package Footprint
– 8-Pin WSON (2.00 mm x 2.00 mm)
In the bq2947 device, an external delay timer is
initiated upon detection of an overvoltage condition
on any cell. Upon expiration of the delay timer, the
output is triggered into its active state (either high or
low, depending on the configuration). The external
delay timer feature also includes the ability to detect
an open or shorted delay capacitor on the CD pin,
which will similarly trigger the output driver in an
overvoltage condition.
For quicker production-line testing, the bq2947 device
provides a Customer Test Mode with reduced delay
time.
2 Applications
•
•
Device Information(1)
Notebook
UPS Battery Backup
PART NUMBER
PACKAGE
BODY SIZE (NOM)
bq294700
WSON (8)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
Simplified Schematic
Pack+
100 Ω
VCELL4
VCELL3
VCELL2
1k
0.1µF
1k
0.1µF
1k
OUT
VDD
1k
0.1µF
V4
CD
V3
VSS
V2
V1
PWPD
0.1 µF
VCELL1
0.1 µF
0.1µF
Pack–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
bq2947
SLUSB15F – SEPTEMBER 2012 – REVISED JANUARY 2017
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Applications ................................................ 13
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (February 2016) to Revision F
Page
•
Added bq294711 to Device Options Table ............................................................................................................................ 4
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 17
Changes from Revision D (November 2015) to Revision E
•
Page
Changed bq297406 device status From: Product Preview To: Active in the Device Options Table .................................... 4
Changes from Revision C (November 2015) to Revision D
Page
•
Changed the device number to bq2947 ................................................................................................................................ 1
•
Deleted the Related Links table from the Device and Documentation Support section....................................................... 17
Changes from Revision B (August 2014) to Revision C
Page
•
Added bq294708 and bq294709 to the datasheet ................................................................................................................. 1
•
Added preview footnote to Device Options Table ................................................................................................................. 4
•
Added bq294708 and bq294709 to Device Options Table .................................................................................................... 4
Changes from Revision A (June 2013) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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Changes from Original (September 2012) to Revision A
•
Page
Added the bq294707 device to Production Data.................................................................................................................... 1
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5 Device Options
PART NUMBER
OVP (V)
OV HYSTERESIS
OUTPUT DRIVE
bq294700
4.350
0.300
CMOS Active High
bq294701
4.250
0.300
CMOS Active High
bq294702
4.300
0.300
CMOS Active High
bq294703
4.325
0.300
CMOS Active High
bq294704
4.400
0.300
CMOS Active High
bq294705
4.450
0.300
CMOS Active High
bq294706
4.550
0.300
CMOS Active High
bq294707
4.225
0.050
NCH Open Drain Active Low
bq294708
4.500
0.300
CMOS Active High
CMOS Active High
bq294709
(1)
(1)
4.160
0.300
bq294711
4.220
0.300
CMOS Active High
bq2947
3.850–4.60
0–0.300
CMOS Active High or Open Drain Active Low
Product Preview only
6 Pin Configuration and Functions
DSG Package
8-Pin WSON
Top View
1 VDD
OUT 8
2 V4
CD 7
3 V3
VSS 6
4 V2
V1 5
Pin Functions
PIN
4
NAME
NO.
I/O
DESCRIPTION
CD
7
OA
External capacitor connection for delay timer
OUT
8
OA
Analog Output drive for overvoltage fault signal. Active High or Open Drain Active Low
PWPD
9
P
TI recommends connecting the exposed pad to VSS on PCB.
V1
5
IA
Sense input for positive voltage of the lowest cell in the stack
V2
4
IA
Sense input for positive voltage of the second cell from the bottom of the stack
V3
3
IA
Sense input for positive voltage of the third cell from the bottom of the stack
V4
2
IA
Sense input for positive voltage of the fourth cell from the bottom of the stack
VDD
1
P
Power supply input
VSS
6
P
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
VDD–VSS
–0.3
30
V
Input voltage
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
–0.3
30
V
Output voltage
OUT–VSS
–0.3
30
V
Continuous total power dissipation, PTOT
See Thermal Information
Lead temperature (soldering, 10 s), TSOLDER
300
Storage temperature, Tstg
(1)
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over-operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD
Input voltage range
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
Operating ambient temperature range, TA
MIN
MAX
UNIT
3
20
V
0
5
V
–40
110
°C
7.4 Thermal Information
bq2947
THERMAL METRIC (1)
WSON
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
62
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
72
°C/W
RθJB
Junction-to-board thermal resistance
32.5
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
33
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
10
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE PROTECTION THRESHOLDS
V(PROTECT) Overvoltage
Detection
VOV
bq294700, RIN = 1 kΩ
4.350
V
bq294701, RIN = 1 kΩ
4.250
V
bq294702, RIN = 1 kΩ
4.300
V
bq294703, RIN = 1 kΩ
4.325
V
bq294704, RIN = 1 kΩ
4.400
V
bq294705, RIN = 1 kΩ
4.450
V
bq294706, RIN = 1 kΩ
4.550
V
bq294707, RIN = 1 kΩ
4.225
V
bq294708, RIN = 1 kΩ
4.500
V
bq294709 (1), RIN = 1 kΩ
4.160
V
(1)
bq294711 , RIN = 1 kΩ
4.220
VHYS
OV Detection Hysteresis
bq2947 (2)
250
VOA
OV Detection Accuracy
TA = 25°C
TA = –40°C
VOADRIFT
OV Detection Accuracy
Across Temperature
300
V
400
mV
–10
10
mV
–40
40
mV
TA = 0°C
–20
20
mV
TA = 60°C
–24
24
mV
TA = 110°C
–54
54
mV
2
µA
0.1
µA
SUPPLY AND LEAKAGE CURRENT
IDD
Supply Current
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 11.)
IIN
Input Current at Vx Pins
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 11.)
ICELL
Input Current (ALL Vx
and VDD Input Pins)
Current Consumption at Power down, (V4–V3) =
(V3–V2) = (V2–V1) = (V1–VSS) = 2.30 V at TA =
25°C
(1)
(2)
6
1
–0.1
1.1
µA
Product Preview only
Future option, contact TI.
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVE OUT, CMOS ACTIVE HIGH VERSIONS ONLY
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV,
VDD = 14.4 V, IOH = 100 µA
VOUT
Output Drive Voltage,
Active High
6
If three of four cells are short circuited, only one
cell remains powered and > VOV, VDD = Vx (cell
voltage), IOH = 100 µA
VDD – 0.3
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
IOUTH
OUT Source Current
(during OV)
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV,
VDD = 14.4 V,
OUT = 0 V, measured out of OUT pin.
IOUTL
OUT Sink Current (no
OV)
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V,
OUT = VDD, measured into OUT pin .Pull resistor
RPU = 5 kΩ to VDD = 14.4 V
V
250
0.5
V
400
mV
4.5
mA
14
mA
400
mV
14
mA
100
nA
OUTPUT DRIVE OUT, CMOS OPEN DRAIN ACTIVE LOW VERSIONS ONLY
VOUT
Output Drive Voltage,
Active High
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
IOUTL
OUT Sink Current (no
OV)
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V,
OUT = VDD, measured into OUT pin. Pull resistor
RPU = 5 kΩ to VDD = 14.4 V
IOUTLK
OUT pin leakage
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V,
OUT = VDD, measured into OUT pin.
tCD
OV Delay Time
CCD = 0.1 µF (see Equation 1)
tCD_GND
OV Delay Time with CD
pin = 0 V
Delay due to CCD capacitor shorted to ground for
Customer Test Mode
250
0.5
DELAY TIMER
1
20
1.5
2
170
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7.6 Typical Characteristics
4.40
4.39
4.38
0.316
Mean
Min
Max
0.315
4.36
VHYS (V)
VOUT (V)
4.37
4.35
4.34
4.33
0.314
0.313
4.32
4.31
4.30
−50
−25
0
25
50
Temperature (°C)
75
100
125
0.312
−50
−25
0
G001
Figure 1. Overvoltage Threshold (Nominal = 4.35 V) vs.
Temperature
25
50
Temperature (°C)
75
100
125
G002
Figure 2. Hysteresis VHYS vs. Temperature
1.6
1.8
1.5
1.6
1.4
1.4
1.2
ICELL (µA)
IDD (µA)
1.3
1.1
1.0
1.2
1.0
0.9
0.8
0.8
0.7
0.6
−50
−25
0
25
50
Temperature (°C)
75
100
125
0.6
−50
Figure 3. IDD Current Consumption vs.
Temperature at VDD = 16 V
8
−3.70
7
−3.72
−3.76
VOUT (V)
IOUT (mA)
25
50
Temperature (°C)
75
100
125
G004
6
−3.74
−3.78
−3.80
−3.82
5
4
3
2
−3.84
1
−3.86
−25
0
25
50
Temperature (°C)
75
100
125
0
0
G005
Figure 5. Output Current IOUT vs.
Temperature
8
0
Figure 4. ICELL vs. Temperature
at VCELL= 9.2 V
−3.68
−3.88
−50
−25
G003
5
10
15
VDD (V)
20
25
30
G006
Figure 6. VOUT vs. VDD
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8 Detailed Description
8.1 Overview
The bq2947 is a second level overvoltage (OV) protector. Each cell is monitored independently by comparing the
actual cell voltage to a protection voltage threshold, VOV. The protection threshold is preprogrammed at the
factory with a range between 3.85 V and 4.65 V.
8.2 Functional Block Diagram
Figure 7 shows a CMOS Active High configuration.
PACK+
RVD
CVD
VDD
1
RIN
V4
2
RIN
V3
3
CIN
RIN
V2
4
Sensing Circuit
CIN
VOV
Enable
OUT
Active
Delay Charge/
Discharge Circuit
CIN
RIN
V1
8
5
CIN
VSS
6
PWPD
9
7
CD
CCD
PACK–
Figure 7. Block Diagram
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
8.3 Feature Description
In the bq2947 family of devices, if any cell voltage exceeds the programmed OV value, a timer circuit is
activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it with a fixed current
back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT terminal goes from
inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD pin successfully
begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error is detected in
either direction, it will similarly trigger the OUT pin to become active. See Figure 9 for details on CD and OUT pin
behavior during an overvoltage event.
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Feature Description (continued)
Cell Voltage (V)
(V4–V3, V3
3 –V2, V2 – V1, V1–VSS)
For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present) and
is high impedance when inactive (no OV).
VOV
VOV –VHYS
tCD
OUT (V)
Figure 8. Timing for Overvoltage Sensing (OUT Pin Is Active High)
Figure 9 shows the behavior of CD pin during an OV sequence.
Fault condition
present
Fault response
becomes active
VCD
V(CD)
tCHGDELAY
tCD
VOUT1
V(OUT)
Note: Active High OUT version shown
Figure 9. CD Pin Mechanism (OUT Pin Is Active High)
NOTE
In the case of an Open Drain Active Low version, the VOUT signal will be high and
transition to low state when the voltage on the VCD capacitor discharges to the set level
based on the tCD timer.
10
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Feature Description (continued)
8.3.1 Pin Details
8.3.1.1 Input Sense Voltage, Vx
These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is
required for noise filtering and stable voltage monitoring.
8.3.1.2 Output Drive, OUT
This terminal serves as the fault signal output, and may be ordered in either Active High or Open Drain Active
Low options.
8.3.1.3 Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
8.3.1.4 External Delay Capacitor, CD
This terminal is connected to an external capacitor that sets the delay timer during an overvoltage fault event.
The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or
open capacitor during an overvoltage event.
The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV
threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor
discharges below a set voltage, the OUT transitions from an inactive to active state.
To calculate the delay, use the following equation:
tCD (sec) = K × CCD (µF), where K = 10 to 20 range.
(1)
Example: If CCD= 0.1 µF (typical), then the delay timer range is
tCD (s) = 10 × 0.1 = 1 s (Minimum)
tCD (s) = 20 × 0.1 = 2 s (Maximum)
NOTE
The tolerance on the capacitor used for CCD increases the range of the tCD timer.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.
The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–V2), and (V4–V3).
The OUT pin is inactive, and is low if configured active high, or, if configured active low, is an open drain being
externally pulled up.
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltage exceeds the overvoltage threshold, VOV for
configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The
OUT pin will either pull high internally, if configured as active high, or will be pulled low internally if configured as
active low. An external FET is then turned on, shorting the fuse to ground, which allows the battery and/or
charger power to blow the fuse. When all of the cell voltages fall below the (VOV–VHYS), the device returns to
NORMAL mode.
8.4.3 Customer Test Mode
It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD
capacitor to VSS. In this case, the OV delay would be reduced to the t(CD_GND) value, which has a maximum of
170 ms.
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Device Functional Modes (continued)
Figure 10 shows the timing for the Customer Test Mode.
OV Condition
V(VCELL)
≤ 170 ms
V(OUT)
CD pin held low
V(CD)
Figure 10. Timing for Customer Test Mode
Figure 11 shows the measurement for current consumption of the product for both VDD and Vx.
IDD
1 VDD
IIN4
I IN3
OUT 8
2 V4
CD 7
3 V3
VSS 6
4 V2
V1 5
ICELL
IIN2
IIN1
ICELL = IDD + IIN1 + I IN2 + IIN3 + I IN4
Figure 11. Configuration for IC Current Consumption Test
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq2947 devices are a family of second-level protectors used for overvoltage protection of the battery pack in
the application. The device, when configuring the OUT pin with active high, drives a NMOS FET that connects
the fuse to ground in the event of a fault condition. This provides a shorted path to use the battery and/or charger
power to blow the fuse and cut the power path. The OUT pin, when configured as active low, can be used to
drive a PMOS FET to connect the fuse to ground instead.
9.2 Typical Applications
9.2.1 Application Configuration for Active High
Figure 12 shows the recommended reference design components.
Pack+
100 Ω
VCELL4
VCELL3
VCELL2
1k
0.1µF
1k
0.1µF
1k
OUT
VDD
1k
0.1µF
V4
CD
V3
VSS
V2
V1
PWPD
0.1 µF
VCELL1
0.1 µF
0.1µF
Pack–
Figure 12. Application Configuration for Active High
9.2.1.1 Design Requirements
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
Changes to the ranges stated in Table 1 will impact the accuracy of the cell
measurements.
Table 1. Parameters
PARAMETER
EXTERNAL COMPONENT
MIN
NOM
MAX
UNIT
Voltage monitor filter resistance
RIN
900
1000
4700
Ω
Voltage monitor filter capacitance
CIN
0.01
0.1
1.0
µF
Supply voltage filter resistance
RVD
100
1000
Ω
Supply voltage filter capacitance
CVD
0.1
1.0
µF
CD external delay capacitance
CCD
0.1
1.0
µF
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NOTE
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this
recommended value changes the accuracy of the cell voltage measurements and VOV
trigger level.
9.2.1.2 Detailed Design Procedure
1. Determine the number of cell in series.
The device supports 2-S to 4-S cell configuration. For 2S and 3S, the top unused pin(s) should be shorted as
shown in Figure 13 and Figure 14.
2. Determine the overvoltage protection delay.
Follow the calculation example described in CD pin description. Select the right capacitor to connect to the
CD pin.
3. Follow the application schematic to connect the device. If the OUT pin is configured to open drain, an
external pull up resistor should be used.
Pack+
100 Ω
VDD
1k
VCELL2
0.1µF
OUT
V4
CD
V3
VSS
V2
0.1µF
1k
V1
PWPD
VCELL1
0.1µF
0.1µF
0.1µF
Pack–
Figure 13. 2-Series Cell Configuration
Pack+
100 Ω
OUT
VDD
V4
CD
V3
VSS
1k
VCELL3
1k
VCELL2
1k
0.1µF
V2
0.1µF
V1
PWPD
0.1µF
VCELL1
0.1µF
0.1µF
Pack–
Figure 14. 3-Series Cell Configuration
14
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SLUSB15F – SEPTEMBER 2012 – REVISED JANUARY 2017
9.2.1.3 Application Curves
4.40
4.39
4.38
0.316
Mean
Min
Max
0.315
4.36
VHYS (V)
VOUT (V)
4.37
4.35
4.34
4.33
0.314
0.313
4.32
4.31
4.30
−50
−25
0
25
50
Temperature (°C)
75
100
125
0.312
−50
Figure 15. Overvoltage Threshold (OVT) vs. Temperature
8
1.5
7
1.4
25
50
Temperature (°C)
75
100
125
G002
6
1.3
1.2
VOUT (V)
IDD (µA)
0
Figure 16. Hysteresis VHYS vs. Temperature
1.6
1.1
1.0
0.9
5
4
3
2
0.8
1
0.7
0.6
−50
−25
G001
−25
0
25
50
Temperature (°C)
75
100
125
0
0
G003
Figure 17. IDD Current Consumption vs.
Temperature at VDD = 16 V
5
10
15
VDD (V)
20
25
Product Folder Links: bq2947
G006
Figure 18. VOUT vs. VDD
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10 Power Supply Recommendations
The maximum power of this device is 20 V on VDD.
11 Layout
11.1 Layout Guidelines
1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The capacitor for CD should be placed close to the IC terminals.
3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack– is sufficient to withstand
the current during fuse blown event.
11.2 Layout Example
Place the RC filters close to the
device terminals
Power Trace Line
VDD
OUT
V4
CD
V3
Pack +
VSS
Pack -
PWPD
VCELL3
V2
V1
VCELL2
VCELL1
Ensure trace can support sufficient current
flow for fuse blow
Figure 19. Layout Example
16
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SLUSB15F – SEPTEMBER 2012 – REVISED JANUARY 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see bq2945xy and bq2947xy Cascade Voltage Monitoring (SLUA662).
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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SLUSB15F – SEPTEMBER 2012 – REVISED JANUARY 2017
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PACKAGE OUTLINE
DSG0008B
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
(0.08)
(0.05)
PIN 1 INDEX AREA
SECTION A-A
SECTION A-A
2.1
1.9
SCALE 30.000
TYPICAL
0.3
0.2
0.4
0.2
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
SEE OPTIONAL
TERMINAL
9
1.6 0.1
8
1
PIN 1 ID
(OPTIONAL)
A
A
8X
0.4
8X
0.2
0.3
0.2
0.1
0.05
C A B
C
4222124/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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SLUSB15F – SEPTEMBER 2012 – REVISED JANUARY 2017
EXAMPLE BOARD LAYOUT
DSG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
8X (0.5)
( 0.2) VIA
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(R0.05) TYP
(1.9)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222124/B 07/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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SLUSB15F – SEPTEMBER 2012 – REVISED JANUARY 2017
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
SYMM
METAL
1
8
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222124/B 07/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Jan-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ294700DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
700
BQ294700DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
700
BQ294701DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
701
BQ294701DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
701
BQ294702DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
702
BQ294702DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
702
BQ294703DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
703
BQ294703DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
703
BQ294704DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
704
BQ294704DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
704
BQ294705DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
705
BQ294705DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
705
BQ294706DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
706
BQ294706DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
706
BQ294707DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
707
BQ294707DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
707
BQ294708DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
-40 to 85
708
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
26-Jan-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ294708DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-2-260C-1 YEAR
-40 to 85
708
BQ294711DSGR
PREVIEW
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
711
BQ294711DSGT
PREVIEW
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
711
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jan-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jan-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
BQ294700DSGR
WSON
DSG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294700DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294701DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294701DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294702DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294702DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294703DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294703DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294704DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294704DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294705DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294705DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294706DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294706DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294707DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294707DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294708DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294708DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jan-2017
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ294711DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294711DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ294700DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294700DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294701DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294701DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294702DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294702DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294703DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294703DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294704DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294704DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294705DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294705DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294706DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294706DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294707DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jan-2017
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ294707DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294708DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294708DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294711DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
BQ294711DSGT
WSON
DSG
8
250
210.0
185.0
35.0
Pack Materials-Page 3
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
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