[AK4223] AK4223 6:2 Audio Switch and 6:2 Video Switch GENERAL DESCRIPTION The AK4223 is an AV switch with 6:2 audio and 6:2 video switches. High performances with low power consumption are achieved by CMOS process. Integrated differential input circuits in audio and video blocks can separate the external ground noise. In audio block, a differential input circuit, audio LPF and 0dB/-6dB gain amplifier are integrated eliminating the needs for external LPF for audio outputs. In video block, an input clamp circuit, 6dB amplifier and video driver are integrated, and they also eliminate the need for external circuits. The AK4223 is offered in a space saving small 48-pin LQFP package, ideal for car navigation applications. FEATURES 1. Audio Section • Selector with 6 inputs and 2 outputs • Differential Input Circuit for Ground Noise Canceling • LPF Circuit for Audio signals • Output Gain Control: 0dB ∼ - 6dB, -1dB Step • S/(N+D): 90dB (@0dBV) • Dynamic Range: 94dB • Channel-Independent Mute Function 2. Video Section • Selector with 6 inputs and 2 outputs • Six Composite Signal Inputs • On-Chip Sync-tip Clamp Circuit • Video Drivers for Composite Signal Output (+6dB/+3dB/0dB/-3dB) • Output Gain Control: -1dB ∼ +1dB, 0.1dB Step • LPF Circuit for Video signals (Bandwidth: 6MHz) • S/N: 65dB • Channel-Independent Mute Function 3. Control Section • Serial µP I/F (I2C) 4. Power Supply: 7.5V ∼ 9.5V 5. Ta = -40 ∼ 85 °C 6. Package: 48pin LQFP MS1251-E-00 1 2010/10 [AK4223] Audio Block SW1 LIN1 VCOM LPF 0dB~ -6dB LOUT1 LPF 0dB~ -6dB ROUT1 LPF 0dB~ -6dB LOUT2 LPF 0dB~ -6dB ROUT2 GND1 RIN1 SW2 Input #1 LIN2 GND2 RIN2 (same circuit) LIN3 GND3 RIN3 (same circuit) LIN4 GND4 RIN4 (same circuit) LIN5 GND5 RIN5 (same circuit) LIN6 GND6 RIN6 (same circuit) Input #2 Input #3 Bias Input #4 VCOM Input #5 Regulator1 Input #6 VSS1 AVDD RVDD VVDD VIN1 SW3 Regulator2 REGV VGND1 VSS2 VIN2 VGND2 VR1 VIN3 VGND3 SW4 GCA LPF (same circuit) VIN5 VGND5 (same circuit) VIN6 VGND6 (same circuit) VOUT1 −3/0/+3/+6dB (same circuit) VIN4 VGND4 SCL SDA LPF (same circuit) GCA VOUT2 VR2 Bias Video Block Register Control RSTN Figure 1. AK4223 Block Diagram MS1251-E-00 2 2010/10 [AK4223] ■ Ordering Guide AK4223VQ AKD4223 -40 ∼ +85°C 48pin LQFP (0.5mm pitch) Evaluation Board for AK4223 MS1251-E-00 LIN3 GND3 RIN3 LIN4 GND4 RIN4 LIN5 GND5 RIN5 LIN6 GND6 RIN6 36 35 34 33 32 31 30 29 28 27 26 25 ■ Pin Layout VSS1 37 24 LOUT1 RIN2 38 23 ROUT1 GND2 39 22 LOUT2 LIN2 40 21 ROUT2 RIN1 41 20 RVDD GND1 42 19 AVDD LIN1 43 18 VVDD 17 RSTN AK4223 Top Vie w 3 10 11 12 VGND1 VIN1 VR2 9 VOUT2 VIN2 13 8 48 VGND2 VGND6 7 VOUT1 VIN3 14 6 47 VGND3 VSS2 5 VR1 VIN4 15 4 46 VGND4 SCL 3 REGV VIN5 16 2 45 VGND5 SDA 1 44 VIN6 VCOM 2010/10 [AK4223] PIN/FUNCTION No. 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name VIN6 VGND5 VIN5 VGND4 VIN4 VGND3 VIN3 VGND2 VIN2 VGND1 VIN1 I/O I I I I I I I I I I I VR2 O 13 14 15 VOUT2 VOUT1 O O VR1 O 16 REGV O 17 RSTN I 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VVDD AVDD RVDD ROUT2 LOUT2 ROUT1 LOUT1 RIN6 GND6 LIN6 RIN5 GND5 LIN5 RIN4 GND4 LIN4 RIN3 GND3 LIN3 VSS1 RIN2 GND2 LIN2 O O O O I I I I I I I I I I I I I I I MS1251-E-00 Function Video Signal Input Pin 6. Video GND Input Pin 5. Video Signal Input Pin 5. Video GND Input Pin 4. Video Signal Input Pin 4. Video GND Input Pin 3. Video Signal Input Pin 3. Video GND Input Pin 2. Video Signal Input Pin 2. Video GND Input Pin 1. Video Signal Input Pin 1. Video Signal Clamp Reference Pin 2. Normally connected to VSS2 with a 0.1μF capacitor. Video Signal Output Pin 2. Video Signal Output Pin 1. Video Signal Clamp Reference Pin 1. Normally connected to VSS2 with a 0.1μF capacitor. Regulator Output Pin for the power supply of Video Core Circuit. 5.0V (typ) For stability of the regulator, this pin must connect to VSS2 with a 10μF capacitor. Reset Mode Pin “L”: Reset mode (All registers are initialized to their default values.) “H”: Normal operation Power Supply Pin: 7.5V~9.5V Power Supply Pin: 7.5V~9.5V Power Supply Pin: 7.5V~9.5V Audio Signal Output Pin ROUT 2. Audio Signal Output Pin LOUT 2. Audio Signal Output Pin ROUT 1. Audio Signal Output Pin LOUT 1. Audio Signal Input Pin RIN 6. Audio GND Input Pin GND 6. Audio Signal Input Pin LIN 6. Audio Signal Input Pin RIN 5. Audio GND Input Pin GND 5. Audio Signal Input Pin LIN 5. Audio Signal Input Pin RIN 4. Audio GND Input Pin GND 4. Audio Signal Input Pin LIN 4. Audio Signal Input Pin RIN 3. Audio GND Input Pin GND 3. Audio Signal Input Pin LIN 3. Audio Ground Pin Audio Signal Input Pin RIN 2. Audio GND Input Pin GND 2. Audio Signal Input Pin LIN 2. 4 2010/10 [AK4223] PIN/FUNCTION (Continued) No. 41 42 43 44 Pin Name RIN1 GND1 LIN1 I/O I I I VCOM O 45 46 47 48 SDA SCL VSS2 VGND6 I/O I I Function Audio Signal Input Pin RIN 1. Audio GND Input Pin GND 1. Audio Signal Input Pin LIN 1. Audio VCOM Voltage Pin. Normally connected to VSS1 with a 1μF electrolytic capacitor. Control Data Pin. Control Data Clock Pin. Video Ground Pin. Video GND Input Pin 6. ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Audio Inputs Video Input Audio, Video Outputs MS1251-E-00 Pin Name LIN1-6, RIN1-6, GND1-6 VIN1-6, VGND1-6 LOUT1-2, ROUT1-2, VOUT1-2 Setting These pins must be open. These pins must be connected to VSS2. These pins must be open. 5 2010/10 [AK4223] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2 =0V; Note 1) Parameter Power Supply Symbol AVDD VVDD RVDD IIN VINA VINV VIND Ta Tstg min max Units -0.3 +14.0 V ±10 AVDD+0.3 5.5 5.5 85 150 mA V V V °C °C Input Current (any pins except for supplies) Audio Input Voltage -0.3 Video Input Voltage -0.3 Digital Input Voltage -0.3 Ambient Operating Temperature -40 Storage Temperature -65 Note 1. All voltages with respect to ground. Note 2. VSS1 and VSS2 must be connected to the same analog ground plane. Note 3. AVDD and RVDD must be the same voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2 = 0V) Parameter Power Supply Symbol AVDD VVDD RVDD Note 3. AVDD and RVDD must be the same voltage. min typ max Units 7.5 9.0 9.5 V *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. ELECTRICAL CHARACTERISTICS (Ta=25°C; AVDD= RVDD= VVDD= 9.0V; VSS1= VSS2 = 0V) Power Supplies Parameter min typ max Power Supply (AVDD+RVDD+VVDD) Normal Operation (Note 4), (RSTN pin = “H”) 33 50 Power-Down Mode (Note 5), (RSTN pin = “L”) 2.1 3.1 Note 4. No input, No load. Note 5. This is the value without analog inputs when all digital input pins are fixed to VSS1 or VSS2. MS1251-E-00 6 Units mA μA 2010/10 [AK4223] ANALOG CHARACTERISTICS (Audio) (Ta=25°C; AVDD= RVDD= VVDD= 9.0V; VSS1=VSS2= 0V; Signal Frequency=1kHz, Measurement Frequency= 20Hz∼20kHz, unless otherwise specified) Parameter Conditions min typ max Units S/(N+D) (Note 6) Input=0dBV 82 90 dB DR (0dBV reference) (Note 6) Input=-60dBV, A-weighted 88 94 dB S/N (0dBV reference) (Note 6) A-weighted 88 94 dB Input Impedance 70 100 kΩ Input Voltage (Note 7) 2 Vrms Gain 0dB -0.4 0 +0.4 dB -6dB -6.4 -6.0 -5.6 dB AGCA step (Note 6) 1.0 dB Interchannel Isolation (Note 8) 100 dB LPF Frequency Response Response at 24kHz -2 -0.5 dB Input=1Vrms, 0dB at 1kHz Response at 96kHz -24 dB Interchannel Gain Mismatch 0.2 dB Gain Drift 20 ppm/°C 300 Load Resistance (Note 9) R1 (Figure 2) Ω 5 R1+R2 (Figure 2) kΩ 1.5 nF Load Capacitance C1 (Figure 2) 30 pF C2 (Figure 2) Power Supply Rejection (Note 10) 74 dB CMRR f=1kHz, 1Vp-p input 35 45 dB Note 6. This is a value when AGCA=0dB. Note 7. The Input Voltage meets S/(N+D)>82dB. Note 8. Between all channels of LIN1-6 and RIN1-6. Note 9. The output resistance of audio output (LOUT1-2 and ROUT1-2) are less than l0Ω (typ). Note 10. Applied to AVDD, RVDD and VVDD with a sine wave (1kHz, 50mVpp). R1 300Ω C3 10uF LOU T/ROUT C21 C22 C2=C21+C22= 30pF(max) C1 R2 4.7kΩ C1= 1.5nF(max) Figure 2. Load Resistance R1, R2 and Load Capacitance C1, C2 MS1251-E-00 7 2010/10 [AK4223] ANALOG CHARACTERISTICS (Video) (Ta = 25°C; AVDD= RVDD= VVDD= 9.0V; VSS1= VSS2 = 0V; VGAIN= +6dB, VGCA=0dB; VR1/2 bit=“0”; unless otherwise specified.) Parameter Conditions min typ max Units Sync tip clamp level VGAIN=+3dB, +6dB 200 mV (Note 11) VGAIN=-3dB, 0dB 500 mV Gain VGCA=+1dB 6dB 7 dB Input=0.3Vp-p, 100kHz 3dB 4 dB 0dB 1 dB -3dB -2 dB VGCA=0dB 6dB 5.6 6 6.4 dB 3dB 2.6 3 3.4 dB 0dB -0.4 0 0.4 dB -3dB -3.4 -3 -2.6 dB 6dB 5 dB VGCA=-1dB 3dB 2 dB 0dB -1 dB -3dB -4 dB VGCA step 0.1 dB Frequency Response Response at 6MHz -1.0 +1.0 dB Input=0.3Vpp, Sin Wave Response at 27MHz -35 dB (0dB at 100kHz) Group Delay Distortion |GD3MHz – GD6MHz| 10 40 ns Input Impedance 300 kΩ Input Signal 1.5 Vpp Inter channel Isolation f=4.43MHz, 1Vpp input 52 dB S/N Reference Level = 0.7Vp-p, 65 dB BW= 100kHz to 6MHz. Differential Gain 0.7Vpp 5steps modulated staircase. +0.4 % Chrominance & burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. +1 Degree Chrominance & burst are 280mVpp, 4.43MHz. Load Resistance VR1/2 bit = “0”, R1+R2 (Figure 4) 140 150 160 Ω VR1/2 bit = “1”, R1 (Figure 5) 100 kΩ Load Capacitance VR1/2 bit = “0”, (Figure 4) C1 1.5 nF C2 15 pF VR1/2 bit = “1”, (Figure 5) C1+C2 15 pF CMRR f=20kHz, 1Vp-p input 34 55 dB Note 11. At the measurement point A in Figure 3. Idling DC output level is 200mV(max) when VGAIN=+6dB or +3db, and 500mV(max) when VGAIN=0dB or -3dB. Measurment point A VOUT Pedestal Volltage 75Ω 0V a a: 100mV(max): VGAIN=+3dB, +6dB 75Ω Figure 3. Measurement Point MS1251-E-00 8 2010/10 [AK4223] R1 75 Ω VOUT R2 75 Ω C1 C2 max: 15pF (C2) max:1.5nF (C1) Figure 4. Load Resistance R1+R2 and Load Capacitance C1/C2 (VR1/2 bit = “0”) R1 100kΩ (min) C VOUT C1 C2 C1+C2=15pF (max) Figure 5. Load Resistance R1+R2 and Load Capacitance C1/C2 (VR1/2 bit = “1”) DC CHARACTERISTICS (Ta=-40~85°C; AVDD= RVDD= VVDD= 7.5∼9.5V) Parameter Symbol High-Level Input Voltage (RSTN,SCL,SDA,CAD pins) VIH Low-Level Input Voltage (RSTN,SCL,SDA,CAD pins) VIL Low-Level Output Voltage (SDA pin: Iout=3mA) Input Leakage Current VOL Iin min 2.7 - typ - max 5.5 0.8 Units V V - - 0.4 ±10 V μA SWITCHING CHARACTERISTICS (Ta= 25°C; AVDD =RVDD= VVDD= 9.0V) Control Interface Timing (I2C Bus) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 13) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Capacitive load on bus Cb Power-down & Reset Timing RSTN Reject Pulse Width tRPD RSTN Pulse Width (Note 14) tPD 150 2 Note 12. I C-bus is a trademark of NXP B.V. Note 13. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 14. The AK4223 can be reset by setting the RSTN pin = “L” when powered up. MS1251-E-00 9 400 0.3 0.3 50 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF 15 ns ns 2010/10 [AK4223] ■ Timing Diagram VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start Figure 6. I2C Bus mode Timing tPD RSTN VIL Figure 7. Reset Mode Timing MS1251-E-00 10 2010/10 [AK4223] OPERATION OVERVIEW ■ Power Up/Down The AK4223 can be reset by bringing the RSTN pin = “L” upon power-up. In reset mode, internal resisters are initialized and the audio and video circuits are in power-down state outputting Hi-Z signals. The RSTN pin must be “L” to execute this reset when power up the AK4223. ■ Audio and Video Signal Inputs 1. Audio Signal Input The ground noise is cancelled by the differential input with the same ground for L and R channels. The output of LIN and RIN are the same phase. LIN1-6, RIN1-6 and GND1-6 pins must be AC coupled with a 0.47uF capacitor. (Cable) LIN1-6 RIN1-6 0.47μF GND1-6 (Cable) 0.47μF Figure 8. Audio Input Circuit (Differential) (Cable) LIN1-6 RIN1-6 0.47μF GND1-6 0.47μF Figure 9. Audio Input Circuit (Single-ended) 2. Video Signal Input Sync-tip output level is fixed by the internal clamp circuit. VIN1-6 pins must be input via a 0.1uF capacitor for AC coupling. VIN1-6 (Cable) 0.1μF (Cable) 0.1μF VGND1-6 Figure 10. Video Input Circuit (Differential) VIN1-6 (Cable) 0.1μF VGND1-6 0.1μF Figure 11. Video Input Circuit (Single-ended) MS1251-E-00 11 2010/10 [AK4223] ■ Input Selector The AK4223 has 6:2 input selectors for audio input, and 6:2 input selectors for video input. The audio input selectors are set by ASEL12-10bits and ASEL22-20 bits, and the video input selectors are set by VSEL12-10bits and VSEL22-20 bits. ASEL12 bit 0 0 0 0 1 1 1 1 ASEL11 bit ASEL10 bit Input Selector 0 0 Off (Note 15) 0 1 LIN1 / RIN1 1 0 LIN2 / RIN2 1 1 LIN3 / RIN3 0 0 LIN4 / RIN4 0 1 LIN5 / RIN5 1 0 LIN6 / RIN6 1 1 (Reserved) Table 1. Audio Input Selector 1 (LOUT1/ROUT1) ASEL22 bit 0 0 0 0 1 1 1 1 ASEL21 bit ASEL20 bit Input Selector 0 0 Off (Note 15) 0 1 LIN1 / RIN1 1 0 LIN2 / RIN2 1 1 LIN3 / RIN3 0 0 LIN4 / RIN4 0 1 LIN5 / RIN5 1 0 LIN6 / RIN6 1 1 (Reserved) Table 2. Audio Input Selector 2 (LOUT2/ROUT2) (default) (default) Note 15. The audio outputs become 3.9V(typ., Gain=0dB) when input selectors are OFF. VSEL12 bit 0 0 0 0 1 1 1 1 VSEL11 bit VSEL10 bit Input Selector 0 0 Off (Note 16) 0 1 VIN1 1 0 VIN2 1 1 VIN3 0 0 VIN4 0 1 VIN5 1 0 VIN6 1 1 (Reserved) Table 3. Video Input Selector 1 (VOUT1) VSEL22 bit 0 0 0 0 1 1 1 1 VSEL21 bit VSEL20 bit Input Selector 0 0 Off (Note 16) 0 1 VIN1 1 0 VIN2 1 1 VIN3 0 0 VIN4 0 1 VIN5 1 0 VIN6 1 1 (Reserved) Table 4. Video Input Selector 2 (VOUT2) (default) (default) Note 16. The video outputs become sync tip level when input selectors are OFF. MS1251-E-00 12 2010/10 [AK4223] ■ Audio Output Level Setting AGCA12-10 bits control the audio output level of the L/ROUT1 pin, and AGCA22-20 bits controls the audio output level of the L/ROUT2 pin. (Table 5, Table 6) AGCA12 bit 0 0 0 0 1 1 1 1 AGCA11 bit 0 0 1 1 0 0 1 1 AGCA10 bit 0 1 0 1 0 1 0 1 L/ROUT1 GAIN [dB] 0 (default) -1 -2 -3 -4 -5 -6 Reserved Output DC Level[V typ] 3.9 3.7 3.5 3.4 3.2 3.1 3.0 - STEP 1dB Table 5. L/ROUT1 Output Level Setting AGCA22 bit 0 0 0 0 1 1 1 1 AGCA21 bit 0 0 1 1 0 0 1 1 AGCA20 bit 0 1 0 1 0 1 0 1 L/ROUT2 GAIN [dB] 0 (default) -1 -2 -3 -4 -5 -6 Reserved Output DC Level[V typ] 3.9 3.7 3.5 3.4 3.2 3.1 3.0 - STEP 1dB Table 6. L/ROUT2 Output Level Setting ■ Audio Output Mute Select The AK4223 has a channel independent mute function for audio outputs. AMUTE1/2 bits control L/ROUT1 and L/ROUT2 outputs mute. (Table 7, Table 8) AMUTE1 bit L/ROUT1 Output 0 Normal Output (default) 1 Mute Table 7. L/ROUT1 Output Mute Control AMUTE2 bit L/ROUT2 Output 0 Normal Output (default) 1 Mute Table 8. L/ROUT2 Output Mute Control MS1251-E-00 13 2010/10 [AK4223] ■ Video Output Level Setting VGAIN11-10 bits control the video output level of the VOUT1 pin, and VGAIN21-20 bits control the video output level of the VOUT2 pin. (Table 9, Table 10) VGAIN11 bit 0 0 1 1 VGAIN21 bit 0 0 1 1 VGAIN10 bit 0 1 0 1 VGAIN20 bit 0 1 0 1 VOUT1 output Level VOUT1 Sync Tip Level (max) +6dB 200mV (default) 0dB 500mV +3dB 200mV -3dB 500mV Table 9.VOUT1 Output Level Setting VOUT2 output Level VOUT2 Sync Tip Level (max) +6dB 200mV 0dB 500mV +3dB 200mV -3dB 500mV Table 10.VOUT2 Output Level Setting (default) VGCA14-10 bits finely tune the video output levels of VOUT1, and VGCA24-20 bits tune VOUT2. (Table 11, Table 12) VGCA14-10 bit VOUT1 GAIN [dB] STEP 00000 −1.0 00001 −0.9 00010 −0.8 : : 01010 0 (default) 0.1dB : : 10010 +0.8 10011 +0.9 10100 +1.0 others Reserved Table 11. Video Output Level (VOUT1) Fine Tuning Setting VGCA24-20 bit VOUT2 GAIN [dB] STEP 00000 −1.0 00001 −0.9 00010 −0.8 : : 01010 0 (default) 0.1dB : : 10010 +0.8 10011 +0.9 10100 +1.0 others Reserved Table 12. Video Output Level (VOUT2) Fine Tuning Setting MS1251-E-00 14 2010/10 [AK4223] ■ Video Output Driver VR1 and VR2 bits control the video output driver of the VOUT1 and VOUT2 pins respectively. VR1 and VR2 bits should be set to “0” when driving 150Ω resistance. VR1 bit VOUT1 0 150Ω Drive (default) 1 min. 100kΩ Drive Table 13. VOUT1 Output Driver Setting VR2 bit VOUT2 0 150Ω Drive (default) 1 min. 100kΩ Drive Table 14. VOUT2 Output Driver Setting ■ Video Output Mute Setting The AK4223 has a channel independent mute function of the video output. VMUTE1 and VMUTE2 bits mute (Sync tip clamp level) VOUT1 and VOUT2 outputs respectively. (Table 15, Table 16) VMUTE1 bit VOUT1 Output 0 Normal Output (default) 1 Mute Table 15. VOUT1 Output Mute Control VMUTE2 bit VOUT2 Output 0 Normal Output (default) 1 Mute Table 16. VOUT2 Output Mute Control MS1251-E-00 15 2010/10 [AK4223] ■ System Reset The RSTN pin must be set to “L” when power up the AK4223. The AK4223 powers up in reset state. The REGV pin starts outputting (typ. 5.0V) when power is supplied to the device. This reset is released by setting the RSTN pin to “H”. Figure 12 shows the reset sequence. Power Supply (VVDD, AVDD, RVDD) (1) REGV pin Output VSS REGV=5.0V(TYP) (2) RSTN Pin Audio⋅Video Circuit (3) Power down Audio Output: Hi-Z Power Up Notes: (1) Time that the REGV output reaches 95% of the maximum value. (typ. 800μs, max. 5ms) (2) Reset Time (min. 150ns) (3) Time to be in a normal operation after reset release. (Video Output: typ. 100ms, Audio Output: typ. 170ms) *The required time to be in a normal operation of audio outputs is proportional to the capacity of an external capacitor at the VCOM pin. This typical value 170ms is for when the external capacitor is 1.0μF. Figure 12 System Reset Diagram MS1251-E-00 16 2010/10 [AK4223] ■ Control Interface The AK4223 supports the fast-mode I2C-bus system (max: 400kHz). 2-1. WRITE Operation Figure 13 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 19). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as “0010000”. If the slave address matches that of the AK4223, the AK4223 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 20). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4223. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 15). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 16). The AK4223 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 19). The AK4223 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4223 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 8-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 06H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 21) except for the START and STOP conditions. S T A R T SDA S T O P R/W = "0" Slave S Address Sub Address(n) Data(n) A C K Data(n+1) A C K A C K Data(n+x) A C K P A C K A C K Figure 13. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 0 0 R/W A2 A1 A0 D2 D1 D0 Figure 14. The First Byte 0 0 0 0 0 Figure 15. The Second Byte D7 D6 D5 D4 D3 Figure 16. Byte Structure after the second byte MS1251-E-00 17 2010/10 [AK4223] 2-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4223. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 06H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4223 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. 2-2-1. CURRENT ADDRESS READ The AK4223 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4223 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4223 ceases transmission. S T A R T SDA S T O P R/W = "1" Slave S Address Data(n+1) Data(n) A C K A C K Data(n+2) A C K Data(n+x) A C K A C K P A C K Figure 17. CURRENT ADDRESS READ 2-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4223 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4223 ceases transmission. S T A R T SDA S T A R T R/W = "0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W = "1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 18. RANDOM ADDRESS READ MS1251-E-00 18 2010/10 [AK4223] SDA SCL S P start condition stop condition Figure 19. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 20. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 21. Bit Transfer on the I2C-Bus MS1251-E-00 19 2010/10 [AK4223] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H Register Name Control Input Selector Control1 Input Selector Control2 Output Level Control1 Output Level Control2 Output Level Control3 Output Level Control4 D7 0 0 0 0 0 0 0 D6 0 ASEL22 VSEL22 AGCA22 VR2 0 0 D5 VMUTE2 ASEL21 VSEL21 AGCA21 VR1 0 0 D4 VMUTE1 ASEL20 VSEL20 AGCA20 0 VGCA14 VGCA24 D3 0 0 0 0 VGAIN21 VGCA13 VGCA23 D2 0 ASEL12 VSEL12 AGCA12 VGAIN20 VGCA12 VGCA22 D1 AMUTE2 ASEL11 VSEL11 AGCA11 VGAIN11 VGCA11 VGCA21 D0 AMUTE1 ASEL10 VSEL10 AGCA10 VGAIN10 VGCA10 VGCA20 Note: Do not write any data to the register over 07H. When the PDN pin changes to “L”, the registers are initialized to their default values. The bits defined as 0 must contain a “0” value. MS1251-E-00 20 2010/10 [AK4223] ■ Register Definitions Addr 00H Register Name Control Default D7 0 0 D6 0 0 D5 VMUTE2 0 D4 VMUTE1 0 D3 0 0 D2 0 0 D1 AMUTE2 0 D0 AMUTE1 0 AMUTE2-1: Audio Output Mute Control (Table 7, Table 8) 0: Normal Operation (default) 1: Mute VMUTE2-1: Video Output Mute Control (Table 15, Table 16) 0: Normal Operation (default) 1: Mute Addr 01H Register Name Input Selector Control1 Default D7 0 0 D6 ASEL22 0 D5 ASEL21 0 D4 ASEL20 0 D3 0 0 D2 ASEL12 0 D1 ASEL11 0 D0 ASEL10 0 D2 VSEL12 0 D1 VSEL11 0 D0 VSEL10 0 D2 AGCA12 0 D1 AGCA11 0 D0 AGCA10 0 ASEL12-10: Audio Input Selector 1 Control (Table 1) The LOUT1/ROUT2 pin outputs 3.9V (typ., Gain=0dB) at the default setting “000”. ASEL22-20: Audio Input Selector 2 Control (Table 2) The LOUT2/ROUT2 pin outputs 3.9V (typ., Gain=0dB) at the default setting “000”. Addr 02H Register Name Input Selector Control2 Default D7 0 0 D6 VSEL22 0 D5 VSEL21 0 D4 VSEL20 0 D3 0 0 VSEL12-10: Video Input Selector 1 Control (Table 3) The video output is sync tip clamp level at the default setting “000”. VSEL22-20: Video Input Selector 2 Control (Table 4) The video output is sync tip clamp level at the default setting “000”. Addr 03H Register Name Output Level Control1 Default D7 0 0 D6 AGCA22 0 D5 AGCA21 0 D4 AGCA20 0 D3 0 0 AGCA11-10: Audio Output L/ROUT1 Level Control (Table 5) 000: 0dB (default) 001: -1dB 010: -2dB … 110: -6dB 111: Reserved AGCA21-20: Audio Output L/ROUT2 Level Control (Table 6) 000: 0dB (default) 001: -1dB 010: -2dB … 110: -6dB 111: Reserved MS1251-E-00 21 2010/10 [AK4223] Addr 04H Register Name Output Level Control2 Default D7 0 0 D6 VR2 0 D5 VR1 0 D4 0 0 D3 VGAIN21 0 D2 VGAIN20 0 D1 VGAIN11 0 D0 VGAIN10 0 VGAIN11-10: Video Output1 Level Control (Table 9) 00: +6dB (default) 01: 0dB 10: +3dB 11: -3dB VGAIN21-20: Video Output2 Level Control (Table 10) 00: +6dB (default) 01: 0dB 10: +3dB 11: -3dB VR1: Video Output1 Load Resistance 0: Drive 150Ω (default) 1: Drive 100kΩ (min) VR2: Video Output2 Load Resistance 0: Drive 150Ω (default) 1: Drive 100kΩ (min) Addr 05H Register Name Output Level Control3 Default D7 0 0 D6 0 0 D5 0 0 D4 VGCA14 0 D3 VGCA13 1 D2 VGCA12 0 D1 VGCA11 1 D0 VGCA10 0 VGCA14-10: Video Output1 Level Control (Table 11) The video output is +6dB (when VGAIN11-10 bits = “00”), 0dB (when VGAIN11-10 bits = “01”), +3dB (when VGAIN11-10 bits= “10”) and -3dB (when VGAIN11-10 bits = “11”) at the default setting “01010”. Addr 06H Register Name Output Level Control4 Default D7 0 0 D6 0 0 D5 0 0 D4 VGCA24 0 D3 VGCA23 1 D2 VGCA22 0 D1 VGCA21 1 D0 VGCA20 0 VGCA24-20: Video Output2 Level Control (Table 12) The video output is +6dB (when VGAIN21-20 bits = “00”), 0dB (when VGAIN21-20 bits = “01”), +3dB (when VGAIN21-20 bits= “10”) and -3dB (when VGAIN21-20 bits = “11”) at the default setting “01010”. MS1251-E-00 22 2010/10 [AK4223] SYSTEM DESIGN Figure 22 shows a system connection diagram. An evaluation board [AKD4223] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Digital Ground Analog Ground Micro Controller RIN2 38 VSS1 37 0.47u 0.47u GND2 39 LIN4 33 0.47u 0.47u 0.47u GND5 29 0.47u RIN5 28 0.47u LIN6 27 Video out 24 LOUT1 10u 300 23 ROUT1 22 LOUT2 21 ROUT2 10u 10u 300 10u 10u 0.1u 300 0.1u 10u 75 75 10u 300 20 RVDD 19 AVDD 15 VR1 18 VVDD RIN6 25 17 RSTN 12 VR2 16 REGV GND6 26 14 VOUT1 11 VIN1 Audio in 0.47u LIN5 30 0.1u 0.1u 0.47u RIN4 31 10 VGND1 0.1u 0.47u GND4 32 9 VIN2 0.1u VSS2 LIN2 40 0.47u RIN1 41 0.47u GND1 42 LIN1 43 SDA 45 4 VGND4 8 VGND2 0.1u 0.1u 75 RIN3 34 7 VIN3 0.1u 75 3 VIN5 6 VGND3 0.1u 0.47u GND3 35 5 VIN4 0.1u 75 VCOM 44 0.47u 0.1u 0.47u LIN3 36 2 VGND5 0.1u 0.1u 75 SCL 46 1 VIN6 0.1u 75 VSS2 47 75 13 VOUT2 Video In VGND6 48 0.1u 0.47u 1u Audio in 0.47u 0.47u VSS1 Audio out Analog 9V Figure 22. Typical Connection Diagram MS1251-E-00 23 2010/10 [AK4223] 1. Grounding and Power Supply Decoupling The AK4223 requires careful attention to power supply and grounding arrangements. AVDD, VVDD and RVDD are usually supplied from the analog power supply in the system. Alternatively if AVDD, VVDD and RVDD are supplied separately, AVDD and RVDD must be powered-up at the same time. The power up sequence between AVDD/RVDD and VVDD is not critical. VSS1 and VSS2 must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the power supply pin of AK4223 as possible. 2. Voltage Reference VCOM is a signal ground of this chip. An 1μF electrolytic capacitor attached between VCOM and VSS1 eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. To avoid coupling to the AK4223, all signals and especially clock signals should be kept away as far as possible from the VCOM pin. 3. Notes for Drawing a Board Analog input and output pins should be as short as possible in order to avoid unwanted coupling into the AK4223. The unused pins should be open. MS1251-E-00 24 2010/10 [AK4223] PACKAGE 48pin LQFP (Unit: mm) 1.70Max 9.0 ± 0.2 0.13 ± 0.13 7.0 36 1.40 ± 0.05 24 48 13 7.0 37 12 1 0.5 9.0 ± 0.2 25 0.22 ± 0.08 0.09 ∼ 0.20 0.10 M 0° ∼ 10° 0.10 0.3 ∼ 0.75 ■ Package & Lead Frame Material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate RoHS Compliance *All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in “lead-free” packages are fully compliant with RoHS. MS1251-E-00 25 2010/10 [AK4223] MARKING AK4223VQ XXXXXXX 1 XXXXXXXX: Date code identifier REVISION HISTORY Date (YY/MM/DD) 10/10/22 MS1251-E-00 Revision 00 Reason First Edition Page Contents 26 2010/10 [AK4223] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1251-E-00 27 2010/10