ALSC AS7C33256PFS18A-150TQI 3.3v 256k ã 16/18 pipeline burst synchronous sram Datasheet

AS7C33256PFS16A
AS7C33256PFS18A
March 2001
®
3.3V 256K × 16/18 pipeline burst synchronous SRAM
Features
• Organization: 262,144 words × 16 or 18 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• “Flow-through” mode
• Single-cycle deselect
- Dual-cycle deselect also available (AS7C33256PFD16A/
AS7C33256PFD18A)
• Pentium®* compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• NTD™* pipeline architecture available
(AS7C33256NTD16A/AS7C33256NTD18A)
Logic block diagram
Pin arrangement
18
A[17:0]
Q
D
18
256K × 16/18
Memory
array
16 18
Address
register
CS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Burst logic
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
FT
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQpb/NC
NC
VSSQ
VDDQ
NC
NC
NC
CLK
16/18 16/18
GWE
BWb
D
DQb
Q
Byte Write
registers
BWE
CLK
D DQa
Q
BWa
Byte Write
registers
CE0
CE1
CE2
D
2
CLK
Enable Q
register
CE
CLK
ZZ
Power
down
D
OE
Output
registers
CLK
Input
registers
CLK
Enable Q
delay
register
CLK
FT
DATA [17:0]
DATA [15:0]
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TQFP 14 × 20mm
A17
NC
NC
VDDQ
VSSQ
NC
DQpa/NC
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CLK
CS
CLR
CLK
ADV
ADSC
ADSP
A6
A7
CE0
CE1
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
LBO
Note: pins 24, 74 are NC for ×16.
Selection guide
AS7C33256PFS16A AS7C33256PFS16A AS7C33256PFS16A AS7C33256PFS16A
–166
–150
–133
–100
Units
Minimum cycle time
6
6.7
7.5
10
ns
Maximum pipelined clock frequency
166
150
133
100
MHz
Maximum pipelined clock access time
3.5
3.8
4
5
ns
Maximum operating current
475
450
425
325
mA
Maximum standby current
130
110
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
30
mA
*
Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are
the property of their respective owners.
3/14/01; V.1.0
Alliance Semiconductor
P. 1 of 11
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33256PFS16A
AS7C33256PFS18A
®
Functional description
The AS7C33256PFS16A and AS7C33256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC™*-based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC),
or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes
are HIGH. Burst operation is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium® count
sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33256PFS16A and AS7C33256PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP packaging.
*PowerPC™ is a tradenark International Business Machines Corporation.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
Address and control pins
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O pins
VIN = VOUT = 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
L
X
X
T
H
L
L
T
H
H
X
F*
H
L
H
F*
Key:
X = Don’t Care, L = Low, H = High, T=True, F=False
* valid read
n = a,b
WE, WEn = internal write signal
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P. 2 of 11
AS7C33256PFS16A
AS7C33256PFS18A
®
Signal descriptions
Signal
I/O
Properties
Description
CLK
I
CLOCK
A0–A17
I
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When
CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on
clock edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe (processor). Asserted LOW to load a new address or to enter
standby mode.
ADSC
I
SYNC
Address strobe (controller). Asserted LOW to load a new address or to enter
standby mode.
ADV
I
SYNC
Burst advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and
BW[a,b] control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]
inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and
BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the
cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is
in read mode.
LBO
I
FT
I
STATIC
Flow-through mode.When LOW, enables single register flow-through mode.
Connect to VDD if unused or for pipelined operation.
ZZ
I
ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if
unused.
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Count mode. When driven HIGH, count sequence follows Intel XOR convention.
STATIC default =
When driven LOW, count sequence follows linear convention. This signal is
HIGH
internally pulled HIGH.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
VDD, VDDQ
–0.5
+4.6
V
Input voltage relative to GND (input pins)
VIN
–0.5
VDD + 0.5
V
Input voltage relative to GND (I/O pins)
VIN
–0.5
VDDQ + 0.5
V
Power dissipation
PD
–
1.8
W
DC output current
IOUT
–
50
mA
Storage temperature (plastic)
Tstg
–65
+150
°C
Temperature under bias
Tbias
–65
+135
°C
Power supply voltage relative to GND
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
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AS7C33256PFS16A
AS7C33256PFS18A
®
Synchronous truth table
CE0
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
CE1
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
ADSC
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
WEn1
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
Key: X = Don’t Care, L = Low, H = High.
1See “Write enable truth table” on page 2 for more information.
2
Q in flow through mode
3
For write operation following a READ, OE must be HIGH before
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
Address accessed
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Cont. read
Cont. read
Suspend read
Suspend read
Cont. read
Cont. read
Suspend read
Suspend read
Begin write
Cont. write
Cont. write
Suspend write
Suspend write
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z2
Hi−Z
Hi−Z2
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
D3
D
D
D
D
the input data set up time and held HIGH throughout the input hold
time.
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
VDD
3.135
3.3
3.6
VSS
0.0
0.0
0.0
3.3V I/O supply
voltage
VDDQ
3.135
3.3
3.6
VSSQ
0.0
0.0
0.0
2.5V I/O supply
voltage
VDDQ
2.35
2.5
2.9
VSSQ
0.0
0.0
0.0
VIH
2.0
–
VDD + 0.3
VIL
–0.5*
–
0.8
VIH
2.0
–
VDDQ + 0.3
VIL
–0.5*
–
0.8
TA
0
–
70
Supply voltage
Input
voltages†
Address and
control pins
I/O pins
Ambient operating temperature
Unit
V
V
V
V
V
°C
* VIL min = –2.0V for pulse width less than 0.2 × tRC.
† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
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Alliance Semiconductor
P. 4 of 11
AS7C33256PFS16A
AS7C33256PFS18A
®
TQFP thermal resistance
Description
Conditions
Thermal resistance
(junction to ambient)*
Symbol
Typical
Units
θJA
46
°C/W
θJC
2.8
°C/W
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Thermal resistance
(junction to top of case)*
* This parameter is sampled.
DC electrical characteristics
–166
Parameter
–150
–133
–100
Symbol
Test conditions
Input leakage
current*
|ILI|
VDD = Max, VIN = GND to VDD
–
2
–
2
–
2
–
2
µA
Output leakage
current
|ILO|
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
–
2
–
2
–
2
–
2
µA
ICC
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
–
475
–
450
–
425
–
325
mA
ISB
Deselected, f = fMax, ZZ ≤ VIL
–
130
–
110
–
100
–
90
ISB1
Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V
–
30
–
30
–
30
–
30
ISB2
Deselected, f = fMax, ZZ ≥ VDD – 0.2V
All VIN ≤ VIL or ≥ VIH
–
30
–
30
–
30
–
30
VOL
IOL = 8 mA, VDDQ = 3.465V
–
0.4
–
0.4
–
0.4
–
0.4
VOH
IOH = –4 mA, VDDQ = 3.135V
2.4
–
2.4
–
2.4
–
2.4
–
Operating power
supply current
Standby power
supply current
Output voltage
Min Max Min Max Min Max Min Max Unit
mA
V
* LBO pin has an internal pull-up and input leakage = ±10 µa.
Note: ICC give with no output loading. ICC increases with faster cycle times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
–166
Parameter
Output leakage
current
Output voltage
–150
–133
–100
Symbol
Test conditions
Min Max Min Max Min Max Min Max Unit
|ILO|
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
–1
1
–1
1
–1
1
–1
1
VOL
IOL = 2 mA, VDDQ = 2.65V
–
0.7
–
0.7
–
0.7
–
0.7
VOH
IOH = –2 mA, VDDQ = 2.35V
1.7
–
1.7
–
1.7
–
1.7
–
µA
V
Timing characteristics over operating range
–166
Parameter
Symbol Min
–150
–133
–100
Max
Min
Max
Min
Max
Min
Max
Unit
Clock frequency
fMax
–
166
–
150
–
133
–
100
MHz
Cycle time (pipelined mode)
tCYC
6
–
6.6
–
7.5
–
10
–
ns
Cycle time (flow-through mode)
tCYCF
10
–
10
–
12
–
12
–
ns
tCD
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock access time (pipelined mode)
3/14/01; V.1.0
Alliance Semiconductor
Notes*
P. 5 of 11
AS7C33256PFS16A
AS7C33256PFS18A
®
–166
Parameter
Symbol Min
–150
–133
–100
Max
Min
Max
Min
Max
Min
Max
Unit
Notes*
Clock access time (flow-through
mode)
tCDF
–
9
–
10
–
10
–
12
ns
Output enable LOW to data valid
tOE
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock HIGH to output Low Z
tLZC
0
–
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
tOH
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
tLZOE
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
tHZOE
–
3.5
–
3.8
–
4.0
–
4.5
ns
2,3,4
Clock HIGH to output High Z
tHZC
–
3.5
–
3.8
–
4.0
–
5.0
ns
2,3,4
Output enable HIGH to invalid output
tOHOE
0
–
0
–
0
–
0
–
ns
Clock HIGH pulse width
tCH
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Clock LOW pulse width
tCL
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Address setup to clock HIGH
tAS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Data setup to clock HIGH
tDS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Write setup to clock HIGH
tWS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
tCSS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,8
Address hold from clock HIGH
tAH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
tDH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
tWH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
tCSH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
tADVS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSP setup to clock HIGH
tADSPS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSC setup to clock HIGH
tADSCS
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADV hold from clock HIGH
tADVH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold fromclock HIGH
tADSPH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
tADSCH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
*“Notes” column refers to “notes” on page 10.
Key to switching waveforms
Rising input
3/14/01; V.1.0
Falling input
Alliance Semiconductor
Undefined/don’t care
P. 6 of 11
AS7C33256PFS16A
AS7C33256PFS18A
®
Timing waveform of read cycle
tCH
tCYC
tCL
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
tAS
LOAD NEW ADDRESS
tAH
Address
A1
A2
A3
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tCD
tHZOE
tOH
ADV INSERTS WAIT STATES
tHZC
DOUT
(pipelined mode) t
OE
tLZOE
DOUT
(flow-through mode)
Q(A1)
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý10)
Q(A2Ý11)
Q(A2Ý11)
Q(A3)
Q(A3)
Q(A3Ý01)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý10)
Q(A3Ý11)
tHZC
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
BW[a:b] is don’t care.
3/14/01; V.1.0
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AS7C33256PFS16A
AS7C33256PFS18A
®
Timing waveform of write cycle
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
Address
A1
A2
A3
tWS
tWH
BWE
BWa,b
tCSS
tCSH
CE0, CE2
CE1
tADVS
ADV SUSPENDS BURST
tADVH
ADV
OE
tDS
tDH
Data In
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01)
D(A2Ý10)
D(A2Ý11)
D(A3)
D(A3Ý01)
D(A3Ý10)
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
3/14/01; V.1.0
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AS7C33256PFS16A
AS7C33256PFS18A
®
Timing waveform of read/write cycle
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
Address
A2
A1
A3
tWS
tWH
GWE
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDS
tDH
D(A2)
DIN
tLZC
tHZOE
tCD
Q(A1)
DOUT
(pipeline mode)
tOH
tLZOE
tOE
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tCDF
DOUT
(flow-through mode)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
3/14/01; V.1.0
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AS7C33256PFS16A
AS7C33256PFS18A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
Thevenin equivalent:
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O
• Input and output timing reference levels: 1.5V.
+3.0V
Z0 = 50Ω
90%
10%
GND
90%
10%
DOUT
Figure A: Input waveform
50Ω
DOUT
VL = 1.5V
for 3.3V I/O;
30 pF* = V
DDQ/2
for 2.5V I/O
351Ω
Figure B: Output load (A)
317Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load(B)
Notes
1) For test conditions, see AC Test Conditions, Figures A, B, C.
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to GWE, BWE, BW[a:d].
8) Chip select refers to CE0, CE1,
CE2.
Package Dimensions
100-pin quad flat pack (TQFP)
A1
A2
b
c
D
E
e
Hd
He
L
L1
α
TQFP
Min
Max
0.05
0.15
1.35
1.45
0.22
0.38
0.09
0.20
13.90 14.10
19.90 20.10
0.65 nominal
15.90 16.10
21.90 22.10
0.45
0.75
1.00 nominal
0°
7°
Hd
D
b
e
He E
Dimensions in millimeters
α
c
L1
L
3/14/01; V.1.0
A1 A2
Alliance Semiconductor
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AS7C33256PFS16A
AS7C33256PFS18A
®
Ordering information
–166 MHz
–150 MHz
–133 MHz
–100 MHz
AS7C33256PFS16A-166TQC
AS7C33256PFS16A-150TQC
AS7C33256PFS16A-133TQC AS7C33256PFS16A-100TQC
AS7C33256PFS16A-166TQI
AS7C33256PFS16A-150TQI
AS7C33256PFS16A-133TQI
AS7C33256PFS18A-166TQC
AS7C33256PFS18A-150TQC
AS7C33256PFS18A-133TQC AS7C33256PFS18A-100TQC
AS7C33256PFS18A-166TQI
AS7C33256PFS18A-150TQI
AS7C33256PFS18A-133TQI
AS7C33256PFS16A-100TQI
AS7C33256PFS18A-100TQI
Part numbering guide
AS7C
33
256
PF
S
16/18
A
–XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 256=256K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: S=Single cycle deselect
6.Organization: 16=x16; 18=x18
7.Production version: A=first production version
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
3/14/01; V.1.0
Alliance Semiconductor
P. 11 of 11
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