CY7C1370D, CY7C1372D 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades are 250, 200, and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte write capability ■ 3.3 V core power supply (VDD) ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 2.6 ns (for 250 MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA and 165-ball FBGA package ■ IEEE 1149.1 JTAG-compatible boundary scan ■ Burst capability—linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock option The CY7C1370D and CY7C1372D are 3.3 V, 512 K × 36 and 1 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1370D and CY7C1372D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1370D and CY7C1372D are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the byte write selects (BWa–BWd for CY7C1370D and BWa–BWb for CY7C1372D) and a write enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Logic Block Diagram - CY7C1370D (512 K × 36) ADDRESS REGISTER 0 A0, A1, A A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW a BW b BW c BW d MEMORY ARRAY WRITE DRIVERS A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 S T E E R I N G INPUT REGISTER 0 B U F F E R S DQ s DQ Pa DQ Pb DQ Pc DQ Pd E E READ LOGIC SLEEP CONTROL ZZ Cypress Semiconductor Corporation Document Number: 38-05555 Rev. *L E O U T P U T D A T A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 8, 2011 [+] Feedback CY7C1370D, CY7C1372D Logic Block Diagram - CY7C1372D (1 M × 18) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD BW a WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY A M P S BW b WE O U T P U T R E G I S T E R S O U T P U T D A T A B U F F E R S S T E E R I N G E INPUT REGISTER 1 OE CE1 CE2 CE3 ZZ Document Number: 38-05555 Rev. *L E DQ s DQ Pa DQ Pb E INPUT REGISTER 0 E READ LOGIC Sleep Control Page 2 of 33 [+] Feedback CY7C1370D, CY7C1372D Contents Selection Guide ................................................................ 4 Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 7 Functional Overview ........................................................ 8 Single Read Accesses ................................................ 8 Burst Read Accesses .................................................. 8 Single Write Accesses ................................................. 8 Burst Write Accesses .................................................. 9 Sleep Mode ................................................................. 9 Interleaved Burst Address Table (MODE = Floating or VDD) ............................................... 9 Linear Burst Address Table (MODE = GND) .................. 9 ZZ Mode Electrical Characteristics ................................. 9 Truth Table ...................................................................... 10 Partial Write Cycle Description ..................................... 11 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12 Disabling the JTAG Feature ...................................... 12 Test Access Port (TAP) ............................................. 12 PERFORMING A TAP RESET .................................. 12 TAP REGISTERS ...................................................... 12 TAP Instruction Set ................................................... 12 TAP Controller State Diagram ....................................... 14 TAP Controller Block Diagram ...................................... 14 TAP Timing ...................................................................... 14 TAP AC Switching Characteristics ............................... 15 3.3 V TAP AC Test Conditions ....................................... 16 3.3 V TAP AC Output Load Equivalent ......................... 16 2.5 V TAP AC Test Conditions ....................................... 16 Document Number: 38-05555 Rev. *L 2.5 V TAP AC Output Load Equivalent ......................... 16 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 16 Identification Register Definitions ................................ 17 Scan Register Sizes ....................................................... 17 Identification Codes ....................................................... 17 Boundary Scan Order .................................................... 18 Boundary Scan Order .................................................... 19 Maximum Ratings ........................................................... 20 Operating Range ............................................................. 20 Electrical Characteristics ............................................... 20 Capacitance .................................................................... 21 Thermal Resistance ........................................................ 21 AC Test Loads and Waveforms ..................................... 22 Switching Characteristics .............................................. 23 Switching Waveforms .................................................... 24 Ordering Information ...................................................... 26 Ordering Code Definitions ......................................... 26 Package Diagrams .......................................................... 27 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Document History Page ................................................. 31 Sales, Solutions, and Legal Information ...................... 33 Worldwide Sales and Design Support ....................... 33 Products .................................................................... 33 PSoC Solutions ......................................................... 33 Page 3 of 33 [+] Feedback CY7C1370D, CY7C1372D Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current 250 MHz 200 MHz 167 MHz Unit 2.6 350 70 3.0 300 70 3.4 275 70 ns mA mA Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1372D (1 M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A NC(36) NC(72) VSS VDD A A A A A A A NC(72) NC(36) VSS VDD NC(288) NC(144) MODE A A A A A1 A0 Document Number: 38-05555 Rev. *L NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb DQa NC VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC NC(288) NC(144) CY7C1370D (512 K × 36) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS DQc DQc DQc DQc VSS VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DQPc DQc DQc VDDQ A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A Figure 1. 100-pin TQFP Page 4 of 33 [+] Feedback CY7C1370D, CY7C1372D Pin Configurations (continued) Figure 2. 119-ball BGA CY7C1370D (512 K × 36) 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B C D E F G H J K L M N P NC/576M NC/1G DQc CE2 A DQPc A A VSS ADV/LD VDD NC A A VSS CE3 A DQPb NC NC DQb CE1 VSS DQb DQb OE A VSS DQb VDDQ BWb DQb DQb WE VDD VSS NC DQb VDD DQb VDDQ CLK NC VSS BWa DQa DQa DQa DQa R T U DQc DQc VSS VDDQ DQc VSS DQc DQc DQc VDDQ DQc VDD BWc VSS NC DQd DQd DQd DQd BWd VDDQ DQd VSS DQa VDDQ DQd VSS CEN A1 VSS DQd VSS DQa DQa DQd DQPd VSS A0 VSS DQPa DQa NC/144M A MODE VDD NC/288M NC/72M A A NC A A NC NC/36M ZZ VDDQ TMS TDI TCK TDO NC VDDQ VSS CY7C1372D (1 M × 18) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ A A A A A VDDQ NC/576M CE2 A A VSS A VSS CE3 A DQPa NC A NC ADV/LD VDD NC A NC/1G DQb CE1 VSS NC DQa OE A VSS DQa VDDQ NC NC NC DQb VSS VDDQ NC VSS NC DQb VDDQ DQb NC VDD BWb VSS NC WE VDD NC VSS NC NC DQa VDD DQa NC VDDQ NC DQb VSS CLK VSS NC DQa BWa VSS DQa NC NC VDDQ DQb NC NC NC VDDQ DQb VSS DQb NC VSS CEN A1 VSS DQa NC NC DQPb VSS A0 VSS NC DQa NC/144M A MODE VDD NC A NC/288M NC/72M A A NC/36M A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ Document Number: 38-05555 Rev. *L Page 5 of 33 [+] Feedback CY7C1370D, CY7C1372D Pin Configurations (continued) Figure 3. 165-ball FBGA CY7C1370D (512 K × 36) 1 2 3 4 5 6 A B C D E F G H J K L M N P NC/576M A 7 8 9 10 11 A A NC CLK CEN WE ADV/LD CE1 BWc BWb CE3 NC/1G A CE2 DQPc DQc NC DQc BWa VSS VDDQ BWd VSS VDD OE A A NC VSS VSS VSS VSS VSS VDD VDDQ VSS VDDQ NC DQb DQPb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc DQc NC DQd DQc NC DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQb NC DQa DQb ZZ DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQPd DQd NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC DQa DQPa A A TDI A1 TDO A A A NC/288M R MODE A A TMS A0 TCK A A A A 9 10 11 NC/144M NC/72M NC/36M VDDQ CY7C1372D (1 M × 18) A B C D E F G H J K L M N P R 1 2 3 4 NC/576M NC/1G 6 7 8 A CE1 BWb A CE2 NC NC CE3 CEN ADV/LD A A A BWa CLK WE VSS VSS OE VSS VDD A A NC NC NC NC DQb VDDQ VSS VDDQ VSS VDD VSS VSS VSS VDDQ VDDQ NC NC DQPa DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD NC NC DQb DQb NC NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VDD VDDQ NC DQa VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQa DQa ZZ NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb DQPb NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC NC NC NC/144M NC/72M A A TDI A1 TDO A A A NC/36M A A TMS A0 TCK A A A MODE Document Number: 38-05555 Rev. *L 5 NC/288M A Page 6 of 33 [+] Feedback CY7C1370D, CY7C1372D Pin Definitions Pin Name A0, A1, A I/O Type Pin Description InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK. synchronous BWa, BWb, InputByte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on BWc, BWd synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd. WE InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal synchronous must be asserted LOW to initiate a write sequence. ADV/LD InputAdvance/load input used to advance the on-chip address counter or load a new address. When synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select/deselect the device. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select/deselect the device. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. OE InputOutput enable, active LOW. Combined with the synchronous logic block inside the device to control asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQS I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd. MODE Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. output synchronous TDI JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. input synchronous TMS Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK. select synchronous TCK JTAG-clock Clock input to the JTAG circuitry. Document Number: 38-05555 Rev. *L Page 7 of 33 [+] Feedback CY7C1370D, CY7C1372D Pin Definitions (continued) Pin Name VDD VDDQ VSS NC NC/(36M,7 2M, 144M, 288M, 576M, 1G) ZZ I/O Type Pin Description Power supply Power supply inputs to the core of the device. I/O power supply Ground – – Power supply for the I/O circuitry. Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M, 576M and 1G densities. InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with asynchronous data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. ZZ pin has an internal pull down. Functional Overview The CY7C1370D and CY7C1372D are synchronous-pipelined burst NoBL SRAMs designed specifically to eliminate wait states during write/read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Accesses can be initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If clock enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the write enable (WE). BWX can be used to conduct byte write operations. Write operations are qualified by the write enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, (3) the write enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to Document Number: 38-05555 Rev. *L drive out the requested data. During the second clock, a subsequent operation (read/write/deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tristate following the next clock rise. Burst Read Accesses The CY7C1370D and CY7C1372D have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Accesses section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the address register. The write signals are latched into the control logic block. On the subsequent clock rise the data lines are automatically tristated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for CY7C1372D). In addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370D & DQa,b/DQPa,b for CY7C1372D) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. Page 8 of 33 [+] Feedback CY7C1370D, CY7C1372D Sleep Mode The data written during the write operation is controlled by BW (BWa,b,c,d for CY7C1370D and BWa,b for CY7C1372D) signals. The CY7C1370D/CY7C1372D provides byte write capability that is described in the Write Cycle Description table. Asserting the write enable input (WE) with the selected byte write select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) Because the CY7C1370D and CY7C1372D are common I/O devices, data should not be driven into the device while the outputs are active. The output enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for CY7C1372D) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for CY7C1372D) are automatically tristated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1370D/CY7C1372D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Accesses section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1370D and BWa,b for CY7C1372D) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. First Address Second Address Third Address Fourth Address A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address Second Address Third Address Fourth Address A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ VDD 0.2 V – 80 mA tZZS Device operation to ZZ ZZ VDD 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ 0.2 V 2tCYC – ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 38-05555 Rev. *L Page 9 of 33 [+] Feedback CY7C1370D, CY7C1372D Truth Table The Truth Table for CY7C1370D and CY7C1372D follows. [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ Deselect cycle None H L L X X X L L–H Tri-state Continue deselect cycle None X L H X X X L L–H Tri-state Read cycle (begin burst) External L L L H X L L L–H Data out (Q) Read cycle (continue burst) Next X L H X X L L L–H Data out (Q) NOP/dummy read (begin burst) External L L L H X H L L–H Tri-state Dummy read (continue burst) Next X L H X X H L L–H Tri-state Write cycle (begin burst) External L L L L L X L L–H Data in (D) Write cycle (continue burst) Next X L H X L X L L–H Data in (D) NOP/write abort (begin burst) None L L L L H X L L–H Tri-state Write abort (continue burst) Next X L H X H X L L–H Tri-state Ignore clock edge (stall) Current X L X X X X H L–H – Sleep mode None X H X X X X X X Tri-state Notes 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tristated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Three-state when OE is inactive or when the device is deselected, and DQs = data when OE is active. Document Number: 38-05555 Rev. *L Page 10 of 33 [+] Feedback CY7C1370D, CY7C1372D Partial Write Cycle Description The Partial Write Cycle Description follows. [8, 9, 10, 11] WE BWd BWc BWb BWa Read Function (CY7C1370D) H X X X X Write – No bytes written L H H H H Write Byte a – (DQa and DQPa) L H H H L Write Byte b – (DQb and DQPb) L H H L H Write Bytes b, a L H H L L Write Byte c – (DQc and DQPc) L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQd and DQPd) L L H H H Write Bytes d, a L L H H L Write Bytes d, b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L L WE BWb BWa Read Function (CY7C1372D) H X X Write – No Bytes Written L H H Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L Notes 8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 9. Write is defined by WE and BWX. See Write Cycle Description table for details. 10. When a write cycle is detected, all I/Os are tristated, even during byte writes. 11. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document Number: 38-05555 Rev. *L Page 11 of 33 [+] Feedback CY7C1370D, CY7C1372D IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Registers The CY7C1370D/CY7C1372D incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. The CY7C1370D/CY7C1372D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High Z state. Document Number: 38-05555 Rev. *L Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 14. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Page 12 of 33 [+] Feedback CY7C1370D, CY7C1372D Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. EXTEST Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold Document Number: 38-05555 Rev. *L The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tristate IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #85 (for 119-ball BGA package) or bit #89 (for 165-ball FBGA package). When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 13 of 33 [+] Feedback CY7C1370D, CY7C1372D TAP Controller State Diagram 1 TAP Controller Block Diagram TEST-LOGIC RESET 0 Bypass Register 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 1 0 1 1 SELECT IR-SCAN 2 1 0 0 1 CAPTURE-DR TDI Selection Circuitry CAPTURE-IR 0 0 Identification Register SHIFT-IR 1 0 x . . . . . 2 1 0 1 EXIT1-DR 1 Boundary Scan Register 1 EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 TCK 1 0 1 0 EXIT2-DR TAP CONTROLLER TM S EXIT2-IR 1 1 UPDATE-DR 1 TDO 31 30 29 . . . 2 1 0 0 SHIFT-DR Selection Circuitry Instruction Register UPDATE-IR 1 0 0 TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document Number: 38-05555 Rev. *L UNDEFINED Page 14 of 33 [+] Feedback CY7C1370D, CY7C1372D TAP AC Switching Characteristics Over the Operating Range Parameter [12, 13] Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Description Min Max Unit TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time 50 – 20 20 – 20 – – ns MHz ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid – 0 10 – ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 – – – ns ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 – – – ns ns ns Notes 12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 38-05555 Rev. *L Page 15 of 33 [+] Feedback CY7C1370D, CY7C1372D 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input pulse levels ............................................... VSS to 2.5 V Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ....................................... 1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter[14] VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Test Conditions Min Max Unit IOH = –4.0 mA, VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V IOH = –100 µA VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V IOL = 8.0 mA, VDDQ = 3.3 V – 0.4 V IOL = 8.0 mA, VDDQ = 2.5 V – 0.4 V IOL = 100 µA VDDQ = 3.3 V – 0.2 V VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.5 0.7 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Note 14. All voltages referenced to VSS (GND) Document Number: 38-05555 Rev. *L Page 16 of 33 [+] Feedback CY7C1370D, CY7C1372D Identification Register Definitions Instruction Field CY7C1372D CY7C1370D 000 000 Revision Number (31:29) Cypress Device ID (28:12)[15] Description Reserved for version number. 01011001000100101 01011001000010101 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. Reserved for future use. ID Register Presence (0) 1 1 Indicate the presence of an ID register. Scan Register Sizes Register Name Instruction Bit Size (× 18) Bit Size (× 36) 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 85 85 Boundary Scan Order (165-ball FBGA package) 89 89 Identification Codes Code Description EXTEST Instruction 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 15. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 38-05555 Rev. *L Page 17 of 33 [+] Feedback CY7C1370D, CY7C1372D Boundary Scan Order 119-ball BGA [13, 14] Bit # Ball ID 1 H4 2 T4 3 T5 4 Bit # Ball ID Bit # Ball ID Bit # Ball ID 23 F6 45 G4 67 L1 24 E7 46 A4 68 M2 25 D7 47 G3 69 N1 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 E6 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83 N4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 A5 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K Notes 13. Balls which are NC (No Connect) are pre-set LOW. 14. Bit# 85 is pre-set HIGH. Document Number: 38-05555 Rev. *L Page 18 of 33 [+] Feedback CY7C1370D, CY7C1372D Boundary Scan Order 165-ball BGA [15, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 2 N7 32 D10 61 G1 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 89 Internal 29 F10 59 E1 30 E10 60 F1 Notes 15. Balls which are NC (No Connect) are pre-set LOW. 16. Bit# 89 is preset HIGH. Document Number: 38-05555 Rev. *L Page 19 of 33 [+] Feedback CY7C1370D, CY7C1372D Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD Neutron Soft Error Immunity Parameter Description Latch up Current ................................................... > 200 mA Unit Logical Single-Bit Upsets 25 °C 361 394 FIT/ Mb LMBU Logical Multi-Bit Upsets 25 °C 0 0.01 FIT/ Mb Single Event Latch up 85 °C 0 0.1 FIT/ Dev SEL Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001V Max* LSBU DC to Outputs in Tristate ..................–0.5 V to VDDQ + 0.5 V DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Test Conditions Typ * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Operating Range Range Ambient Temperature Commercial 0 °C to +70 °C Industrial –40 °C to +85 °C VDD VDDQ 3.3 V – 5% / +10% 2.5 V – 5% to VDD Electrical Characteristics Over the Operating Range Parameter[17, 18] Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL IX Min Max Unit 3.135 3.6 V for 3.3 V I/O 3.135 VDD V for 2.5 V I/O 2.375 2.625 V for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V for 3.3 V I/O, IOL = 8.0 mA – 0.4 V for 2.5 V I/O, IOL = 1.0 mA – 0.4 V for 3.3 V I/O 2.0 VDD + 0.3 V V for 2.5 V I/O 1.7 VDD + 0.3 V V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O –0.3 0.7 V Input Leakage Current except ZZ GND VI VDDQ and MODE –5 5 A Input Current of MODE Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Input = VDD – 30 A GND VI VDDQ, Output Disabled –5 5 A Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[17] Voltage[17] Input Current of ZZ IOZ Test Conditions Output Leakage Current Notes 17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 18. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ <VDD. Document Number: 38-05555 Rev. *L Page 20 of 33 [+] Feedback CY7C1370D, CY7C1372D Electrical Characteristics (continued) Over the Operating Range Parameter[17, 18] Min Max Unit 4-ns cycle, 250 MHz – 350 mA 5-ns cycle, 200 MHz – 300 mA 6-ns cycle, 167 MHz – 275 mA Automatic CE Power-down Current—TTL Inputs Max. VDD, 4-ns cycle, 250 MHz Device Deselected, VIN VIH or VIN VIL, 5-ns cycle, 200 MHz f = fMAX = 1/tCYC 6-ns cycle, 167 MHz – 160 mA – 150 mA – 140 mA ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VDD, All speed grades Device Deselected, VIN 0.3 V or VIN > VDDQ 0.3 V, f = 0 – 70 mA ISB3 Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected, VIN 0.3 V or VIN > VDDQ 0.3 V, f = fMAX = 1/tCYC 4-ns cycle, 250 MHz – 135 mA 5-ns cycle, 200 MHz – 130 mA 6-ns cycle, 167 MHz – 125 mA – 80 mA IDD Description VDD Operating Supply ISB1 ISB4 Automatic CE Power-down Current—TTL Inputs Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, All speed grades Device Deselected, VIN VIH or VIN VIL, f=0 Capacitance Parameter[19] Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3 V. VDDQ = 2.5 V 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Max Max Max 5 8 9 pF 5 8 9 pF 5 8 9 pF Thermal Resistance Parameter[19] Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Package Package Package 28.66 23.8 20.7 C/W 4.08 6.2 4.0 C/W Note 19. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05555 Rev. *L Page 21 of 33 [+] Feedback CY7C1370D, CY7C1372D AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms 3.3V I/O Test Load R = 317 3.3V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VT = 1.5V INCLUDING JIG AND SCOPE (a) ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) (b) 2.5V I/O Test Load R = 1667 2.5V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 1538 VT = 1.25V (a) Document Number: 38-05555 Rev. *L ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% 1 ns 1 ns (c) Page 22 of 33 [+] Feedback CY7C1370D, CY7C1372D Switching Characteristics Over the Operating Range Parameter [20, 21] tPower[22] Description VCC (typical) to the first access read or write -250 -200 -167 Unit Min Max Min Max Min Max 1 – 1 – 1 – ms 4.0 – 5 – 6 – ns Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency – 250 – 200 – 167 MHz tCH Clock HIGH 1.7 – 2.0 – 2.2 – ns tCL Clock LOW 1.7 – 2.0 – 2.2 – ns Output Times tCO Data Output Valid After CLK Rise – 2.6 – 3.0 – 3.4 ns tEOV OE LOW to Output Valid – 2.6 – 3.0 – 3.4 ns tDOH Data Output Hold After CLK Rise 1.0 – 1.3 – 1.3 – ns Clock to High Z[23, 24, 25] – 2.6 – 3.0 – 3.4 ns tCLZ Clock to Low Z[23, 24, 25] 1.0 – 1.3 – 1.3 – ns tEOHZ OE HIGH to Output High Z[23, 24, 25] – 2.6 – 3.0 – 3.4 ns 0 – 0 – 0 – ns tCHZ tEOLZ OE LOW to Output Low Z[23, 24, 25] Setup Times tAS Address Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tDS Data Input Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tCENS CEN Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tWES WE, BWx Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tALS ADV/LD Setup Before CLK Rise 1.2 – 1.4 – 1.5 – ns tCES Chip Select Setup 1.2 – 1.4 – 1.5 – ns tAH Address Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tDH Data Input Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tCENH CEN Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tWEH WE, BWx Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns tALH ADV/LD Hold after CLK Rise 0.3 – 0.4 – 0.5 – ns tCEH Chip Select Hold After CLK Rise 0.3 – 0.4 – 0.5 – ns Hold Times Notes 20. Timing reference is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 21. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted. 22. This part has a voltage regulator internally; tPower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated. 23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 4 on page 22. Transition is measured ± 200 mV from steady-state voltage. 24. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 25. This parameter is sampled and not 100% tested. Document Number: 38-05555 Rev. *L Page 23 of 33 [+] Feedback CY7C1370D, CY7C1372D Switching Waveforms Figure 5. Read/Write/Timing [26, 27, 28] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 10 CLK t CENS t CENH t CES t CEH t CH t CL CEN CE ADV/LD WE BW x A1 ADDRESS A2 A7 t CO t AS t DS t AH Data In-Out (DQ) t DH D(A1) t CLZ D(A2) D(A2+1) t DOH Q(A3) t OEV Q(A4) t CHZ Q(A4+1) D(A5) Q(A6) t OEHZ t DOH t OELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) DON’T CARE READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes 26. For this waveform ZZ is tied LOW. 27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional. Document Number: 38-05555 Rev. *L Page 24 of 33 [+] Feedback CY7C1370D, CY7C1372D Switching Waveforms (continued) Figure 6. NOP,STALL, and DESELECT Cycles [29, 30, 31] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A5 t CHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Figure 7. ZZ Mode Timing [32, 33] CLK t ZZ ZZ I t t ZZREC ZZI SUPPLY I DDZZ t RZZI A LL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 29. For this waveform ZZ is tied LOW. 30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 31. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 33. I/Os are in High Z when exiting ZZ sleep mode. Document Number: 38-05555 Rev. *L Page 25 of 33 [+] Feedback CY7C1370D, CY7C1372D Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 167 Package Diagram Ordering Code CY7C1370D-167AXC Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Operating Range Commercial CY7C1372D-167AXC CY7C1370D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free CY7C1370D-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Industrial 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial CY7C1372D-167AXI 200 CY7C1370D-200AXC CY7C1372D-200AXC CY7C1370D-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 × 15 × 1.4 mm) CY7C1370D-200BZI 250 Industrial CY7C1370D-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1370D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial Ordering Code Definitions CY 7 C 13XX D - XXX XX X X Temperature Range: X = C or I C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C X = Pb-free; X Absent = Leaded XX = A or BZ A = 100-pin TQFP BZ = 165-ball FBGA Speed Grade: XXX = 167 MHz / 200 MHz / 250 MHz Process Technology 90 nm 13XX = 1370 or 1372 1370 = PL, 512 Kb × 36 (18 Mb) 1372 = PL, 1 Mb × 18 (18 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05555 Rev. *L Page 26 of 33 [+] Feedback CY7C1370D, CY7C1372D Package Diagrams Figure 10: 100-pin TQFP (14 × 20 × 1.4 mm) A100RA, 51-85050 51-85050 *D Document Number: 38-05555 Rev. *L Page 27 of 33 [+] Feedback CY7C1370D, CY7C1372D Package Diagrams (continued) Figure 8. 119-ball PBGA (14 × 22 × 2.4 mm) BG119, 51-85115 51-85115 *C Document Number: 38-05555 Rev. *L Page 28 of 33 [+] Feedback CY7C1370D, CY7C1372D Package Diagrams (continued) Figure 9. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter), 51-85180 51-85180 *C Document Number: 38-05555 Rev. *L Page 29 of 33 [+] Feedback CY7C1370D, CY7C1372D Acronyms Acronym Document Conventions Description Units of Measure BGA ball grid array CE chip enable °C degree Celsius CEN clock enable k kilo ohms CMOS complementary metal oxide semiconductor MHz Mega Hertz FBGA fine-pitch ball grid array µA micro Amperes I/O input/output µs micro seconds JTAG Joint Test Action Group mA milli Amperes LMBU logical multi-bit upsets mV milli Volts LSB least significant bit mm milli meter LSBU logical single-bit upsets ms milli seconds MSB most significant bit ns nano seconds NoBL No Bus Latency ohms OE output enable % percent SEL single event latch-up pF pico Farad SRAM static random access memory ps pico seconds TAP test access port V Volts TCK test clock W Watts TMS test mode select TDI test data-in TDO test data-out TQFP thin quad flat pack TTL transistor-transistor logic WE write enable Document Number: 38-05555 Rev. *L Symbol Unit of Measure Page 30 of 33 [+] Feedback CY7C1370D, CY7C1372D Document History Page Document Title: CY7C1370D/CY7C1372D, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05555 REV. ECN No. Submission Date Orig. of Change ** 254509 See ECN RKF New data sheet *A 276690 See ECN VBL Changed TQFP pkg to Lead-free TQFP in Ordering Information section Added comment of Lead-free BG and BZ packages availability *B 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.1 Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA Packages *C 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed JA and JC for TQFP Package from 31 and 6 C/W to 28.66 and 4.08 C/W respectively Changed JA and JC for BGA Package from 45 and 7 C/W to 23.8 and 6.2 C/W respectively Changed JA and JC for FBGA Package from 46 and 3 C/W to 20.7 and 4.0 C/W respectively Modified VOL, VOH test conditions Removed shading from AC/DC Table and Selection Guide Removed comment of ‘Lead-free BG packages availability’ below the Ordering Information Updated Ordering Information Table Changed from Preliminary to final *D 370734 See ECN PCI Modified test condition in note# 17 from VDDQ < VDD to VDDQ VDD *E 416321 See ECN NXR Converted from preliminary to final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Changed three-state to tri-state Changed the IX current values of MODE on page # 18 from –5 A and 30 A to –30 A and 5 A Changed the IX current values of ZZ on page # 18 from –30 A and 5 A to –5 A and 30 A Changed VIH < VDD to VIH < VDDon page # 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table *F 475677 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. *G 2756940 08/27/2009 VKN Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. *H 2896585 03/21/2010 NJY Removed obsolete parts from Ordering Information table. Updated package diagram, data sheet template, and Sales, Solutions, and Legal Information section. *I 2906603 04/07/2010 NJY Removed inactive part from Ordering Information table. *J 3055192 10/11/2010 NJY Updated Ordering Information and added Ordering Code Definitions. Document Number: 38-05555 Rev. *L Description of Change Page 31 of 33 [+] Feedback CY7C1370D, CY7C1372D Document History Page (continued) Document Title: CY7C1370D/CY7C1372D, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05555 ECN No. Submission Date *K 3067198 10/20/2010 NJY Updated Ordering Information. *L 3306791 07/08/2011 OSN Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. REV. Document Number: 38-05555 Rev. *L Orig. of Change Description of Change Page 32 of 33 [+] Feedback CY7C1370D, CY7C1372D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05555 Rev. *L Revised July 8, 2011 Page 33 of 33 ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback