Micrel B25 Flexible ultra-low jitter clock synthesizer Datasheet

SM803020
Flexible Ultra-Low Jitter Clock Synthesizer
General Description
Features
The SM803020 is a dual-PLL clock generator that
achieves ultra-low, 74.2fs_rms output jitter at 156.25MHz
output frequency. It accepts a crystal input or a reference
input.
• Generates twelve 156.25MHz outputs
• Independently programmable output logic:
− Output logic: LVPECL (default), LVDS, HCSL,
LVCMOS
• 74.2fs jitter at 156.25MHz (1.875MHz to 20MHz)
• Selectable inputs require 39.0625MHz input frequency
− XTAL (default)
− Differential or single-ended reference clock (SPI
selectable)
• 2.5V or 3.3V operating power supply
• Separate output power supplies:
− Different banks can be at different levels
• Industrial temperature range (–40°C to +85°C)
• Green, RoHS, and PFOS compliant
• Available in 84-pin 7mm × 7mm QFN package
Each output channel is individually configurable to a
differential PECL, LVDS, HCSL, or CMOS output logic
level. PECL is selected by default, but can be overridden
through SPI. It is packaged in a dual-row 84-pin
7mm x 7mm package.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Typical Application
Applications
• 1/10/40/100 Gigabit Ethernet
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 22, 2013
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SM803020
Ordering Information
Part Number
Marking
Shipping
Ambient Temperature Range
Package
SM803020UMY
803020
Tray
–40°C to +85°C
84-Pin QFN
SM803020UMYR
803020
Tape and Reel
–40°C to +85°C
84-Pin QFN
Pin Configuration
84-Pin QFN 7mm x 7mm
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SM803020
Pin Description
Pin Number
Pin Name
Pin Type
Pin Level
Pin Function
A19, A20
A17, A18
A15, A16
A13, A14
A10, A11
A8, A9
A36, A37
A38, A39
A40, A41
A42, A43
A1, A2
A3, A4
QA1, /QA1
QA2, /QA2
QA3, /QA3
QB1, /QB1
QB2, /QB2
QB3, /QB3
QC1, /QC1
QC2, /QC2
QC3, /QC3
QD1, /QD1
QD2, /QD2
QD3, /QD3
O, (DIF/SE)
LVPECL
Differential LVPECL (default), HCSL, or LVDS Clock
Outputs or Phase-Adjustable Differential or Single-Ended
CMOS Outputs
B12
B11
B40
A44
FSEL_A
FSEL_B
FSEL_C
FSEL_D
I, (SE)
LVCMOS
Frequency Select, 75kΩ pull-up
1 = Primary Selection
0 = Secondary Selection
A21, A35
VDD
PWR
Power Supply
B18
B17
VDDOA1
VDDOA2
VDDOA3
PWR
Power Supply for Outputs QA1−3
B8
B9
VDDOB1
VDDOB2
VDDOB3
PWR
Power Supply for Outputs QB1−3
B33
B37
VDDOC1
VDDOC2
VDDOC3
PWR
Power Supply for Outputs QC1−3
B2
B3
VDDOD1
VDDOD2
VDDOD3
PWR
Power Supply for Outputs QD1−3
B20
VDDAP1
PWR
Power Supply for PLL1
B31
VDDAP2
PWR
Power Supply for PLL2
A27, B25
VDDI1
PWR
A28
VDDI2
PWR
Power Supply for XO, Reference2, Feedback 2
B30
B36
VSS
(Exposed Pad)
PWR
Core Power Supply Ground. The exposed pad must be
connected to the VSS ground plane.
B15
B16
VSSOA1
VSSOA2
VSSOA3
PWR
Power Supply Ground for Outputs QA1−3
B10
B13
VSSOB1
VSSOB2
VSSOB3
PWR
Power Supply Ground for Outputs QB1−3
July 22, 2013
3.3V only
3
Power Supply for VCXO, Reference1, Feedback 1
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SM803020
Pin Number
Pin Name
Pin Type
B34
B35
VSSOC1
VSSOC2
VSSOC3
PWR
Power Supply Ground for Outputs QC1−3
B4
B39
VSSOD1
VSSOD2
VSSOD3
PWR
Power Supply Ground for Outputs QD1−3
A34
VSSAP1
PWR
Power Supply Ground for PLL1
A22
VSSAP2
PWR
Power Supply Ground for PLL2
A23
VSSI1
PWR
Power Supply Ground for VCXO, Reference1, Feedback 1
A31
VSSI2
PWR
Power Supply Ground for XO, Reference2, Feedback 2
B14
OEA1/2/3
I, (SE)
LVCMOS
Output Enable, Outputs Q0–Q3 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ pull-up
A12
OEB1/2/3
I, (SE)
LVCMOS
Output Enable, Outputs Q4–Q7 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ pull-up
B38
OEC1/2/3
I, (SE)
LVCMOS
Output Enable, Outputs Q4–Q7 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ pull-up
B1
OED1/2/3
I, (SE)
LVCMOS
Output Enable, Outputs Q4–Q7 disable to tri-state,
0 = Disabled, 1 = Enabled, 75kΩ pull-up
A5, A6, A7,
B5, B6, B7
TEST
-
-
A32
A33
REFOUT_P,
REFOUT_N
I, (Diff/SE)
LVPECL
LVDS
HCSL
LVCMOS
I, (Diff/SE)
LVPECL
LVDS
HCSL
LVCMOS
I, (Diff/SE)
LVPECL
LVDS
HCSL
LVCMOS
Reference Clock Input2
I, (Diff/SE)
LVPECL
LVDS
HCSL
LVCMOS
Feedback Clock Input1
Feedback Clock Input2
B21
B22
B28
B29
B23
B24
REF1_P, REF1_N
REF2_P, REF2_N
FB1_P, FB1_N
Pin Level
Pin Function
Factory Test pins. Do not connect anything to these pins.
Reference Clock Output
Reference Clock Input 1
B26
B27
FB2_P, FB2_N
I, (Diff/SE)
LVPECL
LVDS
HCSL
LVCMOS
A29
XTAL_IN
I, (SE)
12pF crystal
Crystal Reference Input, no load caps needed
(See Figure 9.)
A30
XTAL_OUT
O, (SE)
12pF crystal
Crystal Reference Output, no load caps needed
(See Figure 9.)
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SM803020
Pin Number
Pin Name
Pin Type
Pin Level
Pin Function
B19, B32
NC
A25
VCXO_OUT
O, SE
VCXO output, 8 to 10pF, programmable
A26
VCXO_IN
I, SE
VCXO input, 8 to 10pF, programmable
A24
VC
I
Control voltage for VCXO, positive slope
Truth Tables
PLL_BYPASS
XTAL_SEL
OEA
OEB
OEC
OED
Input
Output
0
−
1
1
1
1
−
PLL
1
−
1
1
1
1
−
XTAL/REF_IN
−
0
1
1
1
1
REF_IN
−
−
1
1
1
1
1
XTAL
−
−
−
0
1
1
1
−
QA Tri-state
−
−
1
0
1
1
−
QB Tri-state
−
−
1
1
0
1
−
QC Tri-state
−
−
1
1
1
0
−
QD Tri-state
FSEL
Output Frequency (MHz)
1
Primary
0
Secondary
Output Logic Programming
Available output logic types are LVPECL (default), LVDS,
HCSL and LVCMOS.
Each output can be programmed individually to any of the
four logic types through SPI.
Unused outputs can be disabled to high impedance.
All logic types are differential except LVCMOS. LVCMOS
signals are single ended coming out of the Qx pins. During
LVCMOS operation the /Qx pins are disabled.
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SM803020
Absolute Maximum Ratings(2)
Operating Ratings(3)
Supply Voltage (VDD, VDDA, VDDI, VDDO) ........................ +4.6V
Input Voltage (VIN) ........................................ −0.5V to +4.6V
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts)......................... −65°C to +150°C
ESD Machine Model .................................................... 200V
ESD Human Body Model ........................................... 2000V
Supply Voltage (VDD, VDDO) ................... +2.375V to +3.465V
Ambient Operating Temperature (TA) ......... –40°C to +85°C
Maximum Allowable Junction Temp .......................... 125°C
Junction Thermal Resistance
84-pin QFN 7mm x 7mm θJA Still Air ................. 24°C/W
Electrical Characteristics
Typical values are TA = 25°C, min/max across –40°C ≤ TA ≤ +85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
VDD, VDDO
Supply Voltage
VDDI_1
2.5V Operation
2.375
2.5
2.625
3.3V Operation
3.135
3.3
3.465
Analog Supply Voltage
Note 3
3.135
3.3
3.465
V
VDDI_2
Analog Supply Voltage
Note 3
2.375
3.465
V
VDDA
PLL Core Voltage
2.375
3.465
V
IDDA
PLL Core Current Consumption
60
mA
IDD
Current Consumption
8
mA
0
mA
2
mA
4
mA
2
mA
IDDI_1
Per active PLL
Input 1 Supply Current
XO Input
(3)
Ref Input
IDDI_2
Input 2 Supply Current
XO Input
(3)
Ref Input
Units
V
LVPECL DC Electrical Characteristics
VDDCore = VDD = VDD0 = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. RL = 50Ω to VDDO − 2V
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VOH
Output High Voltage
50Ω to VDDO − 2V
VDDO –1.35
VDDO – 1.01
VDDO – 0.8
V
VOL
Output Low Voltage
50Ω to VDDO − 2V
VDDO –2
VDDO – 1.78
VDDO –1.6
V
VSWING
Peak-to-Peak Output Voltage
Figure 2
0.65
0.77
0.95
V
LVDS DC Electrical Characteristics
VDDCore = VDD = VDD0 = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. RL = 100Ω between Q and /Q.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VOD
Differential Output Voltage
Figure 2
245
350
454
mV
VCM
Common Mode Voltage
1.125
1.2
1.375
V
VOH
Output High Voltage
1.248
1.375
1.602
V
VOL
Output Low Voltage
0.898
1.025
1.252
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. The datasheet limits are not guaranteed if the device exceeds the operating ratings.
3. Crystal input is powered from VDDI_2 analog supply voltage source.
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SM803020
HCSL DC Electrical Characteristics
VDDCore = VDD = VDD0 = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. RL = 50Ω to VSS.
Symbol
Parameter
VOH
Condition
Min.
Typ.
Max.
Units
Output High Voltage
600
700
850
mV
VOL
Output Low Voltage
−150
0
27
mV
VCROSS
Crossing Point Voltage
0.350
V
REF_IN DC Electrical Characteristics
VDD = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C.
Symbol
Parameter
VCMR
Input Common Mode Voltage
VSWING
Input Voltage Swing
Condition
Min.
Typ.
0.3
Peak to Peak, each side of the Diff Input
Max.
Units
VDD − 0.3
V
0.2
VPP
Crystal Characteristics
Parameter
Condition
Min.
Mode of Oscillation
12pF Load Typical
Frequency
Typ.
Max.
Units
Fundamental, Parallel Resonant
39.0625
Equivalent Series Resistance (ESR)
MHz
60
Ω
Load Capacitance, CL
12
Shunt Capacitor, C0
2
4
pF
Correlation Drive Level
10
100
µW
July 22, 2013
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pF
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SM803020
AC Electrical Characteristics
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%
TA = −40°C to +85°C
Symbol
Parameter
FIN
Input Frequency
FOUT
Output Frequency
TR/TF
Condition
LVPECL, LVDS, HCSL, LVCMOS
Output Rise/Fall Time
20% – 80%
ODC
Output Duty Cycle
Tpd
Input to Output Propagation Delay
(4)
TSKEW
Output-to-Output Skew
TLOCK
PLL Lock Time
Tjit(∅)
Min.
Typ.
RMS Phase Jitter
Units
39.0625
MHz
156.25
MHz
LVPECL output
85
135
350
ps
LVDS output
85
140
300
ps
HCSL output
175
340
700
ps
LVCMOS output
100
200
400
ps
45
50
55
%
100
ps
ZDB mode
−100
Synthesizer/Bypass mode
4
Note 5, same output bank
5
(6)
Max.
Integration range (12kHz to 20MHz)
180
ns
50
ps
20
ms
fs
Notes:
4. Defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differential crossing points.
5. Output-to-output skew is only defined for outputs in the same PLL bank [A:B, C:D] with the same output type setting.
6. All phase noise measurements were taken with an Agilent 5052B phase noise system.
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SM803020
Phase Noise Performance
156.25MHz, integration range 1.875MHz to 20MHz: 74.2fs rms
156.25MHz, integration range 12kHz to 20MHz: 182.4fs rms
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SM803020
Application Information
Input Reference
When operating with a crystal input reference, do not apply
a switching signal to a REF_IN.
Crystal Layout
Keep the layers under the crystal as open as possible and
do not place switching signals or noisy supplies under the
crystal.
Crystal load capacitance is built inside the die so no
external capacitance is needed. See the Selecting a
Quartz Crystal for the Clockworks Flex I Family of
Precision Synthesizers application note for more details.
Figure 2. Duty Cycle Timing
Contact Micrel’s HBW applications group if you need help
selecting a suitable crystal for your application at:
[email protected]
Figure 3. All Outputs Rise/Fall Time
Power Supply Filtering Recommendations
Figure 1. Recommended Power Supply Filtering
•
Use the power supply filtering shown in Figure 1 for
VDDAP1, VDDAP2, VDDI1 and VDDI2.
•
Connect the VDDO and VDD pins directly to the VDD
power plane.
•
Connect all VSS pins directly to the ground power
plane.
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SM803020
Figure 4. RMS Phase/Noise Jitter
Figure 5. LVPECL Output Load and Test Circuit
Figure 6. HCSL Output Load and Test Circuit
Figure 7. LVDS Output Load and Test Circuit
Figure 8. LVCMOS Output Load and Test Circuit
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SM803020
Figure 9. Crystal Input Interface
AC-Coupled Signal Interfacing
LVDS
PECL
LVDS: V source = 1.25V
Thevenin Equivalent Conventional Termination
Micrel Any-In Internal Termination
Micrel Any-In Internal Termination
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SM803020
DC-Coupled Signal Interfacing
PECL
LVDS
Conventional Method
Parallel Termination (Thevenin Equivalent)
Micrel Any-In Internal Termination
Notes:
7. Power-saving alternative to Thevenin termination.
8. Place termination resistors as close to destination inputs as possible.
9. Rb resistor set the DC bias voltage, equal to VT.
10. For 2.5V systems, Rb = 19Ω. For 3.3V systems, Rb = 50Ω.
Parallel Termination (3-Resistor)
“Y-Termination”
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SM803020
Package Information(11)
84-Pin QFN 7mm x 7mm
Note:
11. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
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