Anpec APA2607QBI-TRG 6w stereo class-d audio power amplifier Datasheet

APA2607
6W Stereo Class-D Audio Power Amplifier
Features
General Description
•
•
Operating Voltage: 8.0V-16.5V
High Efficiency 90% at P O = 6W, 8Ω Speaker,
The APA2607 is a stereo, high efficiency, Class-D audio
amplifier available in a TQFN5x5-32 package.
•
VDD = 12V
Low Shutdown Current
The filter-free Class-D architecture eliminates the external low pass filters and saves the PCB space and BOM
- IDD=5µA at VDD=16.5V
Power Limit Function
costs. The APA2607 also has spread clock function that
reduces the high frequency radiation and low the EMI
Switchable Non-Clip Function/DRC (Dynamic Range
Control) Function
noise. The Zero-crossing-change function changes the
gain when both output (VOUTP and VOUTN) crossing together
Build-in Oscillator
Spread Clock Function
can minimum the pop noise. The power limit function
can protect the speaker when output signal excesses
External Synchronization Function
Master/Slaver Synchronization Function
the speaker limit rating. The non-clip and DRC functions
eliminate the distortion at large input signal and can fit
DC Detection Function
Stereo/Monaural Function
the high dynamic input signal to a small dynamic speaker.
The operating voltage is from 8V to 16.5V. The APA2607
Shutdown and Mute Function
Thermal and Over-Current Protections with Auto-
is capable of driving 6W at 12V into 8Ω speaker and provides thermal and over-current protections. The APA2607
Recovery
Space Saving Package TQFN5x5-32
also can detect the DC that prevents the speaker voice
coil being destroyed.
•
•
•
•
•
•
•
•
•
•
•
•
Lead Free and Green Devices Available
(RoHS Compliant)
Efficiency vs. Output Power (8Ω)
100
Applications
90
80
LCD TVs
70
Efficiency (%)
•
Simplified Application Circuit
60
50
40
30
Left
Channel
Input
LINP
LINN
LOUTP
LOUTN
Left
Channel
Speaker
10
0
0
APA2607
Right
Channel
Input
RINN
RINP
ROUTN
ROUTP
VDD=12V
RL=8Ω+33µH
fin=1kHz
AUX-0025
AES-17(20kHz)
20
1
2
3 4 5 6 7
Output Power (W)
8
9 10
Right
Channel
Speaker
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
1
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APA2607
25 GAIN1
26 LPVDD
27 LOUTN
28 LOUTN
29 LPGND
30 LOUTP
31 LOUTP
32 LPVDD
Pin Configuration
AVDD 1
24 GAIN0
3V3REG 2
23 DRC1
LINP 3
22 DRC0
LINN 4
21 OSCIN
APA2607
VREF 5
20 OSCO
RINN 6
19 MUTE
18 PFLAG
RINP 7
AGND 8
RPVDD 16
ROUTN 15
ROUTN 14
RPGND 13
ROUTP 12
ROUTP 11
PMAX 9
RPVDD 10
17 SD
TQFN5x5-32
(Top View)
Ordering and Marking Information
APA2607
Package Code
QB : TQFN5x5-32
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APA2607 QB:
APA2607
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
2
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APA2607
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
VDD
Supply Voltage (RPVDD to RPGND, LPVDD to LPGND, AVDD to AGND)
-0.3 to 20
VSD
Input Voltage (SD to AGND)
-0.3 to 20
VIN
Input Voltage (LINN, LINP, RINN and RINP to AGND)
-0.3 to 4
Input Voltage (MUTE, PMAX, DRC0, DRC1, GAIN0 and GAIN1 to AGND)
-0.3 to 4
VCONTROL
VPGND_AGND
TJ
TSTG
TSDR
PD
Input Voltage (LPGND, RPGND to AGND)
Unit
V
-0.3 to +0.3
150
ο
-65 to +150
ο
260
ο
Maximum Junction Temperature
Storage Temperature Range
Maximum Soldering Temperature Range, 10 Seconds
Power Dissipation
C
C
C
Internally Limited
W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Typical Value
Junction-to-Ambient Resistance in Free Air (Note 2)
TQFN5x5-32
Junction-to-Case Resistance in Free Air
28
o
6
o
C/W
(Note 3)
TQFN5x5-32
Unit
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TQFN5X5-32 is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TQFN5X5-32 package.
Recommended Operating Conditions (Note 4)
Symbol
Range
Parameter
VDD
Supply Voltage
VIH
High Level Threshold
Voltage
Unit
Min.
Max.
8.0
16.5
SD
2.5
16.5
MUTE, PMAX, DRC0, DRC1, GAIN0, GAIN1
2.5
3.6
SD
0
1
MUTE, PMAX, DRC0, DRC1, GAIN0, GAIN1
0
1
-
3
VIL
Low Level Threshold
Voltage
VIC
Common Mode Input Voltage
TA
Ambient Temperature Range
-40
85
TJ
Junction Temperature Range
-40
125
RL
Speaker Resistance
3.5
-
V
ο
C
Ω
Note 4: At stereo mode, if the RL=4Ω, the VDD should not excess 12V or it may trigger the Over-Current Protection.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
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APA2607
Electrical Characteristics
o
VDD=12V, GND=0V, TA=25 C (unless otherwise noted)
Symbol
Parameter
V3V3REG
APA2607
Test Conditions
IO=2mA
VVREF
Unit
Min.
Typ.
Max.
2.85
3.3
3.75
-
V3V3REG/2
V
VDET
The DC Detection Active Voltage
at Output
DC detection (>0.5s)
-
2
2.5
VFLAG
Protection Flag Output Voltage
ISOUCING=0.4mA
-
-
0.4
VOSCO
Oscillator Output Voltage
ISINKING=ISOUCING=4mA
2.2
-
-
Recovery Time from Shutdown
C5=0.1µF
-
1
1.5
-
-
0.001
-
18
36
-
2
10
TSD
TMUTE
IDD
IMUTE
ISD
II
Recovery Time from Mute
Supply Current
No Load
Mute Current
Shutdown Current
SD = 0V
-
5
100
Input Current
SD, MUTE, DRC0, DRC1, GAIN0,
GAIN1
-
-
5
FOSC
Internal Oscillator Frequency
400
500
600
FOSCI
External Clock at OSCI Pin
400
500
600
DTOSCI
Duty Cycle of External Clock
40
-
60
Static Drain-Source On-State
Resistance (P-Channel and
N-Channel Power MOSFET)
VDD=8V, IL=0.8A
-
530
-
RDSON
VDD=12V, IL=1A
-
480
-
VDD=16V, IL=1.4A
-
440
-
Ri
Input Resistor
RINN, RINP, LINN, LINP (Gain
independent)
-
10
-
RO
Output Resistor
ROUTN, ROUTP, LOUTN, LOUTP
-
300
-
η
Efficiency
Stereo, RL=8Ω, PO=6W
-
89
-
DRC [1:0] (0,0), GAIN (0,0)
-
22
-
DRC (0,0), GAIN (0,1)
-
28
-
DRC (0,0), GAIN (1,0)
-
34
-
DRC (0,0), GAIN (1,1)
-
16
-
DRC (0,1), GAIN (0,0)
-
34
-
DRC (0,1), GAIN (0,1)
-
40
-
DRC (0,1), GAIN (1,0)
-
46
-
DRC (0,1), GAIN (1,1)
-
28
-
DRC (1,0), GAIN (0,0)
-
34
-
DRC (1,0), GAIN (0,1)
-
40
-
DRC (1,0), GAIN (1,0)
-
46
-
DRC (1,0), GAIN (1,1)
-
28
-
DRC (1,1), GAIN (0,0)
-
34
-
DRC (1,1), GAIN (0,1)
-
40
-
AV
Closed-Loop Gain
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
4
VPP
s
mA
µA
kHz
%
mΩ
kΩ
%
dB
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APA2607
Electrical Characteristics (Cont.)
o
VDD=12V, GND=0V, TA=25 C (unless otherwise noted)
Symbol
AV
Parameter
Closed-Loop Gain
APA2607
Test Conditions
Unit
Min.
Typ.
Max.
DRC (1,1), GAIN (1,0)
-
46
-
DRC (1,1), GAIN (1,1)
-
28
-
dB
Stereo Mode
Symbol
Parameter
APA2607
Test Conditions
Unit
Min.
Typ.
Max.
VDD=16V, TA=25°
C
PO
Output Power
THD+N=1%
fin=1kHz
RL=8Ω
-
12
-
THD+N=10%
fin=1kHz
RL=8Ω
-
15
-
RL=8Ω, PO=6W
-
0.07
0.1
-
-70
-60
fin=100Hz
-
-65
-55
fin=1kHz
-
-65
-55
W
THD+N
Total Harmonic Distortion Pulse
Noise
fin=1kHz
Crosstalk
Channel Separation
PO=0.5W, RL=8Ω,fin=1kHz
Power Supply Rejection Ratio
RL=8Ω
PSRR
CMRR
Common Mode Rejection Ration
fin=1kHz, RL=8Ω,Vin=0.1Vpp
-
-65
-55
AttMute
Mute Attenuation
%
dB
fin=1kHz, RL=8Ω,Vin=1Vpp
-
-115
-100
Shutdown Attenuation
fin=1kHz, RL=8Ω, Vin=1Vpp
-
-115
-100
VOS
Offset Voltage
No load, A v =22dB
-
-
20
mV
Vn
Noise Output Voltage
With A-weighted Filter (Av =22dB)
-
230
500
µVrms
Attshutdown
VDD=12V, TA=25°
C
PO
THD+N
Crosstalk
PSRR
THD+N=1%
fin=1kHz
RL=4Ω
-
10
-
RL=8Ω
-
6
-
THD+N=10%
fin=1kHz
RL=4Ω
-
14
-
RL=8Ω
-
8
-
RL=4Ω, PO=7W
-
0.07
0.1
RL=8Ω, PO=4.5W
-
0.07
0.1
-
-70
-60
fin=100Hz
-
-65
-55
fin=1kHz
-
-65
-55
Output Power
Total Harmonic Distortion Pulse
Noise
fin=1kHz
Channel Separation
PO=0.5W, RL=8Ω, fin=1kHz
Power Supply Rejection Ratio
RL=8Ω
W
%
dB
CMRR
Common Mode Rejection Ration
fin=1kHz, RL=8Ω, VIN=0.1Vpp, AV=22dB
-
-65
-55
AttMute
Mute Attenuation
fin=1kHz, RL=8Ω, VIN=1Vpp
-
-115
-100
Attshutdown
Shutdown Attenuation
fin=1kHz, RL=8Ω, VIN=1Vpp
-
-115
-100
VOS
Offset Voltage
No load, A V=22dB
-
-
20
mV
Vn
Noise Output Voltage
With A-weighting Filter (AV=22dB)
-
230
500
µVrms
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
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APA2607
Electrical Characteristics (Cont.)
o
VDD=12V, GND=0V, TA=25 C (unless otherwise noted)
Stereo Mode (Cont.)
Symbol
Parameter
APA2607
Test Conditions
Unit
Min.
Typ.
Max.
VDD=8V, TA=25°
C
PO
THD+N
Crosstalk
PSRR
THD+N=1%
fin=1kHz
RL=4Ω
-
5.5
-
RL=8Ω
-
3.2
-
THD+N=10%
fin=1kHz
RL=4Ω
-
7
-
Output Power
W
RL=8Ω
-
4
-
RL=4Ω, PO=4.5W
-
0.1
0.2
RL=8Ω, PO=2.5W
-
0.1
0.2
-
-60
-60
fin=100Hz
-
-65
-55
fin=1kHz
-
-65
-55
-
-70
-55
Total Harmonic Distortion Pulse
Noise
fin=1kHz
Channel Separation
PO=0.5W, RL=8Ω, fin=1kHz
Power Supply Rejection Ratio
RL=8Ω
%
dB
CMRR
Common Mode Rejection Ration
AttMute
Mute Attenuation
fin=1kHz, RL=8Ω, VIN=1Vpp
-
-115
-100
Shutdown Attenuation
fin=1kHz, RL=8Ω, VIN=1Vpp
-
-115
-100
VOS
Offset Voltage
No load, A V=22dB
-
-
20
mV
Vn
Noise Output Voltage
With A-weighting Filter (AV=22dB)
-
200
400
µVrms
Attshutdown
fin=1kHz, RL=8Ω, VIN=0.1Vpp, AV=22dB
MONO Mode
Symbol
Parameter
APA2607
Test Conditions
Unit
Min.
Typ.
Max.
VDD=12V, TA=25°
C
PO
Output Power
THD+N=1%
fin=1kHz
RL=4Ω
-
12
-
THD+N=10%
fin=1kHz
RL=4Ω
-
14
-
RL=4Ω
PO=8W
-
0.08
0.2
fin=100Hz
-
-65
-55
fin=1kHz
W
THD+N
Total Harmonic Distortion Pulse
Noise
fin=1kHz
PSRR
Power Supply Rejection Ratio
RL=8Ω
-
-65
-55
CMRR
Common Mode Rejection
Ration
fin=1kHz, RL=8Ω, VIN=0.1Vpp,
AV=22dB
-
-60
-55
AttMute
Mute Attenuation
fin=1kHz, RL=8Ω, VIN=1Vrms
-
-115
-100
Attshutdown
%
dB
Shutdown Attenuation
fin=1kHz, RL=8Ω, VIN=1Vrms
-
-115
-100
VOS
Offset Voltage
No load, A V=22dB
-
-
20
mV
Vn
Noise Output Voltage
With A-weighting Filter (AV=22dB)
-
200
400
µVr
ms
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
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APA2607
Typical Operating Characteristics
Efficiency vs. Output Power (4Ω)
Efficiency vs. Output Power (8Ω)
100
100
90
90
80
Efficiency (%)
Efficiency (%)
70
VDD=8V
60
50
RL=4Ω+33µH
fin=1kHz
Ci=1µf
AV=22dB
THD+N≦10%
AUX-0025
AES-17(20KHz)
40
30
20
10
0
0
2
4
6
8
Output Power (W)
10
60
50
RL=8Ω+33µH
fin=1kHz
Ci=1µf
AV=22dB
THD+N≦10%
AUX-0025
AES-17(20KHz)
40
30
20
10
0
12
0
Output Power vs. Supply Voltage
4
6
8 10 12
Output Power (W)
2
14
16
Output Power vs. Supply Voltage
20
18
14
RL=8Ω
fin=1kHz
Ci=1µF
AV=22dB
AUX-0025
AES-17(20kHz)
Single Channel
THD+N=10%
15
Output Power (W)
RL=4Ω
fin=1kHz
Ci=1µF
AV=22dB
AUX-0025
AES-17(20kHz)
single channel
16
Output Power (W)
VDD=16V
80
VDD=12V
70
VDD=12V
VDD=8V
12
10
THD+N=1%
THD+N=10%
10
THD+N=1%
5
8
6
8
9
10
11
Supply Voltage (V)
0
12
8
10
12
14
Supply Voltage (V)
16
Output Power vs. Supply Voltage
THD+N vs. Output Power
(Mono Mode)
10
20
Output Power (W)
18
16
14
5
THD+N=10%
VDD=12V
1
12
THD+N=1%
10
VDD=8V
2
THD+N (%)
RL=4Ω
fin=1kHz
Ci=1µF
AV=22dB
AUX-0025
AES-17(20kHz)
Mono Mode
0.5
0.2
RL=4Ω
fin=1kHz
Ci=1µF
AV=22dB
AUX-0025
AES-17(20kHz)
single channel
0.1
0.05
8
0.02
6
8
9
10
11
Supply Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
0.01
12
2
4
6
8 10 12 14 16 18 20
Output Power (W)
7
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APA2607
Typical Operating Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Output Power
10
10
VDD=8V
VDD=12V
VDD=8V
VDD=16V
VDD=12V
RL=8Ω
fin=1kHz
Ci=1µF
AV=22dB
AUX-0025
AES-17(20kHz)
0.1
0.01
THD+N (%)
THD+N (%)
1
0
2
4
RL=4Ω
fin=1kHz
Ci=1µF
AV=22dB
AUX-0025
AES-17(20kHz)
Mono Mode
0.1
0.01
6 8 10 12 14 16 18 20 22
Output Power (W)
VDD=16V
1
0
5
THD+N (%)
THD+N (%)
VDD=12V
RL=4Ω
Ci=1µF
AUX-0025
AES-17(20kHz)
PO=10W
PO=10W A =22dB
V
PO=1W AV=34dB
A
=22dB
PO=1W
V
AV=34dB
100
1k
Frequency (Hz)
PO=1W
AV=34dB
Crosstalk (dB)
THD+N (%)
PO=11W
P =11W
AV=34dB O
PO=1W
AV=22dB
AV=34dB PO=1W
AV=22dB
0.01
0.006
1k
100
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
1k
Frequency (Hz)
10k 20k
VDD=12V
RL=4Ω
PO=1W
Ci=1µF
Av=22dB
AUX-0025
AES-17(20kHz)
-120
20
10k 20k
Left channel to Right channel
Right channel to Left channel
100
10k 20k
1k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
PO=6W
PO=1W A =34dB
V
AV=22dB
Crosstalk vs. Frequency
0.1
100
40 45
PO=6W
AV=22dB
0.006
20
10k 20k
VDD=12V
RL=4Ω
Ci=1µF
AUX-0025
AES-17(20kHz)
Mono Mode
20
30 35
0.1
THD+N vs. Frequency
1
25
VDD=12V
RL=8Ω
Ci=1µF
AUX-0025
AES-17(20kHz)
0.01
0.006
20
20
THD+N vs. Frequency
1
0.1
0.01
15
Output Power (W)
THD+N vs. Frequency
1
10
8
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APA2607
Typical Operating Characteristics (Cont.)
Crosstalk vs. Frequency
+0
-10
-40
-50
Output Noise Voltage (µV)
VDD=12V
RL=8Ω
PO=0.6W
Ci=1µF
Av=22dB
AUX-0025
AES-17(20kHz)
-20
-30
Crosstalk (dB)
Output Noise Voltage vs. Frequency
1m
-60
-70
-80
-90
Left channel to Right channel
-100
-120
20
100
1k
Frequency (Hz)
VDD=12V
RL=8Ω
Ci=1µF
AUX-0025
AES-17(20kHz)
A-Weighting
10µ
10k 20k
20
Output Noise Voltage vs. Frequency
10k 20k
+80
+34.5
AV=34dB
AV=28dB
Gain, AV=34dB
+40
AV=22dB
Gain (dB)
+29.5
100µ
AV=16dB
VDD=12V
RL=4Ω
Ci=1µF
AUX-0025
AES-17(20kHz)
A-Weighting
Mono Mode
20
100
+24.5
Phase, AV=22dB
Phase, AV=34dB
+24.5
+22
+17
+14.5
+12
20
100
VDD=12V
RL=8Ω
PO=0.6W
Ci=1µF
AUX-0025
VDD=12V
RL=4Ω
PO=1.1W
Ci=1µF
AUX-0025
Mono Mode
1k
10k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
100
-20
Gain, AV=22dB
-40
-60
1k
10k
Frequency (Hz)
-80
100k
PSRR vs. Frequency
+80
+60
+40
+20
+0
-20
-40
-60
-80
-100
-120
-140
-160
-180
100k
+0
-20
Phase (Degree)
+29.5
+0
+22
+12
20
10k 20k
-40
PSRR (dB)
Gain, AV=34dB
Gain, AV=22dB
Phase, AV=34dB
+14.5
+34.5
+19.5
+20
+27
+17
1k
Frequency (Hz)
+32
Phase, AV=22dB
+19.5
+37
+27
+60
+32
Phase (Degree)
Output Noise Voltage (µV)
1k
Frequency (Hz)
+37
Frequency Response
Gain (dB)
100
Frequency Response
1m
10µ
AV=16dB
AV=22dB
100µ
Right channel to Left channel
-110
AV=34dB
AV=28dB
-60
VDD=12V
RL=8Ω
Ci=1µF
AV=22dB
Vrr=0.2Vrms
Input AC short to
Gnd
AUX-0025
AES-17(20kHz)
-80
-100
-120
20
9
100
1k
Frequency (Hz)
10k 20k
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APA2607
Typical Operating Characteristics (Cont.)
PSRR vs. Frequency
Mute Attenuation vs. Frequency
+0
-20
PSRR (dB)
-30
-40
-50
-60
Mute Attenuation (dB)
VDD=12V
RL=4Ω
Ci=1µF
AV=22dB
Vrr=0.2Vrms
Input AC short to
Gnd
AUX-0025
AES-17(20kHz)
Mono Mode
-10
-70
-80
-90
-100
20
100
1k
Frequency (Hz)
10k 20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
20
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
20
100
10k 20k
VDD=12V
1.0
VDD=8V
0.8
RL=4Ω+33µH
fin=1kHz
Ci=1µF
AV=22dB
THD+N≦1%
AUX-0025
AES-17(20kHz)
Single Channel
0.6
0.4
Left Channel
0.2
1k
Frequency (Hz)
1
0.9
0
10k 20k
0
2
4
6
8
10
12
14
Each Channel Output Power (W)
Supply Current vs. Output Power
2.0
VDD=16V
1.8
VDD=12V
0.7
VDD=8V
0.6
0.5
RL=8Ω+33µH
fin=1kHz
Ci=1µF
AV=22dB
THD+N≦1%
AUX-0025
AES-17(20kHz)
Single Channel
0.4
0.3
0.2
0.1
0
VDD=12V
1.6
Supply Current (A)
0.8
Supply Current (A)
1k
Frequency (Hz)
1.2
Supply Current vs. Output Power
0
100
Left Channel
1.4
VDD=12V
RL=8Ω
Ci=1µF
AV=22dB
VO=2Vrms
AUX-0025
AES-17(20kHz)
Right Channel
Right Channel
Supply Current vs. Output Power
Supply Current (A)
Shutdown Attenuation (dB)
Shutdown Attenuation vs. Frequency
VDD=12V
RL=8Ω
Ci=1µF
AV=22dB
VO=2Vrms
AUX-0025
AES-17(20kHz)
2
4
6
8
10
12
Each Channel Output Power (W)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
1.4
VDD=16V
1.2
VDD=8V
1.0
0.8
0.6
0.4
0.2
0
14
0
10
5
RL=4Ω+33µH
fin=1kHz
Ci=1µF
AV=22dB
THD+N≦1%
Mono Mode
AUX-0025
AES-17(20kHz)
10
15
20
l Output Power (W)
25
30
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APA2607
Typical Operating Characteristics (Cont.)
Supply Current vs. Supply Voltage
Mute Current vs. Supply Voltage
25.0
6
No Load
No Load
5
Supply Current (mA)
Supply Current (mA)
20.0
15.0
10.0
5.0
0.0
4
3
2
1
0
2
4
6
8
0
10 12 14 16 18 20
0
2
4
6
Supply Voltage (V)
Shutdown Current vs. Supply Voltage
10
12
14
16
18
Input Voltage vs. Output Voltage
5
20
No Load
VDD=12V
V
=0.5V
10 CPMAX
i=1µF
Output Voltage (V)
4
Supply Current (µA)
8
Supply Voltage (V)
3
2
AV=46dB
AUX-0025
AES-17(20kHz)
DRC 1 Mode
DRC 2 Mode
Non-Clip Mode
1
1
0
0
2
4
6
8
10
12
14
16
200m
1m
18
10m
Input Voltage vs. Output Voltage
Input Voltage vs. Output Voltage
20
VDD=12V
DRC 2 Mode
VPMAX=1V
Ci=1µF
Non-Clip Mode
AV=46dB
AUX-0025
AES-17(20kHz)
DRC 1 Mode
DRC 2 Mode
10
Output Voltage (V)
Output Voltage (V)
10
1
10m
100m
Input Voltage (V)
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Rev. A.4 - Sep., 2011
Non-Clip Mode
DRC 1 Mode
1
0.2
0.001
200m
1m
1
Input Voltage (V)
Supply Voltage (V)
20
100m
1
VDD=12V
VPMAX=1.3V
Ci=1µF
AV=46dB
AUX-0025
AES-17(20kHz)
0.01
0.1
1
Input Voltage (V)
11
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APA2607
Pin Description
PIN
NO.
I/O/P
FUNCTION
NAME
1
AVDD
P
Power supply for control block.
2
3V3REG
O
Regulator output, 3.3V.
3
LINP
I
The positive input of left channel amplifier.
4
LINN
I
The negative input of left channel amplifier.
5
VREF
P
The reference voltage output.
6
RINN
I
The negative input of right channel amplifier.
7
RINP
I
The positive input of right channel amplifier.
8
AGND
P
Ground connection for control block.
9
PMAX
I
Input for set the power limit function.
10,16
RPVDD
P
The power supply for right channel Class-D amplifier.
11,12
ROUTP
O
The positive output of right channel Class-D amplifier.
13
RPGND
P
Ground connection for right channel Class-D amplifier.
14,15
ROUTN
O
The negative output of right channel Class-D amplifier.
17
SD
I
Shutdown mode control input, place entire IC in shutdown mode when held low.
18
PFLAG
O
Protection flag output.
19
MUTE
I
Mute mode control input; pull low to mute the Class-D amplifier’s output.
20
OSCO
O
The internal oscillator’s output, for synchronization other APA2607s.
21
OSCIN
I
External clock input.
22
DRC0
I
Non-clip and DRC (Dynamic Range Compress) control; LSB bit 0.
23
DRC1
I
Non-clip and DRC (Dynamic Range Compress) control; MSB bit 1.
24
GAIN0
I
Control pin for internal gain setting, LSB, bit0.
25
GAIN1
I
Control pin for internal gain setting, MSB, bit1.
26,32
LPVDD
P
The power supply for left channel Class-D amplifier.
27,28
LOUTN
O
The negative output of left channel Class-D amplifier.
29
LPGND
P
Ground connection for left channel Class-D amplifier.
30,31
LOUTP
O
The positive output of left channel Class-D amplifier.
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APA2607
Block Diagram
RPVDD
VINT
VINT
Gate
Drive
VINT
ROUTN
RINN
Power
Limit
RPGND
VINT
RINP
AGND
Gate
Drive
PMAX
ROUTP
RPVDD
VREF
Biases &
Reference
MUTE
VINT
Mute Control
AVDD
3V3REG
DRC0
DRC1
3.3V
Regulator
DRC/NonClip Control
Protection
Function
GAIN
Control
OSCIN
Oscillator
OSCO
GAIN0
Shutdown
Control
GAIN1
PFLAG
SD
PMAX
LPVDD
VINT
PMAX
MUTE
VINT
Gate
Drive
VINT
LOUTN
LINN
Power
Limit
LPGND
VINT
LINP
Gate
Drive
LOUTP
LPVDD
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APA2607
Typical Application Circuit
Stereo Operation
AVDD 1
22 DRC0
LINP 3
Ci2 1µF
LINN 4
CB
0.1µF
VREF 5
20 OSCO
RINN 6
19 MUTE
RINP 7
18 PFLAG
AGND 8
VDD
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Rev. A.4 - Sep., 2011
RPVDD 16
ROUTN 15
ROUTN 14
PMAX 9
CS5
1µF
RPGND 13
17 SD
R1
R2
21 OSCIN
APA2607
ROUTP 12
Ci3 1µF
23 DRC1
ROUTP 11
Ci1 1µF
Ci4 1µF
CS1
220µF
24 GAIN0
RPVDD 10
Left Channel
Input Signal
Bead
1nF
VDD
C1 1µF3V3REG 2
Left Channel
Input Signal
1nF
VDD
25 GAIN1
26 LPVDD
27 LOUTN
28 LOUTN
29 LPGND
30 LOUTP
31 LOUTP
32 LPVDD
CS2
0.1µF
CS4 VDD
1µF
Gain Setting
Bead
VDD CS3
1µF
CS6
1µF V
DD
14
Gain Setting
No Clip and DRC
Control
External Clock
Clock Output
Mute Control
Protection Flag
Shutdown Control
Bead
1nF
Bead
1nF
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APA2607
Typical Application Circuit (Cont.)
Monaural Operation
Bead
1nF
VDD
VDD
25 GAIN1
26 LPVDD
27 LOUTN
28 LOUTN
CS4
1µF
29 LPGND
30 LOUTP
31 LOUTP
32 LPVDD
CS3
1µF
Gain Setting
Bead
VDD
CS2 0.1µF
AVDD 1
3V3REG
C1 1µF LINP
Input Signal Ci1 1µF
LINN
Ci2 1µF
VREF
CB 0.1µF
VDD
CS1
220µF
24 GAIN0
2
23 DRC1
3
22 DRC0
4
21 OSCIN
APA2607
5
20 OSCO
RINN 6
19 MUTE
RINP 7
18 PFLAG
AGND 8
CS5
1µF
VDD
RPVDD 16
ROUTN 15
ROUTN 14
RPGND 13
ROUTP 12
ROUTP 11
PMAX 9
RPVDD 10
17 SD
R1
R2
1nF
CS6
1µF
VDD
Gain Setting
No Clip and DRC
Control
External Clock
Clock Output
Mute Control
Protection Flag
Shutdown Control
Bead
1nF
Bead
1nF
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APA2607
Function Description
3.3V Regulator Operation
Class-D Operation
The 3V3REG regulates the voltage at 3.3V and only for
Output = 0V
internal circuit used, and connects a capacitor from 1µF
to 4.7µF (X5R or above) for stable. (0.8µF or more should
VOUTP
be secured including its variation and temperature
change.)
VOUTN
VOUT
(VOUTP-VOUTN)
Reference Voltage
The voltage output of VREF pin is equal to 3V3REG/2 and
needs to connect a capacitor of 0.1µF for voltage
IOUT
Output > 0V
stabilization.
VOUTP
Gain Setting Operation
VOUTN
Table 1: The gain setting.
VOUT
(VOUTP-VOUTN)
IOUT
Output < 0V
VOUTP
VOUTN
VOUT
(VOUTP-VOUTN)
IOUT
Figure1. The APA2607 Output Waveform (Voltage&
Current)
GAIN1
GAIN0
DRC1
DRC0
Gain
0
0
0
0
22dB
0
1
0
0
28dB
1
0
0
0
34dB
1
1
0
0
16dB
0
0
X
1
34dB
0
1
X
1
40dB
1
0
X
1
46dB
1
1
X
1
28dB
0
0
1
X
34dB
0
1
1
X
40dB
1
0
1
X
46dB
1
1
1
X
28dB
The APA2607’s gain can be set by GAIN0, GAIN1. The
detail gain setting value is listed at table 1.
The APA2607 power amplifier modulation scheme is
shown in figure 1. The outputs VOUTP and VOUTN are in phase
with each other when no input signals. When output > 0V,
the duty cycle of VOUTP is greater than 50% and VOUTN is
Mute Operation
less than 50%; when Output < 0V, the duty cycle of VOUTP is
less than 50% and VOUTN is greater than 50%. This method
duty at OUTP and OUTN, so differential is zero, and output signals have be disabled. The recovery time of mute
reduces the switching current across the load and reduces the I 2R losses in the load that improves the
state to normal operation is about 1ms (max.).
At the mute state, the Class-D output is forced at 50%
Shutdown Operation
amplifier’s efficiency.
This modulation scheme has very short pulses across
In order to reduce power consumption while not in use,
the load, this making the small ripple current and very
little loss on the load, and the LC filter can be eliminated
the APA2607 contains a shutdown function to externally
turn off the amplifier bias circuitry. This shutdown feature
in most applications. Added the LC filter can increase the
efficiency by filter the ripple current.
turns the amplifier off when logic low is placed on the SD
pin for APA2607. The trigger point between a logic high
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APA2607
Function Description (Cont.)
Shutdown Operation (Cont.)
12dB to compare to the normal mode. The output peak
voltage becomes to the power limit value. If the peak volt-
and logic low level is typically 1.5V. It is best to switch
age excesses the power limit value, it will be the attenuation to the power limit value, and the maximum attenua-
between ground and the supply voltage VDD to provide
maximum device performance. By switching the SD pin
tion is -12dB. The attack time is zero second, and needs
7.7 seconds to release the non-clip function from -12dB
to a low level, the amplifier enters a low-consumptioncurrent state, IDD for APA2607 is in shutdown mode. On
to 0dB.
The Non-clip operation should be switched under power-
normal operating, APA2607’s SD pin should pull to a high
level to keep the IC out of the shutdown mode. The SD pin
off or shutdown mode to prevent the pop noise between
the mode switching.
should be tied to a definite voltage to avoid unwanted
state changes.
DRC Operation
Oscillator Operation
OSCI PIN
Mode
DRC1
OSCO
0 fixed
Internal fixed
clock mode
Internal fixed
clock output
1 fixed
Internal spread
clock mode (5)
Internal spread
clock output
Clock in
External clock
mode
External clock
buffer output
MODE
0
0
Normal mode (DRC mode off,
Non-clip mode off)
0
1
Non-Clip mode
1
0
DRC 1 mode
1
1
DRC 2 mode
DRC1 mode: DRC [1:0]=10 (DRC1=High, and DRC0
When the OSCI pin pull low, the APA2607 works at internal fixed clock mode, and OSCO pin is output that fixed
=Low), the DRC 1 mode is active. The gain is increased
by 12dB to compare to the normal mode. The power limit
clock (500kHz); when the OSCI pin pull high, the APA2607
works at internal spread clock mode, and the clock range
value is the point that active the Dynamic Range Compression function. And the maximum attenuation is -12dB.
is from 400kHz to 600kHz; the OSCO pin is the buffer for
output these spread clock.
The attack time is zero second, and needs 3.9 seconds
to release the non-clip function from -12dB to 0dB.
Apply the external clock to the OSCI pin, the APA2607 will
work at external clock mode, and the external clock should
DRC2 mode: DRC [1:0]=11 (DRC1=High, and DRC0
=High), similar to the DRC 1 mode, but the perform the
at the range from 400kHz to 600kHz and the duty cycle
should be at range from 40% to 60%, and the OSCO is
power limit function.
The DRC operation should be switched under power-off
the external clock’s output buffer.
or shutdown mode to prevent the pop noise between the
mode switching.
Power Limit Operation
This function limits the maximum output power of APA2607
Stereo/Mono Switching Operation
for prevent exceed the maximum power of speaker. Except DRC 2 mode, this function is always enabled. The
When connecting the RINN and RINP to 3V3REG before
power-on, the APA2607 will enter the monaural opera-
setting value can be a voltage divider by the resistor that
connects 3V3REG and GND.
tional when power-on. In this operation, the output of
ROUTP should connect to LOUTP for positive output, and
The maximum power limit value (peak voltage)=(1.65VPMAX)x11.23.
the ROUN should connect to LOUTN for negative output,
the input signal will via LINN and LINP to input the
Non-Clip Operation
APA2607.
This mode can increase more output power to compare
When the DRC [1:0]=01 (DRC1=Low, and DRC0=High),
the non-clip mode is active. The gain is increased by
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
DRC0
to the stereo mode single channel’s output power.
17
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APA2607
Function Description (Cont.)
Multi-APA2607 Synchronization Operation
protection occur.
The external clock synchronization function and clock
Connect PFLAG to SD pin, the over-current protection will
be auto recovery.
output function are prepared and the use of master/slave
configuration realizes carrier clock synchronization.
Thermal Protection
When using it with multi chips synchronized, one is used
as a master chip and the other is used as a slave chip. At
The thermal protection has two modes to prevent the
APA2607 being destroyed by over-temperature.
this time, connect OSCO pin of a master chip to OSCI pin
of a slave chip. When using 3 pieces of APA2607 (master/
When the junction temperature excesses 155°C and under the 165°C, the APA2607 will limit the output power by
slave1/slave2), connect OSCO terminal of a slave1 chip
to OSCI pin of a slave2 chip.
6dB to lower the temperature. This calls thermal limit
mode. When the junction temperature falls down to
Protection Flag Operation
Protection
Function
PFLAG
Output
Latch
130°C, the thermal limit state will be cancelled.
And when junction temperature excesses 165°C, the
Class-D
Cancellation
Output State
Class-D output would turn off, and the PFLAG pin will
pull-low. This calls thermal mute mode. All the state will
DC
Detection
Low
Yes
Weak low
Shutdown or
Power-Off
UVLO
High-Z
-
Weak low
-
be cancelled when junction lower than 130°C. Some
contitions, like VDD=5V, RL=4Ω, can’t meet spec PO=10W
OverCurrent
Protection
Low
Yes
Weak low
Shutdown or
Power-Off
because IC into thermal shutdown. Output power curve
use dot line to indicate thermal limit.
Thermal
protection
(power limit)
-
No
Power limit
(-6dB)
Thermal
protection
(class-D off)
Low
No
Weak low
Shutdown or
Power-Off or
Lower
temperature
Shutdown or
Power-Off or
Low
temperature
DC Detection Operation
When a DC signal applies to the input of APA2607 and the
time excesses 0.5s, the APA2607 will turn off the Class-D
output, and the PFLAG pin will pull low. This function protects the speaker to be destroyed by large DC offset. At
mute mode, the DC detection function will be disabled.
The DC detection state will latch and need power-off or
shutdown to release the protection.
Connect PFLAG to /SD pin, the DC detection will be auto
recovery.
Over-Current Protection
The APA2607 monitors the output current. When the current exceeds the current-limit threshold, the APA2607 turnoff the output to prevent the IC from damages in overcurrent or short-circuit condition, and the APA2607 will
latch at this state until shutdown or power-off to release
the over-current protection. PFLAG will pull-high when
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APA2607
Application Information
Square Wave Into the Speaker
Please note that it is important to confirm the capacitor
Apply the square wave into the speaker may cause the
polarity in the application.
voice coil of speaker jump out the air gap and deface the
voice coil. But this depends on the amplitude of square
Output Low-Pass Filter
If the traces form APA2607 to speaker are short, it doesn’t
require output filter for FCC & CE standard.
wave high enough and the bandwidth of speaker is higher
than the square wave’s frequency. For 500kHz switching
A ferrite bead may need if it’s failing the test for FCC or CE
tested without the LC filter. The figure 2 is the sample for
frequency, this is not issued for the speaker because the
frequency is beyond the audio band and can’t significantly
added ferrite bead; the ferrite show choosing high impedance in high frequency.
move the voice coil, as cone movement is proportional to
1/f2 for frequency out of audio band.
Input Resistance, Ri
The APA2607’s input resistor is fixed and the value is
VON
18kΩ.The input resistance has wide variation (+/-10%)
caused by manufacture.
Ferrite
Bead
1nF
Input Capacitor, Ci
Ferrite
Bead
In the typical application, an input capacitor, Ci, is required
VOP
to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and the
4Ω
1nF
input impedance Ri form a high-pass filter with the corner
frequency determined in the following equation:
FC(highpass ) =
1
2πRiCi
Figure 2. Ferrite bead output filter
(1)
The value of Ci must be considered carefully because it
Figure 3 and Figure 4 are examples for added the LC filter
(But-terworth), it’s recommended for the situation that the
directly affects the low frequency performance of the circuit.
Where Ri is 18kΩ and the specification calls for a flat
trace form amplifier to speaker is too long, and needs to
eliminate the radiated emission or EMI.
bass response down to 40Hz. Equation is reconfigured
as below:
1
Ci =
(2)
2πRiFC
OUTP 36µH
When the input resistance variation is considered, the Ci
is 0.22µF, so a value in the range of 0.22µF to 1.0µF
1µF
would be chosen. A further consideration for this capacitor is the leakage path from the input source through the
OUTN
input network (Ri + Rf, Ci) to the load.
This leakage current creates a DC offset voltage at the
36µH
8Ω
1µF
input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a lowFigure 3. LC output filter for 8Ω speaker
leakage tantalum or ceramic capacitor is the best choice.
When polarized capacitors are used, the positive side of
the capacitor should face the amplifier input in most applications because the DC level there is held at V3C3REG/2.
Copyright  ANPEC Electronics Corp.
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APA2607
Application Information (Cont.)
Output Low-Pass Filter (Cont.)
printed circuit traces. Especial for the high slew rate output PWM signal to speaker, these loops should be as
small as possible.
1. All components should be placed close to the APA2607.
For example, the input capacitor (Ci) should be closed to
OUTP 18µH
APA2607’s input pins to avoid causing noise coupling to
APA2607’s high impedance inputs; the decoupling ca-
2.2µF
OUTN
18µH
pacitor (CS) should be placed by the APA2607’s power pin
to decouple the power rail noise.
4Ω
2. The output traces should be short, wide (>50mil) and
symmetric, and this loop like the figure 5, should be as
2.2µF
small as possible, (this loop is high slew rate and high
current path).
Figure 4. LC output filter for 4Ω speaker
VDD
Figure 3 and 4’s low pass filter cut-off frequency are 25kHz
C11
1µF
C11
1µF
VDD
The APA2607 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
26 LPVDD
27 LOUTN
Power-Supply Decoupling Capacitor, CS
28 LOUTN
(3)
29 LPGND
2π LC
30 LOUTP
1
31 LOUTP
FC(lowpass) =
32 LPVDD
(FC).
APA2607
ensure the output total harmonic distortion (THD) is as
low as possible. Power supply decoupling also prevents
Figure 5. TQFN5x5-32 Land Pattern Recommendation
the oscillations being caused by long lead length between the amplifier and the speaker.
3. The input trace should be short and symmetric.
The optimum decoupling is achieved by using two different types of capacitors that target on different types of
4. The power trace width should greater than 50mil.
5. The TQFN5x5-32 Thermal PAD should be soldered on
noises on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
PCB, and the ground plane needs soldered mask (to avoid
short-circuit) except the Thermal PAD area. Like the fig-
equivalent-series-resistance (ESR) ceramic capacitor,
typically 0.1µF placed as close as possible to the device
ure 6 illustrate.
AVDD pin and 1mF placed to the LPVDD and RPVDD led
for works best. For filtering lower frequency noise signals,
a large aluminum electrolytic capacitor of 220µF or greater
placed near the audio power amplifier is recommended.
Layout Recommendation
In high power Class-D power amplifier, a correct layout is
important to ensure proper operation of the amplifier and
avoid the switch noise radiation. In general, interconnecting impedance should be minimized by using short, wide
Copyright  ANPEC Electronics Corp.
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20
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APA2607
Application Information (Cont.)
Layout Recommendation (Cont.)
ThermalVia
Diameter
0.3mm X 9
1.15mm
3.6mm
0.5mm
4.1mm
0.25mm
3.6mm
Solder Mask
to Prevent
Short-Circuit
Ground
Plane for
ThermalPAD
Figure 6. TQFN5x5-32 Land Pattern Recommendation
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APA2607
Package Information
TQFN5x5-32
D
b
E
A
Pin 1
D2
A1
A3
NX
aaa
c
L K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TQFN5x5-32
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.012
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
D
4.90
5.10
0.193
0.201
D2
3.50
3.80
0.138
0.150
E
4.90
5.10
0.193
0.201
E2
3.50
3.80
0.138
0.150
0.45
0.014
e
0.020 BSC
0.50 BSC
L
0.35
K
0.20
0.018
0.008
aaa
0.08
0.003
Note : Followed JEDEC MO-220 WHHD-4.
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APA2607
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN5x5-32
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
5.30±0.20
5.30±0.20
1.30±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TQFN5x5-32
Tape & Reel
2500
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APA2607
Taping Direction Information
TQFN5x5-32
USER DIRECTION OF FEED
Classification Profile
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APA2607
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2011
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
25
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APA2607
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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