1-/2-/4-Channel
Digital Potentiometers
AD8400/AD8402/AD8403
FUNCTIONAL BLOCK DIAGRAM
256-position variable resistance device
Replaces 1, 2, or 4 potentiometers
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Power shutdown—less than 5 μA
3-wire,SPI-compatible serial data input
10 MHz update data loading rate
2.7 V to 5.5 V single-supply operation
Qualified for automotive applications
AD8403
VDD
8-BIT 8
LATCH
DAC
SELECT
DGND
CK RS
1
2
8-BIT
LATCH
3
A1, A0 4
10-BIT
SERIAL
LATCH
APPLICATIONS
SDI
Mechanical potentiometer replacement
Programmable filters, delays, time constants
Volume control, panning
Line impedance matching
Power supply adjustment
8
D
SHDN
8
CK RS
2
8-BIT
LATCH
RDAC2
SHDN
8
CK RS
CK Q RS
CLK
8-BIT 8
LATCH
CS
RDAC1
RDAC3
SHDN
RDAC4
CK RS
SHDN
RS
SHDN
SDO
A1
W1
B1
AGND1
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
01092-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
100
RWA
RWB
75
50
25
0
0
64
128
CODE (Decimal)
192
255
01092-002
RWA(D), RWB(D) (% of Nominal RAB)
The AD8400/AD8402/AD8403 provide a single-, dual-, or
quad-channel, 256-position, digitally controlled variable resistor
(VR) device. 1 These devices perform the same electronic adjustment function as a mechanical potentiometer or variable
resistor. The AD8400 contains a single variable resistor in the
compact SOIC-8 package. The AD8402 contains two independent
variable resistors in space-saving SOIC-14 surface-mount
packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each
part contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by the digital code
loaded into the controlling serial input register. The resistance
between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. Each variable resistor offers a completely
programmable value of resistance between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%
channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional
switched resistor designs, avoiding any make-before-break
or break-before-make operation.
Figure 2. RWA and RWB vs. Code
(continued on Page 3)
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2010 Analog Devices, Inc. All rights reserved.
AD8400/AD8402/AD8403
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution................................................................................ 11
Applications ....................................................................................... 1
Pin Configurations and Function Descriptions ......................... 12
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 14
Functional Block Diagram .............................................................. 1
Test Circuits ..................................................................................... 19
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 20
Specifications..................................................................................... 4
Programming the Variable Resistor ......................................... 20
Electrical Characteristics—10 kΩ Version................................ 4
Programming the Potentiometer Divider ............................... 21
Electrical Characteristics—50 kΩ and 100 kΩ Versions......... 6
Digital Interfacing ...................................................................... 21
Electrical Characteristics—1 kΩ Version .................................. 8
Applications..................................................................................... 24
Electrical Characteristics—All Versions ................................. 10
Active Filter ................................................................................. 24
Timing Diagrams........................................................................ 10
Outline Dimensions ....................................................................... 26
Absolute Maximum Ratings.......................................................... 11
Ordering Guide .......................................................................... 30
Serial Data-Word Format .......................................................... 11
Automotive Products ................................................................. 31
REVISION HISTORY
7/10—Rev. D to Rev. E
Changes to Features Section ............................................................ 1
Changes to IAB Continuous Current Parameter (Table 5) .........11
Updated Outline Dimensions ........................................................26
Changes to Ordering Guide ...........................................................30
Added Automotive Products Section ...........................................31
10/05—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Features........................................................................... 1
Changes to Table 1 ............................................................................. 4
Changes to Table 2 ............................................................................. 6
Changes to Table 3 ............................................................................. 8
Changes to Table 5 ...........................................................................11
Added Figure 36...............................................................................18
Replaced Figure 37 ..........................................................................19
Changes to Theory of Operation Section .....................................20
Changes to Applications Section ...................................................24
Updated Outline Dimensions ........................................................26
Changes to Ordering Guide ...........................................................28
11/01—Rev. B to Rev. C
Addition of new Figure ..................................................................... 1
Edits to Specifications ....................................................................... 2
Edits to Absolute Maximum Ratings .............................................. 6
Edits to TPCs 1, 8, 12, 16, 20, 24, 35 ............................................... 9
Edits to
the Programming the Variable Resistor Section .......................... 13
Rev. E | Page 2 of 32
AD8400/AD8402/AD8403
GENERAL DESCRIPTION
(continued from Page 1)
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPIcompatible, serial-to-parallel shift register that is loaded from
a standard 3-wire, serial-input digital interface. Ten data bits
make up the data-word clocked into the serial input register.
The data-word is decoded where the first two bits determine
the address of the VR latch to be loaded, and the last eight bits
are the data. A serial data output pin at the opposite end of the
serial register allows simple daisy chaining in multiple VR
applications without additional external decoding logic.
The AD8400 is available in the SOIC-8 surface mount. The
AD8402 is available in both surface-mount (SOIC-14) and
14-lead PDIP packages, while the AD8403 is available in a
narrow-body, 24-lead PDIP and a 24-lead, surface-mount
package. The AD8402/AD8403 are also offered in the 1.1 mm
thin TSSOP-14/TSSOP-24 packages for PCMCIA applications.
All parts are guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.
The reset (RS) pin forces the wiper to midscale by loading 80H
into the VR latch. The SHDN pin forces the resistor to an endto-end open-circuit condition on the A terminal and shorts the
wiper to the B terminal, achieving a microwatt power shutdown
state. When SHDN is returned to logic high, the previous latch
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface is still active in shutdown so
that code changes can be made that will produce new wiper
positions when the device is taken out of shutdown.
Rev. E | Page 3 of 32
AD8400/AD8402/AD8403
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL 2
R-DNL
RWB, VA = no connect
Resistor Nonlinearity2
R-INL
RWB, VA = no connect
Nominal Resistance 3
RAB
TA = 25°C, model: AD840XYY10
Resistance Tempco
ΔRAB/ΔT
VAB = VDD, wiper = no connect
Wiper Resistance
RW
VDD = 5V, IW = VDD/RAB
RW
VDD = 3V, IW = VDD/RAB
Nominal Resistance Match
ΔR/RAB
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
N
Integral Nonlinearity 4
INL
Differential Nonlinearity4
DNL
VDD = 5 V
DNL
VDD = 3 V, TA = 25°C
DNL
VDD = 3 V, TA = −40°C to +85°C
Voltage Divider Tempco
ΔVW/ΔT
Code = 80H
Full-Scale Error
VWFSE
Code = FFH
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range 5
VA, B, W
Capacitance 6 Ax, Capacitance Bx CA, B
f = 1 MHz, measured to GND, code = 80H
Capacitance6 Wx
CW
f = 1 MHz, measured to GND, code = 80H
Shutdown Current 7
IA_SD
VA = VDD, VB = 0 V, SHDN = 0
Shutdown Wiper Resistance
RW_SD
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
Input Logic Low
VIL
VDD = 5 V
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Output Logic High
VOH
RL = 2.2 kΩ to VDD
Output Logic Low
VOL
IOL = 1.6 mA, VDD = 5 V
Input Current
IIL
VIN = 0 V or 5 V, VDD = 5 V
Input Capacitance6
CIL
POWER SUPPLIES
Power Supply Range
VDD range
Supply Current (CMOS)
IDD
VIH = VDD or VIL = 0 V
Supply Current (TTL) 8
IDD
VIH = 2.4 V or 0.8 V, VDD = 5.5 V
Power Dissipation (CMOS) 9
PDISS
VIH = VDD or VIL = 0 V, VDD = 5.5 V
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%
PSS
VDD = 3 V ± 10%
Rev. E | Page 4 of 32
Min
Typ 1
Max
Unit
−1
−2
8
±1/4
±1/2
10
500
50
200
0.2
+1
+2
12
LSB
LSB
kΩ
ppm/°C
Ω
Ω
%
8
−2
−1
−1
−1.5
−4
0
±1/2
±1/4
±1/4
±1/2
15
−2.8
1.3
0
100
1
+2
+1
+1
+1.5
0
2
VDD
75
120
0.01
100
5
200
2.4
0.8
2.1
0.6
VDD − 0.1
0.4
±1
5
2.7
0.01
0.9
0.0002
0.006
5.5
5
4
27.5
0.001
0.03
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
μA
Ω
V
V
V
V
V
V
μA
pF
V
μA
mA
μW
%/%
%/%
AD8400/AD8402/AD8403
Parameter
DYNAMIC CHARACTERISTICS6, 10
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk 11
Symbol
Conditions
BW_10 K
THDW
tS
eNWB
CT
R = 10 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% error band
RWB = 5 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
1
Min
Typ 1
600
0.003
2
9
−65
Max
Unit
kHz
%
μs
nV/√Hz
dB
Typical represents average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
IW = 50 μA for VDD = 3 V and IW = 400 μA for VDD = 5 V for the 10 kΩ versions.
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
2
Rev. E | Page 5 of 32
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—50 KΩ AND 100 KΩ VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL 2
R-DNL
RWB, VA = No Connect
Resistor Nonlinearity2
R-INL
RWB, VA = No Connect
Nominal Resistance 3
RAB
TA = 25°C, Model: AD840XYY50
RAB
TA = 25°C, Model: AD840XYY100
Resistance Tempco
ΔRAB/ΔT
VAB = VDD, Wiper = No Connect
Wiper Resistance
RW
VDD = 5V, IW = VDD/RAB
RW
VDD = 3V, IW = VDD/RAB
Nominal Resistance Match
ΔR/RAB
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
N
Integral Nonlinearity 4
INL
Differential Nonlinearity4
DNL
VDD = 5 V
DNL
VDD = 3 V, TA = 25°C
DNL
VDD = 3 V, TA = −40°C to +85°C
Voltage Divider Tempco
ΔVW/ΔT
Code = 80H
Full-Scale Error
VWFSE
Code = FFH
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range 5
VA, VB, VW
Capacitance 6 Ax, Bx
CA, CB
f = 1 MHz, measured to GND, code = 80H
Capacitance6 Wx
CW
f = 1 MHz, measured to GND, code = 80H
Shutdown Current 7
IA_SD
VA = VDD, VB = 0 V, SHDN = 0
Shutdown Wiper Resistance
RW_SD
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
Input Logic Low
VIL
VDD = 5 V
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Output Logic High
VOH
RL = 2.2 kΩ to VDD
Output Logic Low
VOL
IOL = 1.6 mA, VDD = 5 V
Input Current
IIL
VIN = 0 V or 5 V, VDD = 5 V
Input Capacitance6
CIL
POWER SUPPLIES
Power Supply Range
VDD range
Supply Current (CMOS)
IDD
VIH = VDD or VIL = 0 V
Supply Current (TTL) 8
IDD
VIH = 2.4 V or 0.8 V, VDD = 5.5 V
Power Dissipation (CMOS) 9
PDISS
VIH = VDD or VIL = 0 V, VDD = 5.5 V
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%
PSS
VDD = 3 V ± 10%
Rev. E | Page 6 of 32
Min
Typ 1
Max
Unit
−1
−2
35
70
±1/4
±1/2
50
100
500
50
200
0.2
+1
+2
65
130
LSB
LSB
kΩ
kΩ
ppm/°C
Ω
Ω
%
8
−4
−1
−1
−1.5
−1
0
±1
±1/4
±1/4
±1/2
15
−0.25
+0.1
0
100
1
+4
+1
+1
+1.5
0
+1
VDD
15
80
0.01
100
5
200
2.4
0.8
2.1
0.6
VDD − 0.1
0.4
±1
5
2.7
0.01
0.9
0.0002
0.006
5.5
5
4
27.5
0.001
0.03
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
μA
Ω
V
V
V
V
V
V
μA
pF
V
μA
mA
μW
%/%
%/%
AD8400/AD8402/AD8403
Parameter
DYNAMIC CHARACTERISTICS6, 10
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk 11
Symbol
Conditions
BW_50 K
BW_100 K
THDW
tS_50 K
tS_100 K
eNWB_50 K
eNWB_100 K
CT
R = 50 kΩ
R = 100 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% error band
VA = VDD, VB = 0 V, ±1% error band
RWB = 25 kΩ, f = 1 kHz, RS = 0
RWB = 50 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
1
Min
Typ 1
125
71
0.003
9
18
20
29
−65
Max
Unit
kHz
kHz
%
μs
μs
nV/√Hz
nV/√Hz
dB
Typicals represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
2
Rev. E | Page 7 of 32
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—1 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL 2
R-DNL
RWB, VA = no connect
Resistor Nonlinearity2
R-INL
RWB, VA = no connect
Nominal Resistance 3
RAB
TA = 25°C, model: AD840XYY1
Resistance Tempco
ΔRAB/ΔT
VAB = VDD, wiper = no connect
Wiper Resistance
RW
VDD = 5V, IW = VDD/RAB
RW
VDD = 3V, IW = VDD/RAB
Nominal Resistance Match
ΔR/RAB
CH 1 to CH 2, VAB = VDD, TA = 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
N
Integral Nonlinearity 4
INL
Differential Nonlinearity4
DNL
VDD = 5 V
DNL
VDD = 3 V, TA = 25°C
Voltage Divider Temperature Coefficient ΔVW/ΔT
Code = 80H
Full-Scale Error
VWFSE
Code = FFH
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range 5
VA, VB, VW
Capacitance 6 Ax, Bx
CA, CB
f = 1 MHz, measured to GND, code = 80H
Capacitance6 Wx
CW
f = 1 MHz, measured to GND, code = 80H
Shutdown Supply Current 7
IA_SD
VA = VDD, VB = 0 V, SHDN = 0
Shutdown Wiper Resistance
RW_SD
VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
Input Logic Low
VIL
VDD = 5 V
Input Logic High
VIH
VDD = 3 V
Input Logic Low
VIL
VDD = 3 V
Output Logic High
VOH
RL = 2.2 kΩ to VDD
Output Logic Low
VOL
IOL = 1.6 mA, VDD = 5 V
Input Current
IIL
VIN = 0 V or 5 V, VDD = 5 V
Input Capacitance6
CIL
POWER SUPPLIES
Power Supply Range
VDD range
Supply Current (CMOS)
IDD
VIH = VDD or VIL = 0 V
8
Supply Current (TTL)
IDD
VIH = 2.4 V or 0.8 V, VDD = 5.5 V
Power Dissipation (CMOS) 9
PDISS
VIH = VDD or VIL = 0 V, VDD = 5.5 V
Power Supply Sensitivity
PSS
ΔVDD = 5 V ± 10%
PSS
ΔVDD = 3 V ± 10%
Rev. E | Page 8 of 32
Min
Typ 1
Max
Unit
−5
−4
0.8
−1
±1.5
1.2
700
53
200
0.75
+3
+4
1.6
LSB
LSB
kΩ
ppm/°C
Ω
Ω
%
8
−6
−4
−5
−20
0
±2
−1.5
−2
25
−12
6
0
100
2
+6
+2
+5
0
10
VDD
75
120
0.01
50
5
100
2.4
0.8
2.1
0.6
VDD − 0.1
0.4
±1
5
2.7
0.01
0.9
0.0035
0.05
5.5
5
4
27.5
0.008
0.13
Bits
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
μA
Ω
V
V
V
V
V
V
μA
pF
V
μA
mA
μW
%/%
%/%
AD8400/AD8402/AD8403
Parameter
DYNAMIC CHARACTERISTICS6, 10
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk 11
Symbol
Conditions
BW_1 K
THDW
tS
eNWB
CT
R = 1 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% error band
RWB = 500 Ω, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
1
Min
Typ 1
5,000
0.015
0.5
3
−65
Max
Unit
kHz
%
μs
nV/√Hz
dB
Typicals represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. IW = 500 μA for VDD = 3 V and
IW = 2.5 mA for VDD = 5 V for 1 kΩ version.
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use VDD = 5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
2
Rev. E | Page 9 of 32
AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter
SWITCHING CHARACTERISTICS 2, 3
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay 4
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
Symbol
Conditions
Min
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tRS
tCSH
tCS1
Clock level high or low
10
5
5
1
10
10
50
0
10
RL = 1 kΩ to 5 V, CL ≤ 20 pF
Typ 1
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
1
Typicals represent average readings at 25°C and VDD = 5 V.
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
3
See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and
timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
of 1 V/μs should be maintained.
4
Propagation delay depends on the value of VDD, RL, and CL (see the Applications section).
2
TIMING DIAGRAMS
1
A1
SDI
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
CLK
0
1
0
1
CS
01092-003
VDD
0V
SDO
(DATA OUT)
1
Ax OR Dx
Ax OR Dx
0
tDS
1
A'x OR D'x
tDH
A'x OR D'x
0
tPD_MIN
tPD_MAX
tCH
1
tCS1
CLK
0
1
tCSS
tCL
tCSH
CS
tCSW
0
±1%
±1% ERROR BAND
01092-004
tS
VDD
VOUT
0V
VDD
VDD/2
±1%
±1% ERROR BAND
Figure 5. Reset Timing Diagram
Figure 3. Timing Diagram
SDI
(DATA IN)
VOUT
Figure 4. Detailed Timing Diagram
Rev. E | Page 10 of 32
01092-005
tS
0
VOUT
tRS
RS
DAC REGISTER LOAD
Unit
AD8400/AD8402/AD8403
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VA, VB, VW to GND
Maximum Current
IWB, IWA Pulsed
IWB Continuous (RWB ≤ 1 kΩ, A Open)1
IWA Continuous (RWA ≤ 1 kΩ, B Open)1
IAB Continuous (RAB = 1 kΩ/10 kΩ/
50 kΩ/100 kΩ)1
Digital Input and Output Voltage
to GND
Operating Temperature Range
Maximum Junction Temperature
(TJ Maximum)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Package Power Dissipation
Thermal Resistance (θJA)
SOIC (R-8)
PDIP (N-14)
PDIP (N-24)
SOIC (R-14)
SOIC (R-24)
TSSOP-14 (RU-14)
TSSOP-24 (RU-24)
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V, +8 V
0 V, VDD
±20 mA
±5 mA
±5 mA
±2.1 mA/±2.1 mA/
±540 μA/±540 μA
0 V, 7 V
SERIAL DATA-WORD FORMAT
Table 6.
ADDR
B9
B8
A1
A0
MSB LSB
29
28
−40°C to +125°C
150°C
−65°C to +150°C
300°C
(TJ max − TA)/θJA
B7
D7
MSB
27
B6
D6
B5
D5
DATA
B4 B3
D4 D3
158°C/W
83°C/W
63°C/W
120°C/W
70°C/W
180°C/W
143°C/W
Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package; VDD = 5 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 11 of 32
B2
D2
B1
D1
B0
D0
LSB
20
AD8400/AD8402/AD8403
8
A1
2
AD8400
7
W1
CS
3
TOP VIEW
(Not to Scale)
6
VDD
SDI
4
5
CLK
AGND
B2
Figure 6. AD8400 Pin Configuration
1
14
2
13
3
AD8402
W2
4
TOP VIEW
(Not to Scale)
DGND
5
10
SHDN
6
9
A2
CS
7
12
11
8
B1
AGND2
1
24
B1
A1
B2
2
23
A1
W1
A2
3
22
W1
W2
4
21
AGND1
AGND4
5
AD8403
20
B3
B4
6
TOP VIEW
(Not to Scale)
19
A3
A4
7
18
W3
W4
8
17
AGND3
DGND
9
16
VDD
SHDN 10
15
RS
CS 11
14
CLK
SDI 12
13
SDO
VDD
RS
CLK
SDI
01092-007
1
01092-006
B1
GND
Figure 7. AD8402 Pin Configuration
Figure 8. AD8403 Pin Configuration
Table 7. AD8400 Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
B1
GND
CS
4
5
6
7
8
SDI
CLK
VDD
W1
A1
Description
Terminal B RDAC.
Ground.
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
Serial Data Input.
Serial Clock Input, Positive Edge Triggered.
Positive Power Supply. Specified for operation at both 3 V and 5 V.
Wiper RDAC, Addr = 002.
Terminal A RDAC.
Table 8. AD8402 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
AGND
B2
A2
W2
DGND
SHDN
CS
8
9
10
11
12
13
14
SDI
CLK
RS
VDD
W1
A1
B1
1
Description
Analog Ground.1
Terminal B RDAC 2.
Terminal A RDAC 2.
Wiper RDAC 2, Addr = 012.
Digital Ground.1
Terminal A Open Circuit. Shutdown controls Variable Resistor 1 and Variable Resistor 2.
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
Serial Data Input.
Serial Clock Input, Positive Edge Triggered.
Active Low Reset to Midscale. Sets RDAC registers to 80H.
Positive Power Supply. Specified for operation at both 3 V and 5 V
Wiper RDAC 1, Addr = 002.
Terminal A RDAC 1.
Terminal B RDAC 1.
All AGND pins must be connected to DGND.
Rev. E | Page 12 of 32
01092-008
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD8400/AD8402/AD8403
Table 9. AD8403 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
Mnemonic
AGND2
B2
A2
W2
AGND4
B4
A4
W4
DGND
SHDN
CS
12
13
14
15
16
17
18
19
20
21
22
23
24
SDI
SDO
CLK
RS
VDD
AGND3
W3
A3
B3
AGND1
W1
A1
B1
1
Description
Analog Ground 2.1
Terminal B RDAC 2.
Terminal A RDAC 2.
Wiper RDAC 2, Addr = 012.
Analog Ground 4.1
Terminal B RDAC 4.
Terminal A RDAC 4.
Wiper RDAC 4, Addr = 112.
Digital Ground.1
Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor 1 through Variable Resistor 4.
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
Serial Data Input.
Serial Data Output. Open drain transistor requires a pull-up resistor.
Serial Clock Input, Positive Edge Triggered.
Active Low Reset to Midscale. Sets RDAC registers to 80H.
Positive Power Supply. Specified for operation at both 3 V and 5 V.
Analog Ground 3.1
Wiper RDAC 3, Addr = 102.
Terminal A RDAC 3.
Terminal B RDAC 3.
Analog Ground 1.1
Wiper RDAC 1, Addr = 002.
Terminal A RDAC 1.
Terminal B RDAC 1.
All AGND pins must be connected to DGND.
Rev. E | Page 13 of 32
AD8400/AD8402/AD8403
TYPICAL PERFORMANCE CHARACTERISTICS
10
60
SS = 1205 UNITS
VDD = 4.5V
TA = 25°C
VDD = 3V OR 5V
RAB = 10kΩ
48
FREQUENCY
6
4
36
24
12
2
0
0
32
64
96
128
160
192
224
256
CODE (Decimal)
0
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0
WIPER RESISTANCE (Ω)
Figure 9. Wiper to End Terminal Resistance vs. Code
Figure 12. 10 kΩ Wiper-Contact-Resistance Histogram
1.0
5
80H
VDD = 5V
INL NONLINEARITY ERROR (LSB)
FFH
4
VWB VOLTAGE (V)
40H
20H
3
CODE = 10H
2
1
05H
0
1
2
3
0.5
TA = +25°C
TA = –40°C
0
–0.5
TA = +85°C
TA = 25°C
VDD = 5V
4
5
6
7
IWB CURRENT (mA)
–1.0
01092-010
0
01092-012
RWA
01092-009
RWB
0
32
64
96
128
160
192
224
256
DIGITAL INPUT CODE (Decimal)
01092-013
RESISTANCE (kΩ)
8
Figure 13. Potentiometer Divider Nonlinearity Error vs. Code
Figure 10. Resistance Linearity vs. Conduction Current
60
1.0
SS = 184 UNITS
VDD = 4.5V
TA = 25°C
VDD = 5V
48
FREQUENCY
TA = +85°C
0
TA = –40°C
36
24
TA = +25°C
–0.5
–1.0
0
32
64
96
128
160
192
224
256
DIGITAL INPUT CODE (Decimal)
Figure 11. Resistance Step Position Nonlinearity Error vs. Code
0
35
37
39
41
43
45
47
49
51
53
WIPER RESISTANCE (Ω)
Figure 14. 50 kΩ Wiper-Contact-Resistance Histogram
Rev. E | Page 14 of 32
55
01092-014
12
01092-011
R-INL ERROR (LSB)
0.5
AD8400/AD8402/AD8403
60
700
FREQUENCY
48
36
24
0
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0
WIPER RESISTANCE (Ω)
500
400
300
200
100
0
–100
01092-015
12
VDD = 5V
TA = –40°C/+85°C
VA = NO CONNECT
RWB MEASURED
600
0
32
64
96
128
160
192
224
01092-018
RHEOSTAT MODE TEMPCO (ppm/°C)
SS = 184 UNITS
VDD = 4.5V
TA = 25°C
256
CODE (Decimal)
Figure 18. ΔRWB/ΔT Rheostat Mode Tempco
Figure 15. 100 kΩ Wiper-Contact-Resistance Histogram
10
20mV
8
RW
(20mV/DIV)
6
RWB (WIPER-TO-END)
CODE = 80H
4
CS
(5V/DIV)
2
25
50
75
100
125
TEMPERATURE (°C)
TIME 500ns/DIV
Figure 19. One Position Step Change at Half-Scale (Code 7FH to 80H)
Figure 16. Nominal Resistance vs. Temperature
6
70
VDD = 5V
TA = –40°C/+85°C
VA = 2V
VB = 0V
60
CODE = FF
0
80
–6
50
–12
40
–18
40
GAIN (dB)
20
30
10
–24
08
–30
04
20
–36
10
–42
0
–48
02
01
TA = 25°C
–10
–54
0
32
64
96
128
160
192
224
CODE (Decimal)
256
01092-017
POTENTIOMETER MODE TEMPCO (ppm/°C)
500ns
01092-019
5V
0
01092-016
RAB = 10kΩ
0
–25
–75
–50
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 20. 10 kΩ Gain vs. Frequency vs. Code
(See Figure 43)
Figure 17. ΔVWB/ΔT Potentiometer Mode Tempco
Rev. E | Page 15 of 32
1M
01092-020
NOMINAL RESISTANCE (k Ω)
RAB (END-TO-END)
AD8400/AD8402/AD8403
10
0.75
0.50
1
AVERAGE + 2 SIGMA
0.25
THD + NOISE (%)
ΔRWB RESISTANCE (%)
FILTER = 22kHz
VDD = 5V
TA = 25°C
CODE = 80H
VDD = 5V
SS = 158 UNITS
AVERAGE
0
–0.25
0.1
AVERAGE – 2 SIGMA
0.01
100
0
200
300
400
500
600
HOURS OF OPERATION AT 150°C
0.001
01092-021
–0.75
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 21. Long-Term Drift Accelerated by Burn-In
01092-024
–0.50
Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency
(See Figure 41 and Figure 42)
45.25μs
2V
OUTPUT
VOUT
(50mV/DIV)
INPUT
50mV
TIME 500μs/DIV
200ns
01092-025
01092-022
5μs
5V
TIME 200ns/DIV
Figure 25. Digital Feedthrough vs. Time
Figure 22. Large Signal Settling Time
6
6
CODE = FFH
CODE = FFH
0
0
–6
–6
80H
80H
GAIN (dB)
40H
–18
20H
–24
10H
–30
40H
–12
20H
–18
10H
–24
08H
–30
08H
04H
–36
–36
04H
02H
–42
–42
01H
02H
–48
–48
–54
1k
10k
100k
FREQUENCY (Hz)
1M
–54
1k
10k
100k
FREQUENCY (Hz)
Figure 26. 100 kΩ Gain vs. Frequency vs. Code
Figure 23. 50 kΩ Gain vs. Frequency vs. Code
Rev. E | Page 16 of 32
1M
01092-026
01H
01092-023
GAIN (dB)
–12
AD8400/AD8402/AD8403
NORMALIZED GAIN FLATNESS (0.1dB/DIV)
f–3dB = 700kHz, R = 10k Ω
6
0
–6
GAIN (dB)
R = 10kΩ
R = 50kΩ
Ω
f–3dB = 71kHz, R = 100k
–12
f–3dB = 125kHz, R = 50k Ω
–18
–24
–30
10
100
1k
VIN = 100mV rms
VDD = 5V
RL = 1MΩ
–36
10k
100k
1M
FREQUENCY (Hz)
–42
1k
10k
Figure 27. Normalized Gain Flatness vs. Frequency
(See Figure 43)
Figure 30. −3 dB Bandwidths
10
1200
IDD – SUPPLY CURRENT (μA)
1000
1
VDD = 5V
0.1
TA = 25°C
A: VDD = 5.5V
CODE = 55H
B: VDD = 3.3V
CODE = 55H
C: VDD = 5.5V
CODE = FFH
D: VDD = 3.3V
CODE = FFH
TA = 25°C
IDD – SUPPLY CURRENT (mA)
1M
100k
FREQUENCY (Hz)
01092-030
R = 100kΩ
01092-027
X
12
CODE = 80H
VDD = 5V
TA = 25°C
800
600
400
B
A
200
VDD = 3V
C
1
2
3
4
5
DIGITAL INPUT VOLTAGE (V)
0
01092-028
0
1k
1M
10M
Figure 31. Supply Current vs. Clock Frequency
160
VDD = +5V DC ±1V p-p AC
TA = 25°C
CODE = 80H
CL = 10pF
VA = 4V, VB = 0V
TA = 25°C
140
VDD = 2.7V
120
RON (Ω)
100
40
80
VDD = 5.5V
60
20
40
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 29. Power Supply Rejection Ratio vs. Frequency
(See Figure 40)
0
0
1
2
3
4
5
VBIAS (V)
Figure 32. AD8403 Incremental Wiper On Resistance vs. VDD
(See Figure 39)
Rev. E | Page 17 of 32
6
01092-032
20
01092-029
PSRR (dB)
60
100k
FREQUENCY (Hz)
Figure 28. Supply Current vs. Digital Input Voltage
80
10k
01092-031
D
0.01
AD8400/AD8402/AD8403
LOGIC INPUT
VOLTAGE = 0, VDD
–10
IDD – SUPPLY CURRENT (μA)
–20
0
–45
–90
VDD = 5V TA = 25°C
0.1
VDD = 5.5V
0.01
WIPER SET AT
HALF-SCALE 80H
200k
400k
1M
2M
4M
6M
10M
FREQUENCY (Hz)
0.001
–55
01092-033
100k
VDD = 3.3V
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
01092-035
PHASE (Degrees)
GAIN (dB)
1
0
Figure 35. Supply Current vs. Temperature
Figure 33. 1 kΩ Gain and Phase vs. Frequency
100
6
VDD = 5V
RAB = 1kΩ
1
–55
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
105
125
Figure 34. Shutdown Current vs. Temperature
VA = VB = OPEN
TA = 25°C
4
3
2
RAB = 10kΩ
1
RAB = 50kΩ
RAB = 100kΩ
0
0
32
64
96
128
160
CODE (Decimal)
Figure 36. IWB_MAX vs. Code
Rev. E | Page 18 of 32
192
224
256
01092-057
THEORETICAL IWB_MAX (mA)
10
01092-034
IA SHUTDOWN CURRENT (nA)
5
AD8400/AD8402/AD8403
TEST CIRCUITS
A
V+
V+ = VDD
1LSB = V+/256
B
VMS
5V
W
~
W
VOUT
VIN
OP279
OFFSET
GND
01092-036
A
B
DUT
01092-040
DUT
2.5V DC
Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 41. Inverting Programmable Gain
5V
NO CONNECT
VOUT
IW
VIN
01092-037
VMS
Figure 42. Noninverting Programmable Gain
A
W
VIN
RW = [VMS1 – VMS2]/IW
+15V
W
DUT
2.5V
–15V
Figure 43. Gain vs. Frequency
Figure 39. Wiper Resistance
RSW =
DUT
VA
~
V+ = VDD ± 10%
W
B
PSRR (dB) = 20LOG
VMS
B
ΔV
( ΔVMS )
0.1V
ISW
CODE =
H
+
0.1V
ISW
–
DD
PSS (%/%) =
ΔVMS%
ΔVDD%
01092-039
V+
W
A
VOUT
OP42
B
OFFSET
GND
01092-038
VMS1
~
VBIAS
Figure 40. Power Supply Sensitivity (PSS, PSRR)
A = NC
01092-043
VW
IW = VDD/RNOMINAL
B
VDD
B
DUT
DUT
VMS2
W
A
2.5V
Figure 38. Resistor Position Nonlinearity Error
(Rheostat Operations; R-INL, R-DNL)
A
~
OFFSET
GND
01092-041
B
OP279
01092-042
DUT
A
W
Figure 44. Incremental On Resistance
Rev. E | Page 19 of 32
AD8400/AD8402/AD8403
THEORY OF OPERATION
The AD8400/AD8402/AD8403 provide a single, dual, and quad
channel, 256-position, digitally controlled variable resistor (VR)
device. Changing the programmed VR setting is accomplished
by clocking in a 10-bit serial data-word into the SDI (Serial
Data Input) pin. The format of this data-word is two address
bits, MSB first, followed by eight data bits, also MSB first.
Table 6 provides the serial register data-word format. The
AD8400/AD8402/AD8403 have the following address assignments for the ADDR decoder, which determines the location
of the VR latch receiving the serial register data in Bit B7 to
Bit B0:
VR# = A1 × 2 + A0 + 1
(1)
The single-channel AD8400 requires A1 = A0 = 0. The dualchannel AD8402 requires A1 = 0. VR settings can be changed
one at a time in random sequence. A serial clock running at
10 MHz makes it possible to load all four VRs under 4 μs
(10 × 4 × 100 ns) for AD8403. The exact timing requirements
are shown in Figure 3, Figure 4, and Figure 5.
The AD8400/AD8402/AD8403 do not have power-on midscale
preset, so the wiper can be at any random position at power-up.
However, the AD8402/AD8403 can be reset to midscale by
asserting the RS pin, simplifying initial conditions at power-up.
Both parts have a power shutdown SHDN pin that places the
VR in a zero-power-consumption state where Terminal Ax is
open-circuited and the Wiper Wx is connected to Terminal Bx,
resulting in the consumption of only the leakage current in the
VR. In shutdown mode, the VR latch settings are maintained
so that upon returning to the operational mode, the VR settings
return to the previous resistance values. The digital interface is
still active in shutdown, except that SDO is deactivated. Code
changes in the registers can be made during shutdown that will
produce new wiper positions when the device is taken out of
shutdown.
RS
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
Wx
RS = RNOMINAL/256
The nominal resistance of the VR (RDAC) between Terminal A
and Terminal B is available with values of 1 kΩ, 10 kΩ, 50 kΩ,
and 100 kΩ. The final digits of the part number determine the
nominal resistance value; that is, 10 kΩ = 10; 100 kΩ = 100.
The nominal resistance (RAB) of the VR has 256 contact points
accessible by the wiper terminal, and the resulting resistance
can be measured either across the wiper and B terminals (RWB)
or across the wiper and A terminals (RWA). The 8-bit data-word
loaded into the RDAC latch is decoded to select one of the
256 possible settings. The wiper’s first connection starts at the
B terminal for data 00H. This B terminal connection has a wiper
contact resistance of 50 Ω. The second connection (for the 10 kΩ
part) is the first tap point located at 89 Ω = [RAB (nominal
resistance) + RW = 39 Ω + 50 Ω] for data 01H. The third
connection is the next tap point representing 78 Ω + 50 Ω =
128 Ω for data 02H. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
10,011 Ω. Note that the wiper does not directly connect to the
B terminal even for data 00H. See Figure 45 for a simplified
diagram of the equivalent RDAC circuit.
The AD8400 contains one RDAC, the AD8402 contains
two independent RDACs, and the AD8403 contains four
independent RDACs. The general transfer equation that
determines the digitally programmed output resistance
between Wx and Bx is
R WB (D ) =
D
× R AB + R W
256
(2)
where D, in decimal, is the data loaded into the 8-bit RDAC#
latch, and RAB is the nominal end-to-end resistance.
For example, when the A terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following RWB (for the 10 kΩ version):
D (Dec)
255
128
1
0
RS
RS
Rheostat Operation
Table 10.
RS
Bx
01092-044
SHDN
Ax
PROGRAMMING THE VARIABLE RESISTOR
RWB (Ω)
10,011
5,050
89
50
Output State
Full scale
Midscale (RS = 0 condition)
1 LSB
Zero-scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
50 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Figure 45. AD8402/AD8403 Equivalent VR (RDAC) Circuit
Rev. E | Page 20 of 32
AD8400/AD8402/AD8403
256 − D
× RAB + RW
256
(3)
where D is the data loaded into the 8-bit RDAC# latch, and RAB
is the nominal end-to-end resistance.
For example, when the B terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following RWA (for the 10 kΩ version):
Table 11.
D (Dec)
255
128
1
0
RWA (Ω)
89
5,050
10,011
10,050
Output State
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
Zero-Scale
The typical distribution of RAB from channel to channel
matches within ±1%. However, device-to-device matching
is process lot dependent and has a ±20% variation. The temperature coefficient, or the change in RAB with temperature,
is 500 ppm/°C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases because the contribution of
the CMOS switch wiper resistance becomes an appreciable
portion of the total resistance from the B terminal to the
Wiper W. See Figure 17 for a plot of potentiometer tempco
performance vs. code setting.
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contain a standard SPIcompatible, 3-wire, serial input control interface. The three
inputs are clock (CLK), chip select (CS), and serial data input
(SDI). The positive-edge sensitive CLK input requires clean
transitions to avoid clocking incorrect data into the serial input
register. For the best result, use logic transitions faster than
1 V/μs. Standard logic families work well. If mechanical switches
are used for product evaluation, they should be debounced by
a flip-flop or other suitable means. The block diagrams in
Figure 46, Figure 47, and Figure 48 show the internal digital
circuitry in more detail. When CS is taken active low, the clock
loads data into the 10-bit serial register on each positive clock
edge (see Table 12).
VDD
CS
CLK
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not contribute any significant temperature related errors. The graph in
Figure 18 shows the performance of RWB tempco vs. code. Using
the potentiometer with codes below 32 results in the larger
temperature coefficients plotted.
A1
D7
EN
ADDR
DEC
A1
A0
D0
W1
RDAC
LATCH
NO. 1
B1
D7
10-BIT
SER
REG
SDI
AD8400
DI D0
8
GND
PROGRAMMING THE POTENTIOMETER DIVIDER
Figure 46. AD8400 Block Diagram
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper starting
at 0 V up to 1 LSB less than 5 V. Each LSB is equal to the voltage
applied across the A to B terminals divided by the 256-position
resolution of the potentiometer divider. The general equation
defining the output voltage with respect to ground for any given
input voltage applied to the A to B terminals is
VW =
D
× VAB + VB
256
AD8402
CS
CLK
(4)
D7
10-BIT
SER
REG
DI
D0
RDAC
LATCH
NO. 1
R
W1
B1
A4
D7
D0
D0
8
RDAC
LATCH
NO. 2
R
W4
B4
SHDN
DGND
Operation of the digital potentiometer in the voltage divider
mode results in more accurate operation over temperature.
ADDR
DEC
A1
A0
SDI
A1
D7
EN
RS
AGND
Figure 47. AD8402 Block Diagram
Rev. E | Page 21 of 32
VDD
01092-046
RWA (D ) =
Here the output voltage is dependent on the ratio of the internal
resistors, not the absolute value; therefore, the temperature drift
improves to 15 ppm/°C.
01092-045
Like a mechanical potentiometer, RDAC is symmetrical. The
resistance between the Wiper W and Terminal A also produces
a digitally controlled complementary resistance, RWA. When
these terminals are used, the B terminal can be tied to the wiper
or left floating. RWA starts at the maximum and decreases as the
data loaded into the RDAC latch increases. The general transfer
equation for this RWA is
AD8400/AD8402/AD8403
If two AD8403 RDACs are daisy-chained, it requires 20 bits
of address and data in the format shown in Table 6. During
shutdown (SHDN = logic low), the SDO output pin is forced
to the off (logic high) state to disable power dissipation in the
pull-up resistor. See Figure 50 for equivalent SDO output circuit
schematic.
VDD
CS
CLK
A1
D7
EN
DO
SDO
ADDR
DEC
A1
A0
D7
D0
SER
REG
SDI
DI
W1
RDAC
LATCH
NO. 1
R
B1
The data setup and hold times in the specification table determine the data valid time requirements. The last 10 bits of the
data-word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder, which enables one of the two (AD8402) or four (AD8403)
positive edge-triggered RDAC latches. See Figure 49 and Table 13.
AD8403
A4
D7
D0
8
D0
W4
RDAC
LATCH
NO. 4
R
B4
Table 13. Address Decode Table
DGND
RS
AGND
A1
0
0
1
1
01092-047
SHDN
Figure 48. AD8403 Block Diagram
A0
0
1
0
1
Latch Decoded
RDAC#1
RDAC#2
RDAC#3 AD8403 Only
RDAC#4 AD8403 Only
Table 12. Input Logic Control Truth Table1
RS
SHDN
Register Activity
L
L
H
H
H
H
No SR effect; enables SDO pin
Shift one bit in from the SDI pin. The
10th previously entered bit is shifted
out of the SDO pin.
Load SR data into RDAC latch based
on A1, A0 decode (Table 13).
No operation
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared
Latches all RDAC latches to 80H
Open-circuits all Resistor A terminals,
connects W to B, turns off SDO
output transistor.
X
P
H
H
X
X
H
X
H
L
H
H
X
X
1
H
H
P
H
H
L
AD8403
CS
ADDR
DECODE
RDAC 4
CLK
SERIAL
REGISTER
SDI
Figure 49. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data-word completing one RDAC update. In the case of
AD8403, four separate 10-bit data-words must be clocked in to
change all four VR settings.
SHDN
CS
P = positive edge, X = don’t care, SR = shift register
The serial data output (SDO) pin, which exists only on the
AD8403 and not on the AD8400 or AD8402, contains an
open-drain, n-channel FET that requires a pull-up resistor to
transfer data to the SDI pin of the next package. The pull-up
resistor termination voltage may be larger than the VDD supply
(but less than the max VDD of 8 V) of the AD8403 SDO output
device. For example, the AD8403 could operate at VDD = 3.3 V,
and the pull-up for interface to the next device could be set at 5 V.
This allows for daisy-chaining several RDACs from a single processor serial data line. The clock period needs to be increased
when using a pull-up resistor to the SDI pin of the following
device in the series. Capacitive loading at the daisy-chain node
SDO to SDI between devices must be accounted for in order to
transfer data successfully. When daisy chain is used, CS should
be kept low until all the bits of every package are clocked into
their respective serial registers and the address and data bits are
in the proper decoding location.
RDAC 1
RDAC 2
01092-048
CS
L
P
SDI
SDO
SERIAL
REGISTER
D
Q
CK RS
CLK
RS
01092-049
CLK
Figure 50. Detailed SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 51. This structure
applies to digital pins CS, SDI, SDO, RS, SHDN, and CLK. The
digital input ESD protection allows for mixed power supply
applications where 5 V CMOS logic can be used to drive an
AD8400, AD8402, or AD8403 operating from a 3 V power
supply. Analog Pin A, Pin B, and Pin W are protected with a
20 Ω series resistor and parallel Zener diode (see Figure 52).
Rev. E | Page 22 of 32
AD8400/AD8402/AD8403
1kΩ
DIGITAL
PINS
Listing I. Macro Model Net List for RDAC
01092-050
LOGIC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA A 0 {DW/256*90.4E-12+30E-12}
RAW A W {(1-DW/256)*RDAC+50}
CW W 0 120E-12
RBW W B {DW/256*RDAC+50}
CB B 0 {(1-DW/256)*90.4E-12+30E-12}
*
.ENDS DPOT
Figure 51. Equivalent ESD Protection Circuits
20Ω
01092-051
A, B, W
Figure 52. Equivalent ESD Protection Circuit (Analog Pins)
RDAC
10kΩ
A
B
CA
CB
W
CA = 90.4pF (DW/256) + 30pF
CB = 90.4pF [1 – (DW/256)] + 30pF
01092-052
CW
120pF
Figure 53. RDAC Circuit Simulation Model for RDAC = 10 kΩ
The AC characteristics of the RDAC are dominated by the
internal parasitic capacitances and the external capacitive loads.
The −3 dB bandwidth of the AD8403AN10 (10 kΩ resistor)
measures 600 kHz at half scale as a potentiometer divider.
Figure 30 provides the large signal Bode plot characteristics
of the three available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ.
The gain flatness vs. frequency graph of the 1 kΩ version predicts
filter applications performance (see Figure 33). A parasitic
simulation model has been developed and is shown in Figure 53.
Listing I provides a macro model net list for the 10 kΩ RDAC.
The total harmonic distortion plus noise (THD + N), shown in
Figure 41, is measured at 0.003% in an inverting op amp circuit
using an offset ground and a rail-to-rail OP279 amplifier.
Thermal noise is primarily Johnson noise, typically 9 nV/√Hz
for the 10 kΩ version at f = 1 kHz. For the 100 kΩ device,
thermal noise becomes 29 nV/√Hz. Channel-to-channel
crosstalk measures less than −65 dB at f = 100 kHz. To achieve
this isolation, the extra ground pins provided on the package to
segregate the individual RDACs must be connected to circuit
ground. AGND and DGND pins should be at the same voltage
potential. Any unused potentiometers in a package should be
connected to ground. Power supply rejection is typically −35 dB
at 10 kHz. Care is needed to minimize power supply ripple in
high accuracy applications.
Rev. E | Page 23 of 32
AD8400/AD8402/AD8403
APPLICATIONS
256
The digital potentiometer (RDAC) allows many of the applications of a mechanical potentiometer to be replaced by a solidstate solution offering compact size and freedom from vibration,
shock, and open contact problems encountered in hostile
environments. A major advantage of the digital potentiometer
is its programmability. Any settings can be saved for later recall
in system memory.
DIGITAL CODE (Decimal)
224
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and
the rheostat (2-terminal configuration) connections shown
in Figure 37 and Figure 38.
192
160
128
96
64
0
0.1
1
10
INVERTING GAIN (V/V)
Figure 54. Inverting Programmable Gain Plot
ACTIVE FILTER
The state variable active filter is one of the standard circuits
used to generate a low-pass, high-pass, or band-pass filter.
The digital potentiometer allows full programmability of the
frequency, gain, and Q of the filter outputs. Figure 55 shows
the filter circuit using a 2.5 V virtual ground, which allows a
±2.5 VP input and output swing. RDAC2 and RDAC3 set the
LP, HP, and BP cutoff and center frequencies, respectively.
These variable resistors should be programmed with the same
data (as with ganged potentiometers) to maintain the best
Circuit Q. Figure 56 shows the measured filter response at the
band-pass output as a function of the RDAC2 and RDAC3
settings that produce a range of center frequencies from 2 kHz
to 20 kHz. The filter gain response at the band-pass output is
shown in Figure 57. At a center frequency of 2 kHz, the gain is
adjusted over a −20 dB to +20 dB range determined by RDAC1.
Circuit Q is adjusted by RDAC4. For more detailed reading on
the state variable active filter, see Analog Devices’ application
note AN-318.
10kΩ
RDAC4
10kΩ
B
0.01μF
0.01μF
VIN
B RDAC1 A1
B
A2
RDAC2
A3
LOWPASS
B
RDAC3
A4
OP279 × 2
BANDPASS
HIGHPASS
Figure 55. Programmable State Variable Active Filter
Rev. E | Page 24 of 32
01092-054
Certain boundary conditions must be satisfied for proper
AD8400/AD8402/AD8403 operation. First, all analog signals
must remain within the GND to VDD range used to operate the
single-supply AD8400/AD8402/AD8403. For standard
potentiometer divider applications, the wiper output can be
used directly. For low resistance loads, buffer the wiper with
a suitable rail-to-rail op amp such as the OP291 or the OP279.
Second, for ac signals and bipolar dc adjustment applications,
a virtual ground is generally needed. Whichever method is used
to create the virtual ground, the result must provide the necessary
sink and source current for all connected loads, including
adequate bypass capacitance. Figure 41 shows one channel of
the AD8402 connected in an inverting programmable gain
amplifier circuit. The virtual ground is set at 2.5 V, which allows
the circuit output to span a ±2.5 V range with respect to virtual
ground. The rail-to-rail amplifier capability is necessary for the
widest output swing. As the wiper is adjusted from its midscale
reset position (80H) toward the A terminal (code FFH), the
voltage gain of the circuit is increased in successively larger
increments. Alternatively, as the wiper is adjusted toward the B
terminal (code 00H), the signal becomes attenuated. The plot in
Figure 54 shows the wiper settings for a 100:1 range of voltage
gain (V/V). Note the ±10 dB of pseudologarithmic gain around
0 dB (1 V/V). This circuit is mainly useful for gain adjustments
in the range of 0.14 V/V to 4 V/V; beyond this range the step
sizes become very large, and the resistance of the driving circuit
can become a significant term in the gain equation.
01092-053
32
AD8400/AD8402/AD8403
40
40
–19.01
20.0000 k
20
20
0
0
AMPLITUDE (dB)
–20
–40
–60
–20
–40
–60
20
100
1k
10k
FREQUENCY (Hz)
100k 200k
01092-055
–80
2.00000 k
–80
20
Figure 56. Programmed Center Frequency Band-Pass Response
100
1k
10k
FREQUENCY (Hz)
100k 200k
Figure 57. Programmed Amplitude Band-Pass Response
Rev. E | Page 25 of 32
01092-056
AMPLITUDE (dB)
–0.16
AD8400/AD8402/AD8403
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 58. 8-Lead Standard Small outline package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
8
1
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 59. 14-Lead Plastic Dual-In-Line Package [PDIP]
Narrow Body (N-14)
Dimensions shown in inches and (millimeters)
Rev. E | Page 26 of 32
070606-A
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
AD8400/AD8402/AD8403
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
8
14
1
7
6.20 (0.2441)
5.80 (0.2283)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 60. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. E | Page 27 of 32
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
AD8400/AD8402/AD8403
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
13
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
12
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
071006-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 62. 24-Lead Plastic Dual-In-Line Package [PDIP]
Narrow Body (N-24-1)
Dimensions shown in inches and (millimeters)
15.60 (0.6142)
15.20 (0.5984)
13
24
7.60 (0.2992)
7.40 (0.2913)
12
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
45°
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 63. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-24)
Dimensions shown in millimeters and (inches)
Rev. E | Page 28 of 32
1.27 (0.0500)
0.40 (0.0157)
06-07-2006-A
1
AD8400/AD8402/AD8403
7.90
7.80
7.70
24
13
4.50
4.40
4.30
6.40 BSC
1
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
1.20
MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 64. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
Rev. E | Page 29 of 32
AD8400/AD8402/AD8403
ORDERING GUIDE
Model1, 2, 3
AD8400AR10
AD8400AR10-REEL
AD8400ARZ10
AD8400ARZ10-REEL
AD8400AR50
AD8400AR50-REEL
AD8400ARZ50
AD8400ARZ50-REEL
AD8400AR100
AD8400AR100-REEL
AD8400ARZ100
AD8400ARZ100-REEL
AD8400AR1
AD8400AR1-REEL
AD8400ARZ1
AD8400ARZ1-REEL
AD8402AN10
AD8402ANZ10
AD8402AR10
AD8402AR10-REEL
AD8402ARU10
AD8402ARU10-REEL
AD8402ARUZ10
AD8402ARUZ10-REEL
AD8402ARZ10
AD8402ARZ10-REEL
AD8402AR50
AD8402AR50-REEL
AD8402ARU50
AD8402ARU50-REEL
AD8402ARUZ50
AD8402ARUZ50-REEL
AD8402ARZ50
AD8402ARZ50-REEL
AD8402AR100
AD8402AR100-REEL
AD8402ARU100
AD8402ARU100-REEL
AD8402ARUZ100
AD8402ARUZ100-REEL
AD8402ARZ100
AD8402ARZ100-REEL
AD8402AR1
AD8402AR1-REEL
AD8402ARU1
AD8402ARUZ1
AD8402ARUZ1-REEL
AD8402ARZ1
AD8402ARZ1-REEL
Number of
Channels
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
End-to-End
RAB (kΩ)
10
10
10
10
50
50
50
50
100
100
100
100
1
1
1
1
10
10
10
10
10
10
10
10
10
10
50
50
50
50
50
50
50
50
100
100
100
100
100
100
100
100
1
1
1
1
1
1
1
Temperature
Range (°C)
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
Package
Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
14-Lead PDIP
14-Lead PDIP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
Rev. E | Page 30 of 32
Package
Option
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
N-14
N-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
R-14
R-14
Ordering
Quantity
98
2,500
98
2,500
98
2,500
98
2,500
98
2,500
98
2,500
98
2,500
98
2,500
25
25
56
2,500
96
2,500
96
2,500
96
2,500
56
2,500
96
2,500
96
2,500
96
2,500
56
2,500
96
2,500
96
2,500
96
2,500
56
2,500
96
96
2,500
56
2,500
Branding Information
AD8400A10
AD8400A10
AD8400A10
AD8400A10
AD8400A50
AD8400A50
AD8400A50
AD8400A50
AD8400AC
AD8400AC
AD8400AC
AD8400AC
AD8400A1
AD8400A1
AD8400A1
AD8400A1
AD8402A10
AD8402A10
AD8402A10
AD8402A10
8402A10
8402A10
8402A10
8402A10
AD8402A10
AD8402A10
AD8402A50
AD8402A50
8402A50
8402A50
8402A50
8402A50
AD8402A50
AD8402A50
AD8402AC
AD8402AC
8402A-C
8402A-C
8402A-C
8402A-C
AD8402AC
AD8402AC
AD8402A1
AD8402A1
8402A1
AD8402A1
AD8402A1
AD8402A1
AD8402A1
AD8400/AD8402/AD8403
Model1, 2, 3
AD8403AN10
AD8403AR10
AD8403AR10-REEL
AD8403ARU10
AD8403ARU10-REEL
AD8403ARUZ10
AD8403ARUZ10-REEL
AD8403ARZ10
AD8403ARZ10-REEL
AD8403AN50
AD8403AR50
AD8403AR50-REEL
AD8403ARU50
AD8403ARUZ50
AD8403ARUZ50-REEL
AD8403ARZ50
AD8403ARZ50-REEL
AD8403AR100
AD8403AR100-REEL
AD8403ARU100
AD8403ARU100-REEL
AD8403ARUZ100
AD8403ARUZ100-REEL
AD8403ARZ100
AD8403ARZ100-REEL
AD8403AR1
AD8403AR1-REEL
AD8403ARU1
AD8403ARU1-REEL
AD8403ARUZ1
AD8403ARUZ1-REEL
AD8403ARZ1
AD8403ARZ1-REEL
AD8403WARZ50-REEL
EVAL-AD8403SDZ
Number of
Channels
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
End-to-End
RAB (kΩ)
10
10
10
10
10
10
10
10
10
50
50
50
50
50
50
50
50
100
100
100
100
100
100
100
100
1
1
1
1
1
1
1
1
50
Temperature
Range (°C)
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
Package
Description
24-Lead PDIP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead PDIP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
Evaluation Board
Package
Option
N-24-1
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
RW-24
RW-24
N-24-1
RW-24
RW-24
RU-24
RU-24
RU-24
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
RW-24
RW-24
RW-24
Ordering
Quantity
15
31
1,000
63
2,500
63
2,500
63
2,500
15
31
1,000
63
2,500
2,500
63
2,500
31
1,000
63
2,500
63
2,500
63
2,500
31
1,000
63
2,500
63
2,500
63
2,500
2,500
Branding Information
AD8403A10
AD8403A10
AD8403A10
8403A10
8403A10
8403A10
8403A10
AD8403A10
AD8403A10
AD8403A50
AD8403A50
AD8403A50
8403A50
8403A50
8403A50
AD8403A50
AD8403A50
AD8403A100
AD8403A100
8403A100
8403A100
8403A100
8403A100
AD8403A100
AD8403A100
AD8403A1
AD8403A1
8403A1
8403A1
8403A1
8403A1
AD8403A1
AD8403A1
1
Non-lead-free parts have date codes in the format of either YWW or YYWW, and lead-free parts have date codes in the format of #YWW, where Y/YY is the year of
production and WW is the work week. For example, a non-lead-free part manufactured in the 30th work week of 2005 has the date code of either 530 or 0530, while a
lead-free part has the date code of #530.
2
Z = RoHS Compliant Part.
3
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD8403W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. E | Page 31 of 32
AD8400/AD8402/AD8403
NOTES
© 2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01092-0-7/10(E)
Rev. E | Page 32 of 32