AD AN-414 Quad 150 mhz rail-to-rail amplifier Datasheet

a
Quad 150 MHz
Rail-to-Rail Amplifier
AD8044
FEATURES
Single AD8041 and Dual AD8042 Also Available
Fully Specified at +3 V, +5 V, and ⴞ5 V Supplies
Output Swings to Within 25 mV of Either Rail
Input Voltage Range Extends 200 mV Below Ground
No Phase Reversal with Inputs 1 V Beyond Supplies
Low Power of 2.75 mA/Amplifier
High Speed and Fast Settling on +5 V
150 MHz –3 dB Bandwidth (G = +1)
170 V/␮s Slew Rate
40 ns Settling Time to 0.1%
Good Video Specifications (RL = 150 ⍀, G = +2)
Gain Flatness of 0.1 dB to 12 MHz
0.06% Differential Gain Error
0.15ⴗ Differential Phase Error
Low Distortion
–68 dBc Total Harmonic @ 5 MHz
Outstanding Load Drive Capability
Drives 30 mA 0.5 V from Supply Rails
APPLICATIONS
Active Filters
Video Switchers
Distribution Amplifiers
A/D Driver
Professional Cameras
CCD Imaging Systems
Ultrasound Equipment (Multichannel)
CONNECTION DIAGRAM
14-Lead Plastic DIP and SOIC
OUT A
1
14 OUT D
–IN A
2
13 –IN D
+IN A
3
V+
4
+IN B
5
10 +IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
12 +IN D
AD8044
11 V–
TOP VIEW
The output voltage swing extends to within 25 mV of each rail,
providing the maximum output dynamic range. Additionally, it
features gain flatness of 0.1 dB to 12 MHz, while offering differential gain and phase error of 0.04% and 0.22∞ on a single +5 V
supply. This makes the AD8044 useful for video electronics,
such as cameras, video switchers, or any high speed portable
equipment. The AD8044’s low distortion and fast settling make
it ideal for active filter applications.
The AD8044 offers low power supply current of 13.1 mA max
and can run on a single +3.3 V power supply. These features are
ideally suited for portable and battery-powered applications
where size and power are critical.
PRODUCT DESCRIPTION
The AD8044 is a quad, low power, voltage feedback, high
speed amplifier designed to operate on +3 V, +5 V, or ± 5 V
supplies. It has true single-supply capability with an input voltage range extending 200 mV below the negative rail and within
1 V of the positive rail.
The wide bandwidth of 150 MHz, along with 170 V/ms of slew
rate on a single +5 V supply, make the AD8044 useful in many
general-purpose, high speed applications where dual power
supplies of up to ± 6 V and single supplies from +3 V to +12 V
are needed. The AD8044 is available in 14-lead PDIP and
SOIC.
18
VS = +5V
G = +1
15
5V
2.5V
NORMALIZED GAIN (dB)
12
VS = +5V
9
6
3
0
–3
–6
0V
–9
1V
2␮s
Figure 1. Output Swing: Gain = –1, RL = 2 kW
–12
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 2. Frequency Response: Gain = +1, VS = +5 V
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
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IMPORTANT LINKS for the AD8044*
Last content update 08/19/2013 03:06 pm
PARAMETRIC SELECTION TABLES
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
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DOCUMENTATION
AN-581: Biasing and Decoupling Op Amps in Single Supply
Applications
AN-402: Replacing Output Clamping Op Amps with Input Clamping
Amps
AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design
Constraints in Low Voltage High Speed Systems
AN-414: Low Cost, Low Power Devices for HDSL Applications
MT-060: Choosing Between Voltage Feedback and Current Feedback
Op Amps
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps
MT-056: High Speed Voltage Feedback Op Amps
MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR
MT-052: Op Amp Noise Figure: Don’t Be Mislead
MT-050: Op Amp Total Output Noise Calculations for Second-Order
System
MT-049: Op Amp Total Output Noise Calculations for Single-Pole
System
MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and
Equivalent Noise Bandwidth
MT-047: Op Amp Noise
MT-033: Voltage Feedback Op Amp Gain and Bandwidth
MT-032: Ideal Voltage Feedback (VFB) Op Amp
A Stress-Free Method for Choosing High-Speed Op Amps
UG-111: Universal Evaluation Board for Quad, High Speed Op Amps
Offered in 14-Lead SOIC Packages
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SAMPLE & BUY
EVALUATION KITS & SYMBOLS & FOOTPRINTS
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AD8044
View Price & Packaging
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* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
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This content may be frequently modified.
AD8044–SPECIFICATIONS (@ T = +25ⴗC, V = +5 V, R = 2 k⍀ to 2.5 V, unless otherwise noted.)
A
S
L
Parameter
Conditions
Min
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 1%
Settling Time to 0.1%
G = +1
G = +2, RL = 150 W
G = –1, VO = 4 V Step
VO = 2 V p-p
G = –1, VO = 2 V Step
80
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
AD8044A
Typ
140
fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kW
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 W to 2.5 V
G = +2, RL = 150 W to 2.5 V
f = 5 MHz, RL = 1 kW, G = +2
DC PERFORMANCE
Input Offset Voltage
MHz
MHz
V/ms
MHz
ns
ns
–68
16
850
0.04
0.22
–60
dB
nV/÷Hz
fA/÷Hz
%
Degrees
dB
1.0
8
2
TMIN –TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
RL = 1 kW
TMIN –TMAX
82
VCM = 0 V to 3.5 V
80
RL = 10 kW to 2.5 V
RL = 1 kW to 2.5 V
RL = 150 W to 2.5 V
TMIN –TMAX, VOUT = 0.5 V to 4.5 V
Sourcing
Sinking
G = +2
0.25 to 4.75
0.55 to 4.4
0.2
94
88
70
OPERATING TEMPERATURE RANGE
–40
6
8
4.5
4.5
1.2
mV
mV
mV/∞C
mA
mA
mA
dB
dB
225
1.6
–0.2 to 4
90
kW
pF
V
dB
0.03 to 4.975
0.075 to 4.91
0.25 to 4.65
30
45
85
40
V
V
V
mA
mA
mA
pF
3
VS = 0, +5 V, ± 1 V
Units
150
12
170
26
30
40
TMIN –TMAX
Offset Drift
Input Bias Current
Max
11
80
12
13.1
V
mA
dB
+85
∞C
Specifications subject to change without notice.
–2–
REV. B
SPECIFICATIONS (@ T = +25ⴗC, V = +3 V, R = 2 k⍀ to 1.5 V, unless otherwise noted.)
A
S
Parameter
Conditions
Min
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 1%
Settling Time to 0.1%
G = +1
G = +2, RL = 150 W
G = –1, VO = 2 V Step
VO = 2 V p-p
G = –1, VO = 2 V Step
80
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
AD8044
L
110
fC = 5 MHz, VO = 2 V p-p, G = –1, RL = 100 W
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 W to 1.5 V, Input VCM = 0.5 V
G = +2, RL = 150 W to 1.5 V, Input VCM = 0.5 V
f = 5 MHz, RL = 1 kW, G = +2
DC PERFORMANCE
Input Offset Voltage
AD8044A
Typ
MHz
MHz
V/ms
MHz
ns
ns
–48
16
600
0.13
0.3
–60
dB
nV/÷Hz
fA/÷Hz
%
Degrees
dB
1.5
8
2
TMIN –TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
RL = 1 kW
TMIN –TMAX
80
RL = 10 kW to 1.5 V
RL = 1 kW to 1.5 V
RL = 150 W to 1.5 V
TMIN –TMAX, VOUT = 0.5 V to 2.5 V
Sourcing
Sinking
G = +2
0.025 to 2.98
0.17 to 2.82 0.06 to 2.93
0.35 to 2.55 0.15 to 2.75
25
30
50
35
3
70
0
Specifications subject to change without notice.
–3–
5.5
7.5
4.5
4.5
1.2
225
1.6
–0.2 to 2
90
76
OPERATING TEMPERATURE RANGE
REV. B
0.2
92
88
VCM = 0 V to 1.5 V
VS = 0, +3 V, +0.5 V
Units
135
10
150
22
35
55
TMIN –TMAX
Offset Drift
Input Bias Current
Max
10.5
80
mV
mV
mV/∞C
mA
mA
mA
dB
dB
kW
pF
V
dB
V
V
V
mA
mA
mA
pF
12
12.5
V
mA
dB
+70
∞C
AD8044–SPECIFICATIONS (@ T = +25ⴗC, V = ⴞ5 V, R = 2 k⍀ to 0 V, unless otherwise noted.)
A
S
L
Parameter
Conditions
Min
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
Settling Time to 0.01%
G = +1
G = +2, RL = 150 W
G = –1, VO = 8 V Step
VO = 2 V p-p
G = –1, VO = 2 V Step
85
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
150
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 W
G = +2, RL = 150 W
f = 5 MHz, RL = 1 kW, G = +2
DC PERFORMANCE
Input Offset Voltage
AD8044A
Typ
MHz
MHz
V/ms
MHz
ns
ns
–72
16
900
0.06
0.15
–60
dB
nV/÷Hz
fA/÷Hz
%
Degrees
dB
1.4
10
2
TMIN –TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
RL = 1 kW
TMIN –TMAX
82
VCM = –5 V to 3.5 V
RL = 10 kW
RL = 1 kW
RL = 150 W
TMIN –TMAX, VOUT = –4.5 V to +4.5 V
Sourcing
Sinking
G = +2
76
–4.6 to +4.6
–4.0 to +3.8
0.2
96
92
OPERATING TEMPERATURE RANGE
70
–40
6.5
9
4.5
4.5
1.2
mV
mV
mV/∞C
mA
mA
mA
dB
dB
225
1.6
–5.2 to 4
90
kW
pF
V
dB
–4.97 to +4.97
–4.85 to +4.85
–4.5 to +4.5
30
60
100
40
V
V
V
mA
mA
mA
pF
3
VS = –5, +5 V, ± 1 V
Units
160
15
190
29
30
40
TMIN –TMAX
Offset Drift
Input Bias Current
Max
11.5
80
12
13.6
V
mA
dB
+85
∞C
Specifications subject to change without notice.
–4–
REV. B
AD8044
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V
Internal Power Dissipation2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . 1.6 Watts
Small Outline Package (R) . . . . . . . . . . . . . . . . . . 1.0 Watts
Input Voltage (Common-Mode) . . . . . . . . . . . . . . ± VS ± 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 3.4 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (N, R) . . . . . . . –65∞C to +125∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for the device in free air:
14-Lead Plastic Package: qJA = 75∞C/W
14-Lead SOIC Package: qJA = 120∞C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8044 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature
of the plastic, approximately +150∞C. Exceeding this limit
temporarily may cause a shift in parametric performance due to
a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175∞C for an extended
period can result in device failure.
While the AD8044 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction temperature (+150∞C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
2.5
TJ = +150 C
MAXIMUM POWER DISSIPATION (W)
ABSOLUTE MAXIMUM RATINGS 1
2.0
14-LEAD PLASTIC DIP PACKAGE
1.5
14-LEAD SOIC
1.0
0.5
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE (ⴗC)
80 90
Figure 3. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD8044AN
AD8044AR-14
AD8044AR-14-REEL
AD8044AR-14-REEL7
AD8044ARZ-14*
AD8044ARZ-14-REEL*
AD8044ARZ-14-REEL7*
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
14-Lead PDIP
14-Lead SOIC
14-Lead SOIC 13" REEL
14-Lead SOIC 7" REEL
14-Lead Plastic SOIC
14-Lead SOIC 13" REEL
14-Lead SOIC 7" REEL
N-14
R-14
R-14
R-14
R-14
R-14
R-14
*Z = Pb free part
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE
AD8044–Typical Performance Characteristics
100
11
VS = +5V
TA = +25ⴗC
62 PARTS
MEAN = 350␮V
STD DEVIATION = 560␮V
NUMBER OF PARTS IN BIN
9
8
95
OPEN-LOOP GAIN (dB)
10
7
6
5
4
3
2
90
85
VS = +5V
T = +25ⴗC
80
75
1
0
–3 –2.5 –2 –1.5 –1 –0.5 0 0.5
VOS (mV)
70
1
1.5
2
2.5
0
3
Figure 4. Typical Distribution of VOS
750
1000 1250
1500
LOAD RESISTANCE (⍀)
1750
2000
100
VS = +5V
RL = 1k⍀ TO +2.5V
MEAN = 7.9␮V/ⴗC
STD DEV = 2.3␮V/ⴗC
SAMPLE SIZE = 62
VS = +5
97
OPEN-LOOP GAIN (dB)
NUMBER OF PARTS IN BIN
500
Figure 7. Open-Loop Gain vs. RL to +2.5 V
15
12
250
9
6
94
91
3
88
0
2.0 3.0
85
–40
4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0
VOS DRIFT (␮V/ⴗC)
Figure 5. VOS Drift Over –40 ∞C to +85 ∞C
–20
0
20
40
60
TEMPERATURE (ⴗC)
80
100
Figure 8. Open-Loop Gain vs. Temperature
2.4
100
VS = +5V
90
RL = 500⍀
VS = +5V
OPEN-LOOP GAIN (dB)
INPUT BIAS CURRENT ( ␮A)
80
2.2
2.0
1.8
70
RL = 50⍀
60
50
40
30
20
10
0
–45 –35 –25 –15 –5
5 15 25 35 45 55
TEMPERATURE (ⴗC)
65
0
75 85
Figure 6. IB vs. Temperature
0 0.15 0.35 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.45 4.65 4.85 5
OUTPUT VOLTAGE (V)
Figure 9. Open-Loop Gain vs. Output Voltage
–6–
REV. B
AD8044
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
–0.04
VS = +5V
G = +2
RL = 150⍀
DIFF GAIN (%)
100
30
0
DIFF PHASE (Degrees)
INPUT VOLTAGE NOISE (nV/ Hz)
300
10
3
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0.20
0.15
0.10
0.05
0.00
–0.05
–0.10
–0.15
–0.20
0
10
20
30
40
50
60
70
80
90
100
VS = +5V
G = +2
RL = 150⍀
10
20
30
40
50
60 70
80
MODULATING RAMP LEVEL (IRE)
90
100
Figure 10. Input Voltage Noise vs. Frequency
Figure 13. Differential Gain and Phase Errors
–30
VS = +3V,
RL = 100⍀
AV = –1
–50
VS = +5V,
RL = 100⍀
AV = +1
VS = +5V,
RL = 100⍀
AV = +2
0.3
0.2
0.1
NORMALIZED GAIN (dB)
TOTAL HARMONIC DISTORTION (dBc)
VO = 2V p-p
–40
–60
–70
–80
VS = +5V,
RL = 1k⍀
AV = +2
–90
–100
1
VS = +5V,
RL = 1k⍀
AV = +1
2
3
4
5
6 7
FUNDAMENTAL FREQUENCY (MHz)
11.6MHz
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
VS = +5V
RF = 200⍀
RL = 150⍀ TO 2.5V
G = +2
Vi = 0.2V p-p
8 9 10
–0.6
1M
10M
FREQUENCY (Hz)
Figure 11. Total Harmonic Distortion
100M
Figure 14. 0.1 dB Gain Flatness
–30
80
10MHz
–60
60
–70
–80
5MHz
–90
1MHz
–100
–110
VS = +5V
RL = 2k⍀ TO 2.5V
G = +2
–120
–130
–140
VS = +5V
RL = 2k⍀
CL = 5pF
70
OPEN-LOOP GAIN (dB)
WORST HARMONIC (dBc)
–50
50
40
GAIN
30
180
20
90
0
45
–10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
–20
30k
OUTPUT VOLTAGE (V p-p)
Figure 12. Worst Harmonic vs. Output Voltage
135
PHASE
10
80MHz
100k
10M
1M
FREQUENCY (Hz)
0
100M
Figure 15. Open-Loop Gain and Phase Margin
vs. Frequency
REV. B
–7–
PHASE MARGIN (Degrees)
–40
AD8044
4
CLOSED-LOOP GAIN (dB)
2
1
VS = +3V, 0.1%
VS = +5V, 0.1% AND
VS = ⴞ5V, 0.1%
50
0
–1
40
30
–2
VS = +3V, 1%
20
VS = +5V, 1% AND
VS = ⴞ5V, 1%
–3
10
–4
–5
1M
10M
FREQUENCY (Hz)
0
0.5
100M
6
5
4
3
1
1.5
INPUT STEPS (V p-p)
2
Figure 19. Settling Time vs. Input Step
Figure 16. Closed-Loop Frequency Response
vs. Temperature
0
G = +1
RL = 2k⍀
CL = 5pF
VO = 0.2V p-p
+3V
–10
VS = ⴞ5V
+5V
–20
ⴞ5V
2
CMRR (dB)
CLOSED-LOOP GAIN (dB)
G = –1
RL = 2k⍀
60
TIME (ns)
3
70
+85ⴗC
+25ⴗC
–40ⴗC
VS = +5V
RL = 2k⍀ TO 2.5V
CL = 5pF
G = +1
VO = 0.2V p-p
1
0
–30
VS = +3V
–40
–50
ⴞ5V
–1
–60
–2
+3V
–3
–70
+5V
–4
100k
1M
10M
FREQUENCY (Hz)
–80
0.03
100M
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 20. CMRR vs. Frequency
Figure 17. Closed-Loop Frequency Response vs. Supply
1.00
OUTPUT RESISTANCE (⍀)
100
10
OUTPUT SATURATION VOLTAGE (V)
RBT = 50⍀
G = +1
VS = +5V
RBT
1
VOUT
RBT = 0⍀
0.1
0.01
0.03
VS = +5V
0.875
+5V –VOH (+125ⴗC)
0.750
+5V –VOH (+25ⴗC)
0.625
+5V –VOH (–55ⴗC)
0.500
0.375
0.250
VOL (+125ⴗC)
0.125
VOL (–55ⴗC)
0.1
1
10
FREQUENCY (MHz)
100
0.00
500
0
3
6
9
VOL (+25ⴗC)
12
15
18
21
LOAD CURRENT (mA)
24
27
30
Figure 21. Output Saturation Voltage vs. Load Current
Figure 18. Output Resistance vs. Frequency
–8–
REV. B
AD8044
60
12.0
G = +2, RS = 0⍀,
VO = 100mV STEP
RF = RG = 750⍀
G = +1, RS = 20⍀,
VO = 100mV STEP
VS = ⴞ5V
50
VS = +5V
11.0
% OVERSHOOT
SUPPLY CURRENT (mA)
11.5
VS = +3V
10.5
10.0
40
RF = 0, RG =
G = +1, RS = 40⍀,
VO = 100mV STEP
30
G = +3, RS = 0⍀,
VO = 150mV STEP
RF = 750⍀
RG = 375⍀
RG
RF = 0, RG =
RF
+2.5V
VOUT
20
VIN
50⍀
10
RS
–2.5V
9.5
0
9.0
–40
–20
0
20
40
60
TEMPERATURE (ⴗC)
80
2
10
VS = +5V
NORMALIZED OUTPUT (dB)
1
–10
PSRR (dB)
–PSRR
–20
–30
+PSRR
–40
–50
1
10
FREQUENCY (MHz)
100
–4
–7
100k
500
G = +2
G = +5
–3
–6
VS = +5V
RL = 5k⍀ TO 2.5V
RF = 2k⍀
G = +10
1M
10M
FREQUENCY (Hz)
100M
500M
Figure 26. Frequency Response vs. Closed-Loop Gain
10
–10
VS = ⴞ5V
RL = 2k⍀
9
–20
8
–30
7
–40
CROSSTALK (dB)
VOUT p-p (V)
250
–2
–70
0.1
G = +2
RL = 150⍀ TO 2.5V
RF = 200⍀
–1
–5
Figure 23. PSRR vs. Frequency
6
5
4
VS = ⴞ5V
VIN = 1V p-p
G = +2
RF = 1k⍀
RL = 100⍀
–50
–60
–70
RL = 1k⍀
–80
3
2
–90
1
–100
1
10
FREQUENCY (MHz)
100
–110
0.1
500
Figure 24. Output Voltage Swing vs. Frequency
REV. B
200
0
–60
0
0.1
100
150
LOAD CAPACITANCE (pF)
3
20
–80
0.01
50
Figure 25. % Overshoot vs. Capacitive Load
Figure 22. Supply Current vs. Temperature
0
0
100
1
10
FREQUENCY (MHz)
100
400
Figure 27. Crosstalk (Output to Output) vs. Frequency
–9–
AD8044
5V
4.656V
2.6V
VS = +5V
G = +1
RL = 2k⍀
CL = 5pF
VS = +5V
RL = 150⍀ TO +2.5V
2.55V
CL = 5pF
G = –1
2.5V
2.5V
2.45V
0.211V
500mV
0V
2.4V
100␮s
50mV
Figure 28a. Output Swing vs. Load Reference Voltage,
VS = +5 V, G = –1
40ns
Figure 30. 100 mV Step Response, VS = +5 V, G = +1
5V
3V
4.309V
+2.920V
VS = +5V
RL = 150⍀ TO GND
CL = 5pF
G = –1
VIN = 3V p-p
RL = 2k⍀
CL = 5pF
VS = +3V
G = –1
2.5V
2V
2.5V
1.5V
1V
500mV
+10mV
0.5V
100␮s
+22mV
500mV
200␮s
0V
Figure 31. Output Swing, VS = +3 V
Figure 28b. Output Swing vs. Load Reference Voltage,
VS = +5 V, G = –1
1.60V
4.5V
3.5V
VIN = 0.1V p-p
RL = 2k⍀
CL = 5pF
VS = +3V
1.58V
VS = +5V
G = +2
RL = 2k⍀
VIN = 1V p-p
CL = 5pF
1.56V
1.54V
G = +1
1.52V
1.50V
2.5V
1.48V
1.46V
1.5V
1.44V
500mV
1.42V
20ns
20mV
20ns
1.40V
0.5V
Figure 32. Step Response, G = +1, VIN = 100 mV
Figure 29. One Volt Step Response, VS = +5 V, G = +2
–10–
REV. B
AD8044
Overdrive Recovery
Driving Capacitance Loads
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 33, the AD8044 recovers
within 50 ns from negative overdrive and within 25 ns from
positive overdrive.
The capacitive load drive of the AD8044 can be increased by
adding a low valued resistor in series with the load. Figure 35
shows the effects of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor with lower closed-loop gains
accomplishes this same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and capacitive load.
VS = +5V
AV = +2
RF = 2k⍀
RL = 2k⍀
VOUT
1V/DIV
VCC
I1
VIN
2V/DIV
I10
R26
I2
I3
R39
Q4
Q25
Q36
Q5
Q51
Q39
I5
Q23
Q40
R15 R2
Q22
VEE
VINP
1V
SIP
50ns
The AD8044 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process which
enables the construction of PNP and NPN transistors with
similar fTs in the 2 GHz–4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems
caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply
currents. This design uses a differential output input stage to
maximize bandwidth and headroom (see Figure 34). The
smaller signal swings required on the first stage outputs (nodes
S1P, S1N) reduce the effect of nonlinear currents due to
junction capacitances and improve the distortion performance.
With this design harmonic distortion of better than –85 dB
@ 1 MHz into 100 W with VOUT = 2 V p-p (Gain = +2) on a
single 5 volt supply is achieved.
The AD8044’s rail-to-rail output range is provided by a complementary common-emitter output stage. High output drive capability is provided by injecting all output stage predriver currents
directly into the bases of the output devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along with a
common-mode feedback loop (not shown). This circuit topology allows the AD8044 to drive 50 mA of output current with
the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from –0.2 V
below the negative rail to within 1.2 V of the positive rail. Exceeding these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
REV. B
C9
–11–
Q8
Q11
Q3
C7
VOUT
Q27
SIN
Q2
Figure 33. Overdrive Recovery, VS + 5 V, VIN = 4 V Step
Circuit Description
C3
Q31
Q21
VINN
2V
VEE
R23 R27
Q7
Q17
Q13
I9
Q50
R5
Q24
R21
R3
I7
Q47
I8
I11
VEE
Figure 34. AD8044 Simplified Schematic
VCC
AD8044
+5V
1000
GRAPHICS
IC
CAPACITIVE LOAD (pF)
VS = +5V
< 30% OVERSHOOT
RS
R
0⍀
=1
RS
⍀
=0
75⍀
G
75⍀
100
B
75⍀
RG
RS
VIN
100mV STEP
10
1
75⍀
RF
CL
75⍀
AD8044
2
3
4
5
RGB
MONITOR #1
+3V OR +5V
75⍀
VOUT
0.1␮F
6
ACL (V/V)
A
Figure 35. Capacitive Load Drive vs. Closed-Loop Gain
10␮F
75⍀
V+
1k⍀
APPLICATIONS
RGB Buffer
1k⍀
The AD8044 can provide buffering of RGB signals that include
ground while operating from a single +3 V or +5 V supply.
75⍀
AD8044
75⍀
B
When driving two monitors from the same RGB video source it
is necessary to provide an additional driver for one of the monitors to prevent the double termination situation that the second
monitor presents. This has usually required a dual-supply op
amp because the level of the input signal from the video driver
goes all the way to ground during horizontal blanking. In singlesupply systems it can be a major inconvenience and expense to
add an additional negative supply.
75⍀
1k⍀
1k⍀
75⍀
AD8044
75⍀
C
V–
RGB
MONITOR #2
1k⍀
A single AD8044 can provide the necessary drive capability and
yet does not require a negative supply in this application. Figure 36 is a schematic that uses three amplifiers out of a single
AD8044 to provide buffering for a second monitor.
1k⍀
Figure 36. Single Supply RGB Video Driver
The source of the RGB signals is shown to be from a set of three
current output DACs that are within a single-supply graphics
IC. This is typically the situation in most PCs and workstations
that may use either a standalone triple DAC or DACs that are
integrated into a larger graphics chip.
During horizontal blanking, the current output from the DACs
is turned off and the RGB outputs are pulled to ground by the
termination resistors. If voltage sources were used for the RGB
signals, then the termination resistors near the graphics IC
would be in series and the rest of the circuit would remain the
same. This is because a voltage source is an ac short circuit, so a
series resistor is required to make the drive end of the line see
75 W to ac ground. On the other hand, a current source has a
very high output impedance, so a shunt resistor is required to
make the drive end of the line see 75 W to ground. In either
case, the monitor terminates its end of the line with 75 W.
Figure 37 is an oscilloscope photo of the circuit in Figure 36
operating from a +3 V supply and driven by the Blue signal of a
color bar pattern. Note that the input and output are at ground
during the horizontal blanking interval. The RGB signals are
specified to output a maximum of 700 mV peak. The output of
the AD8044 is 1.4 V with the termination resistors providing a
divide-by-two.
500mV
VIN
5␮s
100
90
GND
VOUT
GND
10
The circuit in Figure 36 shows minimum signal degradation
when using a single-supply for the AD8044. The circuit performs equally well on either a +3 V or +5 V supply.
0%
500mV
Figure 37. +3 V, RGB Buffer
–12–
REV. B
AD8044
Active Filters
Layout Considerations
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
The specified high speed performance of the AD8044 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
Figure 38 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8044 package. Such
circuits are sometimes used in medical ultrasound systems to
lower the noise bandwidth of the analog signal before A/D
conversion.
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the
area near the input pins to reduce the stray capacitance.
R6
1k⍀
C1
50pF
R1
3k⍀
VIN
R2
2k⍀
R4
2k⍀
2
1
C2
50pF
R3
2k⍀ 6
3
7
R5
2k⍀
9
5
AD8044
8
10
AD8044
VOUT
AD8044
Figure 38. 2 MHz Biquad Band-pass Filter Using AD8044
The frequency response of the circuit is shown in Figure 39.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large (0.47 mF
– 10 mF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 W or 75 W and properly terminated at each end.
0
GAIN (dB)
–10
–20
–30
–40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 39. Frequency Response of 2 MHz Band-pass
Biquad Filter
REV. B
–13–
AD8044
OUTLINE DIMENSIONS
14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
Dimensions shown in inches and (millimeters)
0.685 (17.40)
0.665 (16.89)
0.645 (16.38)
14
8
1
7
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
MIN
0.180 (4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56) 0.060 (1.52)
0.018 (0.46) 0.050 (1.27)
0.014 (0.36) 0.045 (1.14)
SEATING
PLANE
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MO-095-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
14
8
1
7
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
ⴛ 45ⴗ
0.25 (0.0098)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–14–
REV. B
AD8044
Revision History
Location
Page
8/04—Data Sheet changed from Rev. A to Rev. B
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REV. B
–15–
–16–
C01060–0–8/04(B)