TI1 CC3220MODSF12MOBR/T Simplelink wi-fi certified wireless module solution Datasheet

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CC3220MOD
SWRS206 – MARCH 2017
CC3220MOD SimpleLink™ Wi-Fi® CERTIFIED® Wireless Module Solution
1 Module Overview
1.1
Features
• CC3220MODS and the CC3220MODSF are Wi-Fi®
Modules that Consist of CC3220SM2ARGK and
CC3220SF12ARGK Single-Chip Wireless MCUs,
respectively. Fully Integrated, Industrial
Temperature Grade Modules Include all Required
Clocks, SPI Flash, and Passives
• CC3220MODx SimpleLink™ Wi-Fi Wireless
Microcontroller Unit (MCU) System-on-Chip (SoC)
is a Single-Chip With Two Separate Execution
Environments:
– User Application Dedicated ARM® Cortex®-M4
MCU
– Network Processor MCU to Run All Wi-Fi and
Internet Logical Layers
• FCC, IC, TELEC, and China Certified
• Wi-Fi CERTIFIED™ Modules, Can Request
Certificate Transfer for Wi-Fi Alliance Members
• 1.27-mm Pitch LGA Package for Easy Assembly
and Low-Cost PCB Design
• Applications MCU Subsystem
– ARM Cortex-M4 Core at 80 MHz
– Embedded Memory
– CC3220MODS Variant Includes 256KB of
RAM
– CC3220MODSF Variant is Flash-Based MCU
with Integrated 1MB of Flash and 256KB of
RAM
– Peripheral Drivers in ROM
– McASP Supports Two I2S Channels
– SD
– SPI
– I2C
– UART
– 8-Bit Parallel Camera
– Four General-Purpose Timers (GPTs) With 16Bit PWM Mode
– One Watchdog Timer Module
– 4-Channel, 12-Bit Analog-to-Digital Converters
(ADCs)
– Debug Interfaces: JTAG, cJTAG, and SWD
• Wi-Fi Network Processor Subsystem
– Wi-Fi Internet-on-a-chip™ Dedicated ARM MCU
Completely Offloads Wi-Fi and Internet
Protocols from the Application MCU
– Wi-Fi Modes
– 802.11b/g/n Station
– 802.11b/g/n Access Point Supports up to
Four Stations
– Wi-Fi Direct® Client and Group Owner
– WPA2 Personal and Enterprise Security:
WEP, WPA, WPA2 PSK, and WPA2
Enterprise (802.1x)
– IPv4 and IPv6 TCP and IP Stack
– Industry-Standard BSD Socket Application
Programming Interfaces (APIs)
– 16 Simultaneous TCP or UDP Sockets
– 6 Simultaneous TLS and SSL Sockets
– IP Addressing: StaticIP, LLA, DHCPv4,
DHCPv6 With DAD
– SimpleLink Technology Connection Manager
for Autonomous and Fast Wi-Fi Connections
– Flexible Wi-Fi Provisioning With
SmartConfig™ Technology, AP Mode, and
WPS2 Options
– RESTful API Support Using Internal HTTP
Server
– Embedded Network Applications Running on
Dedicated Network Processor
– Wide Set of Security Features
– Hardware Features:
– Separation Execution Environments
– Device Identity
– Hardware Crypto Engine for Advanced
Fast Security, Including: AES, DES,
3DES, SHA2, MD5, CRC, and
Checksum
– Initial Secure Programming
– Debug Security
– JTAG and Debug Ports are Locked
– Personal and Enterprise Wi-Fi Security
– Secure Sockets (SSLv3, TLS1.0, TLS1.1,
TLS1.2)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
CC3220MOD
SWRS206 – MARCH 2017
www.ti.com
ADVANCE INFORMATION
– Networking Security
– HTTPS Server
– Trusted Root-Certificate Catalog
– TI Root-of-Trust Public Key
– SW IP Protection
– Secure Key Storage
– File System Security
– Software Tamper Detection
– Cloning Protection
– Secure Boot: Validate Integrity and
Authenticity of Runtime Binary During
Boot
– Embedded Network Applications Running on
Dedicated Network Processor
– HTTP and HTTPS Web Server With
Dynamic User Callbacks
– mDNS, DNS-SD, and DHCP Servers
– Ping
– Recovery Mechanism: Can Recover to
Factory Defaults or to Complete Factory
Image
– Wi-Fi TX Power
– 17.0 dBm at 1 DSSS
– 13.5 dBm at 54 OFDM
– Wi-Fi RX Sensitivity
– –94.7 dBm at 1 DSSS
– –73 dBm at 54 OFDM
– Application Throughput
– UDP: 16 Mbps
– TCP: 13 Mbps
• Power-Management Subsystem
1.2
•
•
•
Applications
Internet of Things (IoT) applications, including:
– Cloud Connectivity
– Internet Gateway
– Home and Building Automation
– Appliances
– Access Control
– Security Systems
1.3
•
– Integrated DC-DC Converter With a
Wide-Supply Voltage:
– VBAT: 2.3 to 3.6 V
– Advanced Low-Power Modes:
– Shutdown: 1 µA
– Hibernate: 6 µA
– Low-Power Deep Sleep (LPDS): 135 µA
(Measured on CC3220MODS and
CC3220MODSF with 256-KB RAM Retention)
– RX Traffic (MCU Active): 59 mA (Measured
on CC3220MODS; CC3220MODSF
Consumes an Additional 15 mA) at 54 OFDM
– TX Traffic (MCU Active): 223 mA (Measured
on CC3220MODS; CC3220MODSF
Consumes an Additional 15 mA) at 54
OFDM, Maximum Power
– Idle Connected (MCU in LPDS): 710 µA
(Measured on CC3220MODS and
CC3220MODSF with 256-KB RAM
Rentention) at DTIM = 1
Additional Integrated Components
– 40.0-MHz Crystal
– 32.768-kHz Crystal (RTC)
– 32-Mbit SPI Serial Flash RF Filter and Passive
Components
LGA Package
– 1.27-mm Pitch, 63-Pin, 20.5-mm × 17.5-mm
LGA Package for Easy Assembly and Low-Cost
PCB Design
Operating Temperature
– Ambient Temperature Range: –40°C to +85°C
Device Supports SimpleLink Developers
Ecosystem
–
–
–
–
–
–
–
Smart Energy
Industrial Control
Smart Plug and Metering
Wireless Audio
IP Network Sensor Nodes
Asset Tracking
Medical Devices
Description
Start your design with the fully programmable FCC, IC, CE, and Wi-Fi Certified wireless microcontroller
(MCU) module with built-in Wi-Fi connectivity. Created for the IoT, the SimpleLink CC3220MODx module
family from Texas Instruments™ is a wireless module that integrates two physically separated on-chip
MCUs.
• An application processor – ARM Cortex-M4 MCU with a user-dedicated 256KB of RAM, and an
optional 1MB of XIP Flash.
• A network processor MCU to run all Wi-Fi and Internet logical layers. This ROM-based subsystem
includes an 802.11b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure
internet connections with 256-bit encryption.
2
Module Overview
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The CC3220MODx wireless MCU family supports the following modes: station, AP, and Wi-Fi Direct. The
CC3220MODx device also supports WPA2 personal and enterprise security. This subsystem includes
embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols. The device
supports a variety of Wi-Fi provisioning methods, including HTTP based on AP mode, SmartConfig
technology, and WPS2.0.
The power-management subsystem includes integrated DC-DC converters that support a wide range of
supply voltages. This subsystem enables low-power consumption modes for extended battery life, such as
low-power deep sleep, hibernate with RTC (consuming only 7µA), and shutdown mode (consuming only 1
µA).
The device includes a wide variety of peripherals, including a fast parallel camera interface, I2S, SD,
UART, SPI, I2C, and a 4-channel ADC.
The SimpleLink CC3220MODx device family comes in two different device variants: CC3220MODS and
CC3220MODSF.
• The CC3220MODS device includes 256KB on application-dedicated embedded RAM for code and
data.
• The CC3220MODSF device includes application-dedicated 1MB of XIP Flash and 256KB of RAM for
code and data.
Both devices integrate the 40-MHz crystal, 32.768-kHz RTC clock, 32-Mb SPI serial Flash, RF filter, and
passive components. The devices also have additional security features, such as encrypted and
authenticated file systems, user IP encryption and authentication, secured boot (authentication and
integrity validation of the application image at Flash boot time), and more.
The CC3220MODx device is part of the SimpleLink microcontroller (MCU) platform which consists of WiFi®, Bluetooth® low energy, Sub-1 GHz and host MCUs. All share a common, easy-to-use development
environment with a single core software development kit (SDK) and rich tool set. A one-time integration of
the SimpleLink platform lets you add any combination of devices from the portfolio into your design. The
ultimate goal of the SimpleLink platform is to achieve 100 percent code reuse when your design
requirements change.
The CC3220MODx device family is a complete platform solution including software, sample applications,
tools, user and programming guides, reference designs, and the E2E™ online community. The module
family is also part of the SimpleLink MCU portfolio and supports the SimpleLink developers ecosystem.
For more information, visit www.ti.com/simplelink.
Device Information
PART NUMBER
PACKAGE
BODY SIZE
CC3220MODSM2MOBR/T
MOB (63)
20.5 mm × 17.5 mm
CC3220MODSF12MOBR/T
MOB (63)
20.5 mm × 17.5 mm
Module Overview
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3
ADVANCE INFORMATION
The CC3220MODx wireless MCU family is part of the second generation of TI's Internet-on-a-chip family
of solutions. This generation introduces new features and capabilities that further simplify the connectivity
of things to the internet. The new capabilities include:
• IPv6
• Enhanced Wi-Fi provisioning
• Optimized low-power management
• Enhanced file-system security
• Wi-Fi AP connection with up to four stations
• More concurrently opened BSD sockets — up to 16 BSD sockets (6 are secure HTTPS support)
• HTTPS support
• RESTful API support
• Asymmetric keys crypto library
CC3220MOD
SWRS206 – MARCH 2017
1.4
www.ti.com
Functional Block Diagrams
Figure 1-1 shows the functional block diagram of the CC3220MODx module.
CC3x20
40 MHz
RF_ANT1
32 kHz
BGN
SPI
MAC/PHY
UART
WRF
F
nReset
ADVANCE INFORMATION
2.3 V to 3.6 V
VBAT
PM
32-Mbit
SFlash
External SPI
Programming
User GPIOs
Copyright © 2017, Texas Instruments Incorporated
Figure 1-1. CC3220MODx Functional Block Diagram
4
Module Overview
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Figure 1-2 shows the an overview of the CC3220MODx hardware.
CC32xx ± Single-Chip Wireless MCU
x
x
x
1-MB Flash (optional)
x
256-kB RAM
ARM®
Cortex®-M4
80 MHz
ROM
2x SPI
2x UART
1x I2S/PCM
DMA
2x SD/MMC
Timers
8-bit Camera
GPIOs
ADVANCE INFORMATION
System
Peripherals
1 I 2C
Application
Protocols
Wi-Fi® Driver
TCP/IP Stack
Oscillators
(ARM Cortex)
DC-DC
ROM
Baseband
MAC
Processor
Radio
Synthesizer
RTC
x
Crypto Engine
RAM
Power
Management
x
Network Processor
x
x
4x ADC
Copyright © 2017, Texas Instruments Incorporated
Figure 1-2. CC3220MODx Hardware Overview
Module Overview
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SWRS206 – MARCH 2017
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Figure 1-3 shows the an overview of the CC3220MODx embedded software.
Customer Application
NetApp
Peripherals
Driver
BSD
Socket
Wi-Fi®
SimpleLinkTM Driver APIs
Host Interface
Network Applications
WLAN Security
and
Management
TCP/IP Stack
ADVANCE INFORMATION
WLAN MAC and PHY
Copyright © 2017, Texas Instruments Incorporated
Figure 1-3. CC3220MODx Embedded Software Overview
6
Module Overview
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Table of Contents
2
3
Module Overview
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagrams ........................... 4
Revision History ......................................... 7
Device Comparison ..................................... 8
4.1
CC3220MODx Pin Diagram ......................... 10
4.2
Pin Attributes ........................................ 11
4.3
Connections for Unused Pins ....................... 12
4.4
4.5
Pin Attributes and Pin Multiplexing.................. 13
Drive Strength and Reset States for Analog-Digital
Multiplexed Pins ..................................... 27
Pad State After Application of Power To Chip, But
Before Reset Release ............................... 28
Specifications ........................................... 29
5.1
Absolute Maximum Ratings ......................... 29
5.2
ESD Ratings
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
6
Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.6
5
1
Features .............................................. 1
3.1
4
........................................
1.1
........................................
Power-On Hours (POH) .............................
Recommended Operating Conditions ...............
Current Consumption (CC3220MODS) .............
Current Consumption (CC3220MODSF)............
.................
Electrical Characteristics ............................
WLAN Receiver Characteristics ....................
WLAN Transmitter Characteristics ..................
Reset Requirement .................................
8
29
29
29
30
31
TX Power and IBAT versus TX Power Level
Settings .............................................. 32
Brownout and Blackout Conditions
7
34
35
37
37
37
Thermal Resistance Characteristics for MOB
Package ............................................. 38
Timing and Switching Characteristics ............... 38
Detailed Description ................................... 50
9
............................................
....
6.3
Wi-Fi Network Processor Subsystem ...............
6.4
Security ..............................................
6.5
Power-Management Subsystem ....................
6.6
Low-Power Operating Mode ........................
6.7
Memory ..............................................
6.8
Restoring Factory Default Configuration ............
6.9
Boot Modes..........................................
6.10 Certification ..........................................
6.11 End Product Labeling ...............................
6.12 Manual Information to the End User ................
Applications, Implementation, and Layout .......
7.1
Typical Application ..................................
7.2
Device Connection and Layout Fundamentals ......
7.3
PCB Layout Guidelines .............................
6.1
Overview
50
6.2
ARM® Cortex®-M4 Processor Core Subsystem
50
50
53
56
56
57
60
60
62
63
63
64
64
65
65
Environmental Requirements and
Specifications ........................................... 71
8.1
Temperature ......................................... 71
8.2
Handling Environment
8.3
Storage Condition ................................... 71
8.4
Baking Conditions ................................... 71
8.5
Soldering and Reflow Condition
..............................
....................
71
71
Device and Documentation Support ............... 73
9.1
Device Support ...................................... 73
9.2
Documentation Support ............................. 73
9.3
Trademarks.......................................... 74
9.4
Electrostatic Discharge Caution ..................... 74
9.5
Export Control Notice
9.6
Glossary ............................................. 74
...............................
74
10 Mechanical, Packaging, and Orderable
Information .............................................. 75
10.1
Mechanical Drawing................................. 75
11 Tape and Reel Information ........................... 78
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
February 2017
SWRS206*
Initial Release
Revision History
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ADVANCE INFORMATION
1
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SWRS206 – MARCH 2017
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3 Device Comparison
Table 3-1 shows the features supported across different CC3x20 devices.
Table 3-1. Device Features Comparison
DEVICE
FEATURE
ADVANCE INFORMATION
CC3120MOD
CC3220MODS
CC3220MODSF
Onboard Chip
CC3120
CC3220S
CC3220SF
Onboard ANT
No
No
No
sFlash
32-Mbit
32-Mbit
32-Mbit
Regulatory Certification
FCC, IC, CE, TELEC, China
FCC, IC, CE, TELEC, China
FCC, IC, CE, TELEC, China
Wi- Fi Alliance Certification
Yes
Yes
Yes
Input Voltage
2.3 V to 3.6 V
2.3 V to 3.6 V
2.3 V to 3.6 V
Package
17.5 mm × 20.5 mm LGA
17.5 mm × 20.5 mm LGA
17.5 mm × 20.5 mm LGA
Operating Temperature Range
–40° to 85°C
–40° to 85°C
–40° to 85°C
Classification
Wi-Fi Network Processor
Wireless Microcontroller
Wireless Microcontroller
Standard
802.11 b/g/n
802.11 b/g/n
802.11 b/g/n
Frequency
2.4 GHz
2.4 GHz
2.4 GHz
TCP / IP Stack
IPv4, IPv6
IPv4, IPv6
IPv4, IPv6
Sockets
16
16
16
Integrated MCU
–
ARM Cortex-M4 at 80 MHz
ARM Cortex-M4 at 80 MHz
On Chip Memory
–
RAM
–
256KB
256KB
Flash
–
–
1MB
Universal Asynchronous
1
Receiver and Transmitter (UART)
2
2
Serial Port Interface (SPI)
1
1
1
Multi-Channel Audio Serial Port
(McASP)- I2S or PCM
–
2-ch
2-ch
Inter-Integrated Circuit (I C)
–
1
1
Analog to Digital Converter
(ADC)
–
4-ch, 12-bit
4-ch, 12-bit
Parallel Interface (8-bit PI)
–
1
1
General Purposes Timers
–
4
4
Multimedia Card (MMC / SD)
–
1
1
Wi-Fi® Level of Security
WEP, WPS, WPA / WPA2 PSK
WPA2 (802.1x)
WEP, WPS, WPA / WPA2 PSK
WPA2 (802.1x)
WEP, WPS, WPA / WPA2 PSK
WPA2 (802.1x)
Secure Sockets (SSL v3 or TLS
1.0 /1.1/ 1.2)
6
6
6
Additional Networking Security
Unique Device Identity
Trusted Root-Certificate
Catalog
TI Root-of-Trust Public key
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Hardware Acceleration
Hardware Crypto Engines
Hardware Crypto Engines
Hardware Crypto Engines
Secure Boot
–
Yes
Yes
–
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
Peripherals and Interfaces
2
Security Features
Enhanced Application Level
Security
8
Device Comparison
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3.1
SWRS206 – MARCH 2017
Related Products
For information about other devices in this family of products or related products see the links below.
The SimpleLink™ MCU Portfolio offers a single development environment that delivers flexible
hardware, software and tool options for customers developing wired and wireless
applications. With 100 percent code reuse across host MCUs, Wi-Fi™, Bluetooth® low
energy, Sub-1GHz devices and more, choose the MCU or connectivity standard that fits your
design. A one-time investment with the SimpleLink software development kit (SDK) allows
you to reuse often, opening the door to create unlimited applications. For more information,
visit www.ti.com/simplelink.
SimpleLink Wi-Fi Family offers several Internet-on-a-chip™ solutions, which address the need of battery
operated, security enabled products. Texas instruments offers a single chip wireless
microcontroller and a wireless network processor which can be paired with any MCU, to
allow developers to design new wi-fi products, or upgrade existing products with wi-fi
capabilities. For more information, visit www.ti.com/simplelinkwifi.
Reference Designs for CC3200 and CC3220 Devices TI Designs Reference Design Library is a robust
reference design library spanning analog, embedded processor and connectivity. Created by
TI experts to help you jump start your system design, all TI Designs include schematic or
block diagrams, BOMs and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
The SimpleLink Wi-Fi CC3220 SDK contains drivers for the CC3220 programmable MCU, sample
applications, and documentation required to start development with CC3220 solutions. For
more information, visit www.ti.com/cc3220sdk.
Device Comparison
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9
ADVANCE INFORMATION
BoosterPack Plug-In Modules extend the functionality of TI LaunchPad Kit . Application specific
BoosterPack Plug in modules allow you to explore a broad range of applications, including
capacitive touch, wireless sensing, LED Lighting control, and more. Stack multiple
BoosterPack modules onto a single LaunchPad kit to further enhance the functionality of
your design. For more information, visit www.ti.com/ww/en/launchpad/boosterpacks.html.
CC3220MOD
SWRS206 – MARCH 2017
www.ti.com
4 Terminal Configuration and Functions
4.1
CC3220MODx Pin Diagram
GND
27
ANT_SEL2
GND
NC
GND
RF_BG
GND
NC
SOP0
nRESET
VBAT_RESET
VBAT1
GND
NC / VBAT3
VBAT2
NC
GPIO30
GND
Figure 4-1 shows the pin diagram for the CC3220MODx device.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
CC3220MODx
GPIO0
26
45
NC
ANT_SEL1
25
46
GPIO1
SOP1
24
47
GPIO2
SOP2
23
48
GPIO3
49
GPIO4
50
GPIO5
51
GPIO6
52
GPIO7
53
GPIO8
54
GPIO9
22
GND
14
13
12
11
10
9
8
7
6
5
GPIO14
4
3
2
1
GND
15
GND
16
GPIO15
GND
GPIO16
17
GND
55
56
GPIO17
FLASH_SPI_MOSI
57
GND
GPIO12
18
GPIO13
JTAG_TDO
GND
58
GPIO22
19
59
JTAG_TDI
GPIO28
60
GND
FLASH_SPI_MISO
20
FLASH_SPI_nCS_IN
NC
FLASH_SPI_CLK
21
61
GND
JTAG_TCK
62
63
GND
GPIO10
JTAG_TMS
GND
GPIO11
ADVANCE INFORMATION
44
NOTE: Figure 4-1 shows the approximate location of pins on the module. For the actual mechanical diagram, see Section 10.
Figure 4-1. CC3220MODx Pin Diagram Bottom View
10
Terminal Configuration and Functions
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4.2
SWRS206 – MARCH 2017
Pin Attributes
Table 4-1 lists the pin descriptions of the CC3220MODx module.
Table 4-1. Module Pin Attributes
NAME
TYPE
CC3220 DEVICE
PIN NO.
MODULE PIN DESCRIPTION
1
GND
–
–
Ground
2
GND
–
–
Ground
3
GPIO10
I/O
1
GPIO(1)
4
GPIO11
I/O
2
GPIO(1)
5
GPIO14
I/O
5
GPIO(1)
6
GPIO15
I/O
6
GPIO(1)
7
GPIO16
I/O
7
GPIO(1)
8
GPIO17
I/O
8
GPIO(1)
9
GPIO12
I/O
3
GPIO(1)
10
GPIO13
I/O
4
GPIO(1)
11
GPIO22
I/O
15
GPIO(1)
12
JTAG_TDI
I/O
16
GPIO(1)
13
FLASH_SPI_MISO
I
–
External Serial Flash Programming: SPI data in
14
FLASH_SPI_nCS_IN
I
–
External Serial Flash Programming: SPI chip select (active low)
15
FLASH_SPI_CLK
O
–
External Serial Flash Programming: SPI clock
16
GND
–
–
Ground
17
FLASH_SPI_MOSI
O
–
External Serial Flash Programming: SPI data out
18
JTAG_TDO
I/O
17
GPIO(1)
19
GPIO28
I/O
18
GPIO(1)
21
JTAG_TCK
I/O
19
JTAG TCK input. Leave unconnected if not used on product.(1)
22
JTAG_TMS
I/O
20
JTAG TMS input. Leave unconnected if not used on product.(1)
23
SOP2
–
21
See for SOP[2:0] configuration modes.
24
SOP1
–
34
See for SOP[2:0] configuration modes.
25
ANT_SEL1
I/O
29
Antenna selection control(1)
26
ANT_SEL2
I/O
30
Antenna selection control(1)
27
GND
–
–
Ground
28
GND
–
–
Ground
30
GND
–
–
Ground
31
RF_BG
I/O
31
2.4-GHz RF input/output
32
GND
–
–
Ground
34
SOP0
–
35
See for SOP[2:0] configuration modes.
35
nRESET
I
32
Power-on reset. TI recommends connecting the pin to a GPIO
from the host.
36
VBAT_RESET
–
37
TI recommends leaving this pin unconnected. If the nRESET pin
is not connected to the host, pull this pin to VBAT.
37
VBAT1
–
39
Power supply for the device, must be connected to battery (2.3
V to 3.6 V)
38
GND
–
–
Ground
40
VBAT2
–
10, 44, 54
42
GPIO30
I/O
53
GPIO(1)
43
GND
–
–
Ground
44
GPIO0
I/O
50
GPIO(1)
46
GPIO1
I/O
55
GPIO(1)
Power supply for the device, must be connected to battery (2.3
V to 3.6 V)
Terminal Configuration and Functions
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ADVANCE INFORMATION
MODULE PIN
NO.
CC3220MOD
SWRS206 – MARCH 2017
www.ti.com
Table 4-1. Module Pin Attributes (continued)
MODULE PIN
ADVANCE INFORMATION
TYPE
CC3220 DEVICE
PIN NO.
GPIO2
I/O
57
GPIO(1)
48
GPIO3
I/O
58
GPIO(1)
49
GPIO4
I/O
59
GPIO(1)
50
GPIO5
I/O
60
GPIO(1)
51
GPIO6
I/O
61
GPIO(1)
52
GPIO7
I/O
62
GPIO(1)
53
GPIO8
I/O
63
GPIO(1)
54
GPIO9
I/O
64
GPIO(1)
55
GND
–
–
Thermal ground
56
GND
–
–
Thermal ground
57
GND
–
–
Thermal ground
58
GND
–
–
Thermal ground
59
GND
–
–
Thermal ground
60
GND
–
–
Thermal ground
61
GND
–
–
Thermal ground
62
GND
–
–
Thermal ground
63
GND
–
–
Thermal ground
NO.
NAME
47
MODULE PIN DESCRIPTION
(1) For pin multiplexing details, see the CC3220MODx device data sheet (CC3220x SimpleLink™ Wi-Fi® Wireless and Internet-of-Things
Solution, a Single-Chip Wireless MCU).
4.3
Connections for Unused Pins
All unused pins must be left as no connect (NC) pins. Table 4-2 lists the NC pins on the CC3220MODx
module.
Table 4-2. Connections for Unused Pins
12
PIN
DEFAULT
FUNCTION
STATE AT RESET AND
HIBERNATE
I/O TYPE
20
NC
WLAN analog
–
Reserved. Do not connect.
29
NC
WLAN analog
–
Reserved. Do not connect.
33
NC
WLAN analog
–
Reserved. Do not connect.
39
NC
WLAN analog
–
Reserved. Do not connect.
41
NC
WLAN analog
–
Reserved. Do not connect.
45
NC
WLAN analog
–
Reserved. Do not connect.
Terminal Configuration and Functions
DESCRIPTION
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4.4
SWRS206 – MARCH 2017
Pin Attributes and Pin Multiplexing
The module makes extensive use of pin multiplexing to accommodate the large number of peripheral
functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled
using a combination of hardware configuration (at module reset) and register control.
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware
does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode
used. Table 4-3 describes the general pin attributes and presents an overview of pin multiplexing. All pin
multiplexing options are configurable using the pin mux registers. The following special considerations
apply:
• All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is individually configurable for each
pin.
• All I/Os support 10-μA pullup and pulldown resistors.
• By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
• All digital I/Os are non fail-safe.
ADVANCE INFORMATION
NOTE
If an external device drives a positive voltage to the signal pads and the CC3220MODx
device is not powered, DC is drawn from the other device. If the drive strength of the external
device is adequate, an unintentional wakeup and boot of the CC3220MODx device can
occur. To prevent current draw, TI recommends any one of the following conditions:
• All devices interfaced to the CC3220MODx device must be powered from the same
power rail as the chip.
• Use level shifters between the device and any external devices fed from other
independent rails.
• The nRESET pin of the CC3220MODx device must be held low until the VBAT supply to
the device is driven and stable.
• All GPIO pins default to high impedence unless programmed by the MCU. The
bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other
pins are left in the Hi-Z state.
Terminal Configuration and Functions
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SWRS206 – MARCH 2017
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Table 4-3. Pin Attributes and Pin Multiplexing
GENERAL PIN ATTRIBUTES
Use
Select as
Wakeup
Source
Config.
Addl.
Analog
Mux
Muxed
With
JTAG
Dig. Pin Mux
Config. Reg.
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
Pkg.
Pin
Pin Alias
1
2
ADVANCE INFORMATION
3
FUNCTION
Dig.
Pin
Mux
Config.
Mode
Value
GPIO10
I/O
No
No
No
GPIO_PAD_
CONFIG_10
(0x4402 E0C8)
Signal
Description
Signal
Direction
LPDS(1)
Hib(2)
nRESET = 0
GND
N/A
N/A
N/A
N/A
GND
N/A
N/A
N/A
N/A
I/O
Hi-Z,
Pull,
Drive
I/O
(open
drain)
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0
GPIO10
GPIO
1
I2C_SCL
I2C clock
3
GT_PWM06
Pulse-width
modulated O/P
O
Hi-Z,
Pull,
Drive
7
UART1_TX
UART TX data
O
1
6
SDCARD_CLK
SD card clock
O
0
I
Hi-Z,
Pull,
Drive
12
14
Signal Name
PAD STATES
GT_CCP01
Terminal Configuration and Functions
Timer capture port
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SWRS206 – MARCH 2017
Table 4-3. Pin Attributes and Pin Multiplexing (continued)
Pkg.
Pin
4
5
Pin Alias
GPIO11
GPIO14
Use
I/O
I/O
Select as
Wakeup
Source
Yes
No
FUNCTION
Config.
Addl.
Analog
Mux
No
No
Muxed
With
JTAG
No
No
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_11
(0x4402 E0CC)
GPIO_PAD_
CONFIG_14
(0x4402 E0D8)
PAD STATES
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
0
GPIO11
GPIO
1
I2C_SDA
I2C data
3
GT_PWM07
4
pXCLK (XVCLK)
Signal
Description
Signal
Direction
LPDS(1)
I/O
Hi-Z,
Pull,
Drive
I/O
(open
drain)
Hi-Z,
Pull,
Drive
Pulse-width
modulated O/P
O
Hi-Z,
Pull,
Drive
Free clock to
parallel camera
O
0
I/O
(open
drain)
Hi-Z,
Pull,
Drive
SD card command
line
6
SDCARD_CMD
7
UART1_RX
UART RX data
I
Hi-Z,
Pull,
Drive
12
GT_CCP02
Timer capture port
I
Hi-Z,
Pull,
Drive
13
MCAFSX
I2S audio port
frame sync
O
Hi-Z,
Pull,
Drive
0
GPIO14
GPIO
I/O
5
I2C_SCL
I2C clock
I/O
(open
drain)
7
GSPI_CLK
General SPI clock
I/O
4
pDATA8
(CAM_D4)
Parallel camera
data bit 4
I
12
GT_CCP05
Timer capture port
I
Hi-Z,
Pull,
Drive
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
Terminal Configuration and Functions
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GENERAL PIN ATTRIBUTES
15
CC3220MOD
SWRS206 – MARCH 2017
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
Pkg.
Pin
ADVANCE INFORMATION
6
Pin Alias
GPIO15
Use
I/O
Select as
Wakeup
Source
No
FUNCTION
Config.
Addl.
Analog
Mux
No
Muxed
With
JTAG
No
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_15
(0x4402 E0DC)
PAD STATES
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
0
GPIO15
GPIO
5
I2C_SDA
I2C data
7
GSPI_MISO
4
pDATA9
(CAM_D5)
Parallel camera
data bit 5
I
13
GT_CCP06
Timer capture port
I
8
SDCARD_
DATA0
SD card data
Signal
Description
General SPI MISO
Signal
Direction
LPDS(1)
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
I/O
I/O
(open
drain)
I/O
I/O
Hi-Z,
Pull,
Drive
0
GPIO16
GPIO
I/O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
7
16
GPIO16
I/O
No
No
No
GPIO_PAD_
CONFIG_16
(0x4402 E0E0)
7
GSPI_MOSI
4
pDATA10
(CAM_D6)
5
UART1_TX
13
GT_CCP07
8
SDCARD_CLK
Terminal Configuration and Functions
I/O
Hi-Z,
Pull,
Drive
Parallel camera
data bit 6
I
Hi-Z,
Pull,
Drive
UART1 TX data
O
1
Timer capture port
I
Hi-Z,
Pull,
Drive
SD card clock
O
Zero
General SPI MOSI
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SWRS206 – MARCH 2017
Table 4-3. Pin Attributes and Pin Multiplexing (continued)
Pkg.
Pin
8
9
10
Pin Alias
GPIO17
GPIO12
GPIO13
Use
I/O
I/O
I/O
Select as
Wakeup
Source
Yes
No
Yes
FUNCTION
Config.
Addl.
Analog
Mux
No
No
No
Muxed
With
JTAG
No
No
No
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_17
(0x4402 E0E4)
GPIO_PAD_
CONFIG_12
(0x4402 E0D0)
GPIO_PAD_
CONFIG_13
(0x4402 E0D4)
PAD STATES
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
0
GPIO17
5
UART1_RX
UART1 RX data
I
7
GSPI_CS
General SPI chip
select
I/O
4
pDATA11
(CAM_D7)
Parallel camera
data bit 7
8
SDCARD_
CMD
SD card command
line
I/O
0
GPIO12
GPIO
I/O
Hi-Z,
Pull,
Drive
3
McACLK
I2S audio port
clock output
O
Hi-Z,
Pull,
Drive
4
pVS (VSYNC)
Parallel camera
vertical sync
I
Hi-Z,
Pull,
Drive
5
I2C_SCL
I/O
(open
drain)
Hi-Z,
Pull,
Drive
7
UART0_TX
Signal
Description
GPIO
I2C clock
UART0 TX data
12
GT_CCP03
Timer capture port
0
GPIO13
GPIO
5
I2C_SDA
I2C data
Signal
Direction
LPDS(1)
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
I/O
I
O
1
I
Hi-Z,
Pull,
Drive
I/O
I/O
(open
drain)
4
pHS (HSYNC)
Parallel camera
horizontal sync
7
UART0_RX
UART0 RX data
I
12
GT_CCP04
Timer capture port
I
I
Hi-Z,
Pull,
Drive
Terminal Configuration and Functions
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SWRS206 – MARCH 2017
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
Pkg.
Pin
11
Pin Alias
GPIO22
Use
I/O
Select as
Wakeup
Source
No
FUNCTION
Config.
Addl.
Analog
Mux
No
Muxed
With
JTAG
Dig. Pin Mux
Config. Reg.
No
GPIO_PAD_
CONFIG_22
(0x4402 E0F8)
ADVANCE INFORMATION
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
0
GPIO22
GPIO
I/O
7
McAFSX
I2S audio port
frame sync
O
5
GT_CCP04
Timer capture port
I
TDI
JTAG TDI. Reset
default pinout.
I
1
12
18
JTAG_TDI
I/O
No
No
Muxed
with
JTAG
TDI
GPIO_PAD_
CONFIG_23
(0x4402 E0FC)
PAD STATES
0
GPIO23
2
UART1_TX
9
I2C_SCL
Signal
Description
Signal
Direction
LPDS(1)
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
GPIO
I/O
Hi-Z,
Pull,
Drive
UART1 TX data
O
1
I/O
(open
drain)
Hi-Z,
Pull,
Drive
I2C clock
13
FLASH_
SPI_
MISO
I
N/A
N/A
N/A
N/A
N/A
Data from SPI
FLASH_SPI_MISO serial Flash (fixed
default)
I
Hi-Z
Hi-Z
Hi-Z
14
FLASH_
SPI_
nCS_IN
I
N/A
N/A
N/A
N/A
N/A
Chip select to SPI
FLASH_SPI_nCS_
serial Flash (fixed
IN
default)
I
1
Hi-Z,
Pull,
Drive
Hi-Z
15
FLASH_
SPI_CLK
I
N/A
N/A
N/A
N/A
N/A
FLASH_SPI_
CLK
Clock to SPI serial
Flash (fixed
default)
I
Hi-Z,
Pull,
Drive (3)
Hi-Z,
Pull,
Drive
Hi-Z
16
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
17
FLASH_
SPI_
MOSI
O
N/A
N/A
N/A
N/A
N/A
GND
Data to SPI serial
FLASH_SPI_MOSI Flash (fixed
default)
Terminal Configuration and Functions
N/A
N/A
N/A
N/A
O
Hi-Z,
Pull,
Drive (3)
Hi-Z,
Pull,
Drive
Hi-Z
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
Pkg.
Pin
18
Pin Alias
JTAG_TDO
Use
I/O
Select as
Wakeup
Source
Yes
FUNCTION
Config.
Addl.
Analog
Mux
No
Muxed
With
JTAG
Muxed
with
JTAG
TDO
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_ 24
(0x4402 E100)
PAD STATES
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
Signal
Description
Signal
Direction
1
TDO
JTAG TDO. Reset
default pinout.
O
0
GPIO24
GPIO
I/O
O
I
5
PWM0
Pulse-width
modulated O/P
2
UART1_RX
UART1 RX data
9
I2C_SDA
4
GT_CCP06
2
I C data
I/O
(open
drain)
Timer capture port
I
O
I/O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
N/A
N/A
N/A
N/A
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
No
No
GPIO_PAD_
CONFIG_ 40
(0x4402 E140)
0
GPIO28
20
NC
WLAN
analog
N/A
N/A
N/A
N/A
N/A
NC
Reserved
GPIO_PAD_
CONFIG_ 28
(0x4402 E110)
1
TCK
JTAG/SWD TCK.
Reset default
pinout.
I
No
Muxed
with
JTAG/
SWDTCK
8
GT_PWM03
Pulse-width
modulated O/P
O
Muxed
with
JTAG/
SWDTMSC
GPIO_PAD_
CONFIG_ 29
(0x4402 E114)
1
TMS
22
JTAG_TMS
I/O
No
No
Hi-Z
GPIO
No
No
Hi-Z,
Pull,
Drive
Driven
high in
SWD;
driven
low in
4-wire
JTAG
McAFSX
I/O
I/O
nRESET = 0
6
GPIO28
JTAG_TCK
Hib(2)
I2S audio port
frame sync
19
21
LPDS(1)
0
GPIO29
JTAG/SWD TMS.
Reset default
pinout.
GPIO
I/O
Terminal Configuration and Functions
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
Pkg.
Pin
ADVANCE INFORMATION
23(4)
Pin Alias
SOP2
Use
O only
Select as
Wakeup
Source
No
24
SOP1
Config
sense
N/A
25(7)
ANT_SEL1
O only
No
FUNCTION
Config.
Addl.
Analog
Mux
No
N/A
User
config not
required
Muxed
With
JTAG
No
ANT_SEL2
O only
No
User
config not
required
0
GPIO25
9
Signal
Description
Signal
Direction
LPDS(1)
GPIO
O
Hi-Z,
Pull,
Drive
GT_PWM02
Pulse-width
modulated O/P
O
Hi-Z,
Pull,
Drive
2
McAFSX
I2S audio port
frame sync
O
Hi-Z,
Pull,
Drive
See (5)
TCXO_EN
Enable to optional
external 40-MHz
TCXO
O
0
See (6)
SOP2
Sense-on-power 2
I
Hi-Z,
Pull,
Drive
Hib(2)
nRESET = 0
Driven
Low
Hi-Z
N/A
N/A
SOP1
Sense-on-power 1
N/A
N/A
N/A
N/A
No
GPIO_PAD_
CONFIG_26
(0x4402 E108)
0
ANTSEL1(3)
Antenna selection
control
O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
No
GPIO_PAD_
CONFIG_27
(0x4402 E10C)
0
ANTSEL2(3)
Antenna selection
control
O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
(8)
27
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
28
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
29
NC
WLAN
analog
N/A
N/A
N/A
N/A
N/A
NC
Reserved
N/A
N/A
N/A
N/A
30
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
31
RF_BG
WLAN
analog
N/A
N/A
N/A
N/A
N/A
RF_BG
RF BG band
N/A
N/A
N/A
N/A
32
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
NC
WLAN
analog
N/A
N/A
N/A
N/A
33
20
GPIO_PAD_
CONFIG_ 25
(0x4402 E104)
Signal Name
N/A
(8)
26(7)
Dig. Pin Mux
Config. Reg.
Dig.
Pin
Mux
Config.
Mode
Value
PAD STATES
NC
Terminal Configuration and Functions
Reserved
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
Muxed
With
JTAG
Dig. Pin Mux
Config. Reg.
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
Signal
Description
Signal
Direction
LPDS(1)
Hib(2)
nRESET = 0
Pkg.
Pin
Pin Alias
Use
Select as
Wakeup
Source
34
SOP0
Config
sense
N/A
N/A
N/A
N/A
N/A
SOP0
Sense-on-power 0
N/A
N/A
N/A
N/A
35
nRESET
Global
reset
N/A
N/A
N/A
N/A
N/A
nRESET
Master chip reset.
Active low.
N/A
N/A
N/A
N/A
36
VBAT_
RESET
Global
reset
N/A
N/A
N/A
N/A
N/A
VBAT_RESET
Master chip reset.
Active high.
N/A
N/A
N/A
N/A
37
VBAT1
Supply
input
N/A
N/A
N/A
N/A
N/A
VBAT1
Analog DC-DC
input (connected to
chip input supply
[VBAT])
N/A
N/A
N/A
N/A
38
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
NC
WLAN
analog
N/A
N/A
N/A
N/A
N/A
NC
CC3220MODS:
Reserved
N/A
N/A
N/A
N/A
VBAT3
Supply
input
N/A
N/A
N/A
N/A
N/A
VBAT3
CC3220MODSF:
Analog input
supply VBAT
N/A
N/A
N/A
N/A
40
VBAT2
Supply
input
N/A
N/A
N/A
N/A
N/A
VBAT2
Analog input
supply VBAT
N/A
N/A
N/A
N/A
41
NC
WLAN
analog
N/A
N/A
N/A
N/A
N/A
NC
Reserved
N/A
N/A
N/A
N/A
0
GPIO30
GPIO
I/O
Hi-Z,
Pull,
Drive
9
UART0_TX
UART0 TX data
O
1
O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
39
McACLK
I2S audio port
clock
3
McAFSX
I2S audio port
frame sync
O
Hi-Z,
Pull,
Drive
4
GT_CCP05
Timer capture port
I
Hi-Z,
Pull,
Drive
7
GSPI_MISO
General SPI MISO
I/O
Hi-Z,
Pull,
Drive
2
42
GPIO30
I/O
No
User
config not
required
(8)
No
GPIO_PAD_
CONFIG_30
(0x4402 E118)
Terminal Configuration and Functions
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ADVANCE INFORMATION
Config.
Addl.
Analog
Mux
PAD STATES
21
CC3220MOD
SWRS206 – MARCH 2017
www.ti.com
Table 4-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
Pkg.
Pin
Pin Alias
Use
Select as
Wakeup
Source
43
GND
GND
N/A
ADVANCE INFORMATION
44
GPIO0
I/O
No
FUNCTION
Config.
Addl.
Analog
Mux
Muxed
With
JTAG
N/A
N/A
User
config not
required
No
(8)
45
22
NC
WLAN
analog
N/A
N/A
N/A
Dig. Pin Mux
Config. Reg.
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
N/A
N/A
GND
0
GPIO0
12
UART0_CTS
6
GPIO_PAD_
CONFIG_0
(0x4402 E0A0)
N/A
PAD STATES
Signal
Direction
LPDS(1)
Hib(2)
nRESET = 0
GND
N/A
N/A
N/A
N/A
GPIO
I/O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
UART0 Clear-toSend input (active
low)
I
Hi-Z,
Pull,
Drive
McAXR1
I2S audio port data
1 (RX/TX)
I/O
Hi-Z,
Pull,
Drive
7
GT_CCP00
Timer capture port
I
Hi-Z,
Pull,
Drive
9
GSPI_CS
General SPI chip
select
I/O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
10
UART1_RTS
UART1 Requestto-Send (active
low)
O
1
3
UART0_RTS
UART0 Requestto-Send (active
low)
O
1
4
McAXR0
I2S audio port data
0 (RX/TX)
I/O
Hi-Z,
Pull,
Drive
N/A
NC
Reserved
N/A
N/A
N/A
N/A
Terminal Configuration and Functions
Signal
Description
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
Pkg.
Pin
46
47(10)
48
(10)
Pin Alias
GPIO1
GPIO2
GPIO3
Use
I/O
Analog
input (up to
1.8 V)/
digital I/O
Analog
input (up to
1.8 V)/
digital I/O
Select as
Wakeup
Source
No
Wake-up
source
No
FUNCTION
Config.
Addl.
Analog
Mux
No
See (9)
See
(9)
Muxed
With
JTAG
No
No
No
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_1
(0x4402 E0A4)
GPIO_PAD_
CONFIG_2
(0x4402 E0A8)
GPIO_PAD_
CONFIG_3
(0x4402 E0AC)
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
0
GPIO1
3
PAD STATES
Signal
Description
Signal
Direction
LPDS(1)
GPIO
I/O
Hi-Z,
Pull,
Drive
UART0_TX
UART0 TX data
O
1
4
pCLK (PIXCLK)
Pixel clock from
parallel camera
sensor
I
Hi-Z,
Pull,
Drive
6
UART1_TX
UART1 TX data
O
1
7
GT_CCP01
Timer capture port
I
Hi-Z,
Pull,
Drive
See (5)
ADC_CH0
ADC channel 0
input (1.5-V max)
I
Hi-Z,
Pull,
Drive
0
GPIO2
I/O
Hi-Z,
Pull,
Drive
3
UART0_RX
UART0 RX data
I
Hi-Z,
Pull,
Drive
6
UART1_RX
UART1 RX data
I
Hi-Z,
Pull,
Drive
7
GT_CCP02
Timer capture port
I
Hi-Z,
Pull,
Drive
See (5)
ADC_CH1
ADC channel 1
input (1.5-V max)
I
Hi-Z,
Pull,
Drive
0
GPIO3
GPIO
I/O
Hi-Z,
Pull,
Drive
6
UART1_TX
UART1 TX data
O
1
I
Hi-Z,
Pull,
Drive
4
pDATA7
(CAM_D3)
GPIO
Parallel camera
data bit 3
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
Terminal Configuration and Functions
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GENERAL PIN ATTRIBUTES
23
CC3220MOD
SWRS206 – MARCH 2017
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
Pkg.
Pin
ADVANCE INFORMATION
49(10)
50(10)
24
Pin Alias
GPIO4
GPIO5
Use
Analog
input (up to
1.8 V)/
digital I/O
Analog
input up to
1.5 V
Select as
Wakeup
Source
Wake-up
source
No
FUNCTION
Config.
Addl.
Analog
Mux
See (9)
See(9)
Muxed
With
JTAG
No
No
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_4
(0x4402 E0B0)
GPIO_PAD_
CONFIG_5
(0x4402 E0B4)
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
See(5)
ADC_CH2
0
GPIO4
PAD STATES
Signal
Description
ADC channel 2
input (1.5-V max)
GPIO
Signal
Direction
LPDS(1)
I
Hi-Z,
Pull,
Drive
I/O
Hi-Z,
Pull,
Drive
6
UART1_RX
UART1 RX data
I
Hi-Z,
Pull,
Drive
4
pDATA6
(CAM_D2)
Parallel camera
data bit 2
I
Hi-Z,
Pull,
Drive
See(5)
ADC_CH3
ADC channel 3
input (1.5 V max)
I
i-Z,
Pull,
Drive
0
GPIO5
I/O
Hi-Z,
Pull,
Drive
4
pDATA5
(CAM_D1)
I
Hi-Z,
Pull,
Drive
6
McAXR1
I2S audio port data
1 (RX, TX)
I/O
Hi-Z,
Pull,
Drive
7
GT_CCP05
Timer capture port
I
Hi-Z,
Pull,
Drive
Terminal Configuration and Functions
GPIO
Parallel camera
data bit 1
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
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Table 4-3. Pin Attributes and Pin Multiplexing (continued)
Pkg.
Pin
51
52
53
Pin Alias
GPIO6
GPIO7
GPIO8
Use
I/O
I/O
I/O
Select as
Wakeup
Source
No
No
No
FUNCTION
Config.
Addl.
Analog
Mux
No
No
No
Muxed
With
JTAG
No
No
No
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_6
(0x4402 E0B8)
GPIO_PAD_
CONFIG_7
(0x4402 E0BC)
GPIO_PAD_
CONFIG_8
(0x4402 E0C0)
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
0
GPIO6
5
UART0_RTS
4
PAD STATES
Signal
Description
Signal
Direction
LPDS(1)
GPIO
I/O
Hi-Z,
Pull,
Drive
UART0 Requestto-Send (active
low)
O
1
pDATA4
(CAM_D0)
Parallel camera
data bit 0
I
Hi-Z,
Pull,
Drive
3
UART1_CTS
UART1 Clear to
send (active low)
I
Hi-Z,
Pull,
Drive
6
UART0_CTS
UART0 Clear to
send (active low)
I
Hi-Z,
Pull,
Drive
7
GT_CCP06
Timer capture port
I
Hi-Z,
Pull,
Drive
0
GPIO7
GPIO
I/O
Hi-Z,
Pull,
Drive
13
McACLKX
I2S audio port
clock
O
Hi-Z,
Pull,
Drive
3
UART1_RTS
UART1 Request to
send (active low)
10
UART0_RTS
UART0 Request to
send (active low)
11
UART0_TX
0
GPIO8
6
SDCARD_IRQ
7
McAFSX
12
GT_CCP06
O
1
O
1
UART0 TX data
O
1
GPIO
I/O
Interrupt from SD
card (future
support)
I
I2S audio port
frame sync
O
Timer capture port
I
Hi-Z,
Pull,
Drive
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
Hi-Z,
Pull,
Drive
Hi-Z
Terminal Configuration and Functions
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GENERAL PIN ATTRIBUTES
25
CC3220MOD
SWRS206 – MARCH 2017
www.ti.com
Table 4-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
Pkg.
Pin
ADVANCE INFORMATION
54
Pin Alias
GPIO9
Use
I/O
Select as
Wakeup
Source
No
FUNCTION
Config.
Addl.
Analog
Mux
No
Muxed
With
JTAG
No
Dig. Pin Mux
Config. Reg.
GPIO_PAD_
CONFIG_9
(0x4402 E0C4)
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
0
GPIO9
3
GT_PWM05
6
SDCARD_
DATA0
7
PAD STATES
Signal
Description
Signal
Direction
GPIO
I/O
Pulse-width
modulated O/P
O
SD card data
I/O
McAXR0
I2S audio port data
(RX, TX)
I/O
12
GT_CCP00
Timer capture port
I
LPDS(1)
Hib(2)
nRESET = 0
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
55
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
56
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
57
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
58
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
59
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
60
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
61
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
62
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
63
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
(1) LPDS state: The state of unused I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(2) Hibernate mode: The state of the I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(3) To minimize leakage in some serial Flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldowns on FLASH_SPI_DIN,
FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During
hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(5) For details on proper use, see Drive Strength and Reset States for Analog-Digital Multiplexed Pins.
(6) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the chip hardware power-up mode. For this reason, the pin must be output only when
used for digital functions.
(7) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220MODx device between two antennas. These pins must not be
used for other functionalities.
(8) Device firmware automatically enables the digital path during ROM boot.
(9) Requires user configuration to enable the analog switch of the ADC channel. (The switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the
ADC switch.
26
Terminal Configuration and Functions
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(10) This pin is shared by the ADC inputs and digital I/O pad cells.
NOTE
The ADC inputs are tolerant up to 1.8 V. On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental
damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is,
converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 47], S8 [Pin 48], S9 [Pin 49], and S10 [Pin 50]). For more
information, see Drive Strength and Reset States for Analog-Digital Multiplexed Pins.
Drive Strength and Reset States for Analog-Digital Multiplexed Pins
Table 4-4 describes the use, drive strength, and default state of analog- and digital-multiplexed pins at first-time power up and reset (nRESET
pulled low).
Table 4-4. Drive Strength and Reset States for Analog-Digital Multiplexed Pins
PIN
BOARD LEVEL CONFIGURATION AND USE
DEFAULT STATE AT FIRST POWER UP OR
FORCED RESET
STATE AFTER CONFIGURATION OF ANALOG
SWITCHES (ACTIVE, LPDS, and HIB POWER
MODES)
MAXIMUM
EFFECTIVE DRIVE
STRENGTH (mA)
25
Connected to the enable pin of the RF switch
(ANT_SEL1). Other use is not recommended.
Analog is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
26
Connected to the enable pin of the RF switch
(ANT_SEL2). Other use is not recommended.
Analog is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
44
Generic I/O
Analog is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
42
Generic I/O
Analog is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
47
Analog signal (1.8-V absolute, 1.46-V full scale)
ADC is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
48
Analog signal (1.8-V absolute, 1.46-V full scale)
ADC is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
49
Analog signal (1.8-V absolute, 1.46-V full scale)
ADC is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
50
Analog signal (1.8-V absolute, 1.46-V full scale)
ADC is isolated. The digital I/O cell is also
isolated.
Determined by the I/O state, as are other digital
I/Os.
4
Terminal Configuration and Functions
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4.6
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Pad State After Application of Power To Chip, But Before Reset Release
When a stable power is applied to the CC3220MODx module for the first time or when supply voltage is
restored to the proper value following a prior period with supply voltage below 1.5 V, the level of the digital
pads are undefined in the period starting from the release of nRESET and until the DIG_DCDC of the
CC3220x chip powers up. This period is less than approximately 10 ms. During this period, pads can be
internally pulled weakly in either direction. If a certain set of pins are required to have a definite value
during this pre-reset period, an appropriate pullup or pulldown must be used at the board level. The
recommended value of this external pull is 2.7 kΩ.
ADVANCE INFORMATION
28
Terminal Configuration and Functions
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5 Specifications
5.1
Absolute Maximum Ratings
All measurements are referenced at the module pins unless otherwise indicated. All specifications are over process and
voltage unless otherwise indicated.
over operating free-air temperature range (unless otherwise noted) (1) (2)
MAX
UNIT
VBAT
–0.5
3.8
V
Digital I/O
–0.5
VBAT + 0.5
V
RF pin
–0.5
2.1
V
Analog pins
–0.5
2.1
V
Operating temperature (TA)
–40
85
°C
Storage temperature (Tstg)
–40
85
°C
120
°C
Junction temperature (Tj)
(1)
(2)
(3)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Junction temperature is for the CC3220x device that is contained within the module.
5.2
ESD Ratings
VALUE
VESD
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±2000
Charged device model (CDM),
per JESD22-C101 (2)
±500
All pins
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3
Power-On Hours (POH)
NOTE
This information is provided solely for your convenience and does not extend or modify the
warranty provided under TI's standard terms and conditions for TI semiconductor products.
CONDITIONS
TA up to 85°C
(1)
POWER-ON HOURS [POH] (hours)
(1)
87,600
The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device
can be in any other state.
5.4
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
TYP
MAX
VBAT
2.3
3.3
3.6
V
Operating temperature
–40
25
85
°C
Ambient thermal slew
–20
20
°C/minute
(1)
(2)
(3)
UNIT
To ensure WLAN performance, the ripple on the power supply must be less than ±300 mV. The ripple should not cause the supply to fall
below the brownout voltage.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the transmission.
The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1
V, and care must be taken when operating at the minimum specified voltage.
Specifications
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MIN
CC3220MOD
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5.5
www.ti.com
Current Consumption (CC3220MODS)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS (1)
PARAMETER
(2)
1 DSSS
TX
MCU ACTIVE
6 OFDM
NWP ACTIVE
54 OFDM
MIN
TX power level = 0
272
TX power level = 4
190
TX power level = 0
248
TX power level = 4
182
TX power level = 0
223
TX power level = 4
160
1 DSSS
RX
54 OFDM
59
15.3
1 DSSS
TX
6 OFDM
NWP ACTIVE
ADVANCE INFORMATION
54 OFDM
RX
NWP idle connected
TX power level = 0
269
TX power level = 4
187
TX power level = 0
245
TX power level = 4
179
TX power level = 0
220
TX power level = 4
157
1 DSSS
56
54 OFDM
56
(3)
TX
6 OFDM
NWP active
MCU LPDS
54 OFDM
1 DSSS
RX
54 OFDM
TX power level = 0
266
TX power level = 4
184
TX power level = 0
242
TX power level = 4
176
TX power level = 0
217
TX power level = 4
154
53
0.135
NWP idle connected (3)
0.875
MCU hibernate
NWP hibernate
6
MCU shutdown
NWP shutdown
1
(1)
(2)
(3)
(4)
(5)
30
mA
53
NWP LPDS (4)
(5)
mA
12.2
1 DSSS
Peak calibration current
mA
59
NWP idle connected (3)
MCU SLEEP
TYP MAX UNIT
VBAT = 3.3 V
450
VBAT= 2.3 V
620
µA
mA
TX power level = 0 implies maximum power (see , , and ). TX power level = 4 implies output power backed off approximately 4 dB.
The CC3220MODx system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
DTIM = 1
LPDS current does not include the external serial Flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The
CC3220MODx module can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 μA.
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed
sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two
additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC3x20
SimpleLink™ Wi-Fi® and Internet of Things Network Processor Programmer's Guide.
Specifications
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5.6
SWRS206 – MARCH 2017
Current Consumption (CC3220MODSF)
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS (1)
PARAMETER
(2)
1 DSSS
TX
NWP ACTIVE
54 OFDM
TX power level = 0
286
TX power level = 4
202
TX power level = 0
255
TX power level = 4
192
TX power level = 0
232
TX power level = 4
174
1 DSSS
RX
54 OFDM
74
25.2
1 DSSS
TX
6 OFDM
NWP ACTIVE
54 OFDM
RX
NWP idle connected
TX power level = 0
282
TX power level = 4
198
TX power level = 0
251
TX power level = 4
188
TX power level = 0
228
TX power level = 4
170
1 DSSS
70
54 OFDM
70
(3)
TX
6 OFDM
NWP active
MCU LPDS
54 OFDM
1 DSSS
RX
54 OFDM
TX power level = 0
266
TX power level = 4
184
TX power level = 0
242
TX power level = 4
176
TX power level = 0
217
TX power level = 4
154
53
0.135
NWP idle connected (3)
0.710
MCU hibernate
NWP hibernate
6
MCU shutdown
NWP shutdown
1
(1)
(2)
(3)
(4)
(5)
mA
53
NWP LPDS (4)
(5)
mA
21.2
1 DSSS
Peak calibration current
mA
74
NWP idle connected (3)
MCU SLEEP
TYP MAX UNIT
VBAT= 3.3 V
450
VBAT= 2.3 V
620
µA
mA
TX power level = 0 implies maximum power (see , , and ). TX power level = 4 implies output power backed off approximately 4 dB.
The CC3220MODx system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
DTIM = 1
LPDS current does not include the external serial Flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The
CC3220MODx module can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 μA.
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed
sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two
additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC3x20
SimpleLink™ Wi-Fi® and Internet of Things Network Processor Programmer's Guide.
Specifications
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ADVANCE INFORMATION
MCU ACTIVE
6 OFDM
MIN
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TX Power and IBAT versus TX Power Level Settings
Figure 5-1, Figure 5-2, and Figure 5-3 show TX Power and IBAT versus TX power level settings for the
CC3220MODS device at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the
CC3220MODSF device, the IBAT current has an increase of approximately 10 mA to 15 mA depending on
the transmitted rate. The TX power level will remain the same.
In Figure 5-1, the area enclosed in the circle represents a significant reduction in current during transition
from TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI
recommends using TX power level 4 to reduce the current.
1 DSSS
19.00
280.00
Color by
17.00
264.40
TX Power (dBm)
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
IBAT (VBAT @ 3.6 V)(mAmp)
ADVANCE INFORMATION
TX Power (dBm)
15.00
15
Figure 5-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 5-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
32
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54 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
ADVANCE INFORMATION
TX Power (dBm)
264.40
TX Power (dBm)
15
Figure 5-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
Specifications
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Brownout and Blackout Conditions
The module enters a brownout condition whenever the input voltage dips below VBROWNOUT (see Figure 54 and Figure 5-5). This condition must be considered during design of the power supply routing, especially
if operating from a battery. High-current operations, such as a TX packet or any external activity (not
necessarily related directly to networking) can cause a drop in the supply voltage, potentially triggering a
brownout. The resistance includes the internal resistance of the battery, contact resistance of the battery
holder (four contacts for a 2× AA battery), and the wiring and PCB routing resistance.
NOTE
When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect
during HIBERNATE state.
ADVANCE INFORMATION
Figure 5-4. Brownout and Blackout Levels (1 of 2)
Figure 5-5. Brownout and Blackout Levels (2 of 2)
In the brownout condition, all sections of the device shut down within the module except for the Hibernate
block (including the 32-kHz RTC clock), which remains on. The current in this state can reach
approximately 400 µA.
34
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The blackout condition is equivalent to a hardware reset event in which all states within the module are
lost. Vbrownout = 2.1 V and Vblackout = 1.67 V
Table 5-1 lists the brownout and blackout voltage levels.
Table 5-1. Brownout and Blackout Voltage Levels
CONDITION
5.9
VOLTAGE LEVEL
UNIT
Vbrownout
2.1
V
Vblackout
1.67
V
Electrical Characteristics
TA = 25°C, VBAT = 3.3 V
GPIO Pins Except 25, 26, 42, and 44 (25°C)(1)
TEST CONDITIONS
MIN
NOM
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
VIL
Low-level input voltage
–0.5
0.35 × VDD
IIH
High-level input current
IIL
Low-level input current
VOH
VOL
IOH
IOL
4
High-level output voltage
Low-level output voltage
High-level
source
current,
Low-level sink
current,
pF
5
nA
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤ VDD < 2.4 V
VDD × 0.75
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.7
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤ VDD < 2.4 V
VDD × 0.25
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.35
2-mA drive
2
4-mA drive
4
6-mA drive
6
2-mA drive
2
4-mA drive
4
6-mA drive
6
V
nA
VDD × 0.8
VDD × 0.2
V
5
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
UNIT
V
V
mA
mA
Specifications
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ADVANCE INFORMATION
PARAMETER
CIN
35
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SWRS206 – MARCH 2017
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(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk of
interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
GPIO Pins 25, 26, 42, and 44 (25°C) (1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VIL
Low-level input voltage
–0.5
IIH
High-level input current
50
nA
IIL
Low-level input current
50
nA
VOH
ADVANCE INFORMATION
VOL
IOH
IOL
VIL
(1)
7
UNIT
CIN
High-level output voltage
Low-level output voltage
High-level source
current, VOH = 2.4
Low-level sink
current,
pF
VDD + 0.5 V
0.35 × VDD
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤ VDD < 2.4 V
VDD × 0.75
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤ VDD < 2.4 V
VDD × 0.25
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.35
2-mA drive
1.5
4-mA drive
2.5
6-mA drive
3.5
2-mA drive
1.5
4-mA drive
2.5
6-mA drive
3.5
V
V
V
V
mA
mA
nRESET
0.6
V
TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk of
interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
Pin Internal Pullup and Pulldown (25°C)
PARAMETER
TEST CONDITIONS
MIN
IOH
Pullup current
(VDD = 3.0 V)
5
IOL
Pulldown current
(VDD = 3.0 V)
5
36
Specifications
NOM
MAX
10
UNIT
µA
µA
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5.10 WLAN Receiver Characteristics
TA = 25°C, VBAT = 2.3 V to 3.6 V. Parameters measured at module pin on channel 7 (2442 MHz).
PARAMETER
RATE
Sensitivity
(8% PER for 11b rates, 10% PER for 11g or 11n rates)
(10% PER) (1)
Maximum input level
(10% PER)
TYP
1 DSSS
–94.7
2 DSSS
–92.6
11 CCK
–87.0
6 OFDM
–89.0
9 OFDM
–88.0
18 OFDM
–85.0
36 OFDM
–79.5
54 OFDM
–73.0
MCS7 (mixed mode)
–69.0
802.11b
–3.0
802.11g
–9.0
MAX
UNIT
dBm
dBm
Sensitivity is 1-dB worse on channel 13 (2472 MHz).
5.11 WLAN Transmitter Characteristics
TA = 25°C, VBAT = 2.3 V to 3.6 V. Parameters measured at module pin on channel 7 (2442 MHz) (1).
PARAMETER
Max RMS Output Power measured at 1 dB
from IEEE spectral mask or EVM
RATE
MIN
17
2 DSSS
17
11 CCK
17.25
6 OFDM
16.25
9 OFDM
16.25
18 OFDM
MAX
UNIT
dBm
16
36 OFDM
15
54 OFDM
13.5
MCS7 (mixed mode)
12
Transmit center frequency accuracy
(1)
TYP
1 DSSS
–20
20
ppm
Channel-to-channel variation is up to 1 dB. The edge channels (2412 MHz and 2472 MHz) have reduced TX power to meet FCC
emission limits.
5.12 Reset Requirement
PARAMETER
MIN
VIH
Operation mode level
VIL
Shutdown mode level (1)
0
Minimum time for nReset low for resetting the module
5
Tr and Tf
(1)
Rise and fall times
TYP
MAX
UNIT
0.65 × VBAT
V
0.6
V
ms
20
µs
The nRESET pin must be held below 0.6 V for the module to register a reset.
Specifications
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(1)
MIN
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5.13 Thermal Resistance Characteristics for MOB Package
°C/W (1)
NAME
DESCRIPTION
RΘJC
Junction-to-case
RΘJB
RΘJA
(2)
AIR FLOW (m/s) (3)
11.4
0.00
Junction-to-board
8.0
0.00
Junction-to-free air
18.7
0.00
PsiJT
Junction-to-package top
5.3
0.00
PsiJB
Junction-to-board
7.7
0.00
(1)
(2)
(3)
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
m/s = meters per second.
5.14 Timing and Switching Characteristics
ADVANCE INFORMATION
5.14.1 nRESET Timing
Table 5-2 describes the timing requirements for the first-time power-up and reset removal.
Table 5-2. First-Time Power-Up and Reset Removal Timing Requirements
ITEM
NAME
DESCRIPTION
T1
Supply settling time
T2
Hardware wake-up time
T3
T4
MIN
TYP
Depends on application board power supply, decap, and so on
MAX
UNIT
3
ms
25
ms
Initialization time
Internal 32-kHz XTAL settling plus firmware initialization time plus
radio calibration
App code load time for
CC3220MODS
CC3220MODS
Image size (KB) × 1.7
App code load time for
CC3220MODSF
CC3220MODSF
Image size (KB) × 0.06
1.35
s
ms
Figure 5-6 shows the reset timing diagram for the first-time power-up and reset removal.
T1
T2
T3
T4
FW INIT
APP CODE
LOAD
VBAT
nRESET
STATE
POWER
OFF
RESET
HW INIT
APP CODE
EXECUTION
32-kHz
RTC CLK
Figure 5-6. First-Time Power-Up and Reset Removal Timing Diagram
38
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5.14.2 Wake Up From Hibernate Timing
NOTE
The internal 32.768-kHz XTAL is kept enabled by default when the module goes to
hibernate.
Table 5-3. Software Hibernate Timing Requirements
Figure 5-7 shows the timing diagram for wake up from the hibernate state.
Application software requests
entry to hibernate mode
THIB_MIN
T2
T3
T4
FW INIT
APP CODE
LOAD
ADVANCE INFORMATION
VBAT
nRESET
STATE
ACTIVE
HIBERNATE
HW WAKEUP
EXECUTION
32KHz
RTC CLK
Figure 5-7. Wake Up From Hibernate Timing Diagram
5.14.3 Peripherals Timing
This section describes the peripherals that are supported by the CC3220MODx device:
• SPI
• I2S
• GPIOs
• I2C
• IEEE 1149.1 JTAG
• ADC
• Camera parallel port
• UART
• SD Host
• Timers
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5.14.3.1 SPI
5.14.3.1.1 SPI Master
The CC3220MODx microcontroller includes one SPI module, which can be configured as a master or
slave device. The SPI includes a serial clock with programmable frequency, polarity, and phase; a
programmable timing control between chip select and external clock generation; and a programmable
delay before the first SPI word is transmitted. Slave mode does not include a dead cycle between two
successive words.
Figure 5-8 shows the timing diagram for the SPI master.
I2
CLK
I6
I7
MISO
ADVANCE INFORMATION
I9
I8
MOSI
SWAS032-017
Figure 5-8. SPI Master Timing Diagram
Table 5-4 lists the timing parameters for the SPI master.
Table 5-4. SPI Master Timing Parameters
PARAMETER
NUMBER
F (1)
Clock frequency
Tclk (1)
Clock period
D (1)
Duty cycle
I6
tIS (1)
RX data setup time
1
I7
tIH (1)
RX data hold time
2
I8
tOD (1)
TX data output delay
I9
(1)
I2
(1)
40
MIN
tOH
MAX
UNIT
20
MHz
50
45%
TX data hold time
ns
55%
ns
ns
8.5
ns
8
ns
Timing parameter assumes a maximum load of 20 pF.
Specifications
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5.14.3.1.2 SPI Slave
Figure 5-9 shows the timing diagram for the SPI slave.
I2
CLK
I6
I7
MISO
I9
I8
MOSI
SWAS032-017
Figure 5-9. SPI Slave Timing Diagram
ADVANCE INFORMATION
Table 5-5 lists the timing parameters for the SPI slave.
Table 5-5. SPI Slave Timing Parameters
PARAMETER
NUMBER
MIN
F (1)
I2
Tclk (1)
D
(1)
(1)
MAX
Clock frequency @ VBAT = 3.3 V
20
Clock frequency @ VBAT ≤ 2.3 V
12
Clock period
50
Duty cycle
45%
UNIT
MHz
ns
55%
I6
tIS (1)
RX data setup time
4
ns
I7
tIH (1)
RX data hold time
4
ns
(1)
I8
tOD
I9
tOH (1)
TX data output delay
20
ns
TX data hold time
24
ns
Timing parameter assumes a maximum load of 20 pF at 3.3 V.
Specifications
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5.14.3.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of
transmit and receive sections that operate synchronously and have programmable clock and frame-sync
polarity. A fractional divider is available for bit-clock generation.
5.14.3.2.1 I2S Transmit Mode
Figure 5-10 shows the timing diagram for the I2S transmit mode.
I2
I1
I3
McACLKX
I4
I4
McAFSX
McAXR0/1
SWAS032-015
ADVANCE INFORMATION
Figure 5-10. I2S Transmit Mode Timing Diagram
Table 5-6 lists the timing parameters for the I2S transmit mode.
Table 5-6. I2S Transmit Mode Timing Parameters
PARAMETER
NUMBER
(1)
MIN
MAX
UNIT
MHz
I1
fclk (1)
Clock frequency
9.216
I2
tLP (1)
Clock low period
1/2 fclk
ns
I3
tHT (1)
Clock high period
1/2 fclk
ns
I4
tOH (1)
TX data hold time
22
ns
Timing parameter assumes a maximum load of 20 pF.
5.14.3.2.2 I2S Receive Mode
Figure 5-11 shows the timing diagram for the I2S receive mode.
I2
I1
I3
McACLKX
I5
I4
McAFSX
McAXR0/1
SWAS032-016
Figure 5-11. I2S Receive Mode Timing Diagram
42
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Table 5-7 lists the timing parameters for the I2S receive mode.
Table 5-7. I2S Receive Mode Timing Parameters
PARAMETER
NUMBER
(1)
MIN
I1
fclk
(1)
I2
tLP (1)
I3
tHT
(1)
I4
tOH (1)
I5
tOS (1)
MAX
UNIT
Clock frequency
9.216
MHz
Clock low period
1/2 fclk
ns
Clock high period
1/2 fclk
ns
RX data hold time
0
ns
RX data setup time
15
ns
Timing parameter assumes a maximum load of 20 pF.
5.14.3.3 GPIOs
ADVANCE INFORMATION
All digital pins of the device can be used as general-purpose input/output (GPIO) pins. The GPIO module
consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24
programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and
pulldown strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.
Figure 5-12 shows the GPIO timing diagram.
VDD
80%
20%
tGPIOF
tGPIOR
SWAS031-067
Figure 5-12. GPIO Timing Diagram
5.14.3.3.1 GPIO Output Transition Time Parameters (Vsupply = 1.85 V)
Table 5-8. GPIO Output Transition Times (Vsupply = 1.85 V) (1) (2)
DRIVE
STRENGTH
(mA)
2
4
6
(1)
(2)
DRIVE STRENGTH
CONTROL BITS
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
2MA_EN=1
4MA_EN=1
Tr
Tf
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
11.7
13.9
16.3
11.5
13.9
16.7
ns
13.7
15.6
18.0
9.9
11.6
13.6
ns
5.5
6.4
7.4
3.8
4.7
5.8
ns
Vsupply = 1.8 V, T = 25°C, total pin load = 30 pF
The transition data applies to the pins other than the multiplexed analog-digital pins 25, 26, 42, and 44.
Specifications
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5.14.3.3.2 GPIO Input Transition Time Parameters
Table 5-9 lists the input transition time parameters.
Table 5-9. GPIO Input Transition Time Parameters
tr
Input transition time (tr, tf), 10% to 90%
tf
MIN
MAX
1
3
UNIT
ns
1
3
ns
5.14.3.4 I2C
The CC3220MODx microcontroller includes one I2C module operating with standard (100 kbps) or fast
(400 kbps) transmission speeds.
Figure 5-13 shows the I2C timing diagram.
I2
I6
I5
I2CSCL
ADVANCE INFORMATION
I1
I4
I7
I8
I3
I9
I2CSDA
SWAS031-068
2
Figure 5-13. I C Timing Diagram
44
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Table 5-10 lists the I2C timing parameters.
Table 5-10. I2C Timing Parameters (1)
PARAMETER
NUMBER
(3)
I2
tLP
Clock low period
I3
tSRT
SCL/SDA rise time
See
I4
tDH
Data hold time
I5
tSFT
SCL/SDA fall time
I6
tHT
Clock high time
I7
tDS
Data setup time
I8
tSCSR
Start condition setup time
I9
tSCS
Stop condition setup time
MAX
(2)
UNIT
System clock
See
(3)
ns
NA
3
ns
(2)
System clock
tLP/2
System clock
36
System clock
24
System clock
See
All timing is with 6-mA drive and 20-pF load.
This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal
value programmed in this register.
Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the value of the external signal capacitance and external pullup register.
5.14.3.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to
control the associated test logic. For detailed information on the operation of the JTAG port and TAP
controller, see the IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
Figure 5-14 shows the JTAG timing diagram.
J2
J3
J4
TCK
J7
TMS
TDI
J8
J8
J7
TMS Input Valid
TMS Input Valid
J9
J9
J10
TDI Input Valid
J10
TDI Input Valid
J1
J11
TDO
TDO Output Valid
TDO Output Valid
SWAS031-069
Figure 5-14. JTAG Timing Diagram
Table 5-11 lists the JTAG timing parameters.
Table 5-11. JTAG Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
15
MHz
J1
fTCK
Clock frequency
J2
tTCK
Clock period
1 / fTCK
ns
J3
tCL
Clock low period
tTCK / 2
ns
J4
tCH
Clock high period
tTCK / 2
ns
J7
tTMS_SU
TMS setup time
1
ns
J8
tTMS_HO
TMS hold time
16
ns
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ADVANCE INFORMATION
(1)
(2)
MIN
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Table 5-11. JTAG Timing Parameters (continued)
PARAMETER
NUMBER
MIN
J9
tTDI_SU
TDI setup time
1
J10
tTDI_HO
TDI hold time
16
J11
tTDO_HO
TDO hold time
MAX
UNIT
ns
ns
15
ns
5.14.3.6 ADC
Table 5-12 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on
using the ADC and for application-specific examples.
Table 5-12. ADC Electrical Specifications
PARAMETER
Nbits
TEST CONDITIONS and
ASSUMPTIONS
DESCRIPTION
MIN
Number of bits
TYP
12
ADVANCE INFORMATION
INL
Integral nonlinearity
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
DNL
Differential nonlinearity
Worst-case deviation of any step
from ideal
Input range
LSB
–1
4
LSB
0
1.4
V
100
Ω
Input capacitance
ADC Pin 57
Input impedance
MHz
12
pF
ADC Pin 58
0.7
ADC Pin 59
2.12
ADC Pin 60
1.17
kΩ
4
Fsample
Sampling rate of each pin
F_input_max
Maximum input signal frequency
62.5
SINAD
Signal-to-noise and distortion
I_active
Active supply current
Average for analog-to-digital
during conversion without
reference current
I_PD
Power-down supply current for
core supply
Total for analog-to-digital when
not active (this must be the SoC
level test)
Absolute offset error
KSPS
31
Input frequency DC to 300 Hz
and 1.4 Vpp sine wave input
FCLK = 10 MHz
Gain error
46
10
2.15
Number of channels
Vref
Bits
2.5
Successive approximation input
clock rate
Clock rate
UNIT
–2.5
Driving source
impedance
FCLK
MAX
55
kHz
60
dB
1.5
mA
1
µA
±2
mV
±2%
ADC reference voltage
1.467
Specifications
V
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Figure 5-15 shows the ADC clock timing diagram.
Repeats Every 16 µs
Internal Ch
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
EXT CHANNEL 0
SAR Conversion
16 cycles
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
EXT CHANNEL 1
INTERNAL CHANNEL
SAR Conversion
16 cycles
INTERNAL CHANNEL
Figure 5-15. ADC Clock Timing Diagram
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in
a FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 5-16 shows the timing diagram for the camera parallel port.
13
12
14
pCLK
16
17
pVS, pHS
pDATA
Figure 5-16. Camera Parallel Port Timing Diagram
Table 5-13 lists the timing parameters for the camera parallel port.
Table 5-13. Camera Parallel Port Timing Parameters
PARAMETER NUMBER
MIN
pCLK
Clock frequency
I2
Tclk
Clock period
I3
tLP
I4
tHT
I6
tIS
I7
tIH
MAX
UNIT
2
MHz
1/pCLK
ns
Clock low period
Tclk/2
ns
Clock high period
Tclk/2
ns
RX data setup time
2
ns
RX data hold time
2
ns
5.14.3.8 UART
The CC3220MODx device includes two UARTs with the following features:
• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered
interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Generation and detection of line-breaks
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5.14.3.7 Camera Parallel Port
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•
•
•
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Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Generation and detection of even, odd, stick, or no-parity bits
– Generation of 1 or 2 stop-bits
RTS and CTS hardware flow support
Standard FIFO-level and End-of-Transmission interrupts
Efficient transfers using µDMA:
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed
FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
System clock is used to generate the baud clock.
5.14.3.9 SD Host
ADVANCE INFORMATION
CC3220MODx provides an interface between a local host (LH), such as an MCU and an SD memory card,
and handles SD transactions with minimal LH intervention.
The SD host does the following:
• Provides SD card access in 1-bit mode
• Deals with SD protocol at the transmission level
• Handles data packing
• Adds cyclic redundancy checks (CRC)
• Start and end bit
• Checks for syntactical correctness
The application interface sends every SD command and either polls for the status of the adapter or waits
for an interrupt request. The result is then sent back to the application interface in case of exceptions or to
warn of end-of-operation. The controller can be configured to generate DMA requests and work with
minimum CPU intervention. Given the nature of integration of this peripheral on the CC3220x platform, TI
recommends that developers use peripheral library APIs to control and operate the block. This section
emphasizes understanding the SD host APIs provided in the peripheral library of the CC3220x Software
Development Kit (SDK).
The SD Host features are as follows:
• Full compliance with SD command and response sets, as defined in the SD memory card
– Specifications, v2.0
– Includes high-capacity (size >2 GB) cards HC SD
• Flexible architecture, allowing support for new command structure.
• 1-bit transfer mode specifications for SD cards
• Built-in 1024-byte buffer for read or write
– 512-byte buffer for both transmit and receive
– Each buffer is 32-bits wide by 128-words deep
• 32-bit-wide access bus to maximize bus throughput
• Single interrupt line for multiple interrupt source events
• Two slave DMA channels (1 for TX, 1 for RX)
• Programmable clock generation
• Integrates an internal transceiver that allows a direct connection to the SD card without external
transceiver
• Supports configurable busy and response timeout
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•
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Support for a wide range of card clock frequency with odd and even clock ratio
Maximum frequency supported is 24 MHz
5.14.3.10 Timers
The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:
• Operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM
signal
• Counts up or counts down
• Sixteen 16- or 32-bit capture compare PWM pins (CCP)
• User-enabled stalling when the microcontroller asserts CPU Halt flag during debug
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the
interrupt service routine
• Efficient transfers using micro direct memory access controller (µDMA):
– Dedicated channel for each timer
– Burst request generated on timer interrupt
• Runs from system clock (80 MHz)
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ADVANCE INFORMATION
Programmable timers can be used to count or time external events that drive the timer input pins. The
CC3220MODx general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or
32-bit GPTM block provides two 16-bit timers or counters (referred to as Timer A and Timer B) that can be
configured to operate independently as timers or event counters, or they can be concatenated to operate
as one 32-bit timer. Timers can also be used to trigger µDMA transfers.
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6 Detailed Description
6.1
Overview
The CC3220MODx is a Wi-Fi Internet-on-a chip module that consists of a Cortex-M4 processor with a rich
set of peripherals for diverse application requirements, a Wi-Fi network processor, and powermanagement subsystems. The device optimizes bus matrix and memory management to provide an
advantage to the application developer.
6.2
ARM® Cortex®-M4 Processor Core Subsystem
ADVANCE INFORMATION
The high-performance Cortex-M4 processor provides a low-cost platform that meets the needs of minimal
memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
• The Cortex-M4 core has low-latency interrupt processing with the following features:
– A 32-bit ARM® Thumb® instruction set optimized for embedded applications
– Handler and thread modes
– Low-latency interrupt handling by automatic processor state saving and restoration during entry and
exit
– Support for ARMv6 unaligned accesses
• Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve lowlatency interrupt processing. The NVIC includes the following features:
– Bits of priority configurable from 3 to 8
– Dynamic reprioritization of interrupts
– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt
levels
– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt
processing without the overhead of state saving and restoration between interrupts
– Processor state automatically saved on interrupt entry and restored on interrupt exit with no
instruction overhead
– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support
• Bus interfaces:
– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces
– Bit-band support for memory and select peripheral that includes atomic bit-band write and read
operations
• Low-cost debug solution featuring:
– Debug access to all memory and registers in the system, including access to memory-mapped
devices, access to internal core registers when the core is halted, and access to debug control
registers even while SYSRESETn is asserted
– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access
– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches
6.3
Wi-Fi Network Processor Subsystem
The Wi-Fi network processor subsystem includes a dedicated ARM MCU to completely offload the host
MCU along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast,
secure WLAN and Internet connections with 256-bit encryption. The CC3220MODx devices support
station, AP, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security
and WPS 2.0. The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack.
50
Detailed Description
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WLAN
The WLAN features are as follows:
• 802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station,
AP, Wi-Fi Direct client and group owner with CCK and OFDM rates in the 2.4-GHz ISM band, channels
1 to 13.
NOTE
•
•
•
•
•
6.3.2
Autocalibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna
without requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in serial-Flash allows
automatic fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x).
Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the
provisioning decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point using HTTPS
– SmartConfig Technology: a 1-step, 1-time process to connect a CC3220MODx-enabled module to
the home wireless network, removing dependency on the I/O capabilities of the host MCU; thus, it
is usable by deeply embedded applications
802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without
adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working
channel, rate, and transmitted power. The receiver mode works with the filtering options.
Network Stack
The Network Stack features are as follows:
• Integrated IPv4, IPv6 TCP/IP stack with BSD (BSD adjacent) socket APIs for simple Internet
connectivity with any MCU, microprocessor, or ASIC
NOTE
Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
•
•
•
Support of 16 simultaneous TCP, UDP, or RAW sockets
Support of 6 simultaneous SSL\TLS sockets
Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
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ADVANCE INFORMATION
802.11n is supported only in Wi-Fi station, Wi-Fi direct, and P2P client modes.
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Built-in network application and utilities:
– HTTP/HTTPS
• Web page content stored on serial Flash
• RESTful APIs for setting and configuring application content
• Dynamic user callbacks
– Service discovery: Multicast DNS service discovery lets a client advertise its service without a
centralized server. After connecting to the access point, the CC3220MODx module provides critical
information, such as device name, IP, vendor, and port number.
– DHCP server
– Ping
Table 6-1 describes the NWP features.
Table 6-1. NWP Features
Feature
Description
802.11b/g/n station
Wi-Fi standards
802.11b/g AP supporting up to four stations
ADVANCE INFORMATION
Wi-Fi Direct client and group owner
Wi-Fi channels
1 to 13
Wi-Fi security
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x)
Wi-Fi provisioning
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server
IP protocols
IPv4/IPv6
IP addressing
Static IP, LLA, DHCPv4, DHCPv6 with DAD
Cross layer
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW
Ping
HTTP/HTTPS web server
Network applications and
utilities
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
Device identity
Trusted root-certificate catalog
TI root-of-trust public key
Secure key storage
File system security
Security
Software tamper detection
Cloning protection
Secure boot
Validate the integrity and authenticity of the run-time binary during boot
Initial secure programming
Debug security
JTAG and debug
Power management
Transceiver
Other
52
Enhanced power policy management uses 802.11 power save and deep-sleep power modes
Programmable RX filters with event-trigger mechanism
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Security
The SimpleLink Wi-Fi CC3220MODx Internet-on-a-Chip module enhances the security capabilities
available for development of IoT devices, while completely offloading these activities from the MCU to the
networking subsystem. The security capabilities include the following key features:
ADVANCE INFORMATION
Wi-Fi and Internet Security:
• Personal and enterprise Wi-Fi security
– Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK
• WEP
– Enterprise standards
• EAP Fast
• EAP PEAPv0/1
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TLS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2
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•
ADVANCE INFORMATION
•
•
•
•
54
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Secure sockets
– Protocol versions: SSL v3, TLS 1.0, TLS 1.1, TLS 1.2
– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption
for TLS and SSL connections
– Ciphers suites
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
– Server authentication
– Client authentication
– Domain name verification
– Runtime socket upgrade to secure socket – STARTTLS
Secure HTTP server (HTTPS)
Trusted root-certificate catalog—Verifies that the CA used by the application is trusted and known
secure content delivery
TI root-of-trust public key—Hardware-based mechanism that allows authenticating TI as the genuine
origin of a given content using asymmetric keys
Secure content delivery—Allows encrypted file transfer to the system using asymmetric keys created
by the device
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Device Security:
• Separate execution environments—Application processor and network processor run on separate ARM
cores
• Initial secure programming (not supported in CC3220MODR)—Allows for keeping the content
confidential on the production line
• Debug security (not supported in CC3220MODR)
– JTAG lock
– Debug ports lock
• True random number generator
Figure 6-1 shows the high-level structure of the CC3220S and CC3220SF devices that are contained
within the CC3220MODS and CC3220MODSF modules, respectively. The application image, user data,
and network information files (passwords, certificates) are encrypted using a device-specific key.
CC3220S and CC3220SF
Network Processor + MCU
Peripherals
SPI and I2C
Network Processor
MCU
ARM® Cortex®-M4
GPIO
UART
PWM
ADC
-
256-KB RAM /
Internet
Wi-Fi®
HTTPS
MAC
TLS/SSL
Baseband
Internet
1-MB Flash (CC3220SF)
OEM
Application
TCP/IP
Radio
Serial Flash
OEM
Data Files
Network information
Application
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Figure 6-1. CC3220S and CC3220SF High-Level Structure
Detailed Description
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ADVANCE INFORMATION
Code and Data Security:
• Network passwords and certificates are encrypted and signed.
• Cloning protection—Application and data files are encrypted by a unique key per device.
• Access control—Access to application and data files only by using a token provided in file creation
time. If an unauthorized access is detected, a tamper protection lockdown mechanism takes effect.
• Encrypted and Authenticated file system (not supported in CC3220MODR)
• Secured boot—Authentication of the application image on every boot
• Code and data encryption (not supported in CC3220MODR)—User application and data files are
encrypted in sFlash.
• Code and data authentication (not supported in CC3220MODR)—User Application and data files are
authenticated with a public key certificate.
• Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify
data buffer
• Recovery mechanism
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6.5
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Power-Management Subsystem
The CC3220MODx power-management subsystem contains DC-DC converters to accommodate the
differing voltage or current requirements of the system.
The CC3220MODx is a fully integrated module-based WLAN radio solution used on an embedded system
with a wide-voltage supply range. The internal power management, including DC-DC converters and
LDOs, generates all of the voltages required for the module to operate from a wide variety of input
sources. For maximum flexibility, the module can operate in the modes described in the following sections.
6.5.1
VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the module can be directly connected to two AA alkaline batteries.
All other voltages required to operate the device are generated internally by the DC-DC converters. This
scheme is the most common mode for the device because it supports wide-voltage operation from 2.3 to
3.6 V.
6.6
Low-Power Operating Mode
ADVANCE INFORMATION
From a power-management perspective, the CC3220MODx device comprises the following two
independent subsystems:
• Cortex-M4 application processor subsystem
• Networking subsystem
Each subsystem operates in one of several power states.
The Cortex-M4 application processor runs the user application loaded from an external serial Flash, or
internal Flash (in CC3220MODSF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi
data link layer functions.
The user program controls the power state of the application processor subsystem and can be in one of
the five modes described in Table 6-2.
Table 6-2. User Program Modes
APPLICATION PROCESSOR
(MCU) MODE (1)
DESCRIPTION
MCU active mode
MCU executing code at 80-MHz state rate
MCU sleep mode
The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode
offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity
from any GPIO line or peripheral.
MCU LPDS mode
State information is lost and only certain MCU-specific register configurations are retained. The MCU
can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)
Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory
retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU
can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the
wake-up source.
MCU hibernate mode
The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly
powered by the input supply is retained. The RTC keeps running and the MCU supports wakeup from
an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15 ms
plus the time to load the application from serial Flash, which varies according to code size. In this mode,
the MCU can be configured to wake up using the RTC timer or external event on a GPIO .
MCU shutdown mode
The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in
this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the
nRESET line is changed (low to shut down, high to turn on).
(1)
56
Modes are listed in order of power consumption, with highest power modes listed first.
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The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no
network activity, the NWP sleeps most of the time and wakes up only for beacon reception (see
Table 6-3).
Table 6-3. Networking Subsystem Modes
DESCRIPTION
Transmitting or receiving IP protocol packets
Network active mode
(processing layer 2 and 1)
Transmitting or receiving MAC management frames; IP processing not required.
Network active listen mode
Special power optimized active mode for receiving beacon frames (no other frames supported)
Network connected Idle
A composite mode that implements 802.11 infrastructure power save operation. The CC3220MODx
NWP automatically goes into LPDS mode between beacons and then wakes to active listen mode
to receive a beacon and determine if there is pending traffic at the AP. If not, the NWP returns to
LPDS mode and the cycle repeats.
Network LPDS mode
Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid
wake up.
Network disabled
The network is disabled
The operation of the application and network processor ensures that the device remains in the lowest
power mode most of the time to preserve battery life.
The following examples show the use of the power modes in applications:
• A product that is continuously connected to the network in the 802.11 infrastructure power-save mode
but sends and receives little data spends most of the time in connected idle, which is a composite of
receiving a beacon frame and waiting for the next beacon.
• A product that is not continuously connected to the network but instead wakes up periodically (for
example, every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly
to active mode to transmit data.
6.7
6.7.1
Memory
Internal Memory
The CC3220x device within the CC3220MODx module includes on-chip SRAM to which application
programs are downloaded and executed. The application developer must share the SRAM for code and
data. The micro direct memory access (μDMA) controller can transfer data to and from SRAM and various
peripherals. The CC3220x device ROM holds the rich set of peripheral drivers, which saves SRAM space.
For more information on drivers, see the CC3220x API list.
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NETWORK PROCESSOR MODE
Network active mode
(processing layer 3, 2, and 1)
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6.7.1.1
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SRAM
The CC3220MODx family provides 256KB of on-chip SRAM. Internal RAM is capable of selective
retention during LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map.
Use the μDMA controller to transfer data to and from the SRAM.
When the device enters low-power mode, the application developer can choose to retain a section of
memory based on need. Retaining the memory during low-power mode provides a faster wakeup. The
application developer can choose the amount of memory to retain in multiples of 64KB. For more
information, see the API guide.
6.7.1.2
ROM
The internal zero-wait-state ROM of the CC3220MODx device is at address 0x0000 0000 of the device
memory and is programmed with the following components:
• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
ADVANCE INFORMATION
The bootloader is used as an initial program loader (when the serial Flash memory is empty). The
CC3220MODx DriverLib software library controls on-chip peripherals with a bootloader capability. The
library performs peripheral initialization and control functions, with a choice of polled or interrupt-driven
peripheral support. The DriverLib APIs in ROM can be called by applications to reduce Flash memory
requirements and free the Flash memory to be used for other purposes.
6.7.1.3
Flash Memory
The CC3220SF device within the CC3220MODSF module comes with an on-chip Flash memory of 1MB
that allows application code to execute in place while freeing SRAM exclusively for read-write data. The
Flash memory is used for code and constant data sections and is directly attached to the ICODE/DCODE
bus of the Cortex-M4 core. A 128-bit-wide instruction prefetch buffer allows maintenance of maximum
performance for linear code or loops that fit inside the buffer.
The Flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can
be performed at word (32-bit) level.
58
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Memory Map
Table 6-4 describes the various MCU peripherals and how they are mapped to the processor memory. For
more information on peripherals, see the API document.
Table 6-4. Memory Map
END ADDRESS
0x0000 0000
0x0007 FFFF
On-chip ROM (bootloader + DriverLib)
DESCRIPTION
0x0100 0000
0x010F FFFF
On-chip Flash (for user application code)
0x2000 0000
0x2003 FFFF
Bit-banded on-chip SRAM
0x2200 0000
0x23FF FFFF
Bit-band alias of 0x2000 0000 to 0x200F FFFF
0x4000 0000
0x4000 0FFF
Watchdog timer A0
0x4000 4000
0x4000 4FFF
GPIO port A0
0x4000 5000
0x4000 5FFF
GPIO port A1
0x4000 6000
0x4000 6FFF
GPIO port A2
0x4000 7000
0x4000 7FFF
GPIO port A3
0x4000 C000
0x4000 CFFF
UART A0
0x4000 D000
0x4000 DFFF
UART A1
0x4002 0000
0x4000 07FF
I2C A0 (master)
0x4002 4000
0x4002 4FFF
GPIO group 4
0x4002 0800
0x4002 0FFF
I2C A0 (slave)
0x4003 0000
0x4003 0FFF
General-purpose timer A0
0x4003 1000
0x4003 1FFF
General-purpose timer A1
0x4003 2000
0x4003 2FFF
General-purpose timer A2
0x4003 3000
0x4003 3FFF
General-purpose timer A3
0x400F7000
0x400F 7FFF
Configuration registers
0x400F E000
0x400F EFFF
System control
0x400F F000
0x400F FFFF
µDMA
0x4200 0000
0x43FF FFFF
Bit band alias of 0x4000 0000 to 0x400F FFFF
0x4401 0000
0x4401 0FFF
SDIO master
COMMENT
CC3220FS device only
0x4401 8000
0x4401 8FFF
Camera Interface
0x4401 C000
0x4401 EFFF
McASP
0x4402 0000
0x4402 0FFF
SSPI
Used for external serial Flash
0x4402 1000
0x4402 2FFF
GSPI
Used by application processor
0x4402 5000
0x4402 5FFF
MCU reset clock manager
0x4402 6000
0x4402 6FFF
MCU configuration space
0x4402 D000
0x4402 DFFF
Global power, reset, and clock manager (GPRCM)
0x4402 E000
0x4402 EFFF
MCU shared configuration
0x4402 F000
0x4402 FFFF
Hibernate configuration
0x4403 0000
0x4403 FFFF
Crypto range (includes apertures for all crypto-related
blocks as follows)
0x4403 0000
0x4403 0FFF
DTHE registers and TCP checksum
0x4403 5000
0x4403 5FFF
MD5/SHA
0x4403 7000
0x4403 7FFF
AES
0x4403 9000
0x4403 9FFF
DES
0xE000 0000
0xE000 0FFF
Instrumentation trace Macrocell™
0xE000 1000
0xE000 1FFF
Data watchpoint and trace (DWT)
0xE000 2000
0xE000 2FFF
Flash patch and breakpoint (FPB)
0xE000 E000
0xE000 EFFF
NVIC
0xE004 0000
0xE004 0FFF
Trace port interface unit (TPIU)
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START ADDRESS
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Table 6-4. Memory Map (continued)
START ADDRESS
END ADDRESS
0xE004 1000
0xE004 1FFF
Reserved for embedded trace macrocell (ETM)
0xE004 2000
0xE00F FFFF
Reserved
6.8
DESCRIPTION
COMMENT
Restoring Factory Default Configuration
The device has an internal recovery mechanism that rolls back the file system to its predefined factory
image or restoring the factory default parameters of the device. The factory image is kept in a separate
sector on the sFLASH in a secure manner and cannot be accessed from the host processor. The following
restore modes are supported:
• None—no factory restore settings
• Enable restore of factory default parameters
• Enable restore of factory image and factory default parameters
The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 110 pins
and toggling the nRESET pin from low to high.
ADVANCE INFORMATION
The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The
restore process typically takes about 8 seconds, depending on the attributes of the serial Flash vendor.
6.9
6.9.1
Boot Modes
Overview
The boot process of the application processor is a 2-phase process. The first phase consists of
unrestricted access to all register space and configuration of the specific device setting. In the second
phase, the application processor executes user-specific code.
Figure 6-2 shows the bootloader flow chart.
M4 Power ON
Boot Mode =
(Fn2WJ or Fn4WJ)
(See Note.)
Boot Mode = LDfrUART
(See Note.)
Enable Clk to M4, Release
Reset to M4
Cortex loads the PC with contents of
0x4 location, which is in ROM and part
of BootCode.
Device-Init
done?
Yes
No
Execute Device Init
(From Secure ROM)
SOP=UARTLOAD
Yes
Invoke
downloader
Download the code using
SLProgrammer and jump
to the application
No
Clear
Device-Init-Done
Valid Apps code in
SFLASH?
Yes
Jump to the user code.
No
Infite Loop
SWAS032-012
Note: For definitions of the SoP mode functional configurations, see Table 6-5.
Figure 6-2. Bootloader Flow Chart
60
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Boot Mode List
The CC3220MODx device implements a sense-on-power (SoP) scheme to determine the device operation
mode.
SoP values are sensed from the device pin during power up. This encoding determines the boot flow.
Before the device is taken out of reset, the SoP values are copied to a register and used to determine the
device operation mode while powering up. These values determine the boot flow as well as the default
mapping for some of the pins (JTAG, SWD, UART0). Table 6-5 lists the pull configurations.
Table 6-5. CC3220MODx Functional Configurations
SOP[2]
SOP[1]
SOP[0]
SoP MODE
COMMENT
UARTLOAD
Pullup
Pulldown
Pulldown
LDfrUART
Factory, lab Flash, and SRAM loads
through the UART. The device waits
indefinitely for the UART to load code.
The SOP bits then must be toggled to
configure the device in functional mode.
Also puts JTAG in 4-wire mode.
FUNCTIONAL_2WJ
Pulldown
Pulldown
Pullup
Fn2WJ
Functional development mode. In this
mode, 2-pin SWD is available to the
developer. TMS and TCK are available
for debugger connection.
Fn4WJ
Functional development mode. In this
mode, 4-pin JTAG is available to the
developer. TDI, TMS, TCK, and TDO are
available for debugger connection.
FUNCTIONAL_4WJ
Pulldown
Pulldown
Pulldown
UARTLOAD_FUNCTIONAL_4WJ
Pulldown
Pullup
Pulldown
LDfrUART_FnWJ
Supports Flash and SRAM load through
UART and functional mode. The MCU
bootloader tries to detect a UART break
on UART receive line. If the break signal
is present, the device enters the
UARTLOAD mode, otherwise, the device
enters the functional mode. TDI, TMS,
TCK, and TDO are available for
debugger connection.
RET_FACTORY_IMAGE
Pulldown
Pullup
Pullup
RetFactDef
When device reset is toggled, the MCU
bootloader kickstarts the procedure to
restore factory default images.
The recommended values of pull resistors are 100 kΩ for SOP0 and SOP1 and 2.7 kΩ for SOP2. The
application can use SOP2 for other functions after chip has powered up. However, to avoid spurious SOP
values from being sensed at power up, TI strongly recommends using the SOP2 pin only for output
signals. The SOP0 and SOP1 pins are multiplexed with the WLAN analog test pins and are not available
for other functions.
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NAME
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6.10 Certification
The CC3220MODx module is certified to the standards listed in Table 6-6 (with IDs where applicable):
Table 6-6. CC3220MODx List of Certifications
Regulatory Body
Specification
ID (IF APPLICABLE)
FCC (USA)
Part 15C + MPE FCC RF Exposure
TBD
IC (Canada)
RSS-102 (MPE) and RSS-247 (Wi-Fi)
TBD
ETSI/CE (Europe)
EN300328 v2.1.1 (2.4GHz Wi-Fi)
—
EN62311:2008 (MPE)
—
EN 301489-1 v2.1.1 (General EMC)
—
EN301489-17 v3.1.1 (EMC)
—
EN50024:2010/A1:2015
—
EN55032:2012/AC:2013
—
EN 60950—
1:2006/A11:2009/A1:2010/A12:2011/A2:2013
ADVANCE INFORMATION
Japan MIC
TBD
TBD
SRRC (China)
TBD
TBD
6.10.1 Federal Communications Commission Statement
You are cautioned that changes or modifications not expressly approved by the party responsible for
compliance could void the user’s authority to operate the equipment.
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
• This device may not cause harmful interference.
• This device must accept any interference received, including interference that may cause undesired
operation of the device.
FCC RF Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End
users must follow the specific operating instructions for satisfying RF exposure limits. This transmitter
must not be colocated or operating with any other antenna or transmitter.
6.10.2 Canada, Industry Canada (IC)
This device complies with Industry Canada licence-exempt RSS standards.
Operation is subject to the following two conditions:
• This device may not cause interference.
• This device must accept any interference, including interference that may cause undesired operation of
the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de
licence.
L'exploitation est autorisée aux deux conditions suivantes:
• L'appareil ne doit pas produire de brouillage
• L'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est
susceptible d'en compromettre le fonctionnement.
62
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IC RF Radiation Exposure Statement:
To comply with IC RF exposure requirements, this device and its antenna must not be colocated or
operating in conjunction with any other antenna or transmitter.
Pour se conformer aux exigences de conformité RF canadienne l'exposition, cet appareil et son antenne
ne doivent pas étre co-localisés ou fonctionnant en conjonction avec une autre antenne ou transmetteur.
6.11 End Product Labeling
This module is designed to comply with the FCC statement, FCC ID: TBD. The host system using this
module must display a visible label indicating the following text:
Contains FCC ID: TBD
This module is designed to comply with the IC statement, IC: TBD. The host system using this module
must display a visible label indicating the following text:
Contains IC: TBD
The OEM integrator must be aware not to provide information to the end user regarding how to install or
remove this RF module in the user’s manual of the end product which integrates this module.
The end user manual must include all required regulatory information and warnings as shown in this
manual.
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6.12 Manual Information to the End User
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1
Typical Application
Figure 7-1 shows the typical application schematic using the CC3220MODx module. For a full operational
reference design, refer to the LaunchPad that uses the CC3220MODx module.
Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak cu rrents.
VCC
VCC
ADVANCE INFORMATION
C3
0.1µF
C6
100µF
C7
100µF
GND
C4
0.1µF
U1
1
2
16
27
28
30
32
38
43
55
56
57
58
59
60
61
62
63
VBAT1
VBAT2
VBAT3
VBAT_RESET
RESET
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
C5
0.1µF
GND
37
GND
40
GND
GND
39
Matching circuit shown below is for
the antenna. The module is matched
internally to 50 Ohm. Final solution
may require antenna matching
optimization with a pi-network
36
35
12
18
21
22
TO HOST
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
E1
JTAG /
DEBUG
2
GPIO_0
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
GPIO_08
GPIO_09
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_22
GPIO_28
GPIO_30
1
44
46
47
48
49
50
51
52
53
54
3
4
9
10
5
6
7
8
11
19
42
P50_GPIO_00
P55_GPIO_01
P57_GPIO_02
P58_GPIO_03
P59_GPIO_04
P60_GPIO_05
P61_GPIO_06
P62_GPIO_07
P63_GPIO_08
P64_GPIO_09
P01_GPIO_10
P02_GPIO_11
P03_GPIO_12
P04_GPIO_13
P05_GPIO_14
P06_GPIO_15
P07_GPIO_16
P08_GPIO_17
P15_GPIO_22
P18_GPIO_28
P53_GPIO_30
L1
3.3nH
RF_BG
ANT_SEL1
ANT_SEL2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SOP0
SOP1
SOP2
C2
1pF
31
GND GND
VCC
25
26
P29_GPIO_26
P30_GPIO_27
R1
270
SOP[2:0] USED FOR
FACTORY RESTORE 1
34
24
23
GND
2
4
6
3
5
J1
FLASH_SPI_CLK
FLASH_SPI_CS_IN
FLASH_SPI_MOSI
FLASH_SPI_MISO
NC
NC
NC
NC
NC
15
14
17
13
SFL_CLK
SFL_nCS
SFL_MOSI
SFL_MISO
EXTERNAL
PROGRAMMING
20
29
33
41
45
CC3220MODSF12MOBR
GND
Copyright © 2017, Texas Instruments Incorporated
Note:
For the board files and BOM, see the LAUNCHXL-CC3220MODSF at www.ti.com/product/CC3220MOD.
Figure 7-1. CC3220MODx Typical Application Schematic
64
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Table 7-1 provides the bill of materials for a typical application using the CC3220MODx module in
Figure 7-1.
Table 7-1. Bill of Materials
QTY
PART
REFERENCE
VALUE
MANUFACTURER
PART NUMBER
1
C2
1 pF
Murata
GRM1555C1H1R0BA01D
Capacitor, ceramic, 1 pF,
50 V, ±10%, C0G/NP0, 0402
3
C3, C4, C5
0.1 µF
Murata
GRM155R61A104KA01D
Capacitor, ceramic, 0.1 μF,
10 V, ±10%, X5R, 0402
2
C6, C7
100 µF
Murata
LMK325ABJ107MMHT
Capacitor, ceramic, 100 μF,
10 V, ±20%, X5R,
AEC-Q200 Grade 3, 1210
1
E1
2.45-GHz Ant
Taiyo Yuden
AH316M245001-T
1
L1
3.3 nH
Murata
LQG15HS3N3S02D
1
R1
270
Vishay-Dale
CRCW0402270RJNED
1
U1
CC3220MODSF
Texas Instruments
CC3220MODSF12MOBR
7.2.1
Antenna Bluetooth WLAN
ZigBee® WIMAX
Inductor, multilayer,
air core, 3.3 nH,
0.3 A, 0.17 Ω, SMD
RES, 270, 5%,
0.063 W, 0402
SimpleLink Wi-Fi and Internet-ofThings Module Solution, a
Single-Chip Wireless MCU,
MOB0063A (SIP MODULE-63)
Device Connection and Layout Fundamentals
Power Supply Decoupling and Bulk Capacitors
Depending upon routing resistors and battery type, TI recommends adding two 100-µF ceramic capacitors
to help provide the peak current drawn by the CC3220MODx module.
NOTE
The module enters a brown-out condition whenever the input voltage dips below VBROWN (see
Figure 5-4 and Figure 5-5). This condition must be considered during design of the power
supply routing specifically if operating from a battery. For more details on brown-out
consideration, see Section 5.8.
7.2.2
Reset
The module features an internal RC circuit to reset the device during power ON. The nRESET pin must be
held below 0.6 V for at least 5 ms for the device to successfully reset.
7.2.3
Unused Pins
All unused pins can be left unconnected without any concern to leakage current.
7.3
PCB Layout Guidelines
This section details the PCB guidelines to speed up the PCB design using the CC3220MODx Module.
Follow these guidelines ensures that the design will minimize the risk with regulatory certifications
including FCC, IC, CE, TELEC, and China.
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7.2
DESCRIPTION
CC3220MOD
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7.3.1
www.ti.com
General Layout Recommendations
Ensure that the following general layout recommendations are followed:
• Have a solid ground plane and ground vias under the module for stable system and thermal
dissipation.
• Do not run signal traces underneath the module on a layer where the module is mounted.
• RF traces must have 50-Ω impedance.
• RF trace bends must be made with gradual curves, and 90 degree bends must be avoided.
• RF traces must not have sharp corners.
• There must be no traces or ground under the antenna section.
• RF traces must have via stitching on the ground plane beside the RF trace on both sides.
• RF traces must be as short as possible. The antenna, RF traces, and the module must be on the edge
of the PCB product in consideration of the product enclosure material and proximity.
7.3.2
RF Layout Recommendations
ADVANCE INFORMATION
The RF section of this wireless device gets top priority in terms of layout. It is very important for the RF
section to be laid out correctly to ensure optimum performance from the device. A poor layout can cause
low-output power, EVM degradation, sensitivity degradation, and mask violations.
Figure 7-2 shows the RF placement and routing of the CC3220MODx module.
Figure 7-2. RF Section Layout
66
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ADVANCE INFORMATION
To avoid the impact of mounting shift of the RF components, ensure that the copper cut on the top layer
matches that indicated in Figure 7-3.
Figure 7-3. Top Layer Copper Pullback on RF Pads
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7.3.3
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Antenna Placement and Routing
The antenna is the element used to convert the guided waves on the PCB traces to the free space
electromagnetic radiation. The placement and layout of the antenna are the keys to increased range and
data rates. Table 7-2 provides a summary of the recommended antennas to use with the CC3220MODx
module.
Table 7-2. Antenna Guidelines
SR NO.
GUIDELINES
ADVANCE INFORMATION
1
Place the antenna on an edge or corner of the PCB.
2
Ensure that no signals are routed across the antenna elements on all the layers of the
PCB.
3
Most antennas, including the chip antenna used on the LaunchPad™, require ground
clearance on all the layers of the PCB. Ensure that the ground is cleared on inner layers
as well.
4
Ensure that there is provision to place matching components for the antenna. These must
be tuned for best return loss when the complete board is assembled. Any plastics or
casing must also be mounted while tuning the antenna because this can impact the
impedance.
5
Ensure that the antenna impedance is 50 Ω because the device is rated to work only with
a 50-Ω system.
6
In case of printed antenna, ensure that the simulation is performed with the solder mask
in consideration.
7
Ensure that the antenna has a near omnidirectional pattern.
8
The feed point of the antenna is required to be grounded. This is only for the antenna
type used on the CC3220MODx Launchpad. See the specific antenna data sheets for the
recommendations.
9
To use the FCC certification of the module, refer to CC31xx and CC32xx Radio
Certifications wiki page on CC3220MODx Radio certification
Table 7-3 lists the recommended antennas to use with the CC3220MODx module.
Table 7-3. Recommended Components
CHOICE
1
68
PART NUMBER
AH316M245001-T
MANUFACTURER
NOTES
Taiyo Yuden
Can be placed on edge of the PCB and uses much
less PCB space
Applications, Implementation, and Layout
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Transmission Line Considerations
ADVANCE INFORMATION
The RF signal from the device is routed to the antenna using a Coplanar Waveguide with ground (CPWG) structure. CPW-G structure offers the maximum amount of isolation and the best possible shielding to
the RF lines. In addition to the ground on the L1 layer, placing GND vias along the line also provides
additional shielding. Figure 7-4 shows a cross section of the coplanar waveguide with the critical
dimensions.
Figure 7-4. Coplanar Waveguide (Cross Section)
Figure 7-5 shows the top view of the coplanar waveguide with GND and via stitching.
S
W
Figure 7-5. CPW With GND and Via Stitching (Top View)
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The recommended values for the PCB are provided for 2-layer boards in Table 7-4 and 4-layer boards in
Table 7-5.
Table 7-4. Recommended PCB Values for 2-Layer
Board (L1 to L2 = 41.8 mils)
PARAMETER
VALUE
UNIT
24.5
mils
S
6.5
mils
H
41.8
mils
Er (FR-4 substrate)
4.8
W
Table 7-5. Recommended PCB Values for 4-Layer
Board (L1 to L2 = 16 mils)
PARAMETER
ADVANCE INFORMATION
70
VALUE
UNITS
W
21
mils
S
10
mils
H
16
mils
Er (FR-4 substrate)
4.2
Applications, Implementation, and Layout
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8 Environmental Requirements and Specifications
8.1
Temperature
8.1.1
PCB Bending
The PCB bending specification will maintain planeness at a thickness of less than 0.1 mm.
8.2
Handling Environment
8.2.1
Terminals
The product is mounted with motherboard through land-grid array (LGA). To prevent poor soldering, do
not make skin contact with the LGA portion.
8.2.2
Falling
8.3
Storage Condition
8.3.1
Moisture Barrier Bag Before Opened
A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH.
The calculated shelf life for the dry-packed product will be 12 months from the date the bag is sealed.
8.3.2
Moisture Barrier Bag Open
Humidity indicator cards must be blue, < 30%.
8.4
Baking Conditions
Products require baking before mounting if:
• Humidity indicator cards read > 30%
• Temp < 30°C, humidity < 70% RH, over 96 hours
Baking condition: 90°C, 12 to 24 hours
Baking times: 1 time
8.5
Soldering and Reflow Condition
•
•
•
•
•
•
Heating method: Conventional convection or IR convection
Temperature measurement: Thermocouple d = 0.1 mm to 0.2 mm CA (K) or CC (T) at soldering
portion or equivalent method
Solder paste composition: Sn/3.0 Ag/0.5 Cu
Allowable reflow soldering times: 2 times based on the reflow soldering profile
(see Figure 8-1)
Temperature profile: Reflow soldering will be done according to the temperature profile (see
Figure 8-1)
Peak temperature: 245°C
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ADVANCE INFORMATION
The mounted components will be damaged if the product falls or is dropped. Such damage may cause the
product to malfunction.
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ADVANCE INFORMATION
Figure 8-1. Temperature Profile for Evaluation of Solder Heat Resistance of a Component
(at Solder Joint)
NOTE
TI does not recommend the use of conformal coating or similar material on the SimpleLink
module. This coating can lead to localized stress on the WCSP solder connections inside the
module and impact the device reliability. Use caution during the module assembly process to
the final PCB to avoid the presence of foreign material inside the module.
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9 Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the CC3220MODx applications:
Software Development Tools: Code Composer Studio Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software ( DSP/BIOS™), which provides the basic run-time target
software needed to support any CC3220MODx application.
For a complete listing of development-support tools for the CC3220MODx platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.
9.1.1.1
Firmware Updates
TI updates features in the service pack for this module with no published schedule. Due to the ongoing
changes, TI recommends that the user has the latest service pack in his or her module for production. To
stay informed, sign up for the SDK Alert Me button on the tools page or www.ti.com/tool/cc3220sdk.
9.1.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the
CC3220MODx and support tools (see Figure 9-1).
X
CC 3 2 2 0 MOD XXXX MOB
R
PACKAGING
R = tape/reel
T = small reel
PREFIX
X = preproduction device
no prefix = production device
PACKAGE DESIGNATOR
MOB = LGA package
SM2 = S module
SF12 = SF module
DEVICE FAMILY
CC = wireless connectivity
SERIES NUMBER
3 = Wi-Fi Centric
MODULE
MOD = module
Figure 9-1. CC3220MODx Device Nomenclature
For orderable part numbers of CC3220MODx devices in the MOB package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
9.2
Documentation Support
The following documents describe the CC3220MODx processor/MPU. Copies of these documents are
available on the Internet at www.ti.com.
SimpleLink™ Wi-Fi® CC3220 and Internet of Things Technical Reference Manual
9.2.1
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
Device and Documentation Support
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ADVANCE INFORMATION
Hardware Development Tools: Extended Development System ( XDS™) Emulator
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TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
9.3
Trademarks
SimpleLink, Internet-on-a-chip, SmartConfig, Texas Instruments, E2E, LaunchPad, Code Composer
Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
Thumb is a registered trademark of ARM Ltd.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Macrocell is a trademark of Kappa Global Inc.
Wi-Fi CERTIFIED is a trademark of Wi-Fi Alliance.
Wi-Fi, Wi-Fi Direct are registered trademarks of Wi-Fi Alliance.
ZigBee is a registered trademark of ZigBee Alliance.
9.4
Electrostatic Discharge Caution
ADVANCE INFORMATION
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.5
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
9.6
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
74
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document.
Figure 10-1 shows the CC3220MODx module.
10.1 Mechanical Drawing
17.75
17.25
A
B
PIN 1 INDEX
AREA
ADVANCE INFORMATION
20.75
20.25
2X (0.42)
2X (0.38)
2.45 MAX
C
0.1
0.88
0.72
2X 12.7
(0.3) TYP
20X 1.27
30X 1.27
17
27
16
28
15
9X
2 0.05
1.5
29
(0.3)
TYP
(0.32)
PADS 1,16, 28, and 43
60
57
2X
19.05
63
56
59
62
6X 3
61
55
58
54X
2
1
42
54
44
PIN 1 ID
(45 X1)
0.81
0.15
0.05
0.05
C A B
C
43
1.5
6X 3
Figure 10-1. Mechanical Drawing
NOTE
The total height of the module is 2.45 mm.
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PKG
SEE DETAIL
54X ( 0.81)
44
54
1
43
42
2
( 8.1)
9X ( 2)
0.05 MIN TYP
( 0.2) TYP
VIA
61
55
SOLDER MASK
OPENING
9X
METAL UNDER
SOLDER MASK
59
62
56
PKG
6X (3)
2X (19.1)
(1.5)
63
57
ADVANCE INFORMATION
(0.65)
TYP
60
(1.5)
(0.65)
TYP
6X (3)
(1.27) TYP
15
29
16
(R0.05)
ALL PADS
28
17
27
2X (16.1)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE: 6X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SIGNAL PADS DETAIL
Figure 10-2. Land Pattern Drawing
76
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PKG
54X (
0.81)
54
44
1
(R0.05)
TYP
43
2
42
SOLDER MASK
EDGE, TYP
SOLDER MASK EDGE
58
55
SEE DETAILS
61
59
62
56
PKG
(3) TYP
2X (19.1)
(1.5) TYP
57
63
60
ADVANCE INFORMATION
(1.5) TYP
(3) TYP
(1.27) TYP
15
29
16
28
17
27
2X (16.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PADS PRINTED SOLDER COVERAGE BY AREA
PAD 55: 77.5 %, PADS 56 - 63: 79%
SCALE: 6X
(1.54)
(0.55) TYP
(0.55) TYP
(0.45)
2X ( 0.89)
(R0.05)
TYP
(0.55 TYP)
( 0.89) TYP
(0.55) TYP
METAL
TYP
(R0.05) TYP
PADS 56 - 63 DETAIL
PAD 55 DETAIL
SCALE: 10X
SCALE: 10X
Figure 10-3. Solder Paste Drawing
NOTE
1. All dimensions are in mm.
2. Solder mask should be the same or 5% larger than the dimension of the pad
3. Solder paste must be the same as the pin for all peripheral pads. For ground pins, make
the solder paste 20% smaller than the pad.
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11 Tape and Reel Information
ADVANCE INFORMATION
Surface resistance
Spec
78
Tape and Reel Information
Vendor No.
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ADVANCE INFORMATION
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25
1000
Tape and Reel Information
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
XCC3220MODSF12MOBR
ACTIVE
VQFN
RGK
64
1000
TBD
Call TI
Call TI
-40 to 85
XCC3220MODSM2MOBR
ACTIVE
VQFN
RGK
64
1000
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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