Intersil EL8173FSZ Micropower, single supply, rail-to-rail input-output instrumentation amplifier Datasheet

EL8170, EL8173
®
Data Sheet
February 14, 2008
Micropower, Single Supply, Rail-to-Rail
Input-Output Instrumentation Amplifiers
The EL8170 and EL8173 are micropower instrumentation
amplifiers optimized for single supply operation over the
+2.4V to +5.5V range. Inputs and outputs can operate
rail-to-rail. As with all instrumentation amplifiers, a pair of
inputs provide very high common-mode rejection and are
completely independent from a pair of feedback terminals.
The feedback terminals allow zero input to be translated to
any output offset, including ground. A feedback divider
controls the overall gain of the amplifier.
The EL8170 is compensated for a gain of 100 or more, and
the EL8173 is compensated for a gain of 10 or more. The
EL8170 and EL8173 have bipolar input devices for best
offset and 1/f noise performance.
The amplifiers can be operated from one lithium cell or two
Ni-Cd batteries. The EL8170 and EL8173 input range
includes ground to slightly above positive rail. The output
stage swings to ground and positive supply (no pull-up or
pull-down resistors are needed).
FN7490.4
Features
• 95µA maximum supply current
• Maximum offset voltage
- 200µV (EL8170)
- 1000µV (EL8173)
• Maximum 3nA input bias current
• 396kHz -3dB bandwidth (G = 10)
• 192kHz -3dB bandwidth (G = 100)
• Single supply operation
- Input voltage range is rail-to-rail
- Output swings rail-to-rail
• Pb-free (RoHS compliant)
Applications
• Battery- or solar-powered systems
• Strain gauges
• Current monitors
• Thermocouple amplifiers
Pinout
EL8170, EL8173
(8 LD SOIC)
TOP VIEW
EN 1
IN- 2
+
+
Σ
IN+ 3
8 FB+
7 V+
6 VOUT
V- 4
5 FB-
1
Ordering Information
PART NUMBER
(Note)
PART
MARKING
PACKAGE
PKG.
DWG. #
EL8170FSZ*
8170FSZ
8 Ld SOIC
MDP0027
EL8173FSZ*
8173FSZ
8 Ld SOIC
MDP0027
*Add “-T7” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2007, 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL8170, EL8173
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage (EL8170) . . . . . . . . . . . . . . . . . . . . . . 0.5V
Differential Input Voltage (EL8173) . . . . . . . . . . . . . . . . . . . . . . 1.0V
VEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
110
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Ambient Operating Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = +5V, V- = GND, VCM = 1/2V+, VEN = V-, RL = Open, TA = +25°C, unless otherwise specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by
characterization.
DESCRIPTION
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
DC SPECIFICATIONS
VOS
Input Offset Voltage
EL8170
-200
-300
±50
200
300
µV
EL8173
-1000
-1500
±200
1000
1500
µV
TCVOS
Input Offset Voltage Temperature
Coefficient
IOS
Input Offset Current between IN+, and
IN- and between FB+ and FB-
-2
-3
±0.2
2
3
nA
IB
Input Bias Current (IN+, IN-, FB+, and
FB- terminals)
-3
-4
±0.7
3
4
nA
VIN
Input Voltage Range
Guaranteed by CMRR test
5
V
CMRR
Common Mode Rejection Ratio
EL8170
EL8170
0.24
EL8173
2.5
VCM = 0V to +5V
EL8173
PSRR
Power Supply Rejection Ratio
EL8170
V+ = +2.4V to +5V
EL8173
EG
Gain Error
EL8170
RL = 100kΩ to +2.5V
EL8173
VOUT
Maximum Voltage Swing
0
Supply Current, Enabled
2
µV/°C
90
85
114
dB
85
80
106
dB
85
80
106
dB
75
70
90
dB
-1.5
2
+0.35
1.5
2
%
-0.4
-0.8
+0.1
0.4
0.8
%
4
10
mV
0.13
0.2
0.25
V
Output low, RL = 100kΩ to +2.5V
Output low, RL = 1kΩ to +2.5V
IS,EN
µV/°C
Output high, RL = 100kΩ to +2.5V
4.985
4.980
4.996
V
Output high, RL = 1kΩ to +2.5V
4.75
4.887
V
45
38
65
95
110
µA
FN7490.4
February 14, 2008
EL8170, EL8173
Electrical Specifications
PARAMETER
V+ = +5V, V- = GND, VCM = 1/2V+, VEN = V-, RL = Open, TA = +25°C, unless otherwise specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by
characterization. (Continued)
DESCRIPTION
CONDITIONS
IS,DIS
Supply Current, Disabled
VENH
EN Pin for Shut-down
VENL
EN Pin for Power-on
VSUPPLY
Supply Operating Range
IO+
Output Source Current into 10Ω to V+/2 V+ = +5V
IO-
Output Sink Current into 10Ω to V+/2
EN = V+
MIN
(Note 2)
1.8
1.3
TYP
2.6
MAX
(Note 2)
4
5
2
µA
V
0.8
V+ to V- (Note 3)
UNIT
2.4
5.5
V
V
23
19
32
mA
V+ = +2.4V
6
4.5
8
mA
V+ = +5V
19
15
26
mA
V+ = +2.4V
5
4
7
mA
Gain = 100
192
kHz
Gain = 200
93
kHz
AC SPECIFICATIONS
-3dB BW
-3dB Bandwidth
EL8170
EL8173
eN
Input Noise Voltage
EL8170
Gain = 500
30
kHz
Gain = 1000
13
kHz
Gain = 10
396
kHz
Gain = 20
221
kHz
Gain = 50
69
kHz
Gain = 100
30
kHz
f = 0.1Hz to 10Hz
3.5
µVP-P
3.6
µVP-P
EL8173
Input Noise Voltage Density
iN
Input Noise Current Density
CMRR @ 60Hz Input Common Mode Rejection Ratio
EL8170
58
nV/√Hz
EL8173
220
nV/√Hz
EL8170, fo = 1kHz
0.38
pA/√Hz
EL8173, fo = 1kHz
0.8
pA/√Hz
EL8170
EL8173
PSRR+ @
120Hz
Power Supply Rejection Ratio (V+)
PSRR- @
120Hz
Power Supply Rejection Ratio (V-)
EL8170
EL8173
EL8170
EL8173
fo = 1kHz
VCM = 1VP-P,
RL = 10kΩ to VCM
100
dB
84
dB
V+, V- = ±2.5V,
VSOURCE = 1VP-P,
RL = 10kΩ to VCM
98
dB
78
dB
106
dB
82
dB
V+, V- = ±2.5V,
VSOURCE = 1VP-P,
RL = 10kΩ to VCM
TRANSIENT RESPONSE
SR
RL = 1kΩ to GND
Slew Rate
0.4
0.35
0.55
0.7
0.7
V/µs
NOTES:
2. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
3. VSUPPLY = +5.25V max when VENL = +V (device in disable state).
3
FN7490.4
February 14, 2008
EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified.
90
70
COMMON-MODE INPUT = 1/2V+
GAIN = 10,000V/V
80
COMMON-MODE INPUT = 1/2V+
GAIN = 1000
60
GAIN = 500
GAIN = 5,000V/V
50
GAIN = 2,000V/V
GAIN (dB)
GAIN (dB)
70
GAIN = 1,000V/V
60
GAIN = 500V/V
50
30
GAIN = 100V/V
1
10
GAIN = 100
40
GAIN = 50
30
GAIN = 200V/V
40
GAIN = 200
GAIN = 20
GAIN = 10
20
100
1k
10k
100k
10
1E+00
1M
1E+01
1E+02
1E+03
1E+04
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. EL8170 FREQUENCY RESPONSE vs CLOSED
LOOP GAIN
1E+05
1E+06
FIGURE 2. EL8173 FREQUENCY RESPONSE vs CLOSED
LOOP GAIN
45
V+ = 5V
V+ = 5V
40
20
35
25
GAIN (dB)
30
GAIN (dB)
V+ = 3.3V
V+ = 3.3V
V+ = 2.4V
20
15
10
5
AV = 100
RL = 10kΩ
CL = 10pF
RF/RG = 99.02
RF = 221kΩ
RG = 2.23kΩ
0
100
15
10
5
1k
10k
100k
V+ = 2.4V
AV = 10
R = 10kΩ
CL = 10pF
RF/RG = 9.08Ω
RF = 178kΩ
RG = 19.6kΩ
0
100
1M
1k
FREQUENCY (Hz)
FIGURE 3. EL8170 FREQUENCY RESPONSE vs SUPPLY
VOLTAGE
CL = 100pF
25
CL = 47pF
CL = 820pF
20
GAIN (dB)
CL = 470pF
GAIN (dB)
1M
30
45
40
CL = 220pF
30
100k
FIGURE 4. EL8173 FREQUENCY RESPONSE vs SUPPLY
VOLTAGE
50
35
10k
FREQUENCY (Hz)
CL = 56pF
AV = 100
V+, V- = ±2.5V
RL = 10kΩ
RF/RG = 99.02
RF = 221kΩ
RG = 2.23kΩ
25
100
CL = 27pF
15
CL = 2.7pF
10
5
1k
10k
100k
1M
AV = 10
V+ = 5V
RL = 10kΩ
RF/RG = 9.08Ω
RF = 178kΩ
RG = 19.6kΩ
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. EL8170 FREQUENCY RESPONSE vs CLOAD
4
FIGURE 6. EL8173 FREQUENCY RESPONSE vs CLOAD
FN7490.4
February 14, 2008
EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified.
120
(Continued)
90
80
100
70
60
CMRR
CMRR (dB)
CMRR (dB)
80
60
40
CMRR
50
40
30
20
10
20
0
0
-10
10
100
1k
10k
100k
1M
10
100
FREQUENCY (Hz)
10k
100k
1M
FIGURE 8. EL8173 CMRR vs FREQUENCY
FIGURE 7. EL8170 CMRR vs FREQUENCY
90
140
80
120
PSRR+
70
PSRR+
100
60
PSRR (dB)
PSRR (dB)
1k
FREQUENCY (Hz)
80
PSRR-
60
PSRR50
40
30
40
20
20
10
0
10
100
1k
10k
100k
0
10
1M
100
FREQUENCY (Hz)
100k
1M
2.5
INPUT VOLTAGE NOISE (µV/÷Hz)
250
INPUT VOLTAGE NOISE (nV/√Hz)
10k
FIGURE 10. EL8173 PSRR vs FREQUENCY
FIGURE 9. EL8170 PSRR vs FREQUENCY
200
150
100
50
1k
FREQUENCY (Hz)
2.0
1.5
1.0
0.5
0.0
1
10
100
1k
10k
FREQUENCY (Hz)
FIGURE 11. EL8170 VOLTAGE NOISE DENSITY
5
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 12. EL8173 VOLTAGE NOISE DENSITY
FN7490.4
February 14, 2008
EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified.
5.0
4.5
0.9
CURRENT NOISE (pA/√Hz)
CURRENT NOISE (pA/√Hz)
1.0
(Continued)
0.8
0.7
0.6
0.5
0.4
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.3
1
10
100
1k
10k
0.0
100k
1
10
100
FREQUENCY (Hz)
FIGURE 13. EL8170 CURRENT NOISE DENSITY
VOLTAGE NOISE (0.5µV/DIV)
VOLTAGE NOISE (0.5µV/DIV)
TIME (1s/DIV)
FIGURE 15. EL8170 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
(GAIN = 100)
FIGURE 16. EL8173 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
(GAIN = 10)
90
85
N = 2000
85
80
MAX
75
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
100k
10k
FIGURE 14. EL8173 CURRENT NOISE DENSITY
TIME (1s/DIV)
70
65
MEDIAN
60
55
MIN
50
45
40
1k
FREQUENCY (Hz)
N = 1000
80
MAX
75
MEDIAN
70
65
60
MIN
55
50
45
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
FIGURE 17. EL8170 SUPPLY CURRENT ENABLED vs
TEMPERATURE, V+, V- = ±2.5V, VIN = 0V
6
120
40
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 18. EL8173 SUPPLY CURRENT ENABLED vs
TEMPERATURE, V+, V- = ±2.5V, VIN = 0V
FN7490.4
February 14, 2008
EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified.
5.0
5.0
N = 1000
N = 2000
4.5
SUPPLY CURRENT (µA)
4.5
MAX
SUPPLY CURRENT (µA)
(Continued)
4.0
3.5
3.0
MEDIAN
2.5
MIN
MAX
4.0
3.5
3.0
MEDIAN
2.5
MIN
2.0
2.0
1.5
-40
1.5
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
-40
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 19. EL8170 SUPPLY CURRENT DISABLED vs
TEMPERATURE, V+, V- = ±2.5V, VEN = V+, VIN = 0V
FIGURE 20. EL8173 SUPPLY CURRENT DISABLED vs
TEMPERATURE, V+, V- = ±2.5V, VEN = V+, VIN = 0V
300
1000
N = 2000
N = 1000
MAX
200
-20
MAX
500
VOS (µV)
VOS (µV)
100
MEDIAN
0
-100
MEDIAN
0
-500
MIN
MIN
-1000
-200
-300
-40
-20
0
20
40
60
80
100
-1500
120
-40
-20
0
TEMPERATURE (°C)
FIGURE 21. EL8170 VOS vs TEMPERATURE, V+, V- = ±2.5V,
VIN = 0V
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 22. EL8173 VOS vs TEMPERATURE, V+, V- = ±2.5V,
VIN = 0V
1000
400
N = 1000
N = 2000
MAX
300
MAX
500
VOS (µV)
VOS (µV)
200
100
MEDIAN
0
-100
MIN
0
MEDIAN
-500
-1000
-200
MIN
-1500
-300
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 23. EL8170 VOS vs TEMPERATURE, V+, V- = ±1.2V,
VIN = 0V
7
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 24. EL8173 VOS vs TEMPERATURE, V+, V- = ±1.2V,
VIN = 0V
FN7490.4
February 14, 2008
EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified.
140
140
N = 2000
N = 1000
MAX
130
MAX
130
120
MEDIAN
CMRR (dB)
CMRR (dB)
(Continued)
110
100
120
MEDIAN
110
100
MIN
90
80
-40
90
-20
0
20
40
60
80
100
80
-40
120
MIN
-20
0
TEMPERATURE (°C)
FIGURE 25. EL8170 CMRR vs TEMPERATURE,
VCM = +2.5V TO -2.5V, V+, V- = ±2.5V
140
N = 2000
MAX
130
130
120
120
MEDIAN
110
100
90
N = 1000
60
80
100
120
MAX
110
100
MEDIAN
90
80
80
MIN
MIN
70
70
60
-40
40
FIGURE 26. EL8173 CMRR vs TEMPERATURE,
VCM = +2.5V TO -2.5V, V+, V- = ±2.5V
PSRR (dB)
PSRR (dB)
140
20
TEMPERATURE (°C)
-20
0
20
40
60
80
100
60
-40
120
-20
0
TEMPERATURE (°C)
20
40
60
80
TEMPERATURE (°C)
100
120
100
120
FIGURE 28. EL8173 PSRR vs TEMPERATURE,
V+, V- = ±1.2V TO ±2.5V
FIGURE 27. EL8170 PSRR vs TEMPERATURE,
V+, V- = ±1.2V TO ±2.5V
2.4
0.7
N = 1000
N = 2000
0.6
GAIN ERROR (%)
GAIN ERROR (%)
1.9
MAX
1.4
0.9
MEDIAN
0.4
-20
0.4
MAX
0.3
0.2
MEDIAN
0.1
0
MIN
-0.1
-40
0.5
MIN
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 29. EL8170 %GAIN ERROR vs TEMPERATURE,
RL = 100k
8
-0.1
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 30. EL8173 %GAIN ERROR vs TEMPERATURE,
RL = 100k
FN7490.4
February 14, 2008
EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified.
4.91
4.91
N = 2000
N = 1000
4.90
4.90
MAX
MAX
4.89
MEDIAN
4.88
VOUT (V)
VOUT (V)
4.89
4.87
MEDIAN
4.88
4.87
MIN
MIN
4.86
4.86
4.85
4.85
4.84
-40
-20
0
20
40
60
80
100
4.84
-40
120
-20
0
FIGURE 31. EL8170 VOUT HIGH vs TEMPERATURE,
RL = 1k, V+, V- = ±2.5V
100
120
N = 1000
160
VOUT (mV)
VOUT (mV)
80
180
180
MAX
140
MEDIAN
120
160
MAX
140
120
MIN
MEDIAN
MIN
100
100
-20
0
20
40
60
80
100
80
-40
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 33. EL8170 VOUT LOW vs TEMPERATURE,
RL = 1k, V+, V- = ±2.5V
FIGURE 34. EL8173 VOUT LOW vs TEMPERATURE,
RL = 1k, V+, V- = ±2.5V
0.70
N = 2000
N = 1000
MAX
0.60
MAX
0.65
+ SLEW RATE (V/µS)
+ SLEW RATE (V/µS)
60
200
N = 2000
0.55
MEDIAN
0.50
MIN
0.45
0.40
0.60
MEDIAN
0.55
0.50
MIN
0.45
0.35
0.30
-40
40
FIGURE 32. EL8173 VOUT HIGH vs TEMPERATURE,
RL = 1k, V+, V- = ±2.5V
200
0.65
20
TEMPERATURE (°C)
TEMPERATURE (°C)
80
-40
(Continued)
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 35. EL8170 + SLEW RATE vs TEMPERATURE,
INPUT ±0.015V @ GAIN + 100
9
0.40
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 36. EL8173 + SLEW RATE vs TEMPERATURE,
INPUT ±0.015V @ GAIN + 100
FN7490.4
February 14, 2008
EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified.
0.70
N = 2000
- SLEW RATE (V/µS)
0.65
0.60
MEDIAN
0.55
0.50
MIN
0.45
0.40
MEDIAN
0.60
0.55
MIN
0.50
0.45
0.35
0.30
-40
MAX
N = 1000
MAX
0.65
- SLEW RATE (V/µS)
0.70
(Continued)
-20
0
20
40
60
80
100
0.40
-40
120
-20
0
TEMPERATURE (°C)
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 37. EL8170 - SLEW RATE vs TEMPERATURE,
INPUT ±0.015V @ GAIN + 100
FIGURE 38. EL8173 - SLEW RATE vs TEMPERATURE,
INPUT ±0.015V @ GAIN + 100
Pin Descriptions
EL8170, EL8173
PIN NAME
EQUIVALENT CIRCUIT
PIN FUNCTION
1
EN
Circuit 2
Active LOW logic pins. When pulled above 2V, the corresponding channel turns off
and OUT is high impedance. A channel is enabled when pulled below 0.8V. Built-in
pull downs define each EN pin LOW when left floating.
2
IN-
Circuit 1A, Circuit 1B
3
IN+
Circuit 1A, Circuit 1B
High impedance input terminals. EL8170 input circuit is shown in Circuit 1A, and
the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it is
recommended that the terminals are not overdriven beyond 1V and the input
current must never exceed 5mA.
4
V-
Circuit 4
5
FB-
Circuit 1A, Circuit 1B
8
FB+
Circuit 1A, Circuit 1B
7
V+
Circuit 4
Positive supply terminal.
6
VOUT
Circuit 3
Output Voltage.
Negative supply terminal.
High impedance feedback terminals. EL8170 input circuit is shown in Circuit 1A,
and the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it
is recommended that the terminals are not overdriven beyond 1V and the input
current must never exceed 5mA.
V+
V+
IN+
FB+
INFB-
V+
LOGIC
PIN
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
V-
CIRCUIT 1A
V+
V-
VCIRCUIT 2
VCIRCUIT 3
CIRCUIT 4
V+
INFB-
IN+
FB+
V-
CIRCUIT 1B
10
FN7490.4
February 14, 2008
EL8170, EL8173
Description of Operation and Applications
Information
Product Description
The EL8170 and EL8173 are micropower instrumentation
amplifiers (in-amps) which deliver rail-to-rail input amplification
and rail-to-rail output swing on a single +2.4V to +5.5V supply.
The EL8170 and EL8173 also deliver excellent DC and AC
specifications while consuming only 65µA typical supply
current. Because the EL8170 and EL8173 provide an
independent pair of feedback terminals to set the gain and to
adjust output level, these in-amps achieve high common-mode
rejection ratio regardless of the tolerance of the gain setting
resistors. The EL8173 is internally compensated for a minimum
closed loop gain of 10 or greater, well suited for moderate to
high gains. For higher gains, the EL8170 is internally
compensated for a minimum gain of 100. An EN pin is used to
reduce power consumption, typically 2.6µA, while the
instrumentation amplifier is disabled.
Input Protection
All input and feedback terminals of the EL8170 and EL8173
have internal ESD protection diodes to both positive and
negative supply rails, limiting the input voltage to within one
diode drop beyond the supply rails. The inverting inputs and
FB- inputs have ESD diodes to the V-rail, and the
non-inverting inputs and FB+ terminals have ESD diodes to
the V+ rail. The EL8170 has additional back-to-back diodes
across the input terminals and also across the feedback
terminals. If overdriving the inputs is necessary, the external
input current must never exceed 5mA. On the other hand,
the EL8173 has no clamps to limit the differential voltage on
the input terminals allowing higher differential input voltages
at lower gain applications. It is recommended however, that
the input terminals of the EL8173 are not overdriven beyond
1V to avoid offset drift. An external series resistor may be
used as an external protection to limit excessive external
voltage and current from damaging the inputs.
Input Stage and Input Voltage Range
The input terminals (IN+ and IN-) of the EL8170 and EL8173
are single differential pair bipolar PNP devices aided by an
Input Range Enhancement Circuit to increase the headroom
of operation of the common-mode input voltage. The
feedback terminals (FB+ and FB-) also have a similar
topology. As a result, the input common-mode voltage range
of both the EL8170 and EL8173 is rail-to-rail. These in-amps
are able to handle input voltages that are at or slightly beyond
the supply and ground making these in-amps well suited for
single +5V or +3.3V low voltage supply systems. There is no
need to move the common-mode input of the in-amps to
achieve symmetrical input voltage.
11
Input Bias Cancellation, Input Bias Compensation
Both EL8170 and EL8173 feature an Input Bias
Cancellation/Compensation Circuit for both the input and
feedback terminals (IN+, IN-, FB+ and FB-), achieving a low
input bias current all throughout the input common-mode
range and the operating temperature range. While the PNP
bipolar input stages are biased with an adequate amount of
biasing current for speed and increased noise performance,
the Input Bias Cancellation/Compensation Circuit sinks most
of the base current of the input transistor leaving a small
portion as input bias current, typically 500pA. In addition, the
Input Bias Cancellation/Compensation Circuit maintains a
smooth and flat behavior of input bias current over the
common mode range and over the operating temperature
range. The Input Bias Cancellation, Input Bias Compensation
Circuit operates from input voltages of 10mV above the
negative supply to input voltages slightly above the positive
supply. See “Average Input Bias Current vs Common-Mode
Input Voltage” in the “Typical Performance Curves” beginning
on page 4.
Output Stage and Output Voltage Range
A pair of complementary MOSFET devices drives the output
VOUT to within a few millivolts of the supply rails. At a 100kΩ
load, the PMOS sources current and pulls the output up to
4mV below the positive supply, while the NMOS sinks
current and pulls the output down to 4mV above the negative
supply, or ground in the case of a single supply operation.
The current sinking and sourcing capability of the EL8170
and EL8173 are internally limited to 26mA.
Gain Setting
VIN, the potential difference across IN+ and IN-, is replicated
(less the input offset voltage) across FB+ and FB-. The
objective of the EL8170 and EL8173 in-amp is to maintain
the differential voltage across FB+ and FB- equal to IN+ and
IN-; (FB+ - FB-) = (IN+ - IN-). Consequently, the transfer
function can be derived. The gain of the EL8170 and EL8173
is set by two external resistors, the feedback resistor RF, and
the gain resistor RG.
FN7490.4
February 14, 2008
EL8170, EL8173
+2.4V TO +5.5V
+2.4V TO +5.5V
7
VIN/2
3 IN+
2 IN-
VIN/2
8 FB+
5 FB-
VCM
7
1
V+
+
EL8170/3
3 IN+
EN
6
VIN/2
8 FB+
VOUT
+
-
V+
EN
+
- EL8170,
EL8173
+
-
6
VOUT
V4
REF
R2
RF
FIGURE 39. GAIN IS SET BY TWO EXTERNAL RESISTORS,
RF AND RG
RF ⎞
⎛
V OUT = ⎜ 1 + --------⎟ V IN
R G⎠
⎝
5 FB-
+2.4V TO +5.5V
VCM
R1
V4
RG
1
VIN/2
2 IN-
-
EN
EN
(EQ. 1)
In Figure 39, the FB+ pin and one end of resistor RG are
connected to GND. With this configuration, Equation 1 is only
true for a positive swing in VIN; negative input swings will be
ignored and the output will be at ground.
RG
RF
FIGURE 40. GAIN SETTING AND REFERENCE CONNECTION
The FB+ pin can also be connected to the other end of
resistor, RG. See Figure 41. Keeping the basic concept that
the EL8170 and EL8173 in-amps maintain constant
differential voltage across the input terminals and feedback
terminals (IN+ - IN- = FB+ - FB-), the transfer function of
Figure 41 can be derived (Equation 3). Note that the VREF
gain term is eliminated, and susceptibility to external noise is
reduced.
Reference Connection
Unlike a three op amp instrumentation amplifier, a finite
series resistance seen at the REF terminal does not degrade
the EL8170 and EL8173's high CMRR performance,
eliminating the need for an additional external buffer
amplifier. The circuit shown in Figure 40 uses the FB+ pin as
a REF terminal to center or to adjust the output. Because the
FB+ pin is a high impedance input, an economical resistor
divider can be used to set the voltage at the REF terminal.
The reference voltage error due to the input bias current is
minimized by keeping the values of the voltage divider
resistors, R1 and R2, as low as possible. Any voltage applied
to the REF terminal will shift VOUT by VREF times the closed
loop gain, which is set by resistors RF and RG according to
Equation 2. Note that any noise or unwanted signals on the
reference supply will be amplified at the output according to
Equation 2.
RF ⎞
RF ⎞
⎛
⎛
V OUT = ⎜ 1 + --------⎟ ( V IN ) + ⎜ 1 + --------⎟ ( V REF )
R
R
⎝
⎝
G⎠
G⎠
12
(EQ. 2)
+2.4V TO +5.5V
7
VIN/2
3 IN+
2 IN-
VIN/2
8 FB+
5 FB-
VCM
EN
1
V+
+
- EL8170,
EL8173
+
-
EN
6
VOUT
V4
VREF
RG
RF
FIGURE 41. REFERENCE CONNECTION WITH AN AVAILABLE
VREF
RF ⎞
⎛
V OUT = ⎜ 1 + --------⎟ ( V IN ) + ( V REF )
R
⎝
G⎠
(EQ. 3)
FN7490.4
February 14, 2008
EL8170, EL8173
External Resistor Mismatches
Power Dissipation
Because of the independent pair of feedback terminals
provided by the EL8170 and EL8173, the CMRR is not
degraded by any resistor mismatches. Hence, unlike a three
op amp and especially a two op amp in-amp, the EL8170
and EL8173 reduce the cost of external components by
allowing the use of 1% or more tolerance resistors without
sacrificing CMRR performance. The EL8170 and EL8173
CMRR is maintained regardless of the tolerance of the
resistors used.
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related in Equation 6:
Gain Error and Accuracy
where:
The EL8173 has a Gain Error, EG, of 0.2% typical. The
EL8170 has an EG of 0.3% typical. The gain error indicated
in the “Electrical Specifications” table on page 2 is the
inherent gain error of the EL8170 and EL8173 and does not
include the gain error contributed by the resistors. There is
an additional gain error due to the tolerance of the resistors
used. The resulting non-ideal transfer function effectively
becomes Equation 4:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
RF ⎞
⎛
V OUT = ⎜ 1 + --------⎟ × [ 1 – ( E RG + E RF + E G ) ] × V IN
R
⎝
G⎠
where:
T JMAX = T MAX + ( θ JA xPD MAXTOTAL )
(EQ. 6)
• PDMAX for each amplifier can be calculated as shown in
Equation 7:
V OUTMAX
PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL
(EQ. 7)
(EQ. 4)
• TMAX = Maximum ambient temperature
Where:
• θJA = Thermal resistance of the package
ERG= Tolerance of RG
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage (Magnitude of V+ and V-)
ERF= Tolerance of RF
• IMAX = Maximum supply current of 1 amplifier
EG= Gain Error of the EL8170 or EL8173
The term [1 - (ERG + ERF + EG)] is the deviation from the
theoretical gain. Thus, (ERG + ERF + EG) is the total gain
error. For example, if 1% resistors are used for the EL8170,
the total gain error would be:
= ± ( E RG + E RF + E G ( typical ) )
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
(EQ. 5)
= ± ( 0.01 + 0.01 + 0.003 )
= ± 2.3%
Disable/Power-Down
The EL8170 and EL8173 can be powered down reducing
the supply current to typically 2.9µA. When disabled, the
output is in a high impedance state. The active low EN bar
pin has an internal pull-down and hence can be left floating
and the in-amp enabled by default. When the EN bar is
connected to an external logic, the in-amp will power down
when the EN bar is pulled above 2V, and will power-on when
the EN bar is pulled below 0.8V.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN7490.4
February 14, 2008
EL8170, EL8173
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
14
FN7490.4
February 14, 2008