Rohm BR25S320FJ-W High speed clock action up to 20mhz(max.), wait function by holdb terminal. Datasheet

High Reliability Series Serial EEPROMs
SPI BUS
BR25□□□□family
BR25S□□□ Series
No.10001EBT08
●Description
BR25S□□□ series is a serial EEPROM of SPI BUS interface method.
●Features
1) High speed clock action up to 20MHz (Max.)
2) Wait function by HOLDB terminal
3) Part or whole of memory arrays settable as read only memory area by program
4) 1.7~5.5V single power source action most suitable for battery use
5) Page write mode useful for initial value write at factory shipment
6) Highly reliable connection by Au pad and Au wire
7) For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1)
8) Auto erase and auto end function at data rewrite
9) Low current consumption
At write action (5V)
: 1.5mA (Typ.)
At read action (5V)
: 1.0mA (Typ.)
At standby action (5V)
: 0.1μA (Typ.)
10) Address auto increment function at read action
11) Write mistake prevention function
Write prohibition at power on
Write prohibition by command code (WRDI)
Write prohibition by WPB pin
Write prohibition block setting by status registers (BP1, BP0)
Write mistake prevention function at low voltage
12) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 Package
13) Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0
14) Data kept for 40 years
15) Data rewrite up to 1,000,000 times
●Page Write
Page
Part Number
32Byte
64Byte
BR25S320-W
BR25S640-W
BR25S128-W
BR25S256-W
●BR25S□□□ series
Capacity Bit format
32Kbit
4K×8
Power source
voltage
SOP8
SOP-J8
1.7V~5.5V
●
●
●
SSOP-B8 TSSOP-B8 MSOP8
●
●
●
8K×8
1.7V~5.5V
●
●
●
●
16K×8
1.7V~5.5V
●
●
●
●
256Kbit
32K×8
1.7V~5.5V
●
●
1/18
●
●
64Kbit
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VSON008
X2030
●
128Kbit
© 2010 ROHM Co., Ltd. All rights reserved.
TSSOP-B8J
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Absolute maximum ratings (Ta=25°C)
Parameter Symbol
Limits
Impressed
Vcc
-0.3~+6.5
voltage
450(SOP8)
Permissible
dissipation
Storage
temperature
range
Operating
temperature
range
Terminal
voltage
Pd
●Memory cell characteristics (Ta=25°C , Vcc=1.7V~5.5V)
Unit
Limits
Parameter
Number of
data rewrite times *1
*1
450(SOP-J8)
*2
300(SSOP-B8)
*3
330(TSSOP-B8)
*4
310(MSOP8)
*5
310(TSSOP-B8J)
*6
300(VSON008X2030)
*7
Data hold years
mW
*1
Min.
Min.
1,000,000
-
-
Time
40
-
-
Year
Unit
*1
Not 100% TESTED
●Recommended action conditions
Parameter
Tstg
-65~+125
℃
Topr
-40~+85
℃
Symbol
Limits
Power source voltage
VCC
1.7~5.5
Input voltage
VIN
0~Vcc
V
●Input / output capacity (Ta=25°C, frequency=5MHz)
Parameter
Input capacity *1
-
-0.3~Vcc+0.3
V
Output capacity *1
*1
* When using at Ta=25℃ or higher, 4.5mW(*1, *2),
3.0mW(*3, *7),3.3mW(*4), 3.1mW(*5, *6) to be reduced per 1℃
Symbol Conditions
Min.
Max.
CIN
VIN=GND
-
8
COUT
VOUT=GND
-
8
VIH1
0.7xVcc
-
Vcc+0.3
V
1.7≦Vcc≦5.5V
“L” Input Voltage1
VIL1
-0.3
-
0.3xVcc
V
1.7≦Vcc≦5.5V
“L” Output Voltage1
VOL1
0
-
0.4
V
IOL=2.1mA, 2.5≦Vcc<5.5V
“L” Output Voltage2
VOL2
0
-
0.2
V
IOL=1.0mA, 1.7≦Vcc<2.5V
“H” Output Voltage1
VOH1
Vcc-0.2
-
Vcc
V
IOH=-0.4mA, 2.5V≦Vcc<5.5V
“H” Output Voltage2
VOH2
Vcc-0.2
-
Vcc
V
IOH=-100µA, 1.7≦Vcc<2.5V
Input Leakage Current
ILI
-1
-
1
μA
VIN=0~Vcc
Output Leakage Current
ILO
-1
-
μA
VOUT=0~Vcc, CSB=Vcc
Operating Current Write
Operating Current Read
ICC1
-
-
ICC2
-
-
pF
Conditions
“H” Input Voltage1
1
0.5
1
1
1.5
2
3
Unit
Not 100% TESTED.
●Electrical characteristics (Unless otherwise specified, Ta=-40~+85°C, Vcc=1.7~5.5V)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
Standby Current
Unit
Min.
V
*1
*2
mA
*1
*2
mA
*1
ICC3
-
-
ICC4
-
-
1
mA
ICC5
-
-
1
mA
ICC6
-
-
1.5
mA
ICC7
-
-
2
mA
ICC8
-
-
2
mA
ICC9
-
-
4
mA
ICC10
-
-
8
mA
ISB
-
-
2
μA
*2
mA
Vcc=1.8V, fSCK=5MHz, tE/W=5ms
Byte Write, Page Write, Write Status register
Vcc=2.5V, fSCK=10MHz, tE/W=5ms
Byte Write, Page Write, Write Status register
Vcc=5.5V, fSCK=20MHz, tE/W=5ms
Byte Write, Page Write, Write Status register
Vcc=1.8V, fSCK=5MHz, SO=OPEN
Read, Read Status Register
Vcc=2.5V, fSCK=2MHz, SO=OPEN
Read, Read Status Register
Vcc=2.5V, fSCK=5MHz, SO=OPEN
Read, Read Status Register
Vcc=2.5V, fSCK=10MHz, SO=OPEN
Read, Read Status Register
Vcc=5.5V, fSCK=5MHz, SO=OPEN
Read, Read Status Register
Vcc=5.5V, fSCK=10MHz, SO=OPEN
Read, Read Status Register
Vcc=5.5V, fSCK=20MHz, SO=OPEN
Read, Read Status Register
Vcc=5.5V, SO=OPEN
CSB=HOLDB=WPB=Vcc, SCK=SI=Vcc or GND
*1 BR25S320/640-W
*2 BR25S128/256-W
○ Radiation resistance design is not made
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© 2010 ROHM Co., Ltd. All rights reserved.
2/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Block diagram
CSB
1
8 Vcc
VOLTAGE
INSTRUCTION DECODE
DETECTION
CONTROL CLOCK
GENERATION
SO
2
WRITE
HIGH VOLTAGE
INHIBITION
GENERATOR
7 HOLDB
INSTRUCTION
REGISTER
WPB
3
STATUS REGISTER
ADDRESS
REGISTER
12~15bit *1
ADDRESS
6 SCK
12~15bit *1
DECODER
*1 12bit: BR25S320-W
13bit: BR25S640-W
14bit: BR25S128-W
15bit: BR25S256-W
32~256K
EEPROM
DATA
GND
4
REGISTER
8bit
READ/WRITE
AMP
8bit
5 SI
Fig.1 Block diagram
●Operating timing characteristics (Ta=-40~+85°C, unless otherwise specified, load capacity CL=30pF)
1.7≦Vcc<2.5V 1.8≦Vcc<2.5V 2.5≦Vcc<4.5V 4.5≦Vcc<5.5V
Symbol
Unit
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
fSCK
3
5
10
20 MHz
SCK frequency
tSCKWH 125
80
40
20
ns
SCK high time
tSCKWL 125
80
40
20
ns
SCK low time
tCS
250
90
40
20
ns
CSB high time
tCSS
100
60
30
15
ns
CSB setup time
100
60
30
15
ns
tCSH
CSB hold time
tSCKS 100
50
20
15
ns
SCK setup time
tSCKH 100
50
20
15
ns
SCK hold time
tDIS
30
20
10
5
ns
SI setup time
tDIH
50
20
10
5
ns
SI hold time
tPD
125
80
40
20
ns
Data output delay time
tOH
0
0
0
0
ns
Output hold time
tOZ
200
80
40
20
ns
Output disable time
100
0
0
0
ns
tHFS
HOLDB setting setup time
tHFH
100
20
10
5
ns
HOLDB setting hold time
tHRS
100
0
0
0
ns
HOLDB release setup time
100
20
10
5
ns
tHRH
HOLDB release hold time
tHOZ
100
80
40
20
ns
Time from HOLDB to output High-Z
tHPD
100
80
40
20
ns
Time from HOLDB to output change
*1
tRC
1
1
1
1
μs
SCK rise time
*1
tFC
1
1
1
1
μs
SCK fall time
*1
tRO
100
50
40
20
ns
OUTPUT rise time
*1
t
FO
100
50
40
20
ns
OUTPUT fall time
Write time
tE/W
5
5
5
5
ms
*1 NOT 100% TESTED
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© 2010 ROHM Co., Ltd. All rights reserved.
3/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Pin assignment and description
Vcc
SCK
HOLDB
SI
Terminal
name
Input
/Output
Vcc
-
Power source to be connected
GND
-
All input / output reference voltage, 0V
CSB
Input
Chip select input
SCK
Input
Serial clock input
SI
Input
Start bit, ope code, address, and serial data input
SO
Output
HOLDB
Input
WPB
Input
BR25S320-W
BR25S640-W
BR25S128-W
BR25S256-W
CSB
SO
WPB
GND
Function
Fig.2 Pin assignment diagram
Serial data output
Hold input
Command communications may be suspended temporarily
(HOLD status)
Write protect input
Write command is prohibited
Write status register command is prohibited
●Sync data input / output timing
tCS
tCSS
tCS
CSB
tSCKS
tRC
tSCKWH
tSCKWL
tCSH tSCKH
CSB
tFC
SCK
SCK
tDIS tDIH
SI
SI
tPD
tRO,tFO
tOH
tOZ
High-Z
SO
High-Z
SO
Fig.4
Fig.3 Input timing
SI is taken into IC inside in sync with data rise edge of
SCK. Input address and data from the most significant bit
MSB
Input / Output timing
SO is output in sync with data fall edge of SCK. Data is
output from the most significant bit MSB.
"H"
CSB
"L"
tHFS
tHFH
tHRS tHRH
SCK
tDIS
SI
n
n+1
tHOZ
n-1
tHPD
High-Z
SO
Dn+1
Dn
Dn
Dn-1
HOLDB
Fig.5
HOLD timing
●AC timing characteristics conditions
Parameter
Limits
Symbol
Load capacity
Min.
Typ.
Max.
-
-
30
CL
Unit
pF
Input rise time
-
-
-
50
ns
Input fall time
-
-
-
50
ns
Input voltage
-
0.2Vcc/0.8Vcc
V
Input / Output judgment voltage
-
0.3Vcc/0.7Vcc
V
●Characteristic data (The following characteristic data are Typ. Values.)
6
6
Ta=-40℃
Ta=25℃
Ta=85℃
5
SPEC
4
VIL[V]
VIH[V]
4
3
3
2
1
1
SPEC
Fig.6
1
2
3
Vcc[V]
"H" input voltage
4
5
6
SPEC
0.2
0
0
0
0.6
0.4
2
0
0
1
2
3
Vcc[V]
4
5
6
VIH(CSB,SCK,SI,HOLDB,WPB) Fig.7 "L" input voltage VIL(CSB,SCK,SI,HOLDB,WPB)
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© 2010 ROHM Co., Ltd. All rights reserved.
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
VOL1[V]
5
1
Ta=-40℃
Ta=25℃
Ta=85℃
4/18
0
1
2
3
IOL[mA]
4
5
6
Fig.8 "L" output voltage VOL1 (Vcc=2.5V)
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
1.5
2.5
1
2.4
SPEC
2.3
1.5
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
Ta=-40℃
Ta=25℃
Ta=85℃
0
-0.5
-0.5
0
0.4
0.8
1.2
0
IOH[mA]
Fig.9 "H" output voltage VOH1 (Vcc=2.5V)
4
5
0
6
2
Ta=-40℃
Ta=25℃
Ta=85℃
2
1
0
1
3
4
5
6
Vcc[V]
Fig.12 Current consumption at WRITE operation ICC3
(BR25S320/640-W)
1
2
3
Vcc[V]
4
5
3
Vcc[V]
SPEC
4
5
6
Ta=-40℃
Ta=25℃
Ta=85℃
100
tSCKWH [ns]
SPEC
SPEC
10
1
2
120
fSCK[MHz]
2
1
140
100
SPEC
4
Fig.14 Current Consumption at READ operation ICC10
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
6
0
1000
Ta=-40℃
Ta=25℃
Ta=85℃
6
Fig.11 Output leak current ILO(SO)
6
Fig.13 Current Consumption at WRITE operation ICC3
(BR25S128/256-W)
5
5
0
0
2
4
2
0
0
3
VOUT[V]
8
ICC10[mA]
SPEC
2
DATA=00h
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
1
10
3
ICC3[mA]
ICC3[mA]
3
Vcc[V]
DATA=00h
1
SPEC
SPEC
80
60
SPEC
40
SPEC
0
20
SPEC
0
1
-1
0
1
2
3
Vcc[V]
4
5
0
6
Fig.15 Current Consumption at standby operation ISB
1
2
3
Vcc[V]
4
5
0
6
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
120
100
tCS[ns]
Ta=-40℃
Ta=25℃
Ta=85℃
150
SPEC
50
20
SPEC
0
1
2
3
Vcc[V]
4
5
Fig.18 SCK low time tSCKWL
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© 2010 ROHM Co., Ltd. All rights reserved.
6
5
6
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
20
SPEC
0
0
4
60
40
40
SPEC
3
Vcc[V]
80
100
SPEC
SPEC
100
tCSS[ns]
200
60
2
120
SPEC
250
SPEC
80
1
Fig.17 SCK high time tSCKWH
Fig.16 SCK frequency fSCK
300
140
tSCKWL [ns]
2
4
DATA=00h
ISB[μA]
1
Fig.10 Input leak current ILI(CSB,SCK,SI,HOLDB,WPB)
4
3
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0
2.2
SPEC
1
ILO[μA]
2.6
ILI[μA]
VOH1[V]
●Characteristic data (The following characteristic data are Typ. Values.)
0
0
1
2
3
Vcc[V]
4
5
Fig.19 CSB high time tCS
5/18
6
0
1
2
3
Vcc[V]
4
5
6
Fig.20 CSB setup time tCSS
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Characteristic data (The following characteristic data are Typ. Values.)
50
120
Ta=-40℃
Ta=25℃
Ta=85℃
100
40
SPEC
SPEC
60
40
20
20
10
0
1
2
3
Vcc[V]
4
5
1
SPEC
5
0
6
80
SPEC
60
SPEC
SPEC
90
2
3
Vcc[V]
4
5
1
Fig.24 Data output delay time tPD
2
3
Vcc[V]
4
5
0
tHOZ [ns]
50
SPEC
SPEC
0
1
2
3
Vcc[V]
4
5
1
2
3
Vcc[V]
4
5
100
SPEC
SPE
1
2
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
40
5
6
Ta=-40℃
Ta=25℃
Ta=85℃
6
SPEC
tE/W[ms]
tFO [ns]
SPEC
4
Fig.29 Time from HOLDB to output change tHPD
80
60
3
Vcc[V]
8
100
80
Ta=-40℃
Ta=25℃
SPEC Ta=85℃
SPEC
0
120
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
6
60
6
Fig.28 Time from HOLDB to output High-Z tHOZ
120
5
0
0
Fig.27 HOLDB release hold time tHRH
4
20
0
6
3
Vcc[V]
40
20
-10
2
80
SPEC
SPEC
1
100
60
40
10
SPEC
Fig.26 HOLDB setting hold time tHFH
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
80
SPEC
SPEC
120
SPEC
100
70
30
60
6
tHPD [ns]
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
20
120
90
6
80
Fig.25 Output disable time tOZ
Ta=-40℃
Ta=25℃
Ta=85℃
110
5
0
0
6
130
4
SPEC
SPEC
30
0
1
3
Vcc[V]
40
SPEC
0
0
2
SPEC
100
120
60
SPE
C
20
1
Fig.23 SI hold time tDIH
Ta=-40℃
Ta=25℃
Ta=85℃
150
tOZ [ns]
tPD [ns]
4
120
SPEC
180
40
tHRH [ns]
3
Vcc[V]
tHFH [ns]
Ta=-40℃
Ta=25℃
Ta=85℃
100
tRO [ns]
2
210
140
SPEC
0
Fig.22 SI setup time tDIS
Fig.21 CSB hold time tCSH
120
SPEC
-10
0
6
SPEC
20
SPEC
0
0
30
10
SPEC
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
40
SPEC
SPEC
SPEC
50
30
tDIS[ns]
tCSH[ns]
80
60
Ta=-40℃
Ta=25℃
Ta=85℃
tDIH[ns]
SPEC
60
SPEC
40
4
SPEC
2
20
SPEC
20
SPEC
0
0
0
0
1
2
3
Vcc[V]
4
5
6
Fig.30 Output rise time tRO
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© 2010 ROHM Co., Ltd. All rights reserved.
0
1
2
3
Vcc[V]
4
5
Fig.31 Output fall time tFO
6/18
6
0
1
2
3
Vcc[V]
4
5
6
Fig.32 Write cycle time tE/W
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Features
○Status registers
This IC has status register. The status register expresses the following parameters of 8 bits.
BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are
valid even when power source is turned off.
Rewrite characteristics and data hold time are same as characteristics of the EEPROM.
WEN can be set by write enable command and write disable command. WEN becomes write disable status when power
source is turned off. R/B is for write confirmation, therefore cannot be set externally.
The value of status register can be read by read status register command.
1. Contexture of status register
Product number
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
BP1
BP0
WEN
R/B
BR25S320-W
BR25S640-W
―
WPEN
BR25S128-W
BR25S256-W
bit
Memory
location
Function
WPEN
EEPROM
WPB pin enable / disable designation bit
WPEN=0=invalid
WPEN=1=valid
BP1
BP0
EEPROM
EEPROM write disable block designation bit
WEN
registers
Write and write status register write enable / disable status confirmation bit
WEN=0=prohibited
WEN=1=permitted
Write cycle status (READY / BUSY) status confirmation bit
―
―
R/B
R/B=0=READY
registers
―
R/B=1=BUSY
2. Write disable block setting
Write disable block
BP1
BP0
BR25S320-W
BR25S640-W
BR25S128-W
BR25S256-W
0
0
None
None
None
None
0
1
C00h-FFFh
1800h-1FFFh
3000h-3FFFh
6000h-7FFFh
1
0
800h-FFFh
1000h-1FFFh
2000h-3FFFh
4000h-7FFFh
1
1
000h-FFFh
0000h-1FFFh
0000h-3FFFh
0000h-7FFFh
○WPB pin
By setting WPB=LOW, write command is prohibited. And the write command to be disabled at this moment is WRSR.
However, when write cycle is in execution, no interruption can be made.
Product number
WRSR
WRITE
BR25S320-W
BR25S640-W
BR25S128-W
Prohibition possible
but WPEN bit “1”
Prohibition
impossible
BR25S256-W
○HOLDB pin
By HOLDB pin, data transfer can be interrupted. When SCK=”0”, by making HOLDB from “1” into”0”, data transfer to
EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted.
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7/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Command mode
Command
Contents
WREN
WRDI
READ
WRITE
RDSR
WRSR
Ope code
Write enable command
Write disable command
Read command
Write command
Read status register command
Write status register command
0000
0000
0000
0000
0000
0000
0110
0100
0011
0010
0101
0001
●Timing chart
1. Write enable (WREN) / disable (WRDI) command
WREN (WRITE ENABLE): Write enable
WRDI (WRITE DISABLE): Write disable
CSB
CSB
SCK
0
SI
SO
1
0
2
0
3
0
4
0
5
0
1
6
7
1
SCK
0
1
2
3
5
4
6
7
0
SI
0
0
0
0
0
1
0
0
High-Z
High-Z
SO
Fig.33
Fig.34
Write enable command
Write disable command
This IC has write enable status and write disable status. It is set to write enable status by write enable command, and it is
set to write disable status by write disable command. As for these commands, set CSB LOW, and then input the
respective ope codes. The respective commands are accepted at the 7-th clock rise. Even with input over 7 clocks,
command becomes valid.
When to carry out write command, it is necessary to set write enable status by the write enable command. If write
command is input in the write disable status, the command is cancelled. And even in the write enable status, once write
command is executed, it gets in the write disable status. After power on, this IC is in write disable status.
2. Read command (READ)
~
~
~
~
CSB
~
~
0
1
2
3
4
5
6
7
8
9
10
11
23
~
~
SCK
24
30
0
0
0
0
1
1
*
A14 A13 A12
A1
~
~
0
~
~
0
A0
~
~
High-Z
D7
D6
~
~
~
~
SO
D2
D1
Address
length
A11-A0
BR25S640-W
A12-A0
BR25S128-W
A13-A0
BR25S256-W
A14-A0
31
~
~
SI
Product
number
BR25S320-W
D0
Fig.35 Read command
By read command, data of EEPROM can be read. As for this command, set CSB LOW, then input address after read ope
code. EEPROM starts data output of the designated address. Data output is started from SCK fall of 23-th clock, and
from D7 to D0 sequentially. This IC has increment read function. After output of data for 1 byte (8bits), by continuing input
of SCK, data of the next address can be read. Increment read can read all the addresses of EEPROM. After reading data
of the most significant address, by continuing increment read, data of the most insignificant address is read.
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8/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
3. Write command (WRITE)
0
2
0
3
0
4
0
5
6
0
7
8
0
1
A14
*
11
A12
10
9
A13
23
A1
24
A0
D7
30
~ ~
~
~
D6
D2
D1
31
D0
~
~
SO
0
1
~ ~
~
~
SI
0
~
~
SCK
~ ~
~
~
~
~
CSB
High-Z
*=Don't Care
Fig.36
Product
number
BR25S320-W
Address
length
A11-A0
BR25S640-W
A12-A0
BR25S128-W
A13-A0
BR25S256-W
A14-A0
Write command
By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data
after write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time
of tE/W (Max 5ms). During tE/W, other than read status register command is not accepted. Set CSB HIGH between
taking the last data (D0) and rising the next SCK clock. At the other timing, write command is not executed, and this write
command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input
without setting CSB HIGH, 2byte or more data can be written for one tE/W. The maximum number of write bytes is
specified per device of each capacity. Up to 64 arbitrary bytes can be written (in the case of BR25S128/256-W). In page
write, the insignificant 5 bit of the designated address is incremented internally at every time when data of 1 byte is input
and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and
previously input data is overwritten.
4. Write status register, Read status register command (WRSR/RDSR)
CSB
SCK
SI
SO
0
0
1
0
2
3
0
0
4
5
0
0
6
0
7
8
1
9
10
bit7
bit6
bit5
WPEN
*
*
11
12
bit4
bit3
13
bit2
BP1 BP0
*
14
15
bit1
bit0
*
*
High-Z
*=Don't care
Fig.37
Write status register
Write status register command can write data of status register. The data can be written by this command are 3 bits, that
is, WPEN(bit7), BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of
EEPROM can be set. As for this command, set CSB LOW, and input ope code of write status register, and input data.
Then, by making CSB HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise,
set CSB HIGH between taking the last data bit (bit0) and the next SCK clock rising. At the other timing, command is
cancelled. Write disable block is determined by BP1 BP0, and the block can be selected from 1/4 , 1/2, and entire of
memory array (Refer to the write disable block setting table.). To the write disabled block, write cannot be made, and only
read can be made.
CSB
SCK
SI
SO
0
0
1
0
2
0
3
0
4
0
High-Z
Fig.38
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5
1
7
6
0
8
9
10
11
12
13
14
15
1
bit7
bit6
bit5
bit4
WPEN
0
0
0
bit3
bit2
bit1
bit0
BP1 BP0 WEN R/B
Read status register command
9/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●WPB cancel valid area
WPB is normally fixed to “H” or “L” for use, but when WPB is controlled so as to cancel write status register command, pay
attention to the following WPB valid timing.
While write status register command is executed, by setting WPB = “L” in cancel valid area, command can be cancelled.
The area from command ope code to CSB rise at internal automatic write start becomes the cancel valid area. However,
once write is started, by any input write cycle cannot be cancelled. WPB input becomes Don’t Care, and cancellation
becomes invalid.
SCK
6
7
Ope Code
15
tE/W
Data write time
Data
Valid
(WRSR command is reset by WPB=L)
Fig.39
16
Invalid
WPB valid timing (At inputting WRSR command)
●HOLDB pin
By HOLDB pin, command communication can be stopped temporarily (HOLD status). The command communications are
carried out when the HOLDB pin is HIGH. To get in HOLD status, at command communication, when SCK=LOW, set the
HOLDB pin LOW. At HOLD status, SCK and SI become Don’t Care, and SO becomes high impedance (High-Z). To release
the HOLD status, set the HOLDB pin HIGH when SCK=LOW. After that, communication can be restarted from the point
before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of HOLD
status, by starting A4 address input, read can be restarted. When in HOLD status, keep CSB LOW. When it is set
CSB=HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted.
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10/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Method to cancel each command
○READ, RDSR
・Method to cancel : cancel by CSB = “H”.
Ope code
Address
Data
Ope code
8 bits
16 bits
8 bits
8 bits
Cancel available in all areas of read mode
Data
8 bits
Cancel available in all
areas of rdsr mode
Fig.40 READ cancel valid timing
Fig.41 RDSR cancel valid timing
○WRITE、PAGE WRITE
a:Ope code or address input area
Cancellation is available by CSB=”H”.
b:Data input area (D7~D1 input area)
Cancellation is available by CSB=”H”.
c:Data input area (D0 area)
In this area, cancellation is not available.
When CSB is set HIGH, write starts.
d:tE/W area
In the area c, by rising CSB, write starts.
While writing, by any input, cancellation cannot be made.
Ope code
Address
Data
tE/W
8bits
16bits
8bits
b
d
a
c
SCK
SI
D7
D6
D5
D4
D3
D2
D1
D0
c
b
Fig.42 WRITE cancel valid timing
Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once again.
Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it is
recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more.
○WRSR
a:From ope code to 15-th clock rise
Cancellation is available by CSB=”H”.
b:From 15-th clock rise to 16-th clock rise (write enable area)
In this area, cancellation is not available.
When CSB is set HIGH, write starts.
c:After 16-th clock rise.
Cancellation is available by CSB=”H”.
However, if write starts (CSB is rised)
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
14
SCK
15
D1
SI
b
c
tE/W
Data
8 bits
17
D0
a
Ope code
16
8 bits
a
c
b
Fig.43 WRSR cancel valid timing
Note1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again
Note2) If CSB is rised at the same timing as that of the SCK rise, write execution / cancel becomes unstable, therefore, it
is recommended to rise in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or more.
○WREN/WRDI
a:From ope code to 7-th clock rise, cancellation is available by CSB = “H”.
b:Cancellation is not available 7-th clock.
6
SCK
7
8
Ope code
8 bits
a
b
Fig.44 WREN/WRDI cancel valid timing
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11/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●I/O peripheral circuits
In order to realize stable high speed operations, pay attention to the following input / output pin conditions.
○Input pin pull up, pull down resistance
When to attach pull up, pull down resistance to EEPROM input pin, select an appropriate value for the microcontroller
VOL, IOL with considering VIL characteristics of this IC.
1. Pull up resistance
RPU≧
VOLM≦
Microcontroller
IOLM
EEPROM
RPU
VOLM
IOLM
VILE
・・・①
・・・②
Example) When Vcc=5V, VILE=1.5V, VOLM=0.4V, IOLM=2mA,
from the equation ①,
VILE
“L” output
VCC-VOLM
“L” input
RPU≧
5-0.4
2×10-3
∴RPU≧
2.3[kΩ]
With the value of Rpu to satisfy the above equation, VOLM
becomes 0.4V or lower, and with VILE (=1.5V), the equation ② is
also satisfied.
Fig.45 Pull up resistance
・VILE :EEPROM VIL specifications
・VOLM :Microcontroller VOL specifications
・IOLM :Microcontroller IOL specifications
And, in order to prevent malfunction or erroneous write at power ON/OFF, be sure to make CSB pull up.
2.Pull down resistance
RPD≧
Microcontroller
VOHM
“H” output
Fig.46
VOHM≧
EEPROM
VIHE
IOHM
RPD
VOHM
IOHM
VIHE
・・・③
・・・④
Example) When VCC=5V, VOHM=VCC-0.5V, IOHM=0.4mA,
VIHE=VCC×0.7V, from the equation③,
5-0.5
RPD≧
0.4×10-3
“H” input
∴RPD≧
Pull down resistance
11.3[kΩ]
Further, by amplitude VIHE, VILE of signal input to EEPROM, operation speed changes. By inputting Vcc/GND level
amplitude of signal, more stable high speed operations can be realized. On the contrary, when amplitude of 0.8VCC /
*1
0.2Vcc is input, operation speed becomes slow.
In order to realize more stable high speed operation, it is recommended to make the values of RPU, RPD as large as
possible, and make the amplitude of signal input to EEPROM close to the amplitude of VCC / GND level.
*
( 1 In this case, guaranteed value of operating timing is guaranteed.)
○SO load capacity condition
Load capacity of SO output pin affects upon delay characteristic of SO output (Data output delay time, time from HOLDB
to High-Z, Output rise time, Output fall time.). In order to make output delay characteristic into better, make SO load
capacity small.
EEPROM
SO
CL
Fig.47 SO load capacity
○Other cautions
Make the each wire length from the microcontroller to EEPROM input pin same length, in order to prevent setup / hold
violation to EEPROM, owing to difference of wire length of each input.
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12/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Equivalent circuit
○Output circuit
internal
signal
SO
internal
signal
Fig.48 SO output equivalent circuit
○Input circuit
internal
signal
CSB
internal
signal
Fig.49 CSB input equivalent circuit
SCK
internal
signal
SI
Fig.51 SI input equivalent circuit
Fig.50 SCK input equivalent circuit
HOLDB
internal
signal
WPB
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internal
signal
Fig.53 WPB input equivalent circuit
Fig.52 HOLDB input equivalent circuit
© 2010 ROHM Co., Ltd. All rights reserved.
internal
signal
13/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Notes on power ON/OFF
○At standby
Set CSB “H”, and be sure to set SCK, SI input “L” or “H”. Do not input intermediate electric potantial.
○At power ON/OFF
When Vcc rise or fall, set CSB=”H” (=Vcc).
When CSB is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may
cause malfunction, erroneous write or so. To prevent these, at power ON, set CSB “H”. (When CSB is in “H” status, all
inputs are canceled.)
Vcc
CSB
Good example
Bad example
Fig.54 CSB timing at power ON/OFF
(Good example) CSB terminal is pulled up to Vcc.
At power OFF, take 10ms or more before supply. If power is turned on without observing this condition, the IC
internal circuit may not be reset.
(Bad example) CSB terminal is “L” at power ON/OFF.
In this case, CSB always becomes “L” (active status), and EEPROM may have malfunction or erroneous write owing
to noises and the likes.
Even when CSB input is High-Z, the status becomes like this case.
○Operating timing after power ON
As shown in Fig.55, at standby, when SCK is “H”, even if CSB is fallen, SI status is not read at fall edge. SI status is read
at SCK rise edge after fall of CSB. At standby and at power ON/OFF, set CSB “H” status.
Even if CSB is fallen at SCK=”H”,
SI status is not read at that edge.
CSB
Command start here. SI is read.
SCK
0
1
2
SI
Fig.55
Operating timing
○At power on malfunction preventing function
This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable
status. The POR circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the
recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to
noises and the likes.
tR
Recommended conditions of tR, tOFF, Vbot
tR
tOFF
Vcc
tOFF
10ms or below
100ms or below
Vbot
0
Vbot
10ms or higher
0.3V or below
10ms or higher
0.2V or below
Fig.56 Rise waveform
○Low voltage malfunction preventing function
LVCC (Vcc-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
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14/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Noise countermeasures
○Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1μF) between IC Vcc and GND. At that time, attach it as close to IC as
possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
○SCK noise
When the rise time of SCK (tRC) is long, and a certain degree or more of noise exists, malfunction may occur owing to
clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysteresis width of this circuit is set
about 0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise
time of SCK (tRC) 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise
countermeasures. Make the clock rise, fall time as small as possible.
○WPB noise
During execution of write status register command, if there exist noises on WPB pin, mistake in recognition may occur
and forcible cancellation may result. To avoid this, a Schmitt trigger circuit is built in WPB input. In the same manner, a
Schmitt trigger circuit is built in CSB input, SI input and HOLDB input too.
●Notes for use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of
fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is higher than that
of GND terminal.
(5) Heat design
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal short circuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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© 2010 ROHM Co., Ltd. All rights reserved.
15/18
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Ordering part number
B
R
2
Part No.
5
S
BUS Type
25:SPI
2
Operating
temperature
range
S:-40℃~+85℃
5
6
F
V
T
Capacity
Package
320=32K
640=64K
128=128K
256=256K
F:SOP8
FJ:SOP-J8
FV:SSOP-B8
FVT:TSSOP-B8
FVM:MSOP8
FVJ:TSSOP-B8J
NUX:VSON008X2030
-
W
W-Cell
E
2
Packaging and
forming specification
E2: Embossed
tape and reel
TR: Embossed
tape and reel
●Package specifications
SOP8
<Tape and Reel information>
5.0±0.2
(MAX 5.35 include BURR)
6
+6°
4° −4°
5
6.2±0.3
4.4±0.2
0.3MIN
7
1 2
3
0.9±0.15
8
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.595
1.5±0.1
+0.1
0.17 -0.05
S
S
0.11
0.1
1.27
1pin
0.42±0.1
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SOP-J8
<Tape and Reel information>
4.9±0.2
(MAX 5.25 include BURR)
+6°
4° −4°
6
5
0.45MIN
7
3.9±0.2
6.0±0.3
8
1
2
3
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.545
0.2±0.1
0.175
1.375±0.1
S
1.27
0.42±0.1
0.1 S
1pin
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
Reel
16/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Package specifications (Continue)
SSOP-B8
<Tape and Reel information>
3.0±0.2
(MAX 3.35 include BURR)
0.3MIN
4.4 ± 0.2
6.4 ± 0.3
876 5
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1.15 ± 0.1
1 23 4
0.15±0.1
0.1
S
0.1
0.22±0.10
(0.52)
0.08
M
0.65
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
TSSOP-B8
<Tape and Reel information>
3.0 ± 0.1
(MAX 3.35 include BURR)
8
7
6
4±4
3000pcs
2
3
4
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1.0±0.2
0.5±0.15
6.4±0.2
4.4±0.1
1
+0.05
0.145 −0.03
S
0.1±0.05
1.2MAX
Embossed carrier tape
Quantity
Direction
of feed
0.525
1.0±0.05
Tape
5
0.08 S
+0.05
0.245 −0.04
0.08
M
Direction of feed
1pin
0.65
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
TSSOP-B8J
<Tape and Reel information>
3.0 ± 0.1
(MAX 3.35 include BURR)
8
6
5
Embossed carrier tape
Quantity
2500pcs
0.45±0.15
3
4
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.95±0.2
4.9±0.2
3.0±0.1
2
+0.05
0.145 −0.03
0.525
S
0.1±0.05
0.85±0.05
Tape
Direction
of feed
1
1.1MAX
7
4±4
0.08 S
+0.05
0.32 −0.04
0.08
M
1pin
0.65
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
Reel
17/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.12 - Rev.B
BR25S□□□ Series
Technical Note
●Package specifications (Continue)
MSOP8
<Tape and Reel information>
2.8±0.1
4.0±0.2
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1 2 3 4
1PIN MARK
1pin
+0.05
0.145 −0.03
0.475
+0.05
0.22 −0.04
0.08±0.05
0.75±0.05
0.9MAX
S
0.08 S
Direction of feed
0.65
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
VSON008X2030
<Tape and Reel information>
3.0±0.1
2.0±0.1
0.6MAX
1PIN MARK
0.25
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
(0.12)
+0.03
0.02 −0.02
4000pcs
0.5
1
4
8
5
1.4±0.1
0.3±0.1
C0.25
1.5±0.1
Embossed carrier tape
Quantity
Direction
of feed
S
0.08 S
Tape
1pin
+0.05
0.25 −0.04
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
Reel
18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.12 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
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More detail product informations and catalogs are available, please contact us.
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© 2010 ROHM Co., Ltd. All rights reserved.
R1010A
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