AMD AM29F200 2 megabit (256 k x 8-bit/128 k x 16-bit) cmos 5.0 volt-only, boot sector flash memory Datasheet

Am29F200B
2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F200A device
■ High performance
— Access times as fast as 45 ns
■ Low power consumption
— 20 mA typical active read current (byte mode)
— 28 mA typical active read current for
(word mode)
— 30 mA typical program/erase current
— 1 µA typical standby current
■ Sector erase architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
three 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Top or bottom boot block configurations available
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write/erase cycles guaranteed
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package options
— 44-pin SO
— 48-pin TSOP
— Known Good Die (KGD)
(see publication number 21257)
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■ Data# Polling and Toggle Bit
— Detects program or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Hardware method for detection of program or
erase cycle completion
■ Erase Suspend/Erase Resume
— Supports reading data from a sector not
being erased
■ Hardware RESET# pin
— Resets internal state machine to the reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21526 Rev: B Amendment/+2
Issue Date: July 2, 1999
GENERAL DESCRIPTION
The Am29F200B is a 2 Mbit, 5.0 Volt-only Flash
memory organized as 262,144 bytes or 131,072 words.
The 8 bits of data appear on DQ0–DQ7; the 16 bits on
DQ0–DQ15. The Am29F200B is offered in 44-pin SO
and 48-pin TSOP packages. The device is also available in Known Good Die (KGD) form. For more
information, refer to publication number 21257. This
device is designed to be programmed in-system with
the standard system 5.0 volt VCC supply. A 12.0 volt
VPP is not required for program or erase operations.
The device can also be reprogrammed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and
benefits of the Am29F200A, which was manufactured
using 0.5 µm process technology.
The standard device offers access times of 45, 50, 55,
70, 90, and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
2
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6/
DQ2 (toggle) status bits. After a program or erase
cycle has been completed, the device is ready to read
array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Am29F200B
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F200B
VCC = 5.0 V ± 5%
Speed Option
-45
-50
VCC = 5.0 V ± 10%
-55
-70
-90
-120
Max access time, ns (tACC)
45
50
55
70
90
120
Max CE# access time, ns (tCE)
45
50
55
70
90
120
Max OE# access time, ns (tOE)
30
30
30
30
35
50
BLOCK DIAGRAM
DQ0–DQ15
VCC
VSS
WE#
BYTE#
RESET#
RY/BY#
Buffer
RY/BY#
Input/Output
Buffers
Erase Voltage
Generator
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Timer
A0–A16
Address Latch
STB
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A-1
21526B-1
Am29F200B
3
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for
more information.
NC
RY/BY#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
21526B-2
4
Am29F200B
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for
more information.
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
21526B-3
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1
21526B-4
Am29F200B
5
PIN CONFIGURATION
A0–A16
=
LOGIC SYMBOL
17 addresses
17
DQ0–DQ14 =
15 data inputs/outputs
DQ15/A-1
=
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE#
=
Selects 8-bit or 16-bit mode
CE#
=
Chip enable
OE#
=
Output enable
WE#
=
Write enable
RESET#
RESET#
=
Hardware reset pin, active low
BYTE#
RY/BY#
=
Ready/Busy output
VCC
=
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS
=
Device ground
NC
=
Pin not connected internally
6
A0–A16
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RY/BY#
21526B-5
Am29F200B
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
Am29F200B
T
-45
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C
= Commercial (0°C to +70°C)
I
= Industrial (–40°C to +85°C)
E
= Extended (–55°C to +125°C)
PACKAGE TYPE
E
= 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
F
= 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
S
= 44-Pin Small Outline Package (SO 044)
This device is also available in Known Good Die (KGD) form. See publication number
21257 for more information.
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
B
=
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F200B
2 Megabit (256 K x 8-Bit128 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
Valid Combinations
AM29F200BT-45,
AM29F200BB-45
EC, EI, FC, FI, SC, SI
AM29F200BT-50,
AM29F200BB-50
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM29F200BT-55,
AM29F200BB-55
AM29F200BT-70,
AM29F200BB-70
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
AM29F200BT-90,
AM29F200BB-90
AM29F200BT-120,
AM29F200BB-120
Am29F200B
7
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1.
the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the device. The appropriate device bus
operations table lists the inputs and control levels
required, and the resulting output. The following subsections describe each of these operations in further
detail.
Am29F200B Device Bus Operations
DQ8–DQ15
CE#
OE#
WE#
RESET#
A0–A16
DQ0–DQ7
BYTE#
= VIH
BYTE#
= VIL
Read
L
L
H
H
AIN
DOUT
DOUT
High-Z
Write
L
H
L
H
AIN
DIN
DIN
High-Z
VCC ± 0.5 V
X
X
VCC ± 0.5 V
X
High-Z
High-Z
High-Z
TTL Standby
H
X
X
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
High-Z
High-Z
High-Z
Hardware Reset
X
X
X
L
X
High-Z
High-Z
High-Z
Temporary Sector Unprotect
(See Note)
X
X
X
VID
AIN
DIN
DIN
X
Operation
CMOS Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH. On x16 (word-wide) devices, the
BYTE# pin determines whether the device outputs
array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
8
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
On x16 (word-wide) devices, for program operations,
the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte
Configuration” for more information.
Am29F200B
An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the
entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more
information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Characteristics section in the appropriate data sheet for timing
diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device
requires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data t RH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29F200B
9
Table 2.
Am29F200T Top Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
X
X
X
64/32
00000h–0FFFFh
00000h–07FFFh
SA1
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA2
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA3
1
1
0
X
X
32/16
30000h–37FFFh
18000h–1BFFFh
SA4
1
1
1
0
0
8/4
38000h–39FFFh
1C000h–1CFFFh
SA5
1
1
1
0
1
8/4
3A000h–3BFFFh
1D000h–1DFFFh
SA6
1
1
1
1
X
16/8
3C000h–3FFFFh
1E000h–1FFFFh
Table 3.
(x8)
Address Range
(x16)
Address Range
Am29F200B Bottom Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
X
16/8
00000h–03FFFh
00000h–01FFFh
SA1
0
0
0
1
0
8/4
04000h–05FFFh
02000h–02FFFh
SA2
0
0
0
1
1
8/4
06000h–07FFFh
03000h–03FFFh
SA3
0
0
1
X
X
32/16
08000h–0FFFFh
04000h–07FFFh
SA4
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA5
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA6
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
(x8)
Address Range
(x16)
Address Range
Note for Tables 2 and 3: Address range is A16:A-1 in byte mode and A16:A0 in word mode. See the “Word/Byte Configuration”
sectionfor more information.
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector
10
address must appear on the appropriate highest order
address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table
shows the remaining address bits that are don’t care.
When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Autoselect Command Sequence” for details on using
the autoselect mode.
Am29F200B
Table 4.
Description
Mode
Manufacturer ID: AMD
Am29F200B Autoselect Codes (High Voltage Method)
CE#
OE#
WE#
L
L
H
L
L
H
Device ID:
Am29F200B
(Top Boot Block)
Word
Byte
L
L
H
Device ID:
Am29F200B
(Bottom Boot Block)
Word
L
L
H
A16 A11
to
to
A12 A10
Sector Protection Verification
L
L
L
L
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
X
01h
22h
51h
X
51h
22h
57h
X
57h
X
01h
(protected)
X
00h
(unprotected)
X
VID
X
L
X
L
L
X
X
VID
X
L
X
L
H
VID
X
X
H
H
A6
A5
to
A2
X
X
Byte
A9
A8
to
A7
SA
X
VID
X
L
L
X
X
L
H
H
L
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
START
RESET# = VID
(Note 1)
Sector protection/unprotection must be implemented
using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20551. Contact an
AMD representative to obtain a copy of the appropriate
document.
Perform Erase or
Program Operations
RESET# = VIH
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by
selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram
(Figure 18) shows the timing waveforms, for this
feature.
Temporary Sector
Unprotect
Completed (Note 2)
21526B-6
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1.
Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
Am29F200B
11
gramming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Low VCC Write Inhibit
Logical Inhibit
When V CC is less than V LKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than V LKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the
improper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more information on this mode.
The system must issue the reset command to reenable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
12
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies dur ing Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Am29F200B
Method) table, which is intended for PROM programmers and requires VID on address bit A9.
START
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
Write Program
Command Sequence
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A
read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode)
returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to the Sector Address tables for
valid sector addresses.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Yes
Word/Byte Program Command Sequence
The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or timings. The device automatically provides internally
generated program pulses and verify the programmed
cell margin. The Command Definitions take shows the
address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The program command sequence
should be reinitiated once the device has reset to
reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
No
Increment Address
No
Last Address?
Yes
Programming
Completed
21526B-6
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any com mand s wr i tten to th e chip d ur ing th e
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
Am29F200B
13
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the
sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
14
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to “Write Operation Status” for information on these status bits.
Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program opera tio n. See “Wr ite Operation S tatus” for m ore
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
Am29F200B
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
START
Write Erase
Command Sequence
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
21526B-7
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3.
Am29F200B
Erase Operation
15
Table 5.
Read (Note 6)
Reset (Note 7)
Autoselect (Note 8)
Manufacturer ID
Word
Byte
Device ID,
Top Boot Block
Word
Device ID,
Bottom Boot Block
Word
Byte
Byte
Addr
Data
1
RA
RD
1
XXX
F0
4
4
4
Word
Sector Protect Verify
(Note 9)
Chip Erase
Sector Erase
First
555
AAA
555
AAA
555
AAA
4
Word
Byte
Word
Byte
Word
Byte
Second
AA
AA
AA
555
Byte
Program
Bus Cycles (Notes 2–5)
Cycles
Command
Sequence
(Note 1)
Am29F200B Command Definitions
6
6
2AA
555
2AA
555
2AA
555
AA
555
AAA
555
AAA
555
AAA
Third
Data
Addr
555
55
AAA
555
55
AAA
555
55
AAA
2AA
AAA
4
Addr
55
AA
AA
Erase Suspend (Note 10)
1
XXX
B0
Erase Resume (Note 11)
1
XXX
30
2AA
555
2AA
555
2AA
555
90
90
90
555
AAA
555
55
AAA
555
55
AAA
555
55
AAA
A0
80
80
Data
X00
01
X01
2251
X02
51
X01
2257
X02
57
(SA)
X02
XX00
(SA)
X04
00
PA
PD
90
555
AA
Fourth
Data Addr
555
AAA
555
AAA
Fifth
Sixth
Addr Data
Addr
Data
XX01
01
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A16–A12 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
8. The fourth cycle of the autoselect command sequence is a
read cycle.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
5. Address bits A16–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
6. No unlock or command cycles required when reading array
data.
11. The Erase Resume command is valid only during the Erase
Suspend mode.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
16
Am29F200B
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6,
DQ7, and RY/BY#. Table 1 and the following subsections describe the functions of these bits. DQ7, RY/
BY#, and DQ6 each offer a method for determining
whether a program or erase operation is complete or in
progress. These three bits are discussed first.
Table 1 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 2 µs, then the device returns to reading
array data.
DQ7 = Data?
No
No
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data#
Polling Timings (During Embedded Algorithms) figure
in the “AC Characteristics” section illustrates this.
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
Yes
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29F200B
21526B-8
Figure 4.
Data# Polling Algorithm
17
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 1 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. (The system may use either OE#
or CE# to control the read cycles.) When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
18
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 1 to compare outputs
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
Am29F200B
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 5).
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 1 shows the outputs for DQ3.
START
Read DQ7–DQ0
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Read DQ7–DQ0
(Note 1)
Toggle Bit
= Toggle?
No
Yes
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
No
DQ5 = 1?
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the
system can guarantee that the time between additional
sector erase commands will always be less than 50 µs.
See also the “Sector Erase Command Sequence”
section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Am29F200B
21526B-9
Figure 5.
Toggle Bit Algorithm
19
Table 1.
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Write Operation Status
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
DQ2
(Note 1)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
20
Am29F200B
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Industrial (I) Devices
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . . –2.0 V to +12.5 V
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
VCC Supply Voltages
All other pins (Note 1) . . . . . . . . . –0.5 V to +7.0 V
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
VCC for± 10% devices . . . . . . . . . . . . +4.5 V to +5.5 V
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 7.
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure
of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC
+2.0 V
VCC
+0.5 V
–0.5 V
–2.0 V
2.0 V
20 ns
20 ns
21526B-11
21526B-10
Figure 6.
Maximum Negative Overshoot
Waveform
Figure 7.
Am29F200B
20 ns
Maximum Positive Overshoot
Waveform
21
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Max
Unit
±1.0
µA
50
µA
±1.0
µA
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILIT
A9, OE# , RESET# Input Load
Current
VCC = VCC Max,
A9, OE# , RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
ICC1
VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH
ICC2
VCC Active Program/Erase Current
(Notes 2, 3, 4)
CE# = VIL, OE# = VIH
60
mA
ICC3
VCC Standby Current (Note 2)
VCC = VCC Max, CE# = VIH, OE# = VIH
1.0
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VID
Voltage for Autoselect and Temporary
VCC = 5.0 V
Sector Unprotect
11.5
12.5
V
VOL
Output Low Voltage
IOL = 5.8 mA, VCC = VCC Min
0.45
V
VOH
Output High Voltage
IOH = –2.5 mA, VCC = VCC Min
VLKO
Low VCC Lock-Out Voltage
Byte
40
Word
50
mA
2.4
3.2
Notes:
1. The ICC current is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Program or Erase Algorithm is in progress.
4. Not 100% tested.
22
Min
Am29F200B
V
4.2
V
DC CHARACTERISTICS (Continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILIT
A9, OE# , RESET# Input
Load Current
VCC = VCC Max;
A9, OE# , RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
ICC2
VCC Active Program/Erase
Current (Notes 2, 3, 4)
ICC3
VCC Standby Current
Note (Note 5)
VIL
Input Low Voltage
VIH
Input High Voltage
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 5.0 V
VOL
Output Low Voltage
IOL = 5.8 mA, VCC = VCC Min
VOH1
Output Low Voltage
VOH2
VLKO
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
Byte
20
40
Word
28
50
CE# = VIL, OE# = VIH
30
50
mA
CE# = VCC ± 0.5 V, OE# = VIH
1
5
µA
–0.5
0.8
V
0.7 x VCC
VCC + 0.3
V
11.5
12.5
V
0.45
V
mA
IOH = –2.5 mA, VCC = VCC Min
0.85 VCC
V
IOH = –100 µA, VCC = VCC Min
VCC – 0.4
V
Low VCC Lock-Out Voltage
3.2
4.2
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Program or Erase Algorithm is in progress.
4. Not 100% tested.
5. ICC3 for extended temperature is 20 µA max (>+85°C).
Am29F200B
23
TEST CONDITIONS
Table 6.
Test Specifications
5.0
-45, -50,
-55
Test Condition
2.7 kΩ
Device
Under
Test
CL
Output Load
6.2 kΩ
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
0.0–3.0
0.45–2.4
V
Input timing measurement
reference levels
1.5
0.8, 2.0
V
Output timing measurement
reference levels
1.5
0.8, 2.0
V
Input Pulse Levels
Note:
Diodes are IN3064 or equivalents.
All
others
21526B-12
Figure 8.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
24
Am29F200B
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
-45
-50
-55
-70
-90
-120
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
45
50
55
70
90
120
ns
tAVQV
tACC Address to Output Delay
CE# = VIL
OE# = VIL
Max
45
50
55
70
90
120
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
45
50
55
70
90
120
ns
tGLQV
tOE
Output Enable to Output Delay
(Note 1)
Max
30
30
30
30
35
50
ns
tEHQZ
tDF
Chip Enable to Output High Z
(Note 1)
Max
20
20
20
20
20
30
ns
tGHQZ
tDF
Output Enable to Output High Z
(Note 1)
Max
20
20
20
20
20
30
ns
Output Enable
tOEH Hold Time
(Note 1)
tAXQX
tOH
Test Setup
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
Output Hold Time From
Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 6 for test specifications
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 9. Read Operations Timings
Am29F200B
25
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See Note)
Min
50
ns
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
21526B-13
Figure 10.
26
RESET# Timings
Am29F200B
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std
Speed Options
Description
-45
-50
-55
-70
-90
-120
5
Unit
tELFL/tELFH
CE# to BYTE# Switching Low or High
Max
ns
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
20
20
20
20
20
30
ns
tFHQV
BYTE# Switching High to Output Active
Max
45
50
55
70
90
120
ns
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
21526B-14
Figure 11.
BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
21526B-15
Figure 12.
BYTE# Timings for Write Operations
Am29F200B
27
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-45
-50
-55
-70
-90
-120
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
45
50
55
70
90
120
ns
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
45
45
45
50
ns
tDVWH
tDS
Data Setup Time
Min
25
25
25
30
45
50
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
20
Typ
7
tWHWH1
Programming Operation
(Note 2)
Byte
tWHWH1
Word
Typ
12
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Min
tBUSY
30
30
35
45
50
ns
ns
µs
30
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
28
30
Am29F200B
30
30
30
35
50
ns
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
Read Status Data (last two cycles)
PA
PA
PA
tAH
CE#
tCH
tGHWL
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
21526B-16
Figure 13.
Program Operation Timings
Am29F200B
29
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (”see “Write Operation Status”).
2. Illustration shows device in word mode.
21526B-17
Figure 14.
30
Chip/Sector Erase Operation Timings
Am29F200B
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
21526B-18
Figure 15.
Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
21526B-19
Figure 16.
Toggle Bit Timings (During Embedded Algorithms)
Am29F200B
31
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector.
21526B-20
Figure 17. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
tVIDR
VID Rise and Fall Time (See Note)
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
All Speed Options
Unit
Min
500
ns
Min
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
21526B-21
Figure 18.
32
Temporary Sector Unprotect Timing Diagram
Am29F200B
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
45
45
45
50
ns
tDVEH
tDS
Data Setup Time
Min
25
25
25
30
45
50
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
20
Byte
Typ
7
tWHWH1
tWHWH1
Word
Typ
12
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
1
Programming Operation
(Note 2)
-45
-50
-55
-70
-90
-120
Unit
45
50
55
70
90
120
ns
0
30
30
30
ns
35
45
50
ns
ns
µs
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29F200B
33
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
21526B-22
Figure 19.
34
Alternate CE# Controlled Write Operation Timings
Am29F200B
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1
8
sec
Chip Erase Time
5
Excludes 00h programming prior to
erasure (Note 4)
Byte Programming Time
7
300
µs
Word Programming Time
12
500
µs
Chip Programming Time (Note 3)
1.8
5.4
sec
sec
Excludes system-level overhead
(Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25×C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (VCC = 4.75 V for ±5% devices), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Parameter Description
Input Voltage with respect to VSS on all I/O pins
VCC Current
Min
Max
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
Typ
Max
Unit
VIN = 0
6
7.5
pF
VOUT = 0
8.5
12
pF
VIN = 0
8
10
pF
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
Am29F200B
35
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package (measured in millimeters)
44
23
13.10
13.50
1
15.70
16.30
22
1.27 NOM.
TOP VIEW
28.00
28.40
2.17
2.45
0.10
0.21
2.80
MAX.
0.35
0.50
0.10
0.35
SEATING
PLANE
SIDE VIEW
36
0°
8°
0.60
1.00
END VIEW
16-038-SO44-2
SO 044
DF83
8-8-96 lv
Am29F200B
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
0.08
0.20
0.10
0.21
1.20
MAX
0°
5°
0.25MM (0.0098") BSC
16-038-TS48-2
TS 048
DT95
8-8-96 lv
0.50
0.70
Am29F200B
37
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
SEATING PLANE
0.08
0.20
0.10
0.21
1.20
MAX
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
38
Am29F200B
16-038-TS48
TSR048
DT95
8-8-96 lv
REVISION SUMMARY
Revision A
AC Characteristics
Global: Made formatting and layout consistent with other
data sheets. Used updated common tables and diagrams
Figure 15. Data# Polling Timings (During Embedded
Algorithms): Added text to note.
Revision B
Figure 16. Toggle Bit Timings (During Embedded Algorithms): Added text to note.
Distinctive Characteristics
Revision B+1 (April 12, 1999)
Added bullet for 20-year data retention at 125°C
Product Selector Guide
Ordering Information
The 55 ns option now has a VCC operating range of
±10%.
Optional Processing: Deleted “B = Burn-in”.
DC Characteristics—TTL/NMOS Compatible
ICC1, ICC2, ICC3: Added Note 2 “Maximum ICC specifications are tested with VCC = VCCmax”.
DC Characteristics—CMOS Compatible
ICC1, ICC2, ICC3: Added Note 2 “Maximum ICC specifications are tested with VCC = VCCmax”.
Revision B+2 (July 2, 1999)
Global
Added references to availability of device in Known
Good Die (KGD) form.
Trademarks
Copyright © 1999 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F200B
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