Elpida EDX1032BBBG 1g bits xdr dram Datasheet

DATA SHEET
1G bits XDR DRAM
EDX1032BBBG (32M words × 32 bits)
Overview
Features
The EDX1032BBBG is 1G bits XDR™ DRAM organized as
32M words × 32 bits. They are general-purpose high-performance memory devices suitable for use in a broad range of
applications.
•
Highest pin bandwidth available
Octal Data Rate (ODR) Signaling, 3200 Mb/s
• Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
• Programmable on-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
• Low power PLL/DLL design
•
Highest sustained bandwidth per DRAM device
• EDX1032BBBG:12800 MB/s sustained data rates
• Eight banks: bank-interleaved transactions at full
bandwidth
• Dynamic request scheduling
• Early-read-after-write support for maximum efficiency
• Zero overhead refresh
•
Dynamic width control
• EDX1032BBBG supports × 32, × 16, × 8 and × 4
mode
•
Low latency
• 2.50 ns request packets
• Point-to-point data interconnect for fastest possible
flight time
• Support for low-latency, fast-cycle cores
•
Low power
• 1.5V VDD
• Programmable small-swing I/O signaling (DRSL)
• Low power PLL/DLL design
• Powerdown self-refresh support
• Per pin I/O powerdown for narrow-width operation
The use of Differential Rambus Signaling Level (DRSL) technology permits 3200 Mb/s transfer rates for EDX1032BBBG,
while using conventional system and board design technologies.
The EDX1032BBBG device is capable of sustained data transfers of 12800 MB/s.
XDR DRAM device architecture allows the highest sustained
bandwidth for multiple, interleaved randomly addressed memory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device’s
eight banks support up to four interleaved transactions.
The EDX1032BBBG is packaged in 150-ball FBGA, compatible with Rambus XDR DRAM pin configuration.
Doc. No. E1819E20 (Ver. 2.0)
Date Published March 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc.
2011-2012
EDX1032BBBG
Ordering Information
Part number
Organization
Bandwidth (1/tBIT)*1 Latency (tRAC)*2
Bin
Package
EDX1032BBBG-3C-F
4M × 32 × 8 banks
3.2G
C
150-ball FBGA
35
Notes:1. Data rate measured in Mbit/s per DQ differential pair. Note that tBIT = tCYCLE/8
2. Read access time tRAC (= tRCD-R + tCAC) measured in ns.
Part Number
E D X 10 32 B B BG - 3C - F
Elpida Memory
Environment Code
F: Lead Free (RoHS compliant)
and Halogen Free
Type
D: Packaged Device
Product Family
X: XDR DRAM
Density
10: 1Gb/ 8-bank
Speed
3C: 3.2G (tRAC = 35, C Bin)
Organization
32: x32
Package
BG: FBGA
Power Supply, Interface
B: 1.5V, DRSL
Die Rev.
Data Sheet E1819E20 (Ver. 2.0)
2
EDX1032BBBG
Pin Configuration
x32 bits configuration
R
P
N
M
L
K
J
GND
GND
VDD
H
G
F
E
GND
VDD
VDD
D
C
B
A
MB
DQ24
DQ20
DQ18
DQ30
RQ3
SDI
DQN8
DQN4
DQN2
DQN14
1
DQN31 DQN19 DQN21 DQN25
DQN24 DQN20 DQN18 DQN30
2
DQ31
DQ19
DQ21
DQ25
GND
DQN15
DQN3
DQN5
DQN9
GND
RQ10
CFM
RQ11
CFMN
3
4
DQ15
DQ3
DQ5
DQ9
VDD
GND
GND
VDD
GND
GND
VDD
VDD
VTERM
VDD
VTERM
VDD
GND
GND
GND
RQ4
RQ0
VDD
DQ8
DQ4
DQ2
DQ14
GND
GND
VDD
GND
GND
VTERM
VDD
VDD
5
VDD
6
VTERM
GND
GND
VTERM
GND
VDD
GND
GND
VDD
DQN1
CMD
RQ9
RQ7
DQ1
SCK
RQ8
RQ6
GND
VDD
GND
VTERM
VDD
GND
GND
GND
VTERM
VDD
VTERM
VDD
GND
VREF
VDD
GND
GND
GND
GND
RQ1
RST
DQN0
RQ2
SDO
DQ0
7
8
9
10
11
12
DQN7
DQN11 DQN13
DQN12 DQN10
DQN6
13
DQ7
DQ11
DQ13
RQ5
DQ12
DQ10
DQ6
14
DQN23 DQN27 DQN29 DQN17
MB
MB
DQN16 DQN28 DQN26 DQN22
15
DQ23
DQ27
DQ29
DQ17
GND
VDD
VDD
GND
VDD
VDD
DQ16
DQ28
DQ26
DQ22
Top view of package
MB: Mechanical Ball (Optional).
Other vendor may have optional balls in E2, L14, E14. Elpida 1Gb XDR has no MBs.
Board layout must include solder land pads at these locations.
Data Sheet E1819E20 (Ver. 2.0)
3
EDX1032BBBG
mand. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A
second request packet at clock edge T1 contains a write (WR)
command. This causes the data packet D(a1) at edge T4 to be
written to column Ca1 of the sense amp array for bank Ba. A
third request packet at clock edge T3 contains another write
(WR) command. This causes the data packet D(a2) at edge T6
to also be written to column Ca2. A final request packet at
clock edge T13 contains a precharge (PRE) command.
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device
write and read transactions. There are three sets of pins used
for normal memory access transactions: CFM/CFMN clock
pins, RQ11..0 request pins, and DQ31..0/DQN31..0 data pins.
The “N” appended to a signal name denotes the complementary signal of a differential pair.
A transaction is a collection of packets needed to complete a
memory access. A packet is a set of bit windows on the signals
of a bus. There are two buses that carry packets: the RQ bus
and DQ bus. Each packet on the RQ bus uses a set of 2 bitwindows on each signal, while the DQ bus uses a set of 16 bitwindows on each signal.
The spacings between the request packets are constrained by
the following timing parameters in the diagram: tRCD-W , tCC ,
and tWRP . In addition, the spacing between the request packets
and data packets are constrained by the tCWD parameter. The
spacing of the CFM/CFMN clock edges is constrained by
tCYCLE.
In the write transaction shown in Figure 1, a request packet (on
the RQ bus) at clock edge T0 contains an activate (ACT) comFigure 1
XDR DRAM Device Write and Read Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT WR
a0
a1
t
DQ31..0 RCD-W
DQN31..0
WR
a2
tCC
D(a1)
tCWD
tCYCLE
PRE
a3
tWRP
D(a2)
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ31..0
DQN31..0
ACT
a0
RD
a1
tRCD-R
RD
a2
tCC
tRDP
Q(a1)
tCAC
Transaction a: RD
tCYCLE
PRE
a3
a0 = {Ba,Ra}
Q(a2)
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T0
containing an ACT command. This causes row Ra of bank Ba
of the memory component to load into the sense amp array for
the bank. A second request packet at clock edge T5 contains a
read (RD) command. This causes the data packet Q(a1) at edge
T11 to be read from column Ca1 of the sense amp array for
bank Ba. A third request packet at clock edge T7 contains
another RD command. This causes the data packet Q(a2) at
edge T13 to also be read from column Ca2. A final request
packet at clock edge T10 contains a PRE command.
The spacings between the request packets are constrained by
the following timing parameters in the diagram: tRCD-R , tCC ,
and tRDP . In addition, the spacing between the request and
data packets are constrained by the tCAC parameter.
Data Sheet E1819E20 (Ver. 2.0)
4
EDX1032BBBG
Receive/Transmit Timing ..........................................71
Clocking ............................................................................ 71
RSL RQ Receive Timing ................................................ 72
DRSL DQ Receive Timing ............................................ 73
DRSL DQ Transmit Timing ......................................... 75
Serial Interface Receive Timing ..................................... 77
Serial Interface Transmit Timing .................................. 78
Package Description .................................................. 79
Package Parasitic Summary ............................................ 79
Package Drawing ............................................................. 81
Package Pin Numbering ................................................. 82
Recommended Soldering Conditions ......................... 83
Table of Contents
Overview ....................................................................... 1
Features ........................................................................ 1
Ordering Information ....................................................2
Part Number .................................................................2
Pin Configuration .........................................................3
x32 bits configuration ....................................................... 3
General Description ......................................................4
Table of Contents .........................................................5
Table of Figures ............................................................6
Table of Tables .............................................................6
Pin Description .............................................................7
Block Diagram ..............................................................8
Request Packets ......................................................... 10
Request Packet Formats ................................................. 10
Request Field Encoding .................................................. 12
Request Packet Interactions ........................................... 14
Request Interaction Cases .............................................. 15
Dynamic Request Scheduling ........................................ 20
Memory Operations .................................................... 22
Write Transactions .......................................................... 22
Read Transactions ........................................................... 24
Interleaved Transactions ................................................. 26
Read/Write Interaction .................................................. 28
Propagation Delay ........................................................... 28
Register Operations .................................................... 32
Serial Transactions ........................................................... 32
Serial Write Transaction ................................................. 32
Serial Read Transaction .................................................. 32
Register Summary ............................................................ 34
Maintenance Operations ............................................ 40
Refresh Transactions ....................................................... 40
Interleaved Refresh Transactions .................................. 40
Calibration Transactions ................................................. 42
Power State Management ............................................... 44
Initialization ...................................................................... 46
XDR DRAM Initialization Overview .......................... 47
XDR DRAM Pattern Load with WDSL Reg .............. 48
Special Feature Description ....................................... 54
Dynamic Width Control ................................................. 54
Write Masking .................................................................. 56
Multiple Bank Sets and the ERAW Feature ................ 58
Simultaneous Activation ................................................. 60
Simultaneous Precharge .................................................. 61
Column Address Remapping ......................................... 62
Operating Conditions ................................................. 64
Electrical Conditions ....................................................... 64
Timing Conditions ........................................................... 65
Operating Characteristics ........................................... 66
Electrical Characteristics ................................................. 66
Supply Current Profile .................................................... 67
Timing Characteristics .................................................... 68
Timing Parameters ........................................................... 69
Data Sheet E1819E20 (Ver. 2.0)
5
EDX1032BBBG
DRSL DQ Receive Waveforms .................................. 74
DRSL DQ Transmit Waveforms ................................ 76
Serial Interface Receive Waveforms ........................... 77
Serial Interface Transmit Waveforms ........................ 78
Equivalent Circuits for Package Parasitic ................. 80
x32 Package - Pin Numbering (top view) .................. 82
Table of Figures
XDR DRAM Device Write and Read Transactions .....4
1Gb (8x4Mx32/16/8/4) XDR DRAM Block Diagram .9
Request Packet Formats ..............................................11
ACT-, RD-, WR-, PRE-to-ACT Packet Interactions . 16
ACT-, RD-, WR-, PRE-to-RD Packet Interactions ... 17
ACT-, RD-, WR-, PRE-to-WR Packet Interactions ... 18
ACT-, RD, WR-, PRE-to-PRE Packet Interactions .. 19
Request Scheduling Examples ................................... 21
Write Transactions ..................................................... 23
Read Transactions ...................................................... 25
Interleaved Transactions ............................................ 27
Write/Read Interaction .............................................. 29
Propagation Delay ...................................................... 31
Serial Write Transaction ............................................. 33
Serial Read Transaction — Selected DRAM .............. 33
Serial Read Transaction — Non-selected DRAM ..... 33
Serial Identification (SID) Register ............................ 34
Configuration (CFG) Register .................................... 35
Power Management (PM) Register ............................ 35
Write Data Serial Load (WDSL) Control Register ..... 35
RQ Scan High (RQH) Register ................................. 36
RQ Scan Low (RQL) Register .................................... 36
Refresh Bank (REFB) Control Register ..................... 36
Refresh High (REFH) Row Register ......................... 37
Refresh Middle (REFM) Row Register ..................... 37
Refresh Low (REFL) Row Register ........................... 37
Read Only Memory 2 (ROM2) Register .................... 37
IO Configuration (IOCFG) Register .......................... 38
Current Calibration 0 (CC0) Register ......................... 38
Current Calibration 1 (CC1) Register ......................... 38
Read Only Memory 0 (ROM0) Register .................... 38
Read Only Memory 1 (ROM1) Register ..................... 39
TEST Register ............................................................ 39
Delay (DLY) Control Register .................................... 39
Refresh Transactions .................................................. 41
Calibration Transactions ............................................ 43
Power State Management ........................................... 45
Serial Interface System Topology ............................... 46
Initialization Timing for XDR DRAM[k] Device ..... 46
Multiplexers for Dynamic Width Control .................. 54
D-to-S and S-to-Q Mapping for Dynamic Width
Control ....................................................................... 55
Byte Mask Logic ......................................................... 56
Write-Masked (WRM) Transaction Example ............ 57
Write/Read Interaction — No ERAW Feature ......... 58
Write/Read Interaction — ERAW Feature ............... 58
XDR DRAM Block Diagram with Bank Sets ........... 59
Simultaneous Activation — tRR-D Cases .................. 60
Simultaneous Precharge — tPP-D Cases ................... 61
Alternate Request Packet Formats ............................. 63
Clocking Waveforms ................................................... 71
RSL RQ Receive Waveforms ...................................... 72
Table of Tables
Pin Description ............................................................ 7
Request Field Description ..........................................10
OP Field Encoding Summary .....................................12
ROP Field Encoding Summary ..................................12
POP Field Encoding Summary ..................................13
XOP Field Encoding Summary ..................................13
Packet Interaction Summary ......................................14
SCMD Field Encoding Summary .............................. 32
Initialization Timing Parameters .............................. 47
Logical View of XDR DRAM WDSL-to-Core/DQ/SC
Map (x32/x16/x8, BL=16) ......................................... 49
Logical View of XDR DRAM WDSL-to-Core/DQ/SC
Map (x4, BL=16) ........................................................ 50
Physical View of XDR DRAM WDSL-to-Core/DQ/SC
Map (x32/x16/x8, BL=16) ..........................................51
Physical View of XDR DRAM WDSL-to-Core/DQ/SC
Map (x4, BL=16) ........................................................ 52
Core Data Word-to-WDSL Format ............................ 53
Alternate Request Field Description ......................... 62
Electrical Conditions .................................................. 64
Timing Conditions ..................................................... 65
Electrical Characteristics ........................................... 66
Supply Current Profile ................................................ 67
Timing Characteristics ............................................... 68
Timing Parameters .................................................... 69
Package Parasitic Summary........................................ 79
Data Sheet E1819E20 (Ver. 2.0)
6
EDX1032BBBG
read and write data signals, RQ11..0 for carrying request signals, and CFM and CFMN for carrying timing information
used by the DQ, DQN, and RQ signals.
Pin Description
Table 1 summarizes the pin functionality of the XDR DRAM
device. The first group of pins provide the necessary supply
voltages. These include VDD and GND for the core and interface logic, VREF for receiving input signals, and VTERM for
driving output signals.
The final set of pins comprise the serial interface that is used
for control register accesses. These include RST for initializing
the state of the device, CMD for carrying command signals,
SDI, and SDO for carrying register read data, and SCK for carrying the timing information used by the RST, SDI, SDO, and
CMD signals.
The next group of pins are used for high bandwidth memory
accesses. These include DQ31..0 and DQN31..0 for carrying
Table 1 Pin
Signal
Description
I/O
Type
No. of pins
VDD
-
-
25
Supply voltage for the core and interface logic of the device.
GND
-
-
33
Ground reference for the core and interface logic of the device.
VREF
-
-
1
Logic threshold reference voltage for RSL signals.
VTERM
-
-
8
Termination voltage for DRSL signals.
DQ31..0
I/O
DRSLa
32
Positive data signals that carry write or read data to and from the device.
DQN31..0
I/O
DRSLa
32
Negative data signals that carry write or read data to and from the device.
RQ11..0
I
RSLa
12
Request signals that carry control and address information to the device.
CFM
I
DIFFCLKa
1
Clock from master — Positive interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
CFMN
I
DIFFCLKa
1
Clock from master — Negative interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
RST
I
RSLa
1
Reset input — This pin is used to initialize the device.
CMD
I
RSLa
1
Command input — This pin carries command, address, and control register
write data into the device.
SCK
I
RSLa
1
Serial clock input — Clock source used for reading from and writing to the
control registers.
SDI
I
RSLa
1
Serial data input — This pin carries control register read data through the
device. This pin is also used to initialize the device.
SDO
O
CMOSa
1
Serial data output — This pin carries control register read data from the device.
This pin is also used to initialize the device.
RSRV
-
-
-
Reserved pins — Follow Rambus XDR system design guidelines for connecting RSRV pins
Total pin count per package
Description
150
a. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1.
All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
Data Sheet E1819E20 (Ver. 2.0)
7
EDX1032BBBG
referred to as “opening a page” for the bank.
Block Diagram
Another bank address is decoded for a PRE command. The
indicated bank and associated sense amp array are precharged
to a state in which a subsequent ACT command can be
applied. Precharging a bank is also called “closing the page” for
the bank.
A block diagram of the XDR DRAM device is shown in
Figure 1. It shows all interface pins and major internal blocks.
The CFM and CFMN clock signals are received and used by
the clock generation logic to produce three virtual clock signals: 1/tCYCLE, 2/tCYCLE, and 16/tCC. The frequency of these
signals are 1x, 2x, and 8x that of the CFM and CFMN signals.
These virtual signals show the effective data rate of the logic
blocks to which they connect; they are not necessarily present
in the actual memory component.
After a bank is given an ACT command and before it is given a
PRE command, it may receive read (RD) and write (WR) column commands. These commands permit the data in the
bank’s associated sense amp array to be accessed.
For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the selected
bank is written with the data received from the DQ31..0 pins.
The RQ11..0 pins receive the request packet. Two 12-bit words
are received in one tCYCLE interval. This is indicated by the 2/
tCYCLE clocking signal connected to the 1:2 Demux Block that
assembles the 24-bit request packet. These 24 bits are loaded
into a register (clocked by the 1/tCYCLE clocking signal) and
decoded by the Decode Block. The VREF pin supplies a reference voltage used by the RQ receivers.
The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense amp array
is read. The data is transmitted onto the DQ31..0 pins.
The DQ31..0 pins receive the write data packet (D) for a write
transaction. 32 sixteen-bit words are received in one tCC interval. This is indicated by the 16/tCC clocking signal connected
to the 1:16 Demux Block that assembles the 32x16-bit write
data packet. The write data is then driven to the selected Sense
Amp Array Bank.
Three sets of control signals are produced by the Decode
Block. These include the bank (BA) and row (R) addresses for
an activate (ACT) command, the bank (BR) and row (REFr)
addresses for a refresh activate (REFA) command, the bank
(BP) address for a precharge (PRE) command, the bank (BR)
address for a refresh precharge (REFP) command, and the
bank (BC) and column (C and SC) addresses for a read (RD) or
write (WR or WRM) command. In addition, a mask (M) is used
for a masked write (WRM) command.
32 sixteen-bit words are accessed in the selected Sense Amp
Array Bank for a read transaction. The DQ31..0 pins transmit
this read data packet (Q) in one tCC interval. This is indicated
by the 16/tCC clocking signal connected to the 16:1 Mux
Block. The VTERM pin supplies a termination voltage for the
DQ pins.
These commands can all be optionally delayed in increments of
tCYCLE under control of delay fields in the request. The control
signals of the commands are loaded into registers and presented to the memory core. These registers are clocked at maximum rates determined by core timing parameters, in this case
1/tRR, 1/tPP, and 1/tCC (1/4, 1/4, and 1/2 the frequency of
CFM in the -3200 component). These registers may be loaded
at any tCYCLE rising edge. Once loaded, they should not be
changed until a tRR, tPP, or tCC time later because timing paths
of the memory core need time to settle.
The RST, SCK, and CMD pins connect to the Control Register
block. These pins supply the data, address, and control needed
to write the control registers. The read data for the these registers is accessed through the SDO/SDI pins. These pins are
also used to initialize the device.
The control registers are used to transition between power
modes, and are also used for calibrating the high speed transmit and receive circuits of the device. The control registers also
supply bank (REFB) and row (REFr) addresses for refresh
operations.
A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into the
associated sense amp array for the bank. Sensing a row is also
Data Sheet E1819E20 (Ver. 2.0)
8
EDX1032BBBG
1Gb (8x4Mx32/16/8/4) XDR DRAM Block Diagram
RQ11..0
12
2/tCYCLE
VREF
1
1:2 Demux
12
1/tCYCLE
2/tCYCLE
12
Control Registers
16/ tCC
reg
12
RST,SCK,CMD,SDI SDO
4
1
CFM CFMN
1/tCYCLE
12
Power Mode Logic
Calibration Logic
Refresh Logic
Initialization Logic
Decode
3
WIDTH
ACT delay
{0..1}*tCYCLE
1/tRR
BA,BR,REFB
23
3
1
1
1
PRE
1
Bank 0
PRE
...
decode
reg
3
1
1
R/W
6
reg
COL
Sense Amp 0
COL
4
32x16
8
M
32x16*26
...
SC
Sense Amp Array
R/W
Sense Amp (23 - 1)
32x16
S[31:0][15:0]
32x16
32x16
WIDTH
Byte Mask (WR)
Dynamic Width Mux (RD)
16
16/tCC
...
16
1:16 Demux
16:1 Mux
16/tCC
...
32
32
termination
32
2
VTERM
32x16
...
Q[31:0][15:0]
D[31:0][15:0]
...
Dynamic Width Demux (WR)
32x16
...
C
...
BC
23
Bank (2 - 1)
32x16*26
32x16*26
1/tCC
3
...
3
ROW
23
Col Row
ROW
...
BP,BR,REFB
reg
1/tPP
32x16*26*212
ACT
12
R,REFr
Bank
Array
Bank 0
ACT
{
PRE delay
{0..3}*tCYCLE
...
{0..1}*tCYCLE
12
...
RD,WR
delay
3
decode
3
decode
6+4
REFB,REFr
ACT logic
...
7
PRE logic
reg
COL logic
{
Figure 1
DQ31..0
Data Sheet E1819E20 (Ver. 2.0)
9
32
DQN31..0
EDX1032BBBG
command.
Request Packets
In the ROWA packet, a bank address (BA), row address (R),
and command delay (DELA) are specified for the activate
(ACT) command.
A request packet carries address and control information to
the memory device. This section contains tables and diagrams
for packet formats, field encodings and packet interactions.
In the COL packet, a bank address (BC), column address (C),
sub-column address (SC), command delay (DELC), and
sub-opcode (WRX) are specified for the read (RD) and write
(WR) commands.
Request Packet Formats
There are five types of request packets:
1.
ROWA — specifies an ACT command
2.
COL — specifies RD and WR commands
3.
COLM — specifies a WRM command
4.
ROWP — specifies PRE and REF commands
5.
COLX — specifies the remaining commands
In the COLM packet, a bank address (BC), column address
(C), sub-column address (SC), and mask field (M) are specified
for the masked write (WRM) command.
In the ROWP packet, two independent commands may be
specified. A bank address (BP) and sub-opcode (POP) are
specified for the precharge (PRE) commands. An address field
(RA) and sub-opcode (ROP) are specified for the refresh
(REF and LRR) commands.
Table 2 describes fields within different request packet types.
Various request packet type formats are illustrated in Figure 2.
Each packet type consists of 24 bits sampled on the RQ11..0
pins on two successive edges of the CFM/CFMN clock. The
request packet formats are distinguished by the OP3..0 field.
This field also specifies the operation code of the desired
Table 2 Request
Field
In the COLX packet, a sub-operation code field (XOP) is
specified for the remaining commands.
Field Description
Packet Types
Description
OP3..0
ROWA/COL/COLM/ROWP/COLX
4-bit operation code that specifies packet format.
(Encoded commands are in Table 3 on page 12).
DELA
ROWA
Delay the associated row activate command by 0 or 1 tCYCLE .
BA2..0
ROWA
3-bit bank address for row activate command.
R11..0
ROWA
12-bit row address for row activate command.
WRX
COL
Specifies RD (=0) or WR (=1) command.
DELC
COL
Delay the column read or write command by 0 or 1 tCYCLE .
BC2..0
COL/COLM
3-bit bank address for column read or write command.
C10..5
COL/COLM
6-bit column address for column read or write command.
SC4..0
COL/COLM
5-bit sub-column address for dynamic width (see “Dynamic Width Control” on page 54).
M7..0
COLM
8-bit mask for masked-write command WRM.
POP2..0
ROWP
3-bit operation code that specifies row precharge command with a delay of 0 to 3 tCYCLE.
(Encoded commands are in Table 5 on page 13).
BP2..0
ROWP
3-bit bank address for row precharge command.
ROP2..0
ROWP
3-bit operation code that specifies refresh commands.
(Encoded commands are in Table 4 on page 12).
RA7..0
ROWP
8-bit refresh address field (specifies BR bank address, delay value, and REFr load value
XOP3..0
COLX
4-bit extended operation code that specifies calibration and powerdown commands.
(Encoded commands are in Table 6 on page 13).
Data Sheet E1819E20 (Ver. 2.0)
10
EDX1032BBBG
Figure 2
Request Packet Formats
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
tCYCLE
ACT
a0
RD
a1
WRM
a2
PRE
a3
PDN
-
DQ31..0
DQN31..0
ROWA Packet
COL Packet
tCYCLE
COLM Packet
tCYCLE
tCYCLE
ROWP Packet
tCYCLE
COLX Packet
tCYCLE
CFM
CFMN
RQ11
OP
3
DEL
A
OP
3
DEL
C
OP
3
M
7
OP
3
POP
2
OP
3
rsrv
RQ10
OP
2
R
8
OP
2
rsrv
M
3
M
6
OP
2
ROP
2
OP
2
rsrv
RQ9
R
9
R
7
OP
1
rsrv
M
2
M
5
OP
1
ROP
1
OP
1
rsrv
RQ8
R
10
R
6
OP
0
rsrv
M
1
M
4
OP
0
ROP
0
OP
0
rsrv
RQ7
R
11
R
5
WR
X
C
7
M
0
C
7
POP
1
RA
7
rsrv
rsrv
rsrv
R
4
C
8
C
6
C
8
C
6
POP
0
RA
6
rsrv
rsrv
rsrv
R
3
C
9
C
5
C
9
C
5
rsrv
RA
5
rsrv
rsrv
rsrv
R
2
C
10
SC
4
C
10
SC
4
rsrv
RA
4
rsrv
rsrv
rsrv
R
1
rsrv
SC
3
rsrv
SC
3
rsrv
RA
3
XOP
3
rsrv
RQ2
BA
2
R
0
BC
2
SC
2
BC
2
SC
2
BP
2
RA
2
XOP
2
rsrv
RQ1
BA
1
rsrv
BC
1
SC
1
BC
1
SC
1
BP
1
RA
1
XOP
1
rsrv
RQ0
BA
0
rsrv
BC
0
SC
0
BC
0
SC
0
BP
0
RA
0
XOP
0
rsrv
RQ6
RQ5
RQ4
RQ3
Data Sheet E1819E20 (Ver. 2.0)
11
EDX1032BBBG
each use additional fields to specify multiple commands: WRX,
XOP, and POP/ROP, respectively. The COLM packet specifies
the masked write command WRM. This is like the WR
unmasked write command, except that a mask field M7..0 indicates whether each byte of the write data packet is written or
not written. The ROWA packet specifies the row activate command ACT. The COL packet uses the WRX field to specify the
column read and column write (unmasked) commands.
Request Field Encoding
Operation-code fields are encoded within different packet
types to specify commands. Table 3 through Table 6 provides
packet type and encoding summaries.
Table 3 shows the OP field encoding for the five packet types.
The COLM and ROWA packets each specify a single command: ACT and WRM. The COL, COLX, and ROWP packets
Table 3 OP
OP [3:0]
Field Encoding Summary
Packet
Command
Description
0000
-
NOP
No operation
0001
COL
RD
Column read (WRX=0). Column C9..5 of sense amp in bank BC2..0 is read to DQ bus after (tCAC+DELC)*tCYCLE
WR
Column write (WRX=1). Write DQ bus to column C9..5 of sense amp in bank BC2..0 after (tCWD+DELC)*tCYCLE
0010
COLX
CALy
XOP3..0 specifies a calibrate or powerdown command — see Table 6 on page 13
0011
ROWP
PREx
POP2..0 specifies a row precharge command — see Table 5 on page 13
REFy,LRRr
ROP2..0 specifies a row refresh command or load REFr register command — see Table 4 on page 12
01xx
ROWA
ACT
Row activate command. Row R11..0 of bank BA2..0 is placed into the sense amp of the bank after DELA*tCYCLE
1xxx
COLM
WRM
Column write command (masked) — mask M7..0 specifies which bytes are written
Encoding of the ROP field in the ROWP packet is shown in
Table 4. The first encoding specifies a NOPR (no operation)
command. The REFP command uses the RA field to select a
bank to be precharged. The REFA and REFI commands use
the RA field and REFH/M/L registers to select a bank and
Table 4 ROP
ROP[2:0]
row to be activated for refresh. The REFI command also
increments the REFH/M/L register. The REFP, REFA, and
REFI commands may also be delayed by up to 3*tCYCLE using
the RA[7:6] field. The LRR0, LRR1, and LRR2 commands
load the REFH/M/L registers from the RA[7:0] field.
Field Encoding Summary
Command
Description
000
NOPR
No operation
001
REFP
Refresh precharge command. Bank RA2..0 is precharged.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
010
REFA
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
011
REFI
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp.
This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).
R[11:0] field of REFH/M/L register is incremented after the activate command has completed.
100
LRR0
Load Refresh Low Row register (REFL). RA[7:0] is stored in R[7:0] field.
101
LRR1
Load Refresh Middle Row register (REFM). RA[3:0] is stored in R[11:8] field.
110
LRR2
Load Refresh High Row register — not used with this device.
111
-
Reserved
Data Sheet E1819E20 (Ver. 2.0)
12
EDX1032BBBG
The REFH/M/L registers are also referred to as the REFr registers. Note that only the bits that are needed for specifying the
refresh row (12 bits in all) are implemented in the REFr registers — the rest are reserved. Note also that the RA2..0 field that
specifies the refresh bank address is also referred to as BR2..0.
See “Refresh Transactions” on page 40.
Table 5 POP
POP
[2:0]
Table 5 shows the POP field encoding in the ROWP packet.
The first encoding specifies a NOPP (no operation) command.
There are four variations of PRE (precharge) command. Each
uses the BP field to specify the bank to be precharged. Each
also specifies a different delay of up to 3*tCYCLE using the
POP[1:0] field. A precharge command may be specified in
addition to a refresh command using the ROP field.
Field Encoding Summary
Command
Description
000
NOPP
No operation.
001
-
Reserved.
010
-
Reserved.
011
-
Reserved.
100
PRE0
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 0*tCYCLE.
101
PRE1
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 1*tCYCLE.
110
PRE2
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 2*tCYCLE.
111
PRE3
Row precharge command — Bank BP2..0 is precharged. This command is delayed by 3*tCYCLE.
tion Transactions” on page 42.
Table 6 shows the XOP field encoding in the COLX packet.
This field encodes the remaining commands.
The PDN command causes the device to enter a power-down
state. See “Power State Management” on page 44.
The CALC and CALE commands perform calibration operations to ensure signal integrity on the Channel. See “CalibraTable 6 XOP
XOP
[3:0]
Command
0000
-
0001
Field Encoding Summary
XOP
[3:0]
Command
Reserved.
1000
CALC
Current calibration command.
-
Reserved.
1001
CALZ
Impedance calibration command.
0010
-
Reserved.
1010
CALE
End calibration command (CALC).
0011
-
Reserved.
1011
-
Reserved.
0100
-
Reserved.
1100
PDN
Enter powerdown power state.
0101
-
Reserved.
1101
-
Reserved.
0110
-
Reserved.
1110
-
Reserved.
0111
-
Reserved.
1111
-
Reserved.
Command and Description
Data Sheet E1819E20 (Ver. 2.0)
13
Command and Description
EDX1032BBBG
Any of the packet/command encodings under one of the four
operation types is equivalent in terms of the resource constraints. Therefore, both the horizontal columns (packet “a”)
and vertical rows (packet “b”) of the interaction table are
divided into four major groups.
Request Packet Interactions
A summary of request packet interactions is shown in Table 7.
Each case is limited to request packets with commands that
perform memory operations (including refresh commands).
This includes all commands in ROWA, ROWP, COL, and
COLM packets. The commands in COLX packets are
described in later sections. See “Maintenance Operations” on
page 40.
The four possible operation types for request packets a and b
include:
;
Request packet/command “a” is followed by request packet/
command “b”. The minimum possible spacing between these
two packet/commands is 0*tCYCLE. However, a larger time
interval may be needed because of a resource interaction
between the two packet/commands. If the minimum possible
spacing is 0*tCYCLE, then an entry of “No limit” is shown in
the table.
Note that the spacing values shown in the table are relative to
the effective beginning of a packet/command. The use of the
delay field with a command will delay the position of the effective packet/command from the position of the actual packet/
command. See “Dynamic Request Scheduling” on page 20.
Table 7 Packet
[A] Activate Row
•
ROWA/ACT
•
ROWP/REFA
•
ROWP/REFI
;
[R] Read Column
•
COL/RD
;
[W] Write Column
•
COL/WR
•
COLM/WRM
•
ROWP/PRE
•
ROWP/REFP
;
[P] Precharge Row
Interaction Summary
Second packet/command to bank Bb
Activate Row [A]
Read Column [R]
Write Column [W]
Precharge Row [P]
ROWA - ACT Bb
ROWP - REFA Bb
ROWP - REFI Ba
COL - RD Bb
COL - WR Bb
COLM - WRM Bb
ROWP - PRE Bb
ROWP - REFP Bb
Ba,Bb different
Case AAd: tRR
Case ARd: No limit
Case AWd: No limit
Case APd: No limit
Ba,Bb same
Case AAs: tRC
Case ARs: tRCD-R
Case AWs: tRCD-W
Case APs: tRAS
Ba,Bb different
Case RAd: No limit
Case RRd: tCC
Case RWd:a tΔRW
Case RPd: No limit
Ba,Bb same
Case RAs:b tRDP+tRP
Case RRs: tCC
Case RWs: a tΔRW
Case RPs: tRDP
Write Column [W]
COL - WR Ba
COLM - WRM Ba
Ba,Bb different
Case WAd: No limit
Case WRdc tΔWR
Case WWd: tCC
Case WPd: No limit
Ba,Bb same
Case WAsb: tWRP+tRP
Case WRs:c tΔWR
Case WWs: tCC
Case WPs: tWRP
Precharge Row [P]
ROWP - PRE Ba
ROWP - REFP Ba
Ba,Bb different
Case PAd: No limit
Case PRd: No limit
Case PWd: No limit
Case PPd: tPP
Ba,Bb same
Case PAs: tRP
Case PRs:d tRP+tRCD-R
Case PWs:d tRP+tRCD-W
Case PPs: tRC
Figure 3
Figure 4
Figure 5
Figure 6
First packet/command to bank Ba
Activate Row [A]
ROWA - ACT Ba
ROWP - REFA Ba
ROWP - REFI Ba
Read Column [R]
COL - RD Ba
See Examples:
a. tΔRW is equal to tCC + tRW-BUB,XDRDRAM+ tCAC - tCWD and is defined in Table 21. This also depends upon propagation delay - See “Propagation Delay”
on page 28.
b. A PRE command is needed between the RD and ACT/REFA commands or the WR/WRM and ACT/REFA commands.
c. tΔWR is defined in Table 21.
d. An ACT command is needed between the PRE/REFP and RD commands or the PRE/REFP and WR/WRM commands.
Data Sheet E1819E20 (Ver. 2.0)
14
EDX1032BBBG
minimum interval between two read operations.
The first request is shown along the vertical axis on the left of
the table. The second request is shown along the horizontal
axis at the top of the table. Each request includes a bank specification “Ba” and “Bb”. The first and second banks may be the
same, or they may be different. These two subcases for each
interaction are shown along the vertical axis on the left.
The interaction interval for the WRd and WRs cases is tΔWR.
This is the write-to-read time parameter and represents the
minimum interval between a write and a read operation to any
banks. See “Read/Write Interaction” on page 28.
The interaction interval for the PRs case is tRP+ tRCD-R. An
activate operation must be inserted between the precharge and
the read operation. The minimum interval between a precharge
and an activate operation to a bank is tRP. The minimum interval between an activate and read operation to a bank is tRCD-R.
There are 32 possible interaction cases altogether. The table
gives each case a label of the form “xyz”, where “x” and “y”
are one of the four operation types (“A” for Activate, “R” for
Read, “W” for Write, or “P” for Precharge) for the first and
second request, respectively, and “z” indicates the same bank
(“s”) or different bank (“d”).
In Figure 5, the interaction interval for the AWs case is tRCD-W.
This is the row-to-column-write timing parameter and represents the minimum interval between an activate operation and
a write operation to a bank.
Along the horizontal axis at the bottom of the table are cross
references to four figures (Figure 3 through Figure 6). Each
figure illustrates the eight cases in the corresponding vertical
column. Thus, Figure 3 shows the eight cases when the second
request is an activate operation (“A”). In the following discussion of the cases, only those in which the interaction interval is
greater than tCYCLE will be described.
The interaction interval for the RWd and RWs cases is tΔRW .
This is the read-to-write time parameter and represents the
minimum interval between a read and a write operation to any
banks. See “Read/Write Interaction” on page 28.
The interaction interval for the WWd and WWs cases is tCC.
This is the column-to-column time parameter and represents
the minimum interval between two write operations.
Request Interaction Cases
In Figure 3, the interaction interval for the AAd case is tRR .
This parameter is the row-to-row time and is the minimum
interval between activate commands to different banks of a
device.
The interaction interval for the PWs case is tRP + tRCD-W . An
activate operation must be inserted between the precharge and
the write operation. The minimum interval between a precharge and an activate operation to a bank is tRP . The minimum interval between an activate and a write operation to a
bank is tRCD-W .
The interaction interval for the AAs case is tRC . This is the
row cycle time parameter and is the minimum interval between
activate commands to same banks of a device. A precharge
operation must be inserted between the two activate operations.
In Figure 6, the interaction interval for the APs case is tRAS .
This parameter is the minimum activate-to-precharge time to a
bank.
The interaction interval for the RAs case is tRDP + tRP . A precharge operation must be inserted between the read and activate operation. The minimum interval between a read and a
precharge operation to a bank is tRDP . The minimum interval
between a precharge and an activate operation to a bank is tRP .
The interaction intervals for the RPs and WPs cases are tRDP
and tWRP, respectively. These are the read- or write-to-precharge time parameters to a bank.
The interaction interval for the PPd case is tPP . This parameter
is the precharge-to-precharge time and the minimum interval
between precharge commands to different banks of a device.
The interaction interval for the WAs case is tWRP + tRP . A precharge operation must be inserted between the write and the
activate operation.The minimum interval between a write and a
precharge operation to a bank is tWRP. The minimum interval
between a precharge and an activate operation to a bank is tRP .
The interaction interval for the PPs case is tRC. This is the row
cycle time parameter and the minimum interval between precharge commands to same banks of a device. An activate operation must be inserted between the two precharge operations.
This activate operation must be placed a time tRP after the first,
and a time tRAS before the second precharge.
The interaction interval for the PAs case is tRP . The minimum
interval between a precharge and an activate operation to a
bank is tRP .
In Figure 4, the interaction interval for the ARs case is tRCD-R.
This is the row-to-column-read time parameter and represents
the minimum interval between an activate operation and a read
operation to a bank.
The interaction interval for the RRd and RRs cases is tCC . This
is the column-to-column time parameter and represents the
Data Sheet E1819E20 (Ver. 2.0)
15
EDX1032BBBG
Figure 3
ACT-, RD-, WR-, PRE-to-ACT Packet Interactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
ACT
a
ACT
b
tRR
tRAS
ACT
a
tRC
PRE
a
tRP
ACT
b
DQ31..0
DQ15..0
DQN31..0
DQN15..0
AAd Case (activate-activate-different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba =/ Bb
b: ROWA Packet with ACT,Bb,Rb
T0
T1
T2
T3
T4
T5
T6
T7
T8
AAs Case (activate-activate-same bank)
a: ROWA Packet with ACT,Ba,Ra
Ba = Bb
b: ROWA Packet with ACT,Bb,Rb
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
RD ACT
a
b
DQ31..0
DQ15..0 No
DQN31..0
DQN15..0
RD
a
PRE
a
tRP
tRDP+tRP
ACT
b
limit
RAd Case (read-activate-different bank)
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
T0
tRDP
T1
T2
T3
T4
T5
RAs Case (read-activate-same bank)
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba =/ Bb
T6
T7
T8
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
DQ15..0 No
DQ31..0
DQN15..0
DQN31..0
tWRP
tWRP+tRP
WR
a
WR ACT
a
b
tRP
ACT
b
limit
WAd Case (write-activate-different bank)
a: COL Packet with WR,Ba,Ca
Ba =/ Bb
b: ROWA Packet with ACT,Bb,Rb
T0
PRE
a
T1
T2
T3
T4
T5
T6
T7
T8
WAs Case (write-activate-same bank)
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
DQ15..0
DQ31..0
DQN15..0
DQN31..0
PRE ACT
a
b
PRE
a
tRP
ACT
b
No limit
PAd Case (precharge-activate-different bank)
a: ROWP Packet with PRE,Ba
Ba =/ Bb
b: ROWA Packet with ACT,Bb,Rb
PAs Case (precharge-activate-same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: ROWA Packet with ACT,Bb,Rb
Data Sheet E1819E20 (Ver. 2.0)
16
EDX1032BBBG
Figure 4
ACT-, RD-, WR-, PRE-to-RD Packet Interactions
CFM
CFMN
CFM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFMN
RQ11..0
RQ11..0
ACT RD
a
b
DQ31..0
DQN31..0
DQ15..0
No limit
ACT
a
RD
b
tRCD-R
DQN15..0
ARd Case (activate-read different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba =/ Bb
b: COL Packet with RD,Bb,Cb
T0
T1
T2
T3
T4
T5
T6
T7
T8
ARs Case (activate-read same bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with RD,Bb,Cb
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
RD
a
tCC
RD
a
RD
b
tCC
RD
b
DQ31..0
DQ15..0
DQN31..0
DQN15..0
RRd Case (read-read different bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
T0
T1
T2
T3
T4
T5
RRs Case (read-read same bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba =/ Bb
T6
T7
T8
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
WR
a
RD
b
tΔWR
WR
a
RD
b
tΔWR
DQ31..0
DQ15..0
DQN15..0
DQN31..0
WRd Case (write-read different bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
T0
T1
T2
T3
T4
T5
WRs Case (write-read same bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba =/ Bb
T6
T7
T8
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
PRE RD
a
b
DQ31..0
DQ15..0 No
DQN31..0
DQN15..0
PRE
a
tRP
tRP+tRCD-R
ACT
B
tRCD-R
limit
PRd Case (precharge-read different bank)
a: ROWP Packet with PRE,Ba
Ba =/ Bb
b: COL Packet with RD,Bb,Cb
PRs Case (precharge-read same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: COL Packet with RD,Bb,Cb
Data Sheet E1819E20 (Ver. 2.0)
17
RD
b
EDX1032BBBG
Figure 5
ACT-, RD-, WR-, PRE-to-WR Packet Interactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
ACT WR
a
b
ACT WR
a
b
tRCD-W
No limit
DQ31..0
DQ15..0
DQN15..0
DQN31..0
AWd Case (activate-write different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba =/ Bb
b: COL Packet with WR,Bb,Cb
T0
T1
T2
T3
T4
T5
T6
T7
T8
AWs Case (activate-write same bank)
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with WR,Bb,Cb
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
tΔRW
RD
a
DQ31..D0
DQ15..0
DQN15..0
DQN31..0
WR
b
Q(a)
tCAC
RWd Case (read-write-different bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
T0
T1
T2
T3
T4
RD
a
tCWD
T5
D(b)
tCC tCYCLE
Ba =/ Bb
T6
T7
T8
T9
tΔRW
WR
b
tCAC
RWs Case (read-write-same bank)
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
tCWD
Q(a)
D(b)
tCC tCYCLE
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
WR
a
tCC
WR
a
WR
b
tCC
WR
b
DQ31..0
DQ15..0
DQN15..0
DQN31..0
WWd Case (write-write different bank)
a: COL Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
T0
T1
T2
T3
T4
T5
WWs Case (write-write same bank)
a: COP Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba =/ Bb
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
Ba = Bb
tRCD-W
PRE WR
a
b
PRE
a
tRP
tRP+tRCD-W
ACT WR
B
b
No limit
DQ31..0
DQ15..0
DQN15..0
DQN31..0
PWd Case (precharge-write different bank)
a: ROWP Packet with PRR,Ba
Ba =/ Bb
b: COL Packet with WR,Bb,Cb
PWs Case (precharge-write same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: COP Packet with WR,Bb,Cb
Data Sheet E1819E20 (Ver. 2.0)
18
EDX1032BBBG
Figure 6
ACT-, RD, WR-, PRE-to-PRE Packet Interactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
ACT PRE
a
b
ACT
a
PRE
b
tRAS
No limit
DQ31..0
DQ15..0
DQN15..0
DQN31..0
APd Case (activate-precharge different bank)
a: ROWA Packet with ACT,Ba,Ra
Ba # Bb
b: ROWP Packet with PRE,Bb
T0
T1
T2
T3
T4
T5
T6
T7
T8
APs Case (activate-precharge same bank)
a: ROWA Packet with ACT,Ba,Ra
Ba = Bb
b: ROWP Packet with PRR,Bb
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
RD PRE
a
b
RD
a
tRDP
PRE
b
No limit
DQ31..0
DQ15..0
DQN31..0
DQN15..0
RPd Case (read-precharge different bank)
a: COL Packet with RD,Ba,Ca
Ba # Bb
b: ROWP Packet with PRE,Bb
T0
T1
T2
T3
T4
T5
T6
T7
T8
RPs Case (read-precharge same bank)
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRR,Bb
T9
Ba = Bb
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
WR PRE
a
b
WR
a
tWRP
PRE
b
No limit
DQ31..0
DQ15..0
DQN31..0
DQN15..0
WPd Case (write-precharge different bank)
a: COL Packet with WR,Ba,Ca
Ba # Bb
b: ROWP Packet with PRE,Bb
T0
T1
T2
T3
T4
T5
T6
T7
T8
WPs Case (write-precharge same bank)
a: COL Packet with WR,Ba,Ca
Ba = Bb
b: ROWP Packet with PRE,Bb
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
PRE
a
tPP
PRE
b
PRE
a
tRP
ACT
b
tRAS
tRC
DQ31..0
DQ15..0
DQN31..0
DQN15..0
PPd Case (precharge-precharge different bank)
a: ROWP Packet with PRE,Ba
Ba # Bb
b: ROWP Packet with PRE,Bb
PPs Case (precharge-precharge same bank)
a: ROWP Packet with PRE,Ba
Ba = Bb
b: ROWP Packet with PRE,Bb
Data Sheet E1819E20 (Ver. 2.0)
19
PRE
b
EDX1032BBBG
mand at cycle T2 with the DEL field is set to “01”, and it will
be equivalent to a ROWP packet with a PRE command at cycle
T3 with the DEL field is set to “00”. This equivalence should
be used when analyzing request packet interactions.
Dynamic Request Scheduling
Delay fields are present in the ROWA, COL, and ROWP packets. They permit the associated command to optionally wait for
a time of one (or more) tCYCLE before taking effect. This
allows a memory controller more scheduling flexibility when
issuing request packets. Figure 7 illustrates the use of the delay
fields.
In the fourth timing diagram, a ROWP packet with a REFP
command is present at cycle T0. The DEL field (RA[7:6]) is set
to “11”. This request packet will be equivalent to a ROWP
packet with a REFP command at cycle T1 with the DEL field
is set to “10”, it will be equivalent to a ROWP packet with a
REFP command at cycle T2 with the DEL field is set to “01”,
and it will be equivalent to a ROWP packet with a REFP command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when analyzing request packet
interactions.
In the first timing diagram, a ROWA packet with an ACT command is present at cycle T0. The DELA field is set to “1”. This
request packet will be equivalent to a ROWA packet with an
ACT command at cycle T1 with the DELA field is set to “0”.
This equivalence should be used when analyzing request packet
interactions.
In the second timing diagram, a COL packet with a RD command is present at cycle T0. The DELC field is set to “1”. This
request packet will be equivalent to a COL packet with an RD
command at cycle T1 with the DELC field is set to “0”. This
equivalence should be used when analyzing request packet
interactions.
The two examples for the REFA and REFI commands are
identical to the example just described for the REFP command.
The ROWP packet allows two independent operations to be
specified. A PRE precharge command uses the POP and BP
fields, and the REFP, REFA, or REFI commands uses the
ROP and RA fields. Both operations have an optional delay
field (the POP field for the PRE command and the RA field
with the REFP, REFA, or REFI commands). The two delay
mechanisms are independent of one another. The POP field
does not affect the timing of the REFP, REFA, or REFI commands, and the RA field does not affect the timing of the PRE
command.
In a similar fashion, a COL packet with a WR command is
present at cycle T12. The DELC field is set to “1”. This request
packet will be equivalent to a COL packet with a WR command at cycle T13 with the DELC field is set to “0”. This
equivalence should be used when analyzing request packet
interactions.
In the COL packet with a RD command example, the read data
delay TCAC is measured between the Q read data packet and
the virtual COL packet at cycle T1.
When the interactions of a ROWP packet are analyzed, it must
be remembered that there are two independent commands
specified, both of which may affect how soon the next request
packet can be issued. The constraints from both commands in
a ROWP packet must be considered, and the one that requires
the longer time interval to the next request packet must be
used by the memory controller. Furthermore, the two commands within a ROWP packet may not reference the same
bank in the BP and RA fields.
Likewise, for the example with the COL packet with a WR
command, the write data delay TCWD is measured between the
D write data packet and the virtual COL packet at cycle T13.
In the third timing diagram, a ROWP packet with a PRE command is present at cycle T0. The DEL field (POP[1:0]) is set to
“11”. This request packet will be equivalent to a ROWP packet
with a PRE command at cycle T1 with the DEL field is set to
“10”, it will be equivalent to a ROWP packet with a PRE com-
Data Sheet E1819E20 (Ver. 2.0)
20
EDX1032BBBG
Request Scheduling Examples
Figure 7
ACT w/DEL=1 at T0 is equivalent
to ACT w/DEL=0 at T1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
tCYCLE
ACT ACT
DEL1 DEL0
DQ31..0
DQN31..0
Note
DEL value is specified by DELA field.
ROWA/ACT Command
WR w/DEL=1 at T12 is equivalent
to WR w/DEL=0 at T13
RD w/DEL=1 at T0 is equivalent
to RD w/DEL=0 at T1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
RD RD
DEL1 DEL0
DQ31..0
DQN31..0
Note
tCYCLE
WR WR
DEL1 DEL0
Q
tCAC
D
tCWD
DEL value is specified by DELC field.
COL/RD and COL/WR Commands
PRE w/DEL=3 at T0 is equivalent to PRE w/DEL
=2 at T1 or PRE w/DEL=1 at T2 or PRE w/DEL=0 at T3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
tCYCLE
PRE PRE PRE PRE
DEL3 DEL2 DEL1 DEL0
DQ31..0
DQN31..0
Note
DEL value is specified by {POP1, POP0} field.
ROWP/PRE Command
REFP w/DEL=3 at T0 is equivalent to REFP w/DEL=2
at T1 or REFP w/DEL=1 at T2 or REFP w/DEL=0 at T3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
REFI w/DEL=3 at T13 is equivalent to REFI w/DEL=2
at T14 or REFI w/DEL=1 at T15 or REFI w/DEL=0 at T16
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
REFP REFP REFP REFP
DEL3 DEL2 DEL1 DEL0
DQ31..0
DQN31..0
Note
REFA REFA REFA REFA
DEL3 DEL2 DEL1 DEL0
REFI REFI REFI REFI
DEL3 DEL2 DEL1 DEL0
tCYCLE
REFA w/DEL=3 at T6 is equivalent to REFA w/DEL=2
at T7 or REFA w/DEL=1 at T8 or REFA w/DEL=0 at T9
DEL value is specified by {RA7, RA6} field.
ROWP/REFP,REFA,REFI Commands
Data Sheet E1819E20 (Ver. 2.0)
21
EDX1032BBBG
data packets D(a1) and D(a2) follow these COL packets after
the write data delay tCWD. The two COL packets are separated
by the column-cycle time tCC. This is also the length of each
write data packet.
Memory Operations
Write Transactions
Figure 8 shows four examples of memory write transactions. A
transaction is one or more request packets (and the associated
data packets) needed to perform a memory access. The state of
the memory core and the address of the memory access determine how many request packets are needed to perform the
access.
The third timing diagram shows an example of a page-empty
write transaction. In this case, the selected bank is already
closed (no row is present in the sense amp array for the bank).
No row comparison is necessary for this case; however, the
memory controller must still remember that bank Ba has been
left closed. In this example, the access is made to row Ra of
bank Ba.
The first timing diagram shows a page-hit write transaction. In
this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the
selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done
in the memory controller. In this example, the access is made
to row Ra of bank Ba.
In this case, write data may be not be directly written into the
sense amp array for the bank. It is necessary to access the
requested row (activate). An activate command (ACT to row
Ra of bank Ba) is presented on edge T0. A COL packet with
WR command to column Ca1 of bank Ba is presented on edge
T1 a time tRCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented on edge T3. Two
write data packets D(a1) and D(a2) follow these COL packets
after the write data delay tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of
each write data packet. After the final write command, it may
be necessary to close the present row (precharge). A precharge
command (PRE to bank Ba) is presented on edge T14 a time
tWRP after the last COL packet with a WR command. The
decision whether to close the bank or leave it open is made by
the memory controller and its page policy.
In this case, write data may be directly written into the sense
amp array for the bank, and row operations (activate or precharge) are not needed. A COL packet with WR command to
column Ca1 of bank Ba is presented on edge T0, and a second
COL packet with WR command to column Ca1 of bank Ba is
presented on edge T2. Two write data packets D(a1) and D(a2)
follow these COL packets after the write data delay tCWD. The
two COL packets are separated by the column-cycle time tCC.
This is also the length of each write data packet.
The second timing diagram shows an example of a page-miss
write transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank).
However, the selected row for the memory access does not
match the address of the row already sensed (a page miss). This
comparison must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the
bank contains a row other than Ra.
The fourth timing diagram shows another example of a pageempty write transaction. This is similar to the previous example
except that only a single write command is presented, rather
than two write commands. This example shows that even with
a minimum length write transaction, the tRAS parameter will
not be a constraint. The tRAS measures the minimum time
between an activate command and a precharge command to a
bank. This time interval is also constrained by the sum tRCDW+tWRP which will be larger for a write transaction. These two
constraints ( tRAS and tRCD-W+tWRP) will be a function of the
memory device’s speed bin and the data transfer length (the
number of write commands issued between the activate and
precharge commands), and the tRAS parameter could become a
constraint for write transactions for future speed bins. In this
example, the sum tRCD-W+tWRP is greater than tRAS by the
amount ΔtRAS.
In this case, write data may be not be directly written into the
sense amp array for the bank. It is necessary to close the present row (precharge) and access the requested row (activate). A
precharge command (PRE to bank Ba) is presented on edge
T0. An activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with WR
command to column Ca1 of bank Ba is presented on edge T7 a
time tRCD-W later. A second COL packet with WR command
to column Ca2 of bank Ba is presented on edge T9. Two write
Data Sheet E1819E20 (Ver. 2.0)
22
EDX1032BBBG
Figure 8
Write Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a1
tCYCLE
WR
a2
tCC
DQ31..0
DQN31..0
D(a1)
tCWD
D(a2)
Page-hit Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
PRE
a3
ACT WR
a0
a1
tRP
DQ31..0
DQN31..0
tRCD-W
tCYCLE
WR
a2
tCC
tCWD
Transaction a: WR
D(a1)
a0 = {Ba,Ra}
D(a2)
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-miss Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT WR
a0
a1
DQ31..0 tRCD-W
WR
a2
tCWD
tDP
tWRP
tCC
D(a1)
tCWD
DQN31..0
tCYCLE
PRE
a3
D(a2)
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ31..0
DQN31..0
tRAS
ACT WR
a0
a1
tWRP
tRCD-W
tCWD
Bb = Ba
ΔtRAS
PRE
a3
tRP
ACT
b0
tCYCLE
D(a1)
Transaction a: WR
Transaction b: WR
a0 = {Ba,Ra}
b0 = {Bb,Rb}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
a3 = {Ba}
b3 = {Bb}
Page-empty Write Example - Core Limited
Data Sheet E1819E20 (Ver. 2.0)
23
EDX1032BBBG
the read data delay tCAC. The two COL packets are separated
by the column-cycle time tCC. This is also the length of each
read data packet.
Read Transactions
Figure 9 shows four examples of memory read transactions. A
transaction is one or more request packets (and the associated
data packets) needed to perform a memory access. The state of
the memory core and the address of the memory access determine how many request packets are needed to perform the
access.
The third timing diagram shows an example of a page-empty
read transaction. In this case, the selected bank is already
closed (no row is present in the sense amp array for the bank).
No row comparison is necessary for this case; however, the
memory controller must still remember that bank Ba has been
left closed. In this example, the access is made to row Ra of
bank Ba.
The first timing diagram shows a page-hit read transaction. In
this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the
selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done
in the memory controller. In this example, the access is made
to row Ra of bank Ba.
In this case, read data may not be directly read from the sense
amp array for the bank. It is necessary to access the requested
row (activate). An activate command (ACT to row Ra of bank
Ba) is presented on edge T0. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T5 a
time tRCD-R later. A second COL packet with RD command to
column Ca2 of bank Ba is presented on edge T7. Two read data
packets Q(a1) and Q(a2) follow these COL packets after the
read data delay tCAC. The two COL packets are separated by
the column-cycle time tCC. This is also the length of each read
data packet. After the final read command, it may be necessary
to close the present row (precharge). A precharge command —
PRE to bank Ba — is presented on edge T10 a time tRDP after
the last COL packet with a RD command. Whether the bank
is closed or left open depends on the memory controller and
its page policy.
In this case, read data may be directly read from the sense amp
array for the bank, and no row operations (activate or precharge) are needed. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T0, and a second
COL packet with RD command to column Ca2 of bank Ba is
presented on edge T2. Two read data packets Q(a1) and Q(a2)
follow these COL packets after the read data delay tCAC. The
two COL packets are separated by the column-cycle time tCC.
This is also the length of each read data packet.
The second timing diagram shows an example of a page-miss
read transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank).
However, the selected row for the memory access does not
match the address of the row already sensed (a page miss). This
comparison must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the
bank contains a row other than Ra.
The fourth timing diagram shows another example of a pageempty read transaction. This is similar to the previous example
except that it uses one read command instead of two read commands. In this case, the core parameter tRAS may also be a constraint upon when the precharge command may be issued.
The tRAS measures the minimum time between an activate
command and a precharge command to a bank. This time
interval is also constrained by the sum tRCD-R+ tRDP and must
be set to whichever is larger. These two constraints (tRAS and
tRCD-R+ tRDP) will be a function of the memory device’s speed
bin and the data transfer length (the number of read commands issued between the activate and precharge commands).
In this example, the tRAS is greater than the sum tRCD-R+ tRDP
by the amount ΔtRDP.
In this case, read data may not be directly read from the sense
amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T0.
An activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with RD
command to column Ca1 of bank Ba is presented on edge T11
a time tRCD-R later. A second COL packet with RD command
to column Ca2 of bank Ba is presented on edge T13. Two read
data packets Q(a1) and Q(a2) follow these COL packets after
Data Sheet E1819E20 (Ver. 2.0)
24
EDX1032BBBG
Figure 9
Read Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
RD
a1
tCYCLE
RD
a2
tCC
DQ31..0
DQN31..0
Q(a1)
tCAC
Transaction a: RD
Q(a2)
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-hit Read Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
PRE
a3
ACT
a0
RD
a1
tRP
DQ31..0
DQN31..0
tRCD-R
tCYCLE
RD
a2
tCC
Q(a1)
tCAC
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
Q(a2)
a3 = {Ba}
Page-miss Read Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT
a0
RD
a1
tRCD-R
DQ31..0
DQN31..0
RD
a2
tCC
tRDP
Q(a1)
tCAC
Transaction a: RD
tCYCLE
PRE
a3
a0 = {Ba,Ra}
Q(a2)
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Page-empty Read Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
tRAS
ACT
a0
RD
a1
tRCD-R
DQ31..0
DQN31..0
tRDP
ΔtRDP
Transaction a: RD
Transaction b: RD
ACT
b0
tCYCLE
Q(a1)
tCAC
Bb = Ba
tRP
PRE
a3
a0 = {Ba,Ra}
b0 = {Bb,Rb}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
a3 = {Ba}
b3 = {Bb}
Page-empty Read Example - Core Limited
Data Sheet E1819E20 (Ver. 2.0)
25
EDX1032BBBG
The slots at {T14, T18, T22, ...} are used for ROWP packets
with PRE commands. This frequency of ROWP packet spacing is determined by the tPP parameter. The phasing of the
ROWP packet spacing is determined by the tWRP parameter. If
the value of tWRP required the ROWP packets to occupy the
same request slots as the ROWA or COL packets already
assigned (this case is not shown), the delay field in the ROWP
packet could be used to place the ROWP packet one or more
tCYCLEs earlier.
Interleaved Transactions
Figure 10 shows two examples of interleaved transactions.
Interleaved transactions are overlapped with one another; a
transaction is started before an earlier one is completed.
The timing diagram at the top of the figure shows interleaved
write transactions. Each transaction assumes a page-empty
access; that is, a bank is in a closed state prior to an access, and
is precharged after the access. With this assumption, each
transaction requires the same number of request packets at the
same relative positions. If banks were allowed to be in an open
state, then each transaction would require a different number
of request packets depending upon whether the transaction
was page-empty, page-hit, or page-miss. This situation is more
complicated for the memory controller, and will not be analyzed in this document.
There is an example of an interleaved page-empty read at the
bottom of the figure. As before, there are four sets of request
pins RQ11..0 shown along the left side of the timing diagram,
allowing the pattern used for allocating request slots for the
different packets to be seen more clearly.
The slots at {T0, T4, T8, T12, ...} are used for ROWA packets
with ACT commands. This spacing is determined by the tRR
parameter. There should not be interference between the interleaved transactions due to resource conflicts because each bank
address — Ba, Bb, Bc, and Bd — is assumed to be different
from another. Four different banks are needed because the
effective tRC is 16*tCYCLE.
In the interleaved page-empty write example, there are four
sets of request pins RQ11..0 shown along the left side of the
timing diagram. The first three show the timing slots used by
each of the three request packet types (ACT, COL, and PRE),
and the fourth set (ALL) shows the previous three merged
together. This allows the pattern used for allocating request
slots for the different packets to be seen more clearly.
The slots at {T5, T7, T9, T11, ...} are used for COL packets
with RD commands. This frequency of the COL packet spacing is determined by the tCC parameter and by the fact that
there are two column accesses per row access. The phasing of
the COL packet spacing is determined by the tRCD-R parameter. If the value of tRCD-R required the COL packets to occupy
the same request slots as the ROWA packets (this case is not
shown), the DELC field in the COL packet could be used to
place the packet one tCYCLE earlier.
The slots at {T0, T4, T8, T12, ...} are used for ROWA packets
with ACT commands. This spacing is determined by the tRR
parameter. There should not be interference between the interleaved transactions due to resource conflicts because each bank
address — Ba, Bb, Bc, Bd, and Be — is assumed to be different from another. If two of the bank addresses are the same,
the later transaction would need to wait until the earlier transaction had completed its precharge operation. Five different
banks are needed because the effective tRC (tRC+ΔtRC) is
20*tCYCLE.
The DQ bus slots at {T11, T13, T15, T17, ...} carry the read data
packets {Q(a1), Q(a2), Q(b1), Q(b2), ...}. Two read data packets are read from a bank in each transaction. The DQ bus is
completely filled with read data — that is, no idle cycles need
to be introduced because there are no resource conflicts in this
example.
The slots at {T1, T3, T5 , T7 , T9 , T11 , ...} are used for COL
packets with WR commands. This frequency of the COL
packet spacing is determined by the tCC parameter and by the
fact that there are two column accesses per row access. The
phasing of the COL packet spacing is determined by the tRCDW parameter. If the value of tRCD-W required the COL packets
to occupy the same request slots as the ROWA packets (this
case is not shown), the DELC field in the COL packet could
be used to place the COL packet one tCYCLE earlier.
The slots at {T10, T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of the ROWP packet
spacing is determined by the tPP parameter. The phasing of the
ROWP packet spacing is determined by the tRDP parameter. If
the value of tRDP required the ROWP packets to occupy the
same request slots as the ROWA or COL packets already
assigned (this case is not shown), the delay field in the ROWP
packet could be used to place the ROWP packet one or more
tCYCLEs earlier.
The DQ bus slots at {T7 , T9 , T11, T13, ...} carry the write data
packets {D(a1), D(a2), D(b1), D(b2), ....}. Two write data packets are written to a bank in each transaction. The DQ bus is
completely filled with write data; no idle cycles need to be
introduced because there are no resource conflicts in this
example.
Data Sheet E1819E20 (Ver. 2.0)
26
EDX1032BBBG
Figure 10
Interleaved Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
The effective tRC time is increased by 4 tCYCLE
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
(ACT)
ACT
a0
RQ11..0
(COL)
tRR
WR
a1
DQ31..0 tRCD-W
DQN31..0
RQ11..0
(PRE)
RQ11..0
(ALL)
tRC
ACT
b0
WR
a2
WR
b1
ACT
c0
WR
b2
D(a1)
ACT WR
a0
a1
D(a2)
WR
c2
D(b1)
WR
d1
D(b2)
WR
d2
D(c1)
WR
e1
WR ACT WR
a2
b0
b1
D(c2)
ΔtWRP
tWRP
D(d2)
tRP
PRE
a3
WR
f1
WR
e2
D(d1)
tCYCLE
ACT
f0
WR
f2
D(e1)
D(e1)
PRE
b3
PRE
c3
WR ACT WR PRE WR ACT WR PRE WR ACT WR PRE WR
f1
f2
c2
d0
d1
a3
d2
e0
e1
b3
e2
f0
c3
WR ACT WR
b2
c0
c1
Transaction a: WR
Transaction b: WR
Transaction c: WR
Transaction d: WR
Transaction e: WR
Transaction f: WR
Bf = Ba
WR
c1
ΔtRC
ACT
e0
tCC
tCWD
Ba,Bb,Bc,Bd,Be
are different
banks.
ACT
d0
a0 = {Ba,Ra}
b0 = {Bb,Rb}
c0 = {Bc,Rc}
d0 = {Bd,Rd}
e0 = {Be,Re}
f0 = {Bf,Rf}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
d1 = {Bd,Cd1}
e1 = {Be,Ce1}
f1 = {Bf,Cf1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
c2 = {Bc,Cc2}
d2 = {Bd,Cd2}
e2 = {Be,Ce2}
f2 = {Bf,Cf2}
a3 = {Ba}
b3 = {Bb}
c3 = {Bc}
d3 = {Bd}
e3 = {Be}
f3 = {Bf}
Interleaved Page-empty Write Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
(ACT)
ACT
a0
RQ11..0
(COL)
tRR
DQ31..0
DQN31..0
tRCD-R
ACT
a0
Ba,Bb,Bc,Bd are
different banks.
Be = Ba
RD
a1
ACT
c0
RD
a2
ACT
d0
RD
b1
RD
b2
ACT
e0
RD
c1
RD
c2
tCYCLE
ACT
f0
RD
d1
RD
d2
RD
e1
RD
e2
tCAC
Q(a1)
tCC
RQ11..0
(PRE)
RQ11..0
(ALL)
tRC
ACT
b0
ACT RD
b0
a1
Transaction a: RD
Transaction b: RD
Transaction c: RD
Transaction d: RD
Transaction e: RD
tRDP
PRE
a3
Q(a2)
tRP
PRE
b3
Q(b1)
Q(b2)
PRE
c3
Q(c1)
Q(c2)
PRE
d3
RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD ACT RD PRE RD
a2
c0
b1
a3
b2
d0
c1
b3
c2
e0
d1
c3
d2
f0
e1
d3
e2
a0 = {Ba,Ra}
b0 = {Bb,Rb}
c0 = {Bc,Rc}
d0 = {Bd,Rd}
e0 = {Be,Re}
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
d1 = {Bd,Cd1}
e1 = {Be,Ce1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
c2 = {Bc,Cc2}
d2 = {Bd,Cd2}
e2 = {Be,Ce2}
a3 = {Ba}
b3 = {Bb}
c3 = {Bc}
d3 = {Bd}
e3 = {Be}
Interleaved Page-empty Read Example
Data Sheet E1819E20 (Ver. 2.0)
27
EDX1032BBBG
Read/Write Interaction
Propagation Delay
The previous section described overlapped read transactions
and overlapped write transactions in isolation. This section will
describe the interaction of read and write transactions and the
spacing required to avoid channel and core resource conflicts.
Figure 12 shows two timing diagrams that display the systemlevel timing relationships between the memory component and
the memory controller.
The timing diagram at the top of the figure shows the case of a
write-read-write command and data at the memory component. In this case, the timing will be identical to what has
already been shown in the previous sections; i.e. with all timing
measured at the pins of the memory component. This timing
diagram was produced by merging portions of the top and bottom timing diagrams in Figure 11.
Figure 11 shows a timing diagram (top) for the first case, a
write transaction followed by a read transaction. Two COL
packets with WR commands are presented on cycles T0 and
T2. The write data packets are presented a time tCWD later on
cycles T4 and T6. The device requires a time tΔWR after the second COL packet with a WR command before a COL packet
with a RD command may be presented. Two COL packets
with RD commands are presented on cycles T11 and T13. The
read data packets are returned a time tCAC later on cycles T17
and T19. The time tΔWR is required for turning around internal
bidirectional interconnections (inside the device). This time
must be observed regardless of whether the write and read
commands are directed to the same bank or different banks. A
gap tWR-BUB,XDRDRAM will appear on the DQ bus between the
end of the D(a2) packet and the beginning of the Q(b1) packet
(measured at the appropriate packet reference points). The size
of this gap can be evaluated by calculating the difference
between cycles T2 and T17 using the two timing paths:
tWR-BUB,XDRDRAM ≤ tΔWR + tCAC - tCWD - tCC
The example shown is that of a single COL packet with a write
command, followed by a single COL packet with a read command, followed by a second COL packet with a write command. These accesses all assume a page-hit to an open bank.
A timing interval tΔWR is required between the first WR command and the RD command, and a timing interval tΔRW is
required between the RD command and the second WR command. There is a write data delay tCWD between each WR command and the associated write data packet D. There is a read
data delay tCAC between the RD command and the associated
read data packet Q. In this example, all timing parameters have
assumed their minimum values except tWR-BUB,XDRDRAM.
The lower timing diagram in the figure shows the case where
timing skew is present between the memory controller and the
memory component. This skew is the result of the propagation
delay of signal wavefronts on the wires carrying the signals.
In this example, the value of tWR-BUB,XDRDRAM is greater than
its minimum value of tWR-BUB,XDRDRAM,MIN. The values of
tΔRW and tCAC are equal to their minimum values.
In the second case, the timing diagram displayed at the bottom
of Figure 11 illustrates a read transaction followed by a write
transaction. Two COL packets with RD commands are presented on cycles T0 and T2. The read data packets are returned
a time tCAC later on cycles T6 and T8. The device requires a
time tΔRW after the second COL packet with a RD command
before a COL packet with a WR command may be presented.
Two COL packets with WR commands are presented on cycles
T10 and T12. The write data packets are presented a time tCWD
later on cycles T13 and T15. The time tΔRW is required for turning around the external DQ bidirectional interconnections
(outside the device). This time must be observed regardless
whether the read and write commands are directed to the same
bank or different banks. The time tΔRW depends upon four
timing parameters, and may be evaluated by calculating the difference between cycles T2 and T13 using the two timing paths:
tΔRW + tCWD = tCAC + tCC + tRW-BUB,XDRDRAM
The example in the lower diagram assumes that there is a propagation delay of tPD-RQ along both the RQ wires and the
CFM/CFMN clock wires between the memory controller and
the memory component (the value of tPD-RQ used here is
1*tCYCLE). Note that in an actual system the tPD-RQ value will
be different for each memory component connected to the RQ
wires.
In addition, it is assumed that there is a propagation delay tPDD along the DQ/DQN wires between the memory controller
and the memory component (the direction in which write data
travels, and it is assumed that there is the same propagation
delay tPD-Q along the DQ/DQN wires between the memory
component and the memory controller (the direction in which
read data travels). The sum of these two propagation delays is
also denoted by the timing parameter tPD,CYC = tPD-D+tPD-Q.
or
tΔRW = (tCAC - tCWD)+ tCC + tRW-BUB,XDRDRAM
In this example, the values of tΔRW, tCAC, tCWD, tCC, and tRWBUB,XDRDRAM are equal to their minimum values.
Data Sheet E1819E20 (Ver. 2.0)
28
EDX1032BBBG
Figure 11
Write/Read Interaction
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a1
WR
a2
tCWD
tDR
RD
b1
tΔWR
DQ31..0
DQN31..0
D(a1)
RD
b2
tCYCLE
tCAC
D(a2)
tCWD
Q(b1)
Q(b2)
tWR-BUB,XDRDRAM
tCC
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
Write/Read Turnaround Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
RD
a1
RD
a2
DQ31..0
DQN31..0
WR
b1
tΔRW
tCAC
Q(a1)
WR
b2
Q(a2)
tCC
tCYCLE
tCWD
D(b1)
D(b2)
tRW-BUB,XDRDRAM
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
Read/Write Turnaround Example
Data Sheet E1819E20 (Ver. 2.0)
29
EDX1032BBBG
by evaluating the two timing paths between cycle T9 at the
Controller and cycle T21at the XDR DRAM:
tΔRW + tPD-RQ+ tCWD =
tPD-RQ+ tCAC + tCC+ tRW-BUB,XDRDRAM
As a result of these propagation delays, the position of packets
will have timing skews that depend upon whether they are
measured at the pins of the memory controller or the pins of
the memory component. For example, the CFM/CFMN signals at the pins of the memory component are tPD-RQ later
than at the pins of the memory controller. This is shown by the
cycle numbering of the CFM/CFMN signals at the two locations — in this example cycle T1 at the memory controller
aligns with cycle T0 at the memory component.
or
tΔRW= (tCAC - tCWD)+ tCC + tRW-BUB,XDRDRAM
The following relationship was shown for Figure 11
tΔRW ,MIN= (tCAC - tCWD)+ tCC + tRW-BUB,XDRDRAM,MIN
All the request packets on the RQ wires will have a tPD-RQ
skew at the memory component relative to the memory controller in this example. Because the tPD-D propagation delay of
write data matches the tPD-RQ propagation delay of the write
command, the controller may issue the write data packet D(a0)
relative to the COL packet with the first write command “WR
a0” with the normal write data delay tCWD. If the propagation
delays between the memory controller and memory component were different for the RQ and DQ buses (not shown in
this example), the write data delay at the memory controller
would need to be adjusted.
or
(tΔRW - tΔRW ,MIN)=
(tRW-BUB,XDRDRAM - tRWBUB,XDRDRAM,MIN)
In other words, the two timing parameters tRW-BUB,XDRDRAM
and tΔRW will change together. The relationship of this change
to the propagation delay tPD,CYC (= tPD-D+tPD-Q) can be
derived by looking at the two timing paths from T15 to T21 at
the XDR DRAM:
tPD-Q + tCC + tRW-BUB,XIO+ tPD-D =
tCC+ tRW-BUB,XDRDRAM
A propagation delay is seen by the read command — that is,
the read command will be delayed by a tPD-RQ skew at the
memory component relative to the memory controller. The
memory component will return the read data packet Q(b0) relative to this read command with the normal read data delay
tCAC (at the pins of the memory component).
or
tRW-BUB,XDRDRAM = tRW-BUB,XIO + tPD-D + tPD-Q
or
tRW-BUB,XDRDRAM = tRW-BUB,XIO + tPD,CYC
in a system with minimum propagation delays:
tRW-BUB,XDRDRAM,MIN = tRW-BUB,XIO + tPD,CYC,MIN
The read data packet will be skewed by an additional propagation delay of tPD-Q as it travels from the memory component
back to the memory controller. The effective read data delay
measured between the read command and the read data at the
memory controller will be tCAC +tPD-RQ+tPD-Q.
and since tRW-BUB,XIO is equal to tRW-BUB,XIO,MIN in both
cases, the following is true:
(tPD,CYC - tPD,CYC,MIN) =
(tRW-BUB,XDRDRAM - tRW-BUB,XDRDRAM,MIN) =
(tΔRW - tΔRW ,MIN)=
The tPD-RQ factor is caused by the propagation delay of the
request packets as they travel from memory controller to memory component. The tPD-Q factor is caused by the propagation
delay of the read data packets as they travel from memory component to memory controller.
In other words, the values of the tRW-BUB,XDRDRAM,MIN and
tΔRW ,MIN timing parameters correspond to the value of
tPD,CYC,MIN for the system (this is equal to one tCYCLE). As
tPD,CYC is increased from this minimum value, tRWBUB,XDRDRAM and tΔRW increase from their minimum values
by an equivalent amount.
All timing parameters will be equal to their minimum values
except tWR-BUB,XDRDRAM (as in the top diagram), and the timing parameters tRW-BUB,XDRDRAM and tΔRW. These will be
larger than their minimum values by the amount (tPD,CYCtPD,CYC,MIN), where tPD,CYC = tPD-D+tPD-Q. This may be seen
Data Sheet E1819E20 (Ver. 2.0)
30
EDX1032BBBG
Figure 12
Propagation Delay
XDR DRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a0
DQ31..0
DQN31..0
RD
b0
tΔWR
D(a0)
tCWD
WR
c0
tΔRW
tCAC
tCC
tWR-BUB,XDRDRAM
Transaction a: WR
Transaction b: RD
Transaction c: WR
tCYCLE
tCWD
Q(b0)
D(c0)
tCC
tRW-BUB,XDRDRAM
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
Write-Read-Write at XDR DRAM
(portions of top and bottom timing diagrams of Figure 11 merged)
Controller T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a0
tΔWR
DQ31..0
DQN31..0
tΔRW
RD
b0
tCC
D(a0)
XDR DRAMT
-1
T0
T1
T2
T3
T5
T6
T7
T8
T9
tCYCLE
tRW-BUB,XIO
Q(b0)
tPD-Q
T4
WR
c0
D(c0)
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CFM
CFMN
RQ11..0
DQ31..0
DQN31..0
WR
a0
tPD-RQ
tCYCLE
tPD-D
tCWD
tPD-RQ
RD
b0
tPD-RQ
D(a0)
Q(b0)
tCAC
Transaction a: WR
Transaction b: RD
Transaction c: WR
WR
c0
tPD-D
tCWD
tRW-BUB,XDRDRAMD(c0)
tCC
a0 = {Ba,Ca0}
b0 = {Bb,Cb0}
c0 = {Bc,Cc0}
Write-Read-Write at Controller and XDR DRAM
w/ tPD-RQ = tPD-Q = tPD-D = 1*tCYCLE
tPD-RQ
...
RQ
Controller
DQ
RQ
DQ
tPD-Q
Data Sheet E1819E20 (Ver. 2.0)
31
XDR DRAM
...
tPD-D
EDX1032BBBG
used during either serial write transaction.
Register Operations
Serial Read Transaction
Serial Transactions
The serial device read transaction in Figure 14 begins with the
Start[3:0] field. This consists of bits “1100” on the CMD pin.
This indicates that the remaining 28 bits constitute a serial
transaction.
The serial interface consists of five pins. This includes RST,
SCK, CMD, SDI, and SDO. SDO uses CMOS signaling levels.
The other four pins use RSL signaling levels. RST, CMD, SDI,
and SDO use a timing window which surrounds the falling
edge of SCK). The RST pin is used for initialization.
The next two bits are the SCMD[1:0] field. This field contains
the serial command, and the bits “10” in the case of a serial
device read transaction.
Figure 13 and Figure 14 show examples of a serial write transaction and a serial read transaction. Each transaction starts on
cycle S4 and requires 32 SCK edges. The next serial transaction
can begin on cycle S36. SCK does not need to be asserted if
there is no transaction.
The next eight bits are “00” and the SID[5:0] field. This field
contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field and contain the
serial address of the control register being accessed.
Serial Write Transaction
A single bit “0” follows next. This bit allows one cycle for the
access time to the control register and time to turn on the SDO
output driver.
The serial device write transaction in Figure 13 begins with the
Start[3:0] field. This consists of bits “1100” on the CMD pin.
This indicates to the XDR DRAM that the remaining 28 bits
constitute a serial transaction.
The next eight bits are “00” and the SID[5:0] field. This field
contains the serial identification of the device being accessed.
The next eight bits on the CMD pin are the sequence
“00000000”. At the same time, the eight bits on the SDO pin
are the SRD[7:0] field. This is the read data that is accessed
from the selected control register. Note the output timing convention here: bit SRD[7] is driven from a time tQ,SI,MAX after
edge S26 to a time tQ,SI,MIN after edge S27. The bit is sampled
in the controller by the edge S27
The next eight bits are the SADR[7:0] field. This field contains
the serial address of the control register being accessed.
A final bit “0” is driven on the CMD pin to finish the serial
read transaction.
A single bit “0” follows next. This bit allows one cycle for the
access time to the control register.
A serial forced read is identical except that the contents of the
SID[5:0] field in the transaction is ignored and all devices preform the register read. This is used for device testing.
The next two bits are the SCMD[1:0] field. This field contains
the serial command, the bits 00 in the case of a serial device
write transaction.
The next eight bits on the CMD pin is the SWD[7:0] field. This
is the write data that is placed into the selected control register.
Figure 15 shows the response of a DRAM to a serial device
read transaction when its internal SID[5:0] register field doesn’t
match the SID[5:0] field of the transaction. Instead of driving
read data from an internal register for cycle edges S27 through
S34 on the SDO output pin, it passes the input data from the
SDI input pin to the SDO output pin during this same period.
A final bit “0” is driven on the CMD pin to finish the serial
write transaction.
A serial broadcast write is identical except that the contents of
the SID[5:0] field in the transaction is ignored and all devices
preform the register write. The SDI and SDO pins are not
Table 8 SCMD
SCMD
[1:0]
Field Encoding Summary
Command
Description
00
SDW
Serial device write — one device is written, the one whose SID[5:0] register matches the SID[5:0] field of the transaction.
01
SBW
Serial broadcast write — all devices are written, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field
10
SDR
Serial device read — one device is read, the one whose SID[5:0] register matches the SID[5:0] field of the transaction.
11
SFR
Serial forced read — all devices are read, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field
Data Sheet E1819E20 (Ver. 2.0)
32
EDX1032BBBG
Figure 13
Serial Write Transaction
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
SCK
tCYC,SCK
RST
Start
CMD
transaction
2’h0,SID[5:0]
SCMD
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’‘0’ ‘0’ 5
4
3
2
SADR[7:0]
1
0
7
6 5
4
3
2
SWD[7:0]
1
0 ‘0’ 7
6 5
4
3
2
1
0 ‘0’
SDI
(input)
SDO
(output)
Figure 14
Serial Read Transaction — Selected DRAM
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
SCK
tCYC,SCK
RST
Start
CMD
transaction
2’h0,SID[5:0]
SCMD
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’ 5
4
3
2 1
SADR[7:0]
0
7
6
5
4
3
2
8’h00
1 0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’ ‘0’
SDI
(input)
SDO
(output)
Figure 15
SRD[7:0]
7
6
5
4
3
2
1 0
Serial Read Transaction — Non-selected DRAM
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46 S48
SCK
S28
tCYC,SCK
RST
CMD
Start
SCMD
SDI
transaction
2’h0,SID[5:0]
‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘0’‘0’ ‘0’ 5
4
3
2 1
SADR[7:0]
0
7
6
5
4
3
2
tP,SI
8’h00
1 0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ’0’ ‘0’ ‘0’ ‘0’
SDI
(input)
7
6 5
SDO
(output)
7
6
SRD[7:0]
4
3
2
1
0
SRD[7:0]
Data Sheet E1819E20 (Ver. 2.0)
33
5
4
3
2
1 0
SDO
combinational
propagation
from SDI to SDO
EDX1032BBBG
Figure 18 shows the Power Management Register. It contains
two fields. The first is the PX field. When this field is written
with a 1, the memory component transitions from powerdown
to active state. It is usually unnecessary to write a 0 into this
field; this is done automatically by the PDN command in a
COLX packet. The PST field indicates the current power state
of the memory component.
Register Summary
Figure 16 through Figure 33 show the control registers in the
memory component. The control registers are responsible for
configuring the component’s operating mode, for managing
power state transitions, for managing refresh, and for managing calibration operations.
A control register may contain up to eight bits. Each figure
shows defined bits in white and reserved bits in gray. Reserved
bits must be written as 0 and must be ignored when read.
Write-only fields must be ignored when read
Figure 19 shows the Write Data Serial Load Register. It permits
data to be written into memory via the Serial Interface.
Figure 22 shows the Refresh Bank Control Register. It contains
two fields: BANK and MBR. The BANK field is read-write
and contains the bank address used by self-refresh during the
powerdown state. The MBR field controls how many banks are
refreshed during each refresh operation. Figure 23, Figure 24,
and Figure 25 show different fields of the Refresh Row Register (high, middle, and low). This read-write field contains the
row address used by self- and auto-refresh. See “Refresh Transactions” on page 40 for more details.
Each figure displays the following register information:
1.
register name
2.
register mnemonic
3.
register address (SADR[7:0] value needed to access it)
4.
read-only, write-only or read-write
5.
initialization state
6.
description of each defined register field
Figure 28 and Figure 29 show the Current Calibration 0 and 1
registers. They contain the CCVALUE0 and CCVALUE1
fields, respectively. These are read-write fields which control
the amount of IOL current driven by the DQ and DQN pins
during a read transaction. The Current Calibration 0 Register
controls the even-numbered DQ and DQN pins, and the Current Calibration 1 controls the odd-numbered DQ and DQN
pins.
Figure 16 shows the Serial Identification register. This register
contains the SID[5:0] (serial identification field). This field
contains the serial identification value for the device. The value
is compared to the SID[5:0] field of a serial transaction to
determine if the serial transaction is directed to this device. The
serial identification value is set during the initialization
sequence.
Figure 32 shows the test registers. This includes the TES registers. It is used during device testing. It is not to be read or written during normal operation.
Figure 17 shows the Configuration Register. It contains two
fields. The first is the WIDTH field. This field allows the number of DQ/DQN pins used for memory read and write
accesses to be adjusted. The SLE field enables data to be written into the memory through the serial interface using the
WDSL register.
Figure 16
7
Figure 33 shows the DLY register. This is used to set the value
of tCAC and tCWD used by the component. See “Timing
Parameters” on page 69.
Serial Identification (SID) Register
6
5
4
reserved
3
2
SID[5:0]
1
0
Serial Identification Register
SADR[7:0]: 000000012
Read-only register
SID[7:0] resets to 000000002
SID[5:0] - Serial Identification field.
This field contains the serial identification value for the device.
The value is compared to the SID[5:0] field of a serial transaction
to determine if the serial transaction is directed to this device.
The serial identification value is set during the initialization
sequence.
Data Sheet E1819E20 (Ver. 2.0)
34
EDX1032BBBG
Figure 17
7
Configuration (CFG) Register
6
5
reserved
rsrv
4
3
SLE rsrv
2
1
0
WIDTH[2:0]
Configuration Register
SADR[7:0]: 000000102
Read/write register
CFG[7:0] resets to 000001012
WIDTH[2:0] - Device interface width field.
0002, 0012 - Reserved
0102 - x4 device width
0112 - x8 device width
1002 - x16 device width
1012 - x32 device width
1102, 1112 - Reserved
SLE - Serial Load enable field.
02 - WDSL-path-to-memory disabled
12 - WDSL-path-to-memory enabled
Figure 18
7
Power Management (PM) Register
6
5
4
PST[1:0]
3
2
1
0
PX
reserved
Power Management Register
SADR[7:0]: 000000112
Read/write register
PM[7:0] resets to 000000002
PX - Powerdown exit field.(write-one-only, read=zero)
02 - Powerdown entry - do not write zero - use PDN command
12 - Powerdown exit - write one to exit
PST[1:0] - Power state field (read-only).
002 - Powerdown (with self-refresh)
012 - Active/active-idle
102 - reserved
112 - reserved
Figure 19
7
Write Data Serial Load (WDSL) Control Register
6
5
4
3
WDSD[7:0]
2
1
0
Read/write register
Write Data Serial Load Control Register
WDSL[7:0] resets to 000000002
SADR[7:0]: 000001002
WDSD[7:0] - Writing to this register places eight bits of data into
the serial-to-parallel conversion logic (the “Demux” block of
Figure 1). Writing to this register “2x32” times accumulates a full
“tCC” worth of write data. A subsequent WR command (with
SLE=1 in CFG register in Figure 17) will write this data (rather
than DQ data) to the sense amps of a memory bank. The shifting
order of the write data is shown in Table 10.
Data Sheet E1819E20 (Ver. 2.0)
35
EDX1032BBBG
Figure 20
7
RQ Scan High (RQH) Register
6
5
4
3
2
1
0
RQH[3:0]
reserved
RQ Scan High Register
SADR[7:0]: 000001102
Read/write register
RQH[7:0] resets to 000000002
RQH[3:0] - Latched value of RQ[11:8] in RQ Wire Test Mode.*
* Wire Test Mode is an internal DRAM test feature, and not part
of normal XDR operation.
Figure 21
7
RQ Scan Low (RQL) Register
6
5
4
3
2
1
0
RQL[7:0]
RQ Scan Low Register
SADR[7:0]: 000001112
Read/write register
RQL[7:0] resets to 000000002
RQL[7:0] - Latched value of RQ[7:0] in RQ Wire Test Mode.*
* Wire Test Mode is an internal DRAM test feature, and not part
of normal XDR operation.
Figure 22
7
Refresh Bank (REFB) Control Register
6
MBR[1:0]
5
4
reserved
3
2
1
0
BANK[2:0]
Refresh Bank Control Register
SADR[7:0]: 000010002
Read/write register
REFB[7:0] resets to 000000002
BANK[2:0] - Refresh bank field.
This field returns the bank address for the next self-refresh operation when in Powerdown power state.
MBR[1:0] - Multi-bank and multi-row refresh control field.
102 - Reserved
002 - Single-bank refresh.
112 - Reserved
012 - Reserved
Data Sheet E1819E20 (Ver. 2.0)
36
EDX1032BBBG
Figure 23
7
Refresh High (REFH) Row Register
6
5
4
3
2
1
0
R[18:16]
reserved
Refresh High Row Register
SADR[7:0]: 000010012
Read/write register
REFH[7:0] resets to 000000002
Reserved - Refresh row field.
This field contains the high-order bits of the row address that will
be refreshed during the next refresh interval. This row address
will be incremented after a REFI command for auto-refresh, or
when the BANK[2:0] field for the REFB register equals the maximum bank address for self-refresh.
Figure 24
7
Refresh Middle (REFM) Row Register
6
5
4
3
2
1
0
R[11:8]
reserved
Refresh Middle Row Register
SADR[7:0]: 000010102
Read/write register
REFM[7:0] resets to 000000002
R[11:8] - Refresh row field.
This field contains the middle-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for autorefresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
Figure 25
7
Refresh Low (REFL) Row Register
6
5
4
3
2
1
0
R[7:0]
Refresh Low Row Register
SADR[7:0]: 000010112
Read/write register
REFL[7:0] resets to 000000002
R[7:0] - Refresh row field
This field contains the low-order bits of the row address that will
be refreshed during the next refresh interval. This row address
will be incremented after a REFI command for auto-refresh, or
when the BANK[2:0] field for the REFB register equals the maximum bank address for self-refresh.
Figure 26
7
Read Only Memory 2 (ROM2) Register
6
reserved
5
4
DEN[1:0]
3
2
NW[1:0]
1
0
BL[1:0]
Read Only Memory 2 Register
Read-only register
SADR[7:0]: 000011102
ROM2[7:0] resets to 000101002
BL[1:0] - Burst Length of the device:
002 = BL16 102 = Reserved
012 = BL32 112 = Reserved
NW[1:0] - Native Width of the device:
102 = Reserved
002 = x16
112 = Reserved
012 = x32
DEN[1:0] - Density of the device:
002 = 512Mb 102 = 2Gb
112 = 4Gb
012 = 1Gb
Data Sheet E1819E20 (Ver. 2.0)
37
EDX1032BBBG
Figure 27
7
IO Configuration (IOCFG) Register
6
5
4
3
2
CRM BFE
reserved
1
0
ODF[1:0]
IO Configuration Register
SADR[7:0]: 000011112
Read/write register
IOCFG[7:0] resets to 00000000 2
ODF[1:0] - Overdrive Function field
00 - Nominal VOSW,DQ range
01 - reserved
10 - reserved
11 - reserved
BFE - Bin F Enable field
0 - Nominal
1 - Use for Bin F operations
CRM - Column Remap field
0 - Nominal
1 - Remap COL and COLM to have the same request packet
definition as in XDR DRAM 8x4Mx16/8/4/2
Figure 28
7
Current Calibration 0 (CC0) Register
6
5
4
3
2
1
0
CCVALUE0[5:0]
reserved
Current Calibration 0 Register
SADR[7:0]: 000100002
Read/write register
CC0[7:0] resets to vvvvvvvv2
(vendor-dependent reset value)
CCVALUE0[5:0] - Current calibration value field.
This field controls the amount of current drive for the even-numbered DQ and DQN pins.
Figure 29
7
Current Calibration 1 (CC1) Register
6
5
4
3
2
1
0
CCVALUE1[5:0]
reserved
Current Calibration 1 Register
SADR[7:0]: 000100012
Read/write register
CC1[7:0] resets to vvvvvvvv2
(vendor-dependent reset value)
CCVALUE1[5:0] - Current calibration value field.
This field controls the amount of current drive for the odd-numbered DQ and DQN pins.
Figure 30
7
Read Only Memory 0 (ROM0) Register
6
5
4
VENDOR[3:0]
reserved
3
2
1
MASK[3:0]
0
Read-only register
Read Only Memory 0 Register
ROM0[7:0] resets to vvvvmmmm
SADR[7:0]: 000101102
MASK[3:0] - Version number of mask (00012 is first version).
VENDOR[3:0] - Vendor number for component:
0010 - Elpida
Data Sheet E1819E20 (Ver. 2.0)
38
EDX1032BBBG
Figure 31
7
Read Only Memory 1 (ROM1) Register
6
5
BB[1:0]
4
3
2
RB[2:0]
1
0
CB[2:0]
Read Only Memory 1 Register
SADR[7:0]: 000101112
Read-only register
ROM0[7:0] resets to bbrrrccc
CB[2:0] - Column address bits: #bits = 6 +CB[2:0]
RB[2:0] - Row address bits:
#bits = 10 +RB[2:0]
BB[1:0] - Bank address bits: #bits = 2 +BB[1:0]
These three fields indicate how many column, row, and bank
address bits are present. An offset of {6,10,2} is added to the
field value to give the number of address bits.
Figure 32
7
TEST Register
6
5
WTL WTE
4
3
2
1
0
reserved
TEST Register
SADR[7:0]: 000110002
Read/write register
TEST[7:0] resets to 000000002
Wire Test Enable in RQ Wire Test Mode (WT_Enable).*
Wire Test Latch in RQ Wire Test Mode (WT_Latch).*
* Wire Test mode is an internal DRAM test feature, and not part
of normal XDR operation.
Figure 33
7
Delay (DLY) Control Register
6
5
4
CWD[3:0]
3
2
1
CAC[3:0]
0
DLY Register
SADR[7:0]: 000111112
Read/write register
DLY[7:0] resets to 001101102
CAC[3:0] - Programmed value of tCAC timing parameter:
01102 - tCAC = 6*tCYCLE 10002 - tCAC = 8*tCYCLE
01112 - tCAC = 7*tCYCLE 10012 - tCAC = 9*tCYCLE
others - Reserved.
CWD[3:0] - Programmed value of tCWD timing parameter:
00112 - tCWD = 3*tCYCLE
01002 - tCWD = 4*tCYCLE others - Reserved.
Data Sheet E1819E20 (Ver. 2.0)
39
EDX1032BBBG
REFA command in the top timing diagram.
Maintenance Operations
Interleaved Refresh Transactions
Refresh Transactions
The lower timing diagram in Figure 34 represents one way a
memory controller might handle refresh maintenance in a real
system.
Figure 34 contains two timing diagrams showing examples of
refresh transactions. The top timing diagram shows a single
refresh operation. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is received in a ROWP
packet on clock edge T0. The REFA command causes the row
addressed by the REFr register (REFH/REFM/REFL) to be
opened (sensed) and placed in the sense amp array for the
bank.
A series of eight ROWP packets with REFA commands
(except for the last which is a REFI command) are presented
starting at edge T0. The packets are spaced with intervals of
tRR. Each REFA or REFI command is addressed to a different
bank (Ba through Bh) but uses the same row address from the
REFr (REFH/REFM/REFL) register. The eighth REFI command uses this address and then increments it so the next set
of eight REFA/REFI commands will refresh the next set of
rows in each bank.
Note that the REFA and REFI commands are similar to the
ACT command functionally; both specify a bank address and
delay value, and both cause the selected bank to open (to
become sensed.) The difference is that the ACT command is
accompanied by a row address in the ROWA packet, while the
REFA and REFI commands use a row address in the REFr
register (REFH/REFM/REFL).
A series of eight ROWP packets with REFP commands are
presented effectively at edge T10 (a time tRAS after the first
ROWP packet with a REFA command). The packets are
spaced with intervals of tPP. Like the REFA/REFI commands,
each REFP command is addressed to a different bank (Ba
through Bh).
After a time tRAS, a ROWP packet with REFP command to
bank Ba is presented. This causes the bank to be closed (precharged), leaving the bank in the same state as when the refresh
transaction began.
This burst of eight refresh transactions fully utilizes the memory component. However, other read and write transactions
may be interleaved with the refresh transactions before and
after the burst to prevent any loss of bus efficiency. In other
words, a ROWA packet with ACT command for a read or write
could have been presented at edge T-4 (a time tRR before the
first refresh transaction starts at edge T0). Also, a ROWA
packet with ACT command for a read or write could have been
presented at edge T36 (a time tRR after the last refresh transaction starts at edge T32). In both cases, the other request packets
for the interleaved read or write accesses (the precharge commands and the read or write commands) could be slotted in
among the request packets for the refresh transactions.
Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and delay value,
and both cause the selected bank to close (to become precharged).
After a time tRP , another ROWP packet with REFA command
to bank Bb is presented (banks Ba and Bb are the same in this
example). This starts a second refresh cycle. Each refresh
transaction requires a total time tRC= tRAS+ tRP , but refresh
transactions to different banks may be interleaved like normal
read and write transactions.
Each row of each bank must be refreshed once in every tREF
interval. This is shown with the fourth ROWP packet with a
Data Sheet E1819E20 (Ver. 2.0)
40
EDX1032BBBG
Refresh Transactions
Figure 34
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
tRAS
REFA
RQ11..0
tRP
REFP
a0
a1
tRC
DQ31..0
DQN31..0
REFA
REFA
b0
c0
tCYCLE
tREF
Bb = Ba
Bc/Rc = Ba/Ra
T0
T1
Transaction a: REF
Transaction b: REF
Transaction c: REF
T2
T3
T4
T5
a0 = {Ba,REFR}
b0 = {Bb,REFR}
c0 = {Bc,REFR}
T6
T7
T8
T9
a1 = {Ba}
b1 = {Bb}
c1 = {Bc}
Refresh Transaction
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
(ACT)
REFA
tRR
a0
REFA
REFA
REFA
REFA
REFA
b0
c0
d0
e0
f0
RQ11..0
(PRE)
RQ11..0
(ALL)
REFP
REFP
REFP
REFP
a1
b1
c1
d1
REFA
REFA
REFA
REFP
REFA
REFP
REFA
REFP
REFA
REFP
a0
b0
c0
a1
d0
b1
e0
c1
f0
d1
DQ31..0
DQN31..0
T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CFM
CFMN
This REFI increments REFR
RQ11..0
(ACT)
REFA
REFI
REFA
g0
h0
i0
RQ11..0
(PRE)
RQ11..0
(ALL)
tCYCLE
REFP
REFP
REFP
REFP
e1
f1
g1
h1
REFA
REFP
REFA
REFP
REFA
REFP
REFP
g0
e1
h0
f1
i0
g1
h1
DQ31..0
DQN31..0
Ba,Bb,Bc,Bd,
Be,Bf,Bg and
Bh are
different banks.
Bi = Ba
Transaction a: REF
Transaction b: REF
Transaction c: REF
Transaction d: REF
Transaction e: REF
Transaction f: REF
Transaction g: REF
Transaction h: REF
Transaction i: REF
a0 = {Ba,REFR}
b0 = {Bb,REFR}
c0 = {Bc,REFR}
d0 = {Bd,REFR}
e0 = {Be,REFR}
f0 = {Bf,REFR}
g0 = {Bg,REFR}
h0 = {Bh,REFR}
i0 = {Ba,REFR+1}
a1 = {Ba}
b1 = {Bb}
c1 = {Bc}
d1 = {Bd}
e1 = {Be}
f1 = {Bf}
g1 = {Bg}
h1 = {Bh}
i1 = {Bi}
Data Sheet E1819E20 (Ver. 2.0)
41
Interleaved Refresh Example
EDX1032BBBG
The dynamic termination calibration sequence is shown in the
lower diagram. Note that this memory component does not
use this sequence; termination calibration is performed during
the manufacturing process. However, the termination sequence
shown will be issued by the controller for those memory components which do use a periodic calibration mechanism.
Calibration Transactions
Figure 35 shows the calibration transaction diagrams for the
XDR DRAM device. There is one calibration operation supported: calibration of the output current level IOL for each
DQi and DQNi pin.
The output current calibration sequence is shown in the upper
diagram. It begins when a period of tCMD-CALC is observed
after the last RQ packet (with command “CMD a” in this
example). No request packets should be issued in this period.
It begins when a period of tCMD-CALZ is observed after the
packet at edge T0 (with command CMDa in this example). No
request packets should be issued in this period.
A COLX packet with a CALZ command is then issued at edge
T3 to start the termination calibration sequence. A second
period of tCALZE is observed after this packet. No request
packets should be issued during this period.
A COLX packet with a”CALC b” command is then issued to
start the current calibration sequence. A period of tCALCE is
observed after this packet. No request packets should be issued
during this period.
A COLX packet with a CALE command is then issued at edge
T6 to end the termination calibration sequence. A third period
of tCALE-CMD is observed after this packet. No request packets
should be issued during this period. The first request packet
may be issued at edge T12 (with command CMDd in this example).
A COLX packet with a “CALE c” command is then issued to
end the current calibration sequence. A period of tCALE-CMD is
observed after this packet. No request packets should be issued
during this period. The first request packet may then be issued
(with command “CMD d” in this example).
A second current calibration sequence must be started within
an interval of tCALC. In this example, the next COLX packet
with a “CALC e” command starts a subsequent sequence.
A second termination calibration sequence must be started
within an interval of tCALZ. In this example, the next COLX
packet with a CALZ command occurs at edge T20.
Note that the labels for the CFM clock edges (of the form Ti)
are not to scale, and are used to identify events in the diagrams.
Data Sheet E1819E20 (Ver. 2.0)
42
EDX1032BBBG
Figure 35
Calibration Transactions
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
CMD
CALC
a
b
tCALCE,
tCALE-CMD,
CALE
c
tCMD-CALC
DQ31..0
DQN31..0
CMD
CALC
d
e
tCALC
Packet a: Any CMD
Packet b: CALC
Packet c: CALE
Packet d: Any CMD
Packet e: CALC
T0
T1
T2
tCYCLE
T3
T4
T5
Current Calibration Transaction
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
DQ31..0
DQN31..0
CMD
CALZ
a
b
tCALZE,
CALE
tCALE-CMD,
c
tCMD-CALZ
CMD
CALZ
d
e
tCYCLE
tCALZ
Packet a: Any CMD
Packet b: CALZ
Packet c: CALE
Packet d: Any CMD
Packet e: CALZ
Termination Calibration Transaction
Data Sheet E1819E20 (Ver. 2.0)
43
EDX1032BBBG
exit. The sequence is started with a serial broadcast write (SBW
command) transaction using the serial bus of the XDR
DRAM. This transaction writes the value “00000001” to the
Power Management (PM) register (SADR=”00000011”) of all
XDR DRAMs connected to the serial bus. This sets the PX bit
of the PM register, causing the XDR DRAMs to return to
Active power state.
Power State Management
Figure 36 shows power state transition diagrams for the XDR
DRAM device. There are two power states in the XDR
DRAM: Powerdown and Active. Powerdown state is to be used
in applications in which it is necessary to shut down the CFM/
CFMN clock signals. In this state, the contents of the storage
cells of the XDR DRAM will be retained by an internal state
machine which performs periodic refresh operations using the
REFB and REFr control registers.
The CFM/CFMN clock signals must be stable a time tCFMPDN before the end of the SBW transaction.
The XDR DRAM will enter Active state after an interval of
tPDN-EXIT has elapsed from the end of the SBW transaction
(this is the parameter that should be used for calculating the
power dissipation of the XDR DRAM).
The upper diagram shows the sequence needed for Powerdown entry. Prior to starting the sequence, all banks of the
XDR DRAM must be precharged so they are left in a closed
state. Also, all 23 banks must be refreshed using the current
value of the REFr registers, and the REFr registers must NOT be
incremented with the REFI command at the end of this special set of
refresh transactions. This ensures that no matter what value has
been left in the REFB register, no row of any bank will be
skipped when automatic refresh is first started in Powerdown.
There may be some banks at the current row value in the REFr
registers that are refreshed twice during the Powerdown entry
process.
The first request packet may be issued after an interval of
tPDN-CMD has elapsed from the end of the SBW transaction,
and must contain a “REFA” command in a ROWP packet. In this
example, this packet is denoted with the command “REFA 1”.
No other request packets should be issued during this tPDNCMD interval.
All “n” banks (in the example, n=23) must be refreshed using
the current value of the REFr registers. The “nth” refresh
transaction will use a “REFI” command to increment the
REFr register (instead of a “REFR” command). This ensures
that no matter what value has been left in the REFB register,
no row of any bank will be skipped when normal refresh is
restarted in Active state. There may be some banks at the current row value in the REFr registers that are refreshed twice
during the Powerdown exit process.
After the last request packet (with the command CMDa in the
upper diagram of the figure), an interval of tCMD-PDN is
observed. No request packets should be issued during this
period.
A COLX packet with the PDN command is issued after this
interval, causing the XDR DRAM to enter Powerdown state
after an interval of tPDN-ENTRY has elapsed (this is the parameter that should be used for calculating the power dissipation of
the XDR DRAM). The CFM/CFMN clock signals may be
removed a time tPDN-CFM after the COLX packet with the
PDN command.
Note that during the Powerdown state an internal time source
keeps the device refreshed. However, during the tPDN-CMD
interval, no internal refresh operations are performed. As a
result, an additional burst of refresh transactions must be
issued after the burst of “n” transactions described above.
This second burst consists of “m” refresh transactions:
When the XDR DRAM is in Powerdown, an internal frequency source and state machine will automatically generate
internal refresh transactions. It will cycle through all 23 state
combinations of the REFB register. When the largest value is
reached and the REFB value wraps around, the REFr register
is incremented to the next value. The REFB and REFr values
select which bank and which row are refreshed during the next
automatic refresh transaction.
m = ceiling[23*212*tPDN-CMD/tREF]
Where “212” is the number of rows per bank, and “23” is the
number of banks. Every “nth” refresh transaction (where
n=23) will use a “REFI” command (to increment the REFr
register) instead of a “REFA” command.
The lower diagram shows the sequence needed for Powerdown
Data Sheet E1819E20 (Ver. 2.0)
44
EDX1032BBBG
Figure 36
Power State Management
CFM
CFMN
No signal
CMD
RQ11..0
tCYCLE
tPDN-CFM
PDN
ba
a
Powerdown State...
DQ31..0
DQN31..0
tPDN-ENTRY
tCMD-PDN
Transaction a: Last precharge command
Transaction b: PDN
S0
S2
S4
S6
S8
Powerdown Entry
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34
SCK
RST
CMD
tCYC,SCK
Power-up transaction
Start
2’h0,SID[5:0]
SCMD
‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
5
4
3
2 1
SADR[7:0]
0
7
6
5
4
3
2
SWD[7:0]
1 0 ‘0’ 7
6
5
4
3
2
1 0 ‘0’
SDI
(input)
SDO
(output)
CFM
CFMN
No signal
tCFM-PDN
RQ11..0
tCYCLE
tPDN-EXIT
....Powerdown State
DQ31..0
DQN31..0
tPDN-CMD
CFM
CFMN
RQ11..0
DQ31..0
DQN31..0
REFA
REFA
REFI
REFP
1
2
n
n-2
REFP
REFP
n-1
n
tCYCLE
tPDN-CMD
Transaction 1: REFA
Transaction 2: REFA
The final REFA/REFI command increments the REFr register
Transaction n-1: REFA
Transaction n: REFI
Powerdown Exit
Data Sheet E1819E20 (Ver. 2.0)
45
EDX1032BBBG
to VTERM. The SDO output of each XDR DRAM device is
transmitted to the SDI input of the next XDR DRAM device
(in the direction of the controller). This SDO/SDI daisy-chain
topology continues to the controller, where it ends at the SRD
input of the controller. All the serial interface signals are lowtrue. All the signals use RSL signaling circuits, except for the
SDO output which uses CMOS signaling circuits.
Initialization
Figure 37 shows the topology of the serial interface signals of a
XDR DRAM system. The three signals RST, CMD, and SCK
are transmitted by the controller and are received by each XDR
DRAM device along the bus. The signals are terminated to the
VTERM supply through termination components at the end
farthest from the controller. The SDI input of the XDR
DRAM device furthest from the controller is also terminated
Figure 37
Serial Interface System Topology
VTERM
RST CMD SCK
RST CMD SCK
SRD
SDO
Controller
RST CMD SCK
...
SDI
SDO
XDR DRAM
SDO
SDI
XDR DRAM
On negative SCK edge S8 the RST input is sampled one. It is
sampled one on the next four edges, and is sampled zero on
edge S12 a time tRST-10 after it was first sampled one. The state
of the control registers in the XDR DRAM device are set to
their reset values after the first edge (S8) in which RST is sampled one.
Initialization Timing for XDR DRAM[k] Device
Poweron
tCOREINIT
0
SCK
...
XDR DRAM
Figure 38 shows the initialization timing of the serial interface
for the XDR DRAM[k] device in the system shown above.
Prior to initialization, the RST is held at zero. The CMD input
is not used here, and should also be held at zero. Note that the
inputs are all sampled by the negative edge of the SCK clock
input. The SDI input for the XDR DRAM[0] device is zero,
and is unknown for the remaining devices.
Figure 38
SDI
RST CMD SCK
S0
S2
S4
S6
S8
S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S
tRST-SCK
1
0
RST
1
0
tCYC,SCK
tRST-10
‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDI,00 = k * tCYC,SCK
CMD
1
0
SDI
(input) 1
0
SDO
(output) 1
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
tRST-SDO,11
tSDI-SDO,00
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
The SDI inputs will be sampled one within a time tRST-SDO,11
after RST is first sampled one in all the XDR DRAMs except
for XDR DRAM[0]. XDR DRAM[0]’s SDI input will always
be sampled zero.
XDR DRAM[k] will see its RST input sampled zero at S12, and
will then see its SDI input sampled zero at S16 (after SDI had
Data Sheet E1819E20 (Ver. 2.0)
46
EDX1032BBBG
previously been sampled one). This interval (measured in
tCYC,SCK units) will be equal to the index [k] of the XDR
DRAM device along the serial interface bus. In this example, k
is equal to 4.
SDO to zero around the subsequent edge (S14).
The XDR DRAM[2] device will see SDI sampled zero on edge
S14 (tRST-SDI,00 will be 2*tCYC,SCK units), and will drive its
SDO to zero around the subsequent edge (S15).
This is because each XDR DRAM device will drive its SDO
output zero around the SCK edge a time tSDI-SDO,00 after its
SDI input is sampled zero.
This continues until the last XDR DRAM device drives the
SRD input of the controller. Each XDR DRAM device contains a state machine which measures the interval tRST-SDI,00
between the edges in which RST and SDI are both sampled
zero, and uses this value to set the SID[5:0] field of the SID
(Serial Identification) register. This value allows directed read
and write transactions to be made to the individual XDR
DRAM devices. Table 9 summarizes the range of the timing
parameters used for initialization by the serial interface bus.
In other words, the XDR DRAM[0] device will see RST and
SDI both sampled zero on the same edge S12 (tRST-SDI,00 will
be 0*tCYC,SCK units), and will drive its SDO to zero around the
subsequent edge (S13).
The XDR DRAM[1] device will see SDI sampled zero on edge
S13 (tRST-SDI,00 will be 1*tCYC,SCK units), and will drive its
Table 9 Initialization
Symbol
Timing Parameters
Parameter
Minimum
Maximum
Units
Figure(s)
tRST,10
Number of cycles between RST being sampled one and RST being
sampled zero.
2
-
tCYC,SCK
-
tRST-SDO,11
Number of cycles between RST being sampled one and SDO being
driven to one.
1
1
tCYC,SCK
-
tRST-SDI,00
Number of cycles between RST being sampled zero (after being sampled one for tRST,10,MIN or more cycles) and SDI being sampled zero.
This will be equal to the index [k] of the XDR DRAM device along
the serial interface bus.
0
63
tCYC,SCK
-
tSDI-SDO,00
Number of cycles between SDI being sampled one (after RST has
been sampled one for tRST,10,MIN or more cycles and is then sampled
zero) and SDO being driven to one.
1
1
tCYC,SCK
-
tRST-SCK
The number of SCK falling edges after the first SCK falling edge in
which RST is sampled one.
20
-
tCYC,SCK
-
[6] Perform termination/current calibration. The CALZ/
CALE sequence shown in Figure 35 is issued 128 times, then
the CALC/CALE sequence is issued 128 times. After this, each
sequence is issued once every tCALZ or tCALC interval.
XDR DRAM Initialization Overview
[1] Apply voltage toVDD, VTERM, and VREF pins. VTERM
and VREF voltages must be less or equal to VDD voltage at all
times. Wait a time interval tCOREINIT. Power-on reset circuit in
XDR DRAM places XDR DRAM into low-power state.
[7] Condition the XDR DRAM banks by performing a REFA/
REFI activate and REFP precharge operation to each bank
eight times. This can be interleaved to save time. The row
address for the activate operation will step through eight successive values of the REFr registers. The sequence between
cycles T0 and T32 in the Interleaved Refresh Example in
Figure 34 could be performed eight times to satisfy this conditioning requirement.
[2] Assert RST, SCK, SDI, and CMD to logical zero. Then:
- Pulse SCK to logical one, then to logical zero four times.
- Assert RST to logical one. Reset circuit places XDR
DRAM into low-power state (identical to power-on reset).
- Perform remaining initialization sequence in Figure 38.
[3] XDR DRAM has valid Serial ID and all registers have
default values that are defined in Figure 16 through Figure 33.
[4] Perform broadcast or directed register writes to adjust registers which need a value different from their default value.
[5] Perform Powerdown Exit sequence shown in Figure 36.
This includes the activity from SCK cycle S0 through the final
REFP command.
Data Sheet E1819E20 (Ver. 2.0)
47
EDX1032BBBG
XDR DRAM Pattern Load with WDSL Reg
The XDR memory system requires a method of deterministically loading pattern data to XDR DRAMs before beginning
Receive Timing Calibration (RX TCAL). The method
employed by the XDR DRAMs to achieve this is called Write
Data Serial Load (WDSL). A WDSL packet sends one-byte of
serial data which is serially shifted into a holding register within
the XDR DRAM. Initialization software sends a sequence of
WDSL packets, each of which shifts the new byte in and
advances the shifter by 8 positions. In this way, XDR DRAMs
of varying widths can be loaded with a single command type.
Each sequence of WDSL packets will load one full column of
data to the internal holding register of the target XDR DRAM.
Depending upon the ratio of native device width to programmed width, there may be more than one sub-column per
column. After loading a full column, a series of WR commands will be issued to sequentially transfer each sub-column
of the column to the XDR DRAM core(s), based upon the
SC[4:0] bits..
Data Sheet E1819E20 (Ver. 2.0)
48
EDX1032BBBG
Table 10 Logical
View of XDR DRAM WDSL-to-Core/DQ/SC Map (x32/x16/x8, BL=16)
DQ Pins Used
Core Word
x8
x16
x32
WDSL Core Word
Load Order
x32
WD[n][15:0]
SC[4:0]
= xxxxx
Logical View of XDR DRAM
x16
SC[4:0]
= 0xxxx
x8
SC[4:0]
=1xxxx
SC[4:0]
= 00xxx
SC[4:0]
= 01xxx
SC[4:0]
= 10xxx
SC[4:0]
= 11xxx
Word Written (1 = Written, 0 = Not Written)
DQ0
DQ0
DQ0
WD[0][15:0]
WDSL Word 16
1
1
0
1
0
0
0
DQ1
DQ1
DQ1
WD[1][15:0]
WDSL Word 15
1
1
0
1
0
0
0
DQ2
DQ2
DQ2
WD[2][15:0]
WDSL Word 24
1
1
0
1
0
0
0
DQ3
DQ3
DQ3
WD[3][15:0]
WDSL Word 7
1
1
0
1
0
0
0
DQ4
DQ4
DQ4
WD[4][15:0]
WDSL Word 20
1
1
0
1
0
0
0
DQ5
DQ5
DQ5
WD[5][15:0]
WDSL Word 11
1
1
0
1
0
0
0
DQ6
DQ6
DQ6
WD[6][15:0]
WDSL Word 28
1
1
0
1
0
0
0
DQ7
DQ7
DQ7
WD[7][15:0]
WDSL Word 3
1
1
0
1
0
0
0
DQ0
DQ8
DQ8
WD[8][15:0]
WDSL Word 18
1
1
0
0
1
0
0
DQ1
DQ9
DQ9
WD[9][15:0]
WDSL Word 13
1
1
0
0
1
0
0
DQ2
DQ10
DQ10
WD[10][15:0]
WDSL Word 26
1
1
0
0
1
0
0
DQ3
DQ11
DQ11
WD[11][15:0]
WDSL Word 5
1
1
0
0
1
0
0
DQ4
DQ12
DQ12
WD[12][15:0]
WDSL Word 22
1
1
0
0
1
0
0
DQ5
DQ13
DQ13
WD[13][15:0]
WDSL Word 9
1
1
0
0
1
0
0
DQ6
DQ14
DQ14
WD[14][15:0]
WDSL Word 30
1
1
0
0
1
0
0
DQ7
DQ15
DQ15
WD[15][15:0]
WDSL Word 1
1
1
0
0
1
0
0
DQ0
DQ0
DQ16
WD[16][15:0]
WDSL Word 17
1
0
1
0
0
1
0
DQ1
DQ1
DQ17
WD[17][15:0]
WDSL Word 14
1
0
1
0
0
1
0
DQ2
DQ2
DQ18
WD[18][15:0]
WDSL Word 25
1
0
1
0
0
1
0
DQ3
DQ3
DQ19
WD[19][15:0]
WDSL Word 6
1
0
1
0
0
1
0
DQ4
DQ4
DQ20
WD[20][15:0]
WDSL Word 21
1
0
1
0
0
1
0
DQ5
DQ5
DQ21
WD[21][15:0]
WDSL Word 10
1
0
1
0
0
1
0
DQ6
DQ6
DQ22
WD[22][15:0]
WDSL Word 29
1
0
1
0
0
1
0
DQ7
DQ7
DQ23
WD[23][15:0]
WDSL Word 2
1
0
1
0
0
1
0
DQ0
DQ8
DQ24
WD[24][15:0]
WDSL Word 19
1
0
1
0
0
0
1
DQ1
DQ9
DQ25
WD[25][15:0]
WDSL Word 12
1
0
1
0
0
0
1
DQ2
DQ10
DQ26
WD[26][15:0]
WDSL Word 27
1
0
1
0
0
0
1
DQ3
DQ11
DQ27
WD[27][15:0]
WDSL Word 4
1
0
1
0
0
0
1
DQ4
DQ12
DQ28
WD[28][15:0]
WDSL Word 23
1
0
1
0
0
0
1
DQ5
DQ13
DQ29
WD[29][15:0]
WDSL Word 8
1
0
1
0
0
0
1
DQ6
DQ14
DQ30
WD[30][15:0]
WDSL Word 31
1
0
1
0
0
0
1
DQ7
DQ15
DQ31
WD[31][15:0]
WDSL Word 0
1
0
1
0
0
0
1
Data Sheet E1819E20 (Ver. 2.0)
49
EDX1032BBBG
Table 11 Logical
DQ Pins
Used
Core Word
x4
View of XDR DRAM WDSL-to-Core/DQ/SC Map (x4, BL=16)
WDSL Core Word
Load Order
WD[n][15:0]
x4
SC[4:0]
= 000xx
SC[4:0]
= 001xx
Logical View of XDR DRAM
SC[4:0]
= 010xx
SC[4:0]
= 011xx
SC[4:0]
= 100xx
SC[4:0]
= 101xx
SC[4:0]
= 110xx
SC[4:0]
= 111xx
Word Written (1 = Written, 0 = Not Written)
DQ0
WD[0][15:0]
WDSL Word 16
1
0
0
0
0
0
0
0
DQ1
WD[1][15:0]
WDSL Word 15
1
0
0
0
0
0
0
0
DQ2
WD[2][15:0]
WDSL Word 24
1
0
0
0
0
0
0
0
DQ3
WD[3][15:0]
WDSL Word 7
1
0
0
0
0
0
0
0
DQ0
WD[4][15:0]
WDSL Word 20
0
1
0
0
0
0
0
0
DQ1
WD[5][15:0]
WDSL Word 11
0
1
0
0
0
0
0
0
DQ2
WD[6][15:0]
WDSL Word 28
0
1
0
0
0
0
0
0
DQ3
WD[7][15:0]
WDSL Word 3
0
1
0
0
0
0
0
0
DQ0
WD[8][15:0]
WDSL Word 18
0
0
1
0
0
0
0
0
DQ1
WD[9][15:0]
WDSL Word 13
0
0
1
0
0
0
0
0
DQ2
WD[10][15:0]
WDSL Word 26
0
0
1
0
0
0
0
0
DQ3
WD[11][15:0]
WDSL Word 5
0
0
1
0
0
0
0
0
DQ0
WD[12][15:0]
WDSL Word 22
0
0
0
1
0
0
1
0
DQ1
WD[13][15:0]
WDSL Word 9
0
0
0
1
0
0
1
0
DQ2
WD[14][15:0]
WDSL Word 30
0
0
0
1
0
0
0
0
DQ3
WD[15][15:0]
WDSL Word 1
0
0
0
1
0
0
0
0
DQ0
WD[16][15:0]
WDSL Word 17
0
0
0
0
1
0
0
0
DQ1
WD[17][15:0]
WDSL Word 14
0
0
0
0
1
0
0
0
DQ2
WD[18][15:0]
WDSL Word 25
0
0
0
0
1
0
0
0
DQ3
WD[19][15:0]
WDSL Word 6
0
0
0
0
1
0
0
0
DQ0
WD[20][15:0]
WDSL Word 21
0
0
0
0
0
1
1
0
DQ1
WD[21][15:0]
WDSL Word 10
0
0
0
0
0
1
0
0
DQ2
WD[22][15:0]
WDSL Word 29
0
0
0
0
0
1
0
0
DQ3
WD[23][15:0]
WDSL Word 2
0
0
0
0
0
1
0
0
DQ0
WD[24][15:0]
WDSL Word 19
0
0
0
0
0
0
1
0
DQ1
WD[25][15:0]
WDSL Word 12
0
0
0
0
0
0
1
0
DQ2
WD[26][15:0]
WDSL Word 27
0
0
0
0
0
0
1
0
DQ3
WD[27][15:0]
WDSL Word 4
0
0
0
0
0
0
1
0
DQ0
WD[28][15:0]
WDSL Word 23
0
0
0
0
0
0
0
1
DQ1
WD[29][15:0]
WDSL Word 8
0
0
0
0
0
0
0
1
DQ2
WD[30][15:0]
WDSL Word 31
0
0
0
0
0
0
0
1
DQ3
WD[31][15:0]
WDSL Word 0
0
0
0
0
0
0
0
1
Data Sheet E1819E20 (Ver. 2.0)
50
EDX1032BBBG
Table 12 Physical
View of XDR DRAM WDSL-to-Core/DQ/SC Map (x32/x16/x8, BL=16)
DQ Pins Used
Core Word
x8
x16
WDSL Core Word
Load Order
x32
WD[n][15:0]
SC[4:0]
= xxxxx
x32
Physical View of XDR DRAM
DQ14
DQ6
DQ6
DQ10
DQ2
DQ2
DQ12
DQ4
DQ4
DQ8
DQ0
DQ0
DQ1
DQ1
DQ9
DQ5
DQ5
DQ13
DQ3
DQ3
DQ11
DQ7
DQ7
DQ15
x16
SC[4:0]
= 0xxxx
x8
SC[4:0]
= 1xxxx
SC[4:0]
= 00xxx
SC[4:0]
= 01xxx
SC[4:0]
= 10xxx
SC[4:0]
= 11xxx
Word Written (1 = Written, 0 = Not Written)
DQ30
WD[31][15:0]
WDSL Word 31
1
0
1
0
0
0
1
DQ14
WD[30][15:0]
WDSL Word 30
1
1
0
0
1
0
0
DQ22
WD[29][15:0]
WDSL Word 29
1
0
1
0
0
1
0
DQ6
WD[28][15:0]
WDSL Word 28
1
1
0
1
0
0
0
DQ26
WD[27][15:0]
WDSL Word 27
1
0
1
0
0
0
1
DQ10
WD[26][15:0]
WDSL Word 26
1
1
0
0
1
0
0
DQ18
WD[25][15:0]
WDSL Word 25
1
0
1
0
0
1
0
DQ2
WD[24][15:0]
WDSL Word 24
1
1
0
1
0
0
0
DQ28
WD[23][15:0]
WDSL Word 23
1
0
1
0
0
0
1
DQ12
WD[22][15:0]
WDSL Word 22
1
1
0
0
1
0
0
DQ20
WD[21][15:0]
WDSL Word 21
1
0
1
0
0
1
0
DQ4
WD[20][15:0]
WDSL Word 20
1
1
0
1
0
0
0
DQ24
WD[19][15:0]
WDSL Word 19
1
0
1
0
0
0
1
DQ8
WD[18][15:0]
WDSL Word 18
1
1
0
0
1
0
0
DQ16
WD[17][15:0]
WDSL Word 17
1
0
1
0
0
1
0
DQ0
WD[16][15:0]
WDSL Word 16
1
1
0
1
0
0
0
DQ1
WD[15][15:0]
WDSL Word 15
1
1
0
1
0
0
0
DQ17
WD[14][15:0]
WDSL Word 14
1
0
1
0
0
1
DQ9
WD[13][15:0]
WDSL Word 13
1
1
0
0
1
0
0
DQ25
WD[12][15:0]
WDSL Word 12
1
0
1
0
0
0
1
DQ5
WD[11][15:0]
WDSL Word 11
1
1
0
1
0
0
0
DQ21
WD[10][15:0]
WDSL Word 10
1
0
1
0
0
1
0
DQ13
WD[9][15:0]
WDSL Word 9
1
1
0
0
1
0
0
DQ29
WD[8][15:0]
WDSL Word 8
1
0
1
0
0
0
1
DQ3
WD[7][15:0]
WDSL Word 7
1
1
0
1
0
0
0
DQ19
WD[6][15:0]
WDSL Word 6
1
0
1
0
0
1
0
DQ11
WD[5][15:0]
WDSL Word 5
1
1
0
0
1
0
0
DQ27
WD[4][15:0]
WDSL Word 4
1
0
1
0
0
0
1
DQ7
WD[3][15:0]
WDSL Word 3
1
1
0
1
0
0
0
DQ23
WD[2][15:0]
WDSL Word 2
1
0
1
0
0
1
0
DQ15
WD[1][15:0]
WDSL Word 1
1
1
0
0
1
0
0
DQ31
WD[0][15:0]
WDSL Word 0
1
0
1
0
0
0
1
Data Sheet E1819E20 (Ver. 2.0)
51
EDX1032BBBG
Table 13 Physical
DQ Pins
Used
Core Word
x4
View of XDR DRAM WDSL-to-Core/DQ/SC Map (x4, BL=16)
WDSL Core Word Load
Order
WD[n][15:0]
x4
SC[4:0]
= 000xx
SC[4:0]
= 001xx
Physical View of XDR DRAM
DQ2
DQ0
DQ1
DQ3
SC[4:0]
= 010xx
SC[4:0]
= 011xx
SC[4:0]
= 100xx
SC[4:0]
= 101xx
SC[4:0]
= 110xx
SC[4:0]
= 111xx
Word Written (1 = Written, 0 = Not Written)
WD[30][15:0]
WDSL Word 31
0
0
0
0
0
0
0
1
WD[14][15:0]
WDSL Word 30
0
0
0
1
0
0
0
0
WD[22][15:0]
WDSL Word 29
0
0
0
0
0
1
0
0
WD[6][15:0]
WDSL Word 28
0
1
0
0
0
0
0
0
WD[26][15:0]
WDSL Word 27
0
0
0
0
0
0
1
0
WD[10][15:0]
WDSL Word 26
0
0
1
0
0
0
0
0
WD[18][15:0]
WDSL Word 25
0
0
0
0
1
0
0
0
WD[2][15:0]
WDSL Word 24
1
0
0
0
0
0
0
0
WD[28][15:0]
WDSL Word 23
0
0
0
0
0
0
0
1
WD[12][15:0]
WDSL Word 22
0
0
0
1
0
0
0
0
WD[20][15:0]
WDSL Word 21
0
0
0
0
0
1
0
0
WD[4][15:0]
WDSL Word 20
0
1
0
0
0
0
0
0
WD[24][15:0]
WDSL Word 19
0
0
0
0
0
0
1
0
WD[8][15:0]
WDSL Word 18
0
0
1
0
0
0
0
0
WD[16][15:0]
WDSL Word 17
0
0
0
0
1
0
0
0
WD[0][15:0]
WDSL Word 16
1
0
0
0
0
0
0
0
WD[1][15:0]
WDSL Word 15
1
0
0
0
0
0
0
0
WD[17][15:0]
WDSL Word 14
0
0
0
0
1
0
0
0
WD[9][15:0]
WDSL Word 13
0
0
1
0
0
0
0
0
WD[25][15:0]
WDSL Word 12
0
0
0
0
0
0
1
0
WD[5][15:0]
WDSL Word 11
0
1
0
0
0
0
0
0
WD[21][15:0]
WDSL Word 10
0
0
0
0
0
1
0
0
WD[13][15:0]
WDSL Word 9
0
0
0
1
0
0
0
0
WD[29][15:0]
WDSL Word 8
0
0
0
0
0
0
0
1
WD[3][15:0]
WDSL Word 7
1
0
0
0
0
0
0
0
WD[19][15:0]
WDSL Word 6
0
0
0
0
1
0
0
0
WD[11][15:0]
WDSL Word 5
0
0
1
0
0
0
0
0
WD[27][15:0]
WDSL Word 4
0
0
0
0
0
0
1
0
WD[7][15:0]
WDSL Word 3
0
1
0
0
0
0
0
0
WD[23][15:0]
WDSL Word 2
0
0
0
0
0
1
0
0
WD[15][15:0]
WDSL Word 1
0
0
0
1
0
0
0
0
WD[31][15:0]
WDSL Word 0
0
0
0
0
0
0
0
1
Data Sheet E1819E20 (Ver. 2.0)
52
EDX1032BBBG
.
Table 14 Core
Data Word-to-WDSL Format
DQ Serialization Order
CFM/PCLK Cycle
Cycle 0
Cycle 1
Symbol (Bit) Time
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Bit Transmitted on DQ pins
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
WDSL Byte/Bit Transfer Order
Core Word
Core Word WD[n][15:0]
WDSL Byte Order
SWD Field of Serial Packet
Bit Transmitted on CMD pin
WDSL Byte 0
WDSL Byte 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D15
D11
D7
D3
D14
D10
D6
D2
D13
D9
D5
D1
D12
D8
D4
D0
Data Sheet E1819E20 (Ver. 2.0)
53
EDX1032BBBG
Figure 40, it may be seen that in the SC[4:0] field, the SC[2:0]
sub-column address bits are not used. The remaining SC[4:3]
address bit(s) selects one of the 128-bit blocks of S bus signals,
causing them to be driven onto the Q[7:0][15:0] read data bus,
which in turn is driven to the DQ7..0/DQN7..0 data pins. The
Q[31:8][15:0] signals and DQ31..8/DQN31..8 data pins are
not used for a device width of x8.
Special Feature Description
Dynamic Width Control
This XDR DRAM device includes a feature called dynamic
width control. This permits the device to be configured so that
read and write data can be accessed through differing widths of
DQ pins. Figure 39 shows a diagram of the logic in the path of
the read data (Q) and write data (D) that accomplishes this.
The write path is shown on the left side of Figure 39. As
before, there are 32 sets of S signals (the internal data bus connecting to the sense amps of the memory core), with 16 signals
in each set. When the XDR DRAM device is configured for
maximum width operation (using the WIDTH[2:0] field in the
CFG register), each set of 32 S signals is driven from one of the
32 DQ pins (via the D[31:0][15:0] write bus) from each of the
16 time slots for a write data packet.
The read path is on the right of the figure. There are 32 sets of
S signals (the internal data bus connecting to the sense amps of
the memory core), with 16 signals in each set. When the XDR
DRAM device is configured for maximum width operation
(using the WIDTH[2:0] field in the CFG register), each set of
32 S signals goes to one of the 32 DQ pins (via the
Q[31:0][15:0] read bus) and are driven out in the 16 time slots
for a read data packet.
Figure 40 also shows the mapping from the D bus to the S bus
as a function of the WIDTH[2:0] register field and the SC[4:0]
field of the COL request packet. There is a separate table for
each valid value of WIDTH[2:0]. In each table, there is an entry
in the left column for each valid value of SC[4:0]. This field
should be treated as an extension of the C[10:5] column
address field. The right hand column shows which set of
S[31:0][15:0] signals are mapped from the D write data bus for
a particular value of SC[4:0].
When the XDR DRAM device is configured for a width that is
less than the maximum, some of the DQ pins are used and the
rest are not used. The SC[4:0] field of the COL request packets
select which S[31:0][15:0] signals are passed to the
Q[31:0][15:0] read bus and driven as read data.
Figure 40 shows the mapping from the S bus to the Q bus as a
function of the WIDTH[2:0] register field and the SC[4:0] field
of the COL request packet. There is a separate table for each
valid value of WIDTH[2:0]. In each table, there is an entry in
the left column for each valid value of SC[4:0]. This field
should be treated as an extension of the C[10:5] column
address field. The right hand column shows which set of
S[31:0][15:0] signals are mapped to the Q read data bus for a
particular value of SC[4:0].
For example, assume that the WIDTH[2:0] value is “010”, indicating a device width of x4. Looking at the appropriate table in
Figure 40, it may be seen that in the SC[4:0] field, the SC[1:0]
sub-column address bits are not used. The remaining SC[4:2]
address bit(s) selects one of the 64-bit blocks of S bus signals,
causing them to be driven from the D[3:0][15:0] write data bus,
which in turn is driven from the DQ3..0/DQN3..0 data pins.
The D[31:4][15:0] signals and DQ31..4/DQN31..4 data pins
are not used for a device width of x4.
For example, assume that the WIDTH[2:0] value is “011”, indicating a device width of x8. Looking at the appropriate table in
Figure 39
Multiplexers for Dynamic Width Control
S[31:0][15:0]
32x16
32x16
8
M[7:0]
5+3
WIDTH[2:0]
SC[4:0]
Byte Mask (WR)
32x16
D1[31:0][15:0]
Dynamic Width Demux (WR)
5+3
Dynamic Width Mux (RD)
32x16
32x16
D[31:0][15:0]
Q[31:0][15:0]
Data Sheet E1819E20 (Ver. 2.0)
54
WIDTH[2:0]
SC[4:0]
EDX1032BBBG
The block diagram in Figure 39 indicates that the Dynamic
Width logic is positioned after the serial-to-parallel conversion
(demux block) in the data receiver block and before the parallel-to-serial conversion (mux block) in the data transmitter
block (see also the block diagram in Figure 1). The block diagram is shown in this manner so the functionality of the logic
can be made as clear as possible. Some implementations may
Figure 40
place this logic in the data receiver and transmitter blocks, performing the mapping in Figure 40 on the serial data rather than
the parallel data. However, this design choice will not affect the
functionality of the Dynamic Width logic; it is strictly an implementation decision.
D-to-S and S-to-Q Mapping for Dynamic Width Control
WIDTH[2:0]=100
(x16 device width)
WIDTH[2:0]=010
(x4 device
width)
WIDTH[2:0]=001
(x2 device
width)
WIDTH[2:0]=000 (x1 device
width)
000
S[0][15:0]
000xx
S[3:0][15:0]
00x
S[4,0][15:0]
001
S[1][15:0]
001xx
S[7:4][15:0]
01x
S[5,1][15:0]
010
S[2][15:0]
010xx
S[11:8][15:0]
10x
S[6,2][15:0]
011
S[3][15:0]
011xx
S[15:12][15:0]
11x
S[7,3][15:0]
100
S[4][15:0]
100xx
S[19:16][15:0]
SC[2:0]
D[1:0][15:0]
Q[1:0][15:0]
101
S[5][15:0]
101xx
S[23:20][15:0]
110
S[6][15:0]
110xx
S[27:24][15:0]
0xxxx
S[15:0][15:0]
111
S[7][15:0]
111xx
S[31:28][15:0]
1xxxx
S[31:16][15:0]
SC[2:0]
D[0][15:0]
SC[4:0]
Q[0][15:0]
D[3:0][15:0]
Q[3:0][15:0]
SC[4:0]
D[15:0][15:0]
Q[15:0][15:0]
WIDTH[2:0]=010 (x4 device width)
WIDTH[2:0]=011 (x8 device width)
WIDTH[2:0]=011 (x8 device width)
WIDTH[2:0]=101 (x32 device width)
0xx
1xx
SC[2:0]
S[6,2,4,0][15:0]
00xxx
S[7,3,5,1][15:0]
01xxx
S[7:0][15:0]
SC[2:0]
S[15:8][15:0]
D[3:0][15:0]
10xxx
Q[3:0][15:0]
S[23:16][15:0]
11xxx
S[31:24][15:0]
xxxxx
S[31:0][15:0]
SC[4:0]
D[7:0][15:0]
Q[7:0][15:0]
SC[4:0]
D[31:0][15:0]
Q[31:0][15:0]
xxx
S[7:0][15:0]
D[7:0][15:0]
Q[7:0][15:0]
A8
Data Sheet E1819E20 (Ver. 2.0)
55
EDX1032BBBG
D1[0][7:0]
Write Masking
The eight bits of each byte is compared to the value in the byte
mask field (M[7:0]). If they are not equal (NE), then the corresponding write enable signal (WE) is asserted and the byte is
written into the sense amplifier. If they are equal, then the corresponding write enable signal (WE) is deasserted and the byte
is not written into the sense amplifier.
Figure 41 shows the logic used by the XDR DRAM device
when a write-masked command (WRM) is specified in a
COLM packet. This masking logic permits individual bytes of a
write data packet to be written or not written according to the
value of an eight bit write mask M[7:0].
In Figure 41, there are 32 sets of 16 bit signals forming the
D1[31:0][15:0] input bus for the Byte Mask block. These are
treated as 2x32 8-bit bytes:
D1[31][15:8]
D1[31][7:0]
...
D1[1][15:8]
D1[1][7:0]
D1[0][15:8]
Figure 41
In the example illustrated in Figure 41, a WRM command
performs a masked write of a 64-byte data packet to a single
memory device connected to the RQ bus (and receiving the
command). It is the job of the memory controller to search the
64 bytes to find an eight bit data value that is not used and
place it into the M[7:0] field. This will always be possible
because there are 256 possible 8-bit values and there are only
64 possible values used in the bytes in the data packet.
Byte Mask Logic
S[31][15:8]
S[31][7:0]
8
WE-MSB
[31]
1
NE
8
Compare
8
8
8
8
Compare
8
8
8
D1[31][15:8]
S[0][7:0]
8
WE-MSB
[0]
1
NE
8
8
Compare
8
8
8
D1[31][7:0]
D1[31][15:8]
M[7:0]
S[0][15:8]
WE-LSB
[31]
1
NE
D1[0][15:8]
8
8
D1[31][7:0]
D1[0][15:8]
WE-LSB
[0]
1
NE
Compare
8
8
D1[0][7:0]
8
D1[0][7:0]
S[31:0][15:0]
32x16
32x16
8
M[7:0]
5+3
WIDTH[2:0]
SC[4:0]
Byte Mask (WR)
32x16
D1[31:0][15:0]
Dynamic Width Demux (WR)
32x16
5+3
Dynamic Width Mux (RD)
WIDTH[2:0]
SC[4:0]
32x16
D[31:0][15:0]
Q[31:0][15:0]
Figure 42 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of two
successive WR commands in COL packets. The one difference
Note that other systems might use a data transfer size that is
different than the 64 bytes per tCC interval per RQ bus that is
used in the example in Figure 41.
Data Sheet E1819E20 (Ver. 2.0)
56
EDX1032BBBG
is that the COLM packet includes a M[7:0] field that indicates
the reserved bit pattern (for the eight bits of each byte) that
indicates that the byte is not to be written. This requires that
the alignment of bytes within the data packet be defined, and
also that the bit numbering within each byte be defined (note
that this was not necessary for the unmasked WR command).
Figure 42
In the figure, bytes are contained within a single DQ/DQN
pin pair — this is necessary so the dynamic width feature can be
supported. Thus, each pin pair carries two bytes of each data
packet. Byte[0] is transferred earlier than byte[16+0], and bit
[0] of each byte (corresponding to M[0]) is transferred first, followed by the remaining bits in succession.
Write-Masked (WRM) Transaction Example
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WRM
a1
DQ31..0
DQN31..0
WRM
a2
tCYCLE
RD
a1
tCC
tCWD
D(a1)
D(a2)
tCAC
Q(a1)
Bit- and Byte-numbering convention for write
and read data packets.
Byte [32+0]
Byte [0]
DQ0
DQN0
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Byte [1]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Byte [31]
DQ31
DQN31
[10] [11] [12] [13] [14] [15]
...
[0]
Byte [32+1]
...
DQ1
DQN1
[10] [11] [12] [13] [14] [15]
[0]
[1]
[2]
[3]
[4]
Byte [32+31]
[5]
[6]
[7]
[8]
Data Sheet E1819E20 (Ver. 2.0)
57
[9]
[10] [11] [12] [13] [14] [15]
EDX1032BBBG
Multiple Bank Sets and the ERAW Feature
operation to be reduced, thereby improving performance.
ERAW feature supported for Bin C only.
Figure 43 shows the timing previously presented in Figure 11,
but with the activity on the internal S data bus included. The
write-to-read parameter tΔWR ensures that there is adequate
turnaround time on the S bus between D(a2) and Q(c1).
Figure 45 shows a block diagram of a XDR DRAM in which
the banks are divided into two sets (called the even bank set
and the odd bank set) according to the least-significant bit of
the bank address field. This XDR DRAM supports a feature
called “Early Read After Write” (hereafter called “ERAW”).
When ERAW is supported with odd and even bank sets, the
tΔWR,MIN parameter must be obeyed when the write and read
column operations are to the same bank set, but a second
parameter tΔWR-D permits earlier column operations to the
opposite bank set. Figure 44 shows how this is possible
because there are two internal data buses S0 and S1. In this
example, the four column read operations are made to the
same bank Bb, but they could use different banks as long as
they all belonged to the bank set that was different from the
bank set containing Ba (for the column write operations).
The logic that accepts commands on the RQ11..0 signals is
capable of operating these two bank sets independently. In
addition, each bank set connects to its own internal “S” data
bus (called S0 and S1). The receive interface is able to drive
write data onto either of these internal data buses, and the
transmit interface is able to sample read data from either of
these internal data buses. These capabilities will permit the
delay between a write column operation and a read column
Figure 43
Write/Read Interaction — No ERAW Feature
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
WR
a1
WR
a2
RD
c1
tΔWR
DQ31..0
DQN31..0
D(a1)
D(a2)
tCWD
tCYCLE
tCAC
Q(c1)
tWR-BUB,XDRDRAM
Q(c2)
tCC
turnaround
tCC
S[31:0]
[15:0]
D(a1)
D(a2)
Q(c1)
a1 = {Ba,Ca1}
c1 = {Bc,Cc1}
Transaction a: WR
Transaction c: RD
Figure 44
RD
c2
Q(c2)
a2 = {Ba,Ca2}
c2 = {Bc,Cc2}
Write/Read Interaction — ERAW Feature
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ31..0
DQN31..0
WR
a1
RD
b1
WR
a2
tΔWR-D
D(a1)
tCWD
tCAC
RD
b2
RD
b3
D(a2)
Q(b2)
D(a1)
Q(b1)
Transaction a: WR
Transaction b: RD
Transaction c: RD
Q(b3)
Q(b4)
D(a2)
Q(b2)
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
Data Sheet E1819E20 (Ver. 2.0)
58
Q(c1)
tCC
turnaround
tCC tWR-BUB,XDRDRAM
S1[31:0]
[15:0]
tCYCLE
RD
c1
Q(b1)
S0[31:0]
[15:0]
Bank Restrictions
Bb is in different bank set than Ba
Bc is in same bank set as Ba
RD
b4
Q(c1)
Q(b3)
Q(b4)
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
b3 = {Bb,Cb3}
b4 = {Bb,Cb4}
EDX1032BBBG
Figure 45
XDR DRAM Block Diagram with Bank Sets
RQ11..0
12
1:2 Demux
Reg
COL
decode
6
3
...
1
...
6
6
...
COL
6
6
32x16
Bank (2 -2)
32x16*26
6
R/W
COL
COL
...
WR even
32x16*26
R/W
32x16
...
...
WR odd
Sense Amp Array
Sense Amp 0
3
Sense Amp (2 -2)
32x16
S0[31:0][15:0]
RD odd
RD even
32x16
32x16
Byte Mask (WR)
Dynamic Width Demux (WR)
32x16
Dynamic Width Mux (RD)
Q[31:0][15:0]
D[31:0][15:0]
32x16
16
1:16 Demux
16:1 Mux
16/tCC
......
32
32
32
DQ31..0
32
DQN31..0
Data Sheet E1819E20 (Ver. 2.0)
59
...
16
16/tCC
...
...
1
...
COL logic
3
...
32x16
S1[31:0][15:0]
1
...
COL
1
R/W
Bank 0
PRE
...
1
ROW
PRE
32x16*2
...
Sense Amp(23-1)
6
R/W
ROW
1
32x16*2
Sense Amp Array
Sense Amp 1
PRE logic
1
...
32x16*26
ACT
1
...
Bank(2 -1)
12
12
1
PRE
ACT
1
12
ROW
12
PRE
3
ACT logic
...
1
ACT
ROW
Even
Bank
Array
Bank 0
32x16*26*212
1
...
ACT
32x16*26
3
...
32x16*26*212
Bank 1
ACT
decode
3
12
...
Odd
Bank
Array
Bank 0
PRE
decode
EDX1032BBBG
tion command to one bank set may be inserted between two
activation commands to a different bank set.
Simultaneous Activation
When the XDR DRAM supports multiple bank sets as in
Figure 45, another feature may be supported, in addition to
ERAW. This feature is simultaneous activation, and the timing
of several cases is shown in Figure 46.
Case 1 shows an example when tRR must be at least 4*tCYCLE
and tRR-D must be at least 1*tCYCLE. As in the previous case,
an activation command to one bank set may be inserted
between two activation commands to a different bank set. In
this case, the middle activation command does not have to be
symmetrically placed relative to the two other activation commands.
The tRR parameter specifies the minimum spacing between
packets with activation commands in XDR DRAMs with a single bank set, or between packets to the same bank set in a XDR
DRAM with multiple bank sets. The tRR-D parameter specifies
the minimum spacing between packets with activation commands to different bank sets in a XDR DRAM with multiple
bank sets.
Case 0 shows an example when tRR must be at least 4*tCYCLE
and tRR-D must be at least 0*tCYCLE. This means that two activation commands may be issued on the same CFM clock edge.
This is only possible by using the delay mechanism in one of
the two commands. See “Dynamic Request Scheduling” on
page 20. In the example shown, the packet with the REFA
command is received one cycle before the command with the
ACT command, and the REFA command includes a one cycle
delay. Both activation commands will be issued internally to
different bank sets on the same CFM clock edge.
Case 4 shows an example when both tRR and tRR-D must be at
least 4*tCYCLE. In such a case, activation commands to different bank sets satisfy the same constraint as activation commands to the same bank set.
Case 2 shows an example when tRR must be at least 4*tCYCLE
and tRR-D must be at least 2*tCYCLE. In such a case, an activaFigure 46
Simultaneous Activation — tRR-D Cases
Case 4: tRR-D = 4*tCYCLE
REFA & ACT have same tRR
T0
T1
T2
T3
T4
T5
T6
T7
T8
Case 2: tRR-D = 2*tCYCLE
REFA fits between two ACT
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT
REFA
ACT
ACT
tRR-D
tRR-D
REFA
tRR-D
DQ31..0
DQN31..0
tRR
T1
T2
T3
T4
T5
tCYCLE
note - REFA is directed to bank
set different from two ACT
Case 0: tRR-D = 0*tCYCLE
REFA simultaneous with ACT
(REFA uses delay=1*tCYCLE)
Case 1: tRR-D = 1*tCYCLE
REFA fits between two ACT
T0
ACT
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ31..0
DQN31..0
ACT REFA
REFA ACT
ACT
ACT
tCYCLE
tRR-D
tRR-D
tRR
note - REFA is directed to bank
set different from two ACT
tRR
Data Sheet E1819E20 (Ver. 2.0)
60
note - REFA is directed to bank
set different from ACT at T12
EDX1032BBBG
charge command to one bank set may be inserted between two
precharge commands to a different bank set.
Simultaneous Precharge
When the XDR DRAM supports multiple bank sets as in
Figure 45, another feature may be supported, in addition to
ERAW and simultaneous activation. This feature is simultaneous precharge, and the timing of several cases is shown in
Figure 47.
Case 1 shows an example when tPP must be at least 4*tCYCLE
and tPP-D must be at least 1*tCYCLE. As in the previous case, a
precharge command to one bank set may be inserted between
two precharge commands to a different bank set. In this case,
the middle precharge command does not have to be symmetrically placed relative to the two other precharge commands.
The tPP parameter specifies the minimum spacing between
packets with precharge commands in XDR DRAMs with a single bank set, or between packets to the same bank set in a XDR
DRAM with multiple bank sets. The tPP-D parameter specifies
the minimum spacing between packets with precharge commands to different bank sets in a XDR DRAM with multiple
bank sets.
Case 0 shows an example when tPP must be at least 4*tCYCLE
and tPP-D must be at least 0*tCYCLE. This means that two precharge commands may be issued on the same CFM clock edge.
This is possible by using the delay mechanism in one of the
two commands. See “Dynamic Request Scheduling” on
page 20. It is also possible by taking advantage of the fact that
two independent precharge commands may be encoded within
a single ROWP packet. In the example shown, the ROWP
packet contains both a REFP command and a PRE command.
Both precharge commands will be issued internally to different
bank sets on the same CFM clock edge.
Case 4 shows an example when both tPP and tPP-D must be at
least 4*tCYCLE. In such a case, precharge commands to different bank sets satisfy the same constraint as precharge commands to the same bank set.
Case 2 shows an example when tPP must be at least 4*tCYCLE
and tPP-D must be at least 2*tCYCLE. In such a case, a preFigure 47
Simultaneous Precharge — tPP-D Cases
Case 4: tPP-D = 4*tCYCLE
REFP & PRE have same tPP
T0
T1
T2
T3
T4
T5
T6
T7
T8
Case 2: tPP-D = 2*tCYCLE
REFP fits between two PRE
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
PRE
REFP
PRE
PRE
tPP-D
tPP-D
REFP
tPP-D
DQ31..0
DQN31..0
tPP
T1
T2
T3
T4
T5
tCYCLE
note - REFP is directed to bank
set different from two PRE
Case 0: tPP-D = 0*tCYCLE
REFP simultaneous with PRE
Case 1: tPP-D = 1*tCYCLE
REFP fits between two PRE
T0
PRE
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
DQ31..0
DQN31..0
PRE REFP
PRE
REFP
PRE
PRE
tCYCLE
tPP-D
tPP-D
tPP
note - REFP is directed to bank
set different from two PRE
tPP
Data Sheet E1819E20 (Ver. 2.0)
61
note - REFP is directed to bank
set different from PRE at T12
EDX1032BBBG
This mode allows all the request packet fields to look identical
to that of the 512Mb XDR DRAM device and allows a measure of compatibility to memory controllers designed to work
on the previous devices without the need to issue request packets in the 1Gb XDR DRAM format. For example, a memory
controller connecting to two 512Mb XDR DRAMs in x8
device width can be reconfigured to connect to one 1Gb XDR
DRAM in x16 device width. The WIDTH[2:0] value will have
to change from “011” for the 512Mb XDR DRAMs to “100”
for the 1Gb XDR DRAM.
Column Address Remapping
Table 15 and Figure 48shows an alternate mapping of the column and sub-column fields within the COL and COLM
request packets. This mode is enabled by setting the CRM
value to “1”.
In this mode, the COL / COLM request packets will be
remapped to use the C9..4 / SC3..0 locations in Figure 48
instead of the C10..5 / SC4..1 locations in Figure 2. The subcolumn address field of SC0 in Figure 2 will be left unmapped
and set to “0”.
Table 15 Alternate
Field
Request Field Description
Packet Types
Description
C9..4
COL/COLM
6-bit column address for column read or write command.
SC3..0
COL/COLM
4-bit sub-column address for dynamic width.
Data Sheet E1819E20 (Ver. 2.0)
62
EDX1032BBBG
Figure 48
Alternate Request Packet Formats
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFM
CFMN
CFMN
RQ11..0
RQ11..0
tCYCLE
RD
a0
WRM
a1
DQ31..0
DQN31..0
COL Packet
COLM Packet
tCYCLE
tCYCLE
CFM
CFMN
RQ11
OP
3
DEL
C
OP
3
M
7
RQ10
OP
2
rsrv
M
3
M
6
RQ9
OP
1
rsrv
M
2
M
5
RQ8
OP
0
rsrv
M
1
M
4
RQ7
WR
X
C
7
M
0
C
7
RQ6
C
8
C
6
C
8
C
6
RQ5
C
9
C
5
C
9
C
5
rsrv
C
4
rsrv
C
4
rsrv
SC
3
rsrv
SC
3
RQ2
BC
2
SC
2
BC
2
SC
2
RQ1
BC
1
SC
1
BC
1
SC
1
RQ0
BC
0
SC
0
BC
0
SC
0
RQ4
RQ3
Data Sheet E1819E20 (Ver. 2.0)
63
EDX1032BBBG
The high and low voltages must satisfy a symmetry parameter
with respect to the VREF,RSL.The third section of parameters
determines the input voltage levels for the RSL SI (serial interface) signals. The high and low voltages must satisfy a symmetry parameter with respect to the VREF,RSL.
Operating Conditions
Electrical Conditions
Table 16 summarizes all electrical conditions (temperature and
voltage conditions) that may be applied to the memory component. The first section of parameters is concerned with absolute voltages, storage, and operating temperatures, and the
power supply, reference, and termination voltages.
The fourth section of parameters determines the input voltage
levels for the CFM clock signals. The high and low voltages are
specified by a common-mode value and a swing value.
The fifth section of parameters determines the input voltage
levels for the write data signals on the DRSL DQ pins. The
high and low voltage are specified by a common-mode value
and a swing value.
The second section of parameters determines the input voltage
levels for the RSL RQ signals.
Table 16 Electrical
Symbol
Conditions
Parameter
Minimum
Maximum
Unit
VIN,ABS
Voltage applied to any pin (except VDD) with respect to GND
- 0.300
1.500
V
VDD,ABS
Voltage on VDD with respect to GND
- 0.400
1.975
V
TSTORE
Storage temperature
- 50
100
°C
TJ
Junction temperature under bias during normal operation
0
100
°C
VDD
Supply voltage applied to VDD pins during normal operation
1.5 - 0.075
1.5 + 0.075
V
VREF,RSL
RSL - Reference voltage applied to VREF pin
VTERM,RSL a
- 0.450 - 0.025
VTERM,RSLa
- 0.450 + 0.025
V
VTERM,DRSL
DRSL - Termination voltage applied to VTERM pins
1.200 - 0.060
1.200 + 0.060
V
VIL,RQ
RSL RQ inputs -low voltage
VREF,RSL - 0.450
VREF,RSL - 0.150
V
VIH,RQb
RSL RQ inputs -high voltage
VREF,RSL + 0.150
VREF,RSL + 0.450
V
RA,RQ
RSL RQ inputs - data asymmetry:
RA,RQ = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ)
0.8
1.2
-
VIL,SI
RSL Serial Interface inputs -low voltage
VREF,RSL - 0.450
VREF,RSL - 0.200
V
VIH,SIb
RSL Serial Interface inputs -high voltage
VREF,RSL + 0.200
VREF,RSL + 0.450
V
RA,SI
RSL Serial Interface inputs - data asymmetry:
RA,SI = (VIH,SI-VREF,RSL)/(VREF,RSL-VIL,SI)
0.8
1.2
-
VICM,CFM
CFM/CFMN input - common mode
VTERM,DRSL VISW,CFM/2 - 0.020
VTERM,DRSL VISW,CFM/2 + 0.020
V
VISW,CFM
CFM/CFMN input - high-low swing: VISW,CFM = (VIH,CFMb- VIL,CFM)
0.150
0.300
V
VICM,DQ
DRSL DQ inputs - common mode
VTERM,DRSLVISW,DQ/2 - 0.020
VTERM,DRSL VISW,DQ/2 + 0.020
V
VISW,DQ
DRSL DQ inputs - high-low swing: VISW,DQ = (VIH,DQb - VIL,DQ)
0.050
0.300
V
a. VTERM,RSL is typically 1.200V±0.060V. It connects to the RSL termination components, not to this DRAM component.
b. VIH is typically equal to VTERM,RSL or VTERM,DRSL (whichever is appropriate) under DC conditions in a system.
Data Sheet E1819E20 (Ver. 2.0)
64
EDX1032BBBG
with parameters for the write data signals. The fourth section
of parameters is concerned with parameters for the serial interface signals. The fifth section is concerned with all other
parameters, including those for refresh, calibration, power state
transitions, and initialization.
Timing Conditions
Table 17 summarizes all timing conditions that may be applied
to the memory component. The first section of parameters is
concerned with parameters for the clock signals. The second
section of parameters is concerned with parameters for the
request signals. The third section of parameters is concerned
Table 17 Timing
Symbol
Conditions
Parameter and Other Conditions
tCYCLE or tCYC,CFM
CFM RSL clock - cycle time
tR,CFM, tF,CFM
Minimum
Maximum
Units
Figure(s)
Figure 49
2.500
3.830
ns
CFM/CFMN input - rise and fall time - use minimum for test.
0.080
0.200
tCYCLE
Figure 49
tH,CFM, tL,CFM
CFM/CFMN input - high and low times
40%
60%
tCYCLE
Figure 49
tR,RQ, tF,RQ
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
0.080
0.260
tCYCLE
Figure 50
tS,RQ, tH,RQ
RSL RQ input to sample points
(setup/hold)
0.200
-
ns
0.020
0.074
tCYCLE
-3200
Figure 50
@ 3.333 ns > tCYCLE ≥ 2.500 ns
tIR,DQ, tIF,DQ
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
tS,DQ, tH,DQ
DRSL DQ input to sample points
(setup/hold)
Figure 51
Figure 51
@ 3.333 ns > tCYCLE ≥ 2.500 ns
65
-
ps
-0.080
+0.080
tCYCLE
20
-
ns
tDOFF,DQ
DRSL DQ input delay offset (fixed) to sample points
tCYC,SCK
Serial Interface SCK input - cycle time
tR,SCK, tF,SCK
Serial Interface SCK input - rise and fall times
-
5.0
ns
Figure 53
tH,SCK, tL,SCK
Serial Interface SCK input - high and low times
40%
60%
tCYC,SCK
Figure 53
tIR,SI, tIF,SI
Serial Interface CMD, RST, SDI input - rise and fall times
-
5.0
ns
Figure 53
tS,SI,tH,SI
Serial Interface CMD, RST, SDI input to SCK clock edge setup/hold time
5
-
ns
-3200
Figure 51
Figure 53
Figure 53
-3200
tDLY,SI-RQ
Delay from last SCK clock edge for register operation to first CFM edge with
RQ packet. Also, delay from first CFM edge with RQ packet to the first SCK
clock edge for register operation.
10
-
tCYC,SCK
tREF
Refresh interval. Every row of every bank must be accessed at least once in this
interval with a ROW-ACT, ROWP-REF or ROWP-REFI command.
-
16
ms
Figure 34
tREFA-REFA,AVG
Average refresh command interval. ROWP-REFA or ROWP-REFI commands
must be issued at this average rate. This depends upon tREF and the number of
banks and rows: tREFA-REFA,AVG = tREF/(NB*NR) = tREF/(23*212).
ns
-
tREFI-REFI
Refresh/increment command interval. The interval between two ROWP-REFI
commands.
NREFA,BURST
tREFA-REFA,AVG = 488
tCYCLE
-
128
commands
-
40
-
tCYCLE
-
1.500
-
ms
-
16
-
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands
which can be issued consecutively at the minimum command spacing.
-
tBURST-REFA
Refresh burst interval. The interval between a burst of NREFA,BURST,MAX
ROWP-REFA or ROWP-REFI commands and the next ROWP-REFA or
ROWP-REFI command.
tCOREINIT
Interval between VDD power-on-and-stable to the first RQ or serial transaction
for core initialialization.
Data Sheet E1819E20 (Ver. 2.0)
65
-
EDX1032BBBG
Table 17 Timing
Symbol
Conditions (Continued)
Parameter and Other Conditions
tCALC, tCALZ
Current and termination calibration interval
tCMD-CALC, tCMD-CALZ,
Delay between packet with any command
and CALC/CALZ packet
tCALCE, tCALZE
Minimum
Maximum
Units
Figure(s)
-
100
ms
Figure 35
4
16
-
tCYCLE
Figure 35
Delay between CALC/CALZ packet and CALE packet
12
-
tCYCLE
Figure 35
tCALE-CMD
Delay between CALE packet and packet with any command
24
-
tCYCLE
Figure 35
tCMD-PDN
Last command before PDN entry
16
-
tCYCLE
Figure 36
tPDN-CFM
RSL CFM/CFMN stable after PDN entry
16
-
tCYCLE
Figure 36
tCFM-PDN
RSL CFM/CFMN stable before PDN exit
16
-
tCYCLE
Figure 36
tPDN-CMD
First command after PDN exit (includes lock time for CFM/CFMN)
4096
-
tCYCLE
Figure 36
w/ PRE or REFP command
w/ any other command
Operating Characteristics
The second section of parameters is concerned with the current needed by the RQ pins and VREF pin.
Electrical Characteristics
The third section of parameters is concerned with the current
needed by the DQ pins and voltage levels produced by the DQ
pins when driving read data. This section is also concerned
with the current needed by the VTERM pin, and with the
resistance levels produced for the internal termination components that attach to the DQ pins.
Table 18 summarizes all electrical parameters (temperature,
current, and voltage) that characterize this memory component. The only exception is the supply current values (IDD)
under different operating conditions covered in the “Supply
Current Profile” section.
The fourth section of parameters determines the output voltage levels and the current needed for the serial interface signals.
The first section of parameters is concerned with the thermal
characteristics of the memory component.
Table 18 Electrical
Symbol
Characteristics
Parameter
Minimum
Maximum
Units
ΘJC
Junction-to-case thermal resistance
-
0.5
°C/Watt
II,RSL
RSL RQ or Serial Interface input current @ (VIN=VIH,RQ,MAX)
-10
10
μA
IREF,RSL
VREF,RSL current @ VREF,RSL,MAX flowing into VREF pin
-10
10
μA
VOSW,DQ
DRSL DQ outputs - high-low swing:
VOSW,DQ = (VOH,DQ-VOL,DQN) or (VOH,DQN-VOL,DQ)
0.200
0.400
V
RTERM,DQ
DRSL DQ outputs - termination resistance
40.0
60.0
Ω
VOL,SI
RSL serial interface SDO output - low voltage
0.0
0.250
V
VOH,SI
RSL serial interface SDO output - high voltage
VTERM,RSL a- 0.250
VTERM,RSLa
V
a. VTERM,RSL is typically 1.200V±0.060V. It connects to the RSL termination components, not to this DRAM component.
Data Sheet E1819E20 (Ver. 2.0)
66
EDX1032BBBG
These parameters are shown under different operating
conditions.
Supply Current Profile
In this section, Table 19 summarizes the supply currents (IDD
and ITERM,DRSL) that characterize this memory component.
Table 19 Supply
Symbol
Current Profile
Power State and Steady State
Transaction Rates
Maximum
@tCYCLE= 2.500 ns
@ x32/x16/x8/x4 width
Units
35/35/35/35
mA
IDD,PDN
Device in PDN, self-refresh
enabled. a
IDD,STBY
Device in STBY. This is for a device
in STBY with no packets on the
Channela
220/220/220/220
mA
IDD,ROW
ACT command every tRR,
PRE command every tPP a
450/450/450/450
mA
IDD,WR
ACT command every tRR,
PRE command every tPP,
WR command every tCC.a
1000/820/740/720
mA
IDD,RD
ACT command every tRR,
PRE command every tPP,
RD command every tCCa
1150/900/780/720
mA
ITERM,DRSL,WR
WR command every tCC.b
260/140/80/50
mA
ITERM,DRSL,RD
RD command every tCC.b
470/250/135/75
mA
a. IDD current @ VDD,MAX flowing into VDD pins
b. ITERM,DRSL current @ VTERM,DRSL,MAX flowing into VTERM pins
Data Sheet E1819E20 (Ver. 2.0)
67
EDX1032BBBG
Timing Characteristics
DQ pins when driving read data.
Table 20 summarizes all timing parameters that characterize
this memory component. The only exceptions are the core
timing parameters that are speed-bin dependent. Refer to the
Timing Parameters section for more information.
The second section of parameters is concerned with the timing for the serial interface signals when driving register read
data. The third section of parameters is concerned with the
time intervals needed by the interface to transition between
power states.
The first section of parameters pertains to the timing of the
Table 20 Timing
Symbol
tQ,DQ
Characteristics
Parameter and Other Conditions
Minimum
Maximum
Units
DRSL DQ output delay (variation across 16 Q bits on each DQ pin)
from drive points - output delay
@ 3.333 ns > tCYCLE ≥ 2.500 ns
Figure(s)
Figure 52
-65
+65
ps
tQOFF,DQ
DRSL DQ output delay offset (a fixed value for all 32 Q bits on each
DQ pin) from drive points - output delay
0.000
+0.200
tCYCLE
Figure 52
tOR,DQ, tOF,DQ
DRSL DQ output - rise and fall times (20%-80%).
0.020
0.040
tCYCLE
Figure 52
tQ,SI
Serial SCK-to-SDO output delay @ CLOAD,MAX = 15 pF
2
15
ns
tP,SI
Serial SDI-to-SDO propagation delay @ CLOAD,MAX = 15 pF
-
15
ns
Figure 54
tOR,SI, tOF,SI
Serial SDO output rise/fall (20%-80%) @ CLOAD,MAX = 15 pF
-
10
ns
Figure 54
tPDN-ENTRY
Time for power state to change after PDN entry
-
16
tCYCLE
Figure 36
tPDN-EXIT
Time for power state to change after PDN exit
0
-
tCYCLE
Figure 36
Data Sheet E1819E20 (Ver. 2.0)
68
-3200
Figure 54
EDX1032BBBG
bin. The four sections deal with the timing intervals between
packets with, respectively, row-row commands, row-column
commands, column-column commands, and column-row
commands.
Timing Parameters
Table 21 summarizes the timing parameters that characterize
the core logic of this memory component. These timing
parameters will vary as a function of the component’s speed
Table 21 Timing
Parameters
Min
(C)
Units
Figure(s)
Row-cycle time: interval between
tRC
successiveROWA-ACT or ROWP- tRC-R, 2tCC = tRCD-R + tCC+ tRDP + tRPa
REFA or ROWP-REFI activate
tRC-W, 2tCC, noERAW = tRCD-W,noERAW + tCC+ tWRP + tRPa
commands to the same bank.
tRC-W, 2tCC, ERAW = tRCD-W,ERAW + tCC+ tWRP + tRPa
24
tCYCLE
Figure 3 Figure 6
tRAS
Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI
activate command and a ROWP-PRE or ROWP-REFP precharge command to the same bank.
Note that tRAS,MAX is 64 us for all timing bins.
17
tCYCLE
Figure 3 Figure 6
tRP
Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command and a
ROWA-ACT or ROWP-REFA or ROWP-REFI activate command to the same bank.
7
tCYCLE
Figure 3 Figure 6
tPP
Precharge-to-precharge time: interval between successive
ROWP-PRE or ROWP-REFP precharge commands to different banks.
4
1
tCYCLE
Figure 3 Figure 6
tRR
Row-to-row time: interval between ROWA-ACT or ROWPREFA or ROWP-REFI activate commands to different banks.
4
4
tCYCLE
Figure 3 Figure 6
tRCD-R
Row-to-column-read delay: interval between a ROWA-ACT activate command and
a COL-RD read command to the same bank.
7
tCYCLE
Figure 3 Figure 6
tRCD-W
Row-to-column-write delay: interval between a ROWA-ACT activate
tRCD-W, noERAW
command and a COL-WR or COL-WRM write command to the same bank. tRCD-W, ERAW
3
7
tCYCLE
Figure 3 Figure 6
tCAC
Column access delay: interval from COL-RD read command to Q read data. For bins C, D, E, and
F; these values are not minimum and must be programmed exactly to the CAC field of the Delay
Control Register.
7
tCYCLE
Figure 9
tCWD
Column write delay: interval from a COL-WR or COLM-WRM write command
to D write data. For bins C, D, E, and F; these values are not minimum and must be programmed
exactly to the CWD field of the Delay Control Register.
3
tCYCLE
Figure 8
tCC
Column-to-column time: interval between successive COL-RD commands, or between
successive COL-WR or COLM-WRM commands.
2
tCYCLE
Figure 3 Figure 6
tRW-BUB,
XDRDRAM
Read-to-write bubble time: interval between the end of a Q read data packet and the start of D
write data packet (the end of a data packet is the time interval tCC after its start).
3
tCYCLE
Figure 12
tWR-BUB,
XDRDRAM
Write-to-read bubble time: interval between the end of a D writed data and the start of Q read
data packet (the end of a data packet is the time interval tCC after its start).
3
tCYCLE
Figure 12
tΔRW
Read-to-write time: interval between a COL-RD read command and a COL-WR or
COLM-WRM write command.d
9
tCYCLE
Figure 11
tΔWR
Write-to-read time: interval between a COL-WR or
COLM-WRM write command and a COL-RD read command.
10
2
tCYCLE
Figure 11,
Figure 44
tRDP
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE
precharge command to the same bank.
4
tCYCLE
Figure 3 Figure 6
tWRP
Write-to-precharge time: interval between a COL-WR or COLM-WRM write command
and a ROWP-PRE precharge command to the same bank.
12
tCYCLE
Figure 3 Figure 6
tDR
Write data-to-read time: interval between the start of D write data and a COL-RD read
command to the same bank.
7
tCYCLE
Figure 11
tDP
Write data-to-precharge time: interval between D write data and ROWP-PRE precharge
command to the same bank.
9
tCYCLE
Figure 8
tLRRn-LRRn
Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command. f
24
tCYCLE
Table 4
Symbol
tRC
Parameter and Other Conditions
tPP
tPP-Db
tRR
tRR-Dc
Data Sheet E1819E20 (Ver. 2.0)
69
tΔWR
t ΔWR-De
24
24
28
EDX1032BBBG
Table 21 Timing
Symbol
Parameters (Continued)
Parameter and Other Conditions
Min
(C)
Units
Figure(s)
tREFx-LRRn
Interval between ROWP-REFx command and a subsequent ROWP-LRRn command.
24
tCYCLE
Table 4
tLRRn-REFx
Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
24
tCYCLE
Table 4
a. The tRC,MIN parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation,
depending upon how many column accesses (each requiring tCC) are performed in each row access (tRC). The table lists the special cases (tRC-R, 2tCC, tRC-W,
2tCC, noERAW, tRC-W, 2tCC, ERAW) in which two column accesses are performed in each row access. All other parameters are minimum.
b. tPP-D is the tPP parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 61.
c. tRR-D is the tRR parameter for activates to different bank sets. See “Simultaneous Activation” on page 60.
d. See “Propagation Delay” on page 28.
e. tΔWR-D is the tΔWR parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 58. Also, note that
the value of tΔWR-D may not take on the values {3,5,7} within the range{tΔWR-D,MIN, ... tΔWR,MIN-1}. tΔWR-D may assume any value ≥tΔWR,MIN.
f. ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,ROWP-LRR2}
ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI,ROWP-REFP}
Data Sheet E1819E20 (Ver. 2.0)
70
EDX1032BBBG
diagram). The secondary crossing point includes the low-voltage-to-high-voltage transition of CFM. All timing events on
the RSL signals are referenced to the first set of edges.
Receive/Transmit Timing
Clocking
Timing events are measured to and from the crossing point of
the CFM and CFMN signals. In the timing diagram, this is how
the clock-cycle time (tCYCLE or tCYC,CFM), clock-low time
(tL,CFM) and clock-high time (tH,CFM) are measured.
Figure 49 shows a timing diagram for the CFM/CFMN clock
pins of the memory component. This diagram represents a
magnified view of these pins. This diagram shows only one
clock cycle.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise
(tR,CFM) and fall time (tF,CFM) of the signals are measured from
the 20% and 80% points of the full-swing levels.
CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true signals — a low
voltage represents a logical zero and a high voltage represents a
logical one. There are two crossing points in each clock cycle.
The primary crossing point includes the high-voltage-to-lowvoltage transition of CFM (indicated with the arrowhead in the
Figure 49
20% = VIL,CFM + 0.2*(VIH,CFM-VIL,CFM)
80% = VIL,CFM + 0.8*(VIH,CFM-VIL,CFM)
Clocking Waveforms
tCYCLE or tCYC,CFM
tL,CFM
logic 1
tH,CFM
VIH,CFM
80%
CFM
CFMN
20%
VIL,CFM
logic 0
tR,CFM
tF,CFM
Data Sheet E1819E20 (Ver. 2.0)
71
EDX1032BBBG
and fall time (tF,RQ) of the signals are measured from the 20%
and 80% points of the full-swing levels.
RSL RQ Receive Timing
Figure 50 shows a timing diagram for the RQ11..0 request pins
of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles (CFM and
CFMN are the clock signals). Timing events are measured to
and from the primary CFM/CFMN crossing point in which
CFM makes its high-voltage-to-low-voltage transition. The
RQ11..0 signals are low-true: a high voltage represents a logical
zero and a low voltage represents a logical one. Timing events
on the RQ11..0 pins are measured to and from the point that
the signal reaches the level of the reference voltage VREF,RSL.
20% = VIL,RQ + 0.2*(VIH,RQ-VIL,RQ)
80% = VIL,RQ + 0.8*(VIH,RQ-VIL,RQ)
There are two data receiving windows defined for each
RQ11..0 signal. The first of these (labeled “0”) has a set time,
tS,RQ , and a hold time, tH,RQ , measured around the primary
CFM/CFMN crossing point. The second (labeled “1”) has a
set time (tS,RQ) and a hold time (tH,RQ) measured around a
point 0.5*tCYCLE after the primary CFM/CFMN crossing
point.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR,RQ)
Figure 50
RSL RQ Receive Waveforms
tCYCLE
CFM
CFMN
[1/2]•tCYCLE
tS,RQ
RQ0
tH,RQ
tS,RQ
0
logic 0
VIH,RQ
80%
VREF,RSL
1
20%
VIL,RQ
logic1
tF,RQ
...
tR,RQ
tH,RQ
[1/2]•tCYCLE
tS,RQ
RQ11
tH,RQ
0
tR,RQ
72
tH,RQ
1
tF,RQ
Data Sheet E1819E20 (Ver. 2.0)
tS,RQ
logic 0
VIH,RQ
80%
VREF,RSL
20%
VIL,RQ
logic 1
EDX1032BBBG
DRSL DQ Receive Timing
pairs).
Figure 51 shows a timing diagram for receiving write data on
the DQ/DQN data pins of the memory component. This diagram represents a magnified view of the pins and only a few
clock cycles are shown (CFM and CFMN are the clock signals).
Timing events are measured to and from the primary CFM/
CFMN crossing point in which CFM makes its high-voltageto-low-voltage transition. The DQ31..0/DQN31..0 signals are
high-true: a low voltage represents a logical zero and a high
voltage represents a logical one. They are also differential —
timing events on the DQ31..0/DQN31..0 pins are measured to
and from the point that each differential pair crosses.
The tDOFF,DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair. The 16 receiving windows are placed at
times tDOFF,DQi+(j/8)*tCYCLE (the index “j” may take on the
values {0,1,2, ..15} and refers to each of the receiving windows
for the DQi/DQNi pin pair).
The offset values tDOFF,DQi for each of the 32 DQi/DQNi pin
pairs can be different. However, each is constrained to lie
inside the range {tDOFF,MIN ,tDOFF,MAX}. Furthermore, each
offset value tDOFF,DQi is static and will not change during system operation. Its value can be determined at initialization.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time
(tIR,DQ) and fall time (tIF,DQ) of the signals are measured from
the 20% and 80% points of the full-swing levels.
The 16 receiving windows (j=0..15) for the first pair DQ0/
DQN0 are labeled “0” through “15”. Each window has a set
time (tS,DQ) and a hold time (tH,DQ) measured around a point
tDOFF,DQ0+(j/8)*tCYCLE after the primary CFM/CFMN
crossing point.
20% = VIL,DQ + 0.2*(VIH,DQ-VIL,DQ)
The 16 receiving windows (j=0..15) for each of the other pairs
DQi/DQNi are also labeled “0” through “15”. Each window
has a set time (tS,DQ) and a hold time (tH,DQ) measured around
a point tDOFF,DQi+(j/8)*tCYCLE after the primary CFM/
CFMN crossing point.
80% = VIL,DQ + 0.8*(VIH,DQ-VIL,DQ)
There are 16 data receiving windows defined for each
DQ31..0/DQN31..0 pin pair. The receiving windows for a
particular DQi/DQNi pin pair is referenced to an offset
parameter tDOFF,DQi (the index “i” may take on the values {0,
1, ..31} and refers to each of the DQ31..0/DQN31..0 pin
Data Sheet E1819E20 (Ver. 2.0)
73
EDX1032BBBG
Figure 51
DRSL DQ Receive Waveforms
tCYCLE
CFM
...
CFMN
i = {0,1,2,...31}
tDOFF,MAX
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
tDOFF,MIN
tDOFF,DQ0
[(j)/8]•tCYCLE
tS,DQ
logic 1
VIH,DQ
80%
tH,DQ
DQ0
0
1
2
3
4
5
6
...
...
j
14
15
20%
VIL,DQ
logic 0
DQN0
tIF,DQ
...
tIR,DQ
tDOFF,DQi
[(j)/8]•tCYCLE
tS,DQ
logic 1
VIH,DQ
80%
tH,DQ
DQi
0
1
2
3
4
5
6
...
j
...
14
15
20%
VIL,DQ
logic 0
DQNi
...
tIR,DQ
tIF,DQ
tDOFF,DQ31
[(j)/8]•tCYCLE
logic 1
”V
IH,DQ
80%
tH,DQ
tS,DQ
DQ31
0
1
2
3
4
5
DQN31
tIR,DQ
tIF,DQ
Data Sheet E1819E20 (Ver. 2.0)
74
6
...
j
...
14
15
20%
VIL,DQ
logic 0
EDX1032BBBG
The tQOFF,DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair.
DRSL DQ Transmit Timing
Figure 52 shows a timing diagram for transmitting read data on
the DQ31..0/DQN31..0 data pins of the memory component.
This diagram represents a magnified view of these pins and
only a few clock cycles are shown (CFM and CFMN are the
clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its
high-voltage-to-low-voltage transition. The DQ31..0/
DQN31..0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are
also differential — timing events on the DQ31..0/DQN31..0
pins are measured to and from the point that each differential
pair crosses.
The offset values tQOFF,DQi for each of the 32 DQi/DQNi pin
pairs can be different. However, each is constrained to lie
inside the range {tQOFF,MIN ,tQOFF,MAX}. Furthermore, each
offset value tQOFF,DQi is static; its value will not change during
system operation. Its value can be determined at initialization
time.
The 16 transmitting windows (j=0..15) for the first pair DQ0/
DQN0 are labeled “0” through “15”. Each window begins at
the time (tQOFF,DQ0+tQ,DQ,MAX+((j-0.5)/8)*tCYCLE ) and
ends at the time (tQOFF,DQ0+tQ,DQ,MIN+((j+0.5)/8)*tCYCLE )
measured after the primary CFM/CFMN crossing point.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise
(tOR,DQ) and fall time (tOF,DQ) of the signals are measured
from the 20% and 80% points of the full-swing levels.
The 16 transmitting windows (j=0..15) for the other pairs
DQi/DQNi are also labeled “0” through “15”. Each window
begins at the time (tQOFF,DQi+tQ,DQ,MAX+((j-0.5)/8)*tCYCLE)
and ends at the time (tQOFF,DQi+tQ,DQ,MIN+((j+0.5)/8)*tCYCLE ) measured after the primary CFM/CFMN crossing point.
20% = VOL,DQ + 0.2*(VOH,DQ-VOL,DQ )
80% = VOL,DQ + 0.8*(VOH,DQ-VOL,DQ )
Note that when no read data is to be transmitted on the DQ/
DQN pins (and no other component is transmitting on the
external DQ/DQN wires), then the voltage level on the DQ/
DQN pins will follow the voltage reference value
VTERM,DRSL on the VTERM pin. The logical value of each
DQ/DQN pin pair in this no-drive state will be “1/1”; when
read data is driven, each DQ/DQN pin pair will have either
the logical value of “1/0” or “0/1”.
There are 16 data transmitting windows defined for each
DQ31..0/DQN31..0 pin pair. The transmitting windows for a
particular DQi/DQNi pin pair are referenced to an offset
parameter tQOFF,DQi (the index “i” may take on the values {0,
1,2,..31} and refers to each of the DQ31..0/DQN31..0 pin
pairs).
Data Sheet E1819E20 (Ver. 2.0)
75
EDX1032BBBG
Figure 52
DRSL DQ Transmit Waveforms
tCYCLE
CFM
...
CFMN
i = {0,1,2,...31}
tQOFF,MAX
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
tQOFF,MIN
[(j+0.5)/8]•tCYCLE
tQOFF,DQ0
[(j-0.5)/8]•tCYCLE
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
DQ0
0
1
2
3
4
5
6
7
...
...
j
14
15
20%
VOL,DQ
logic “0”
DQN0
...
tOR,DQ
tOF,DQ
[(j+0.5)/8]•tCYCLE
tQOFF,DQi
[(j-0.5)/8]•tCYCLE
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
DQi
0
1
2
3
4
5
6
7
...
j
...
14
15
20%
VOL,DQ
logic “0”
DQNi
...
tOR,DQ
tOF,DQ
[(j+0.5)/8]•tCYCLE
tQOFF,DQ31
[(j-0.5)/8]•tCYCLE
logic “1”
VOH,DQ
80%
tQ,DQ,MIN
tQ,DQ,MAX
DQ31
0
1
2
3
4
5
6
DQN31
tOR,DQ
tOF,DQ
Data Sheet E1819E20 (Ver. 2.0)
76
7
...
j
...
14
15
20%
VOL,DQ
logic “0”
EDX1032BBBG
are measured from the 20% and 80% points of the full-swing
levels.
Serial Interface Receive Timing
Figure 53 shows a timing diagram for the serial interface pins
of the memory component. This diagram represents a magnified view of the pins only a few clock cycles.
20% = VIL,SI + 0.2*(VIH,SI-VIL,SI)
50% = VIL,SI + 0.5*(VIH,SI-VIL,SI)
The serial interface pins carry low-true signals: a high voltage
represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the VREF,RSL
level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time
(tR,SCK and tIR,SI) and fall time (tF,SCK and tIF,SI) of the signals
Figure 53
80% = VIL,SI + 0.8*(VIH,SI-VIL,SI)
There is one receiving window defined for each serial interface
signal (RST,CMD and SDI pins). This window has a set time
(tS,RQ) and a hold time (tH,RQ) measured around the falling
edge of the SCK clock signal.
Serial Interface Receive Waveforms
tCYC,SCK
logic 0
VIH,SI
80%
tH,SCK
tL,SCK
SCK
VREF,RSL
20%
VIL,SI
tF,SCK
logic 1
tR,SCK
tS,SI
tH,SI
logic 0
VIH,SI
80%
RST
CMD
SDI
VREF,RSL
20%
VIL,SI
tIR,SI
tIF,SI
Data Sheet E1819E20 (Ver. 2.0)
77
logic 1
EDX1032BBBG
There is one transmit window defined for the serial interface
data signal (SDO pins). This window has a maximum delay
time (tQ,SI,MAX) from the falling edge of the SCK clock signal
and a minimum delay time (tQ,SI,MIN) from the next falling
edge of the SCK clock signal.
Serial Interface Transmit Timing
Figure 54 shows a timing diagram for the serial interface pins
of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown.
The serial interface pins carry low-true signals: a high voltage
represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the VREF,RSL
level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time
(tOR,SI) and fall time (tOF,SI) of the signals are measured from
the 20% and 80% points of the full-swing levels.
When the memory component is not selected during a serial
device read transaction, it will simply pass the information on
the SDI input to the SDO output. This combinational propagation delay parameter is tP,SI. The tCYC,SCK will need to be
increased during a serial read transaction (relative to the
tCYC,SCK value for a serial write transaction) because of the
accumulated propagation delay through all of the XDR DRAM
devices on the serial interface.
20% = VOL,SI + 0.2*(VOH,SI-VOL,SI)
During Initialization, when the serial identification is determined, the SDI-to-SDO path is registered, so the tCYC,SCK
value can be set to the same value as for serial write transactions. See “Initialization” on page 46.
50% = VOL,SI + 0.5*(VOH,SI-VOL,SI)
80% = VOL,SI + 0.8*(VOH,SI-VOL,SI)
Figure 54
Serial Interface Transmit Waveforms
tCYC,SCK
logic 0
tH,SCK
tL,SCK
VIH,SI
80%
SCK
VREF,RSL
tF,SCK
20%
VIL,SI
logic 1
tR,SCK
tQ,SI,MAX
tQ,SI,MIN
logic 0
VOH,SI
80%
tP,SI
VREF,RSL
SDO
20%
VOL,SI
tOR,SI
tOF,SI
Combinational propagation from SDI to
SDO when the device is not selected
during a serial device read transaction.
SDI
logic 1
logic 0
VIH,SI
80%
VREF,RSL
20%
VIL,SI
logic 1
Data Sheet E1819E20 (Ver. 2.0)
78
EDX1032BBBG
pins. They include inductance, mutual inductance, capacitance,
and resistance values. There are also limits on the spread in
inductance and capacitance values allowed in any one memory
component. The third group of parameters are specific to the
DQ data pins and include inductance, mutual inductance,
capacitance, and resistance values. There are also limits on the
spread in inductance and capacitance values allowed in any one
memory component.The fourth group of parameters are for
the serial interface pins. They include inductance and capacitance values.
Package Description
Package Parasitic Summary
Table 22 summarizes inductance, capacitance, and resistance
values associated with each pin group for the memory component. Most of the parameters have maximum values only, however some have both maximum and minimum values.
The first group of parameters are for the CFM/CFMN clock
pair pins. They include inductance, capacitance, and resistance
values. The second group of parameters are for the RQ request
Table 22 Package Parasitic Summary
(package parasitic values are measured on randomly-sampled devices)
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
LVTERM
VTERM pin - effective input inductance per four bits
-
2.2
nH
LI ,CFM
CFM/CFMN pins - effective input inductanceb
-
5.0
nH
CI ,CFM
CFM/CFMN pins - effective input capacitanceb
1.8
2.4
pF
RI ,CFM
CFM/CFMN pins - effective input resistance
4
18
Ω
LI ,RQ
RSL RQ pins - effective input inductanceb
-
5.0
nH
CI ,RQ
RSL RQ pins - effective input capacitanceb
1.8
2.4
pF
RI ,RQ
RSL RQ pins - effective input resistance
4
18
Ω
L12,RQ
Mutual inductance between adjacent RSL RQ signals
-
1.8
nH
ΔLI,RQ
Difference in LI,RQ between any RSL RQ pins of a single device
-
1.8
nH
ΔCI,RQ
Difference in CI between CFM/CFMN average and RSL RQ pins of single device
-0.25
+0.25
pF
ZPKG,DQ
DRSL DQ pins - package differential impedance
note - package trace length should be less than 10mm long.
70
130
Ω
CI ,DQ
DRSL DQ pins - effective input capacitancea
-
-
1.5
pF
ΔCI,DQ
Difference in CI between DQi and DQNi of each DRSL paira, c
-
-
0.06
pF
RI ,DQ
DRSL DQ pins - effective input resistance
4
40
Ω
LI ,SI
Serial Interface effective input inductanceb
-
8.0
nH
CI ,SI
Serial Interface effective input capacitanceb
-
3.0
7.0
pF
pF
(RST, SCK, CMD)
(SDI,SDO)
a. This is the effective die input capacitance, and does not include package capacitance.
b. CFM/RQ/SI should include package capacitance / Inductance, only DQ does not include package Capacitance. This value is a combination of the device IO circuitry and package capacitance & inductance.
c. Parameter not measured, guaranteed by design.
Data Sheet E1819E20 (Ver. 2.0)
79
EDX1032BBBG
Figure 55
Equivalent Circuits for Package Parasitic
Pad
RQ Pin
CI,RQ
L12,RQ
LI,RQ
RQ Pin
L12,RQ
RQ Pin
RI,RQ
GND Pin
Pad
Pad
CI,DQ
CI,DQ
RI,DQ
RI,DQ
ZPKG,DQ/2
DQ Pin
ZPKG,DQ/2
DQN Pin
RTERM,DQ
RTERM,DQ
GND Pin
Pad
LI,CFM
Pad
CFM Pin
LI,CFM
CI,CFM
RI,CFM
CFMN Pin
CI,CFM
RI,CFM
GND Pin
Pad
LI,SI
SCK,CMD,RST Pin
SDI,SDO Pin
CI,SI
GND Pin
Data Sheet E1819E20 (Ver. 2.0)
80
EDX1032BBBG
Package Drawing
150-ball FBGA
•
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
15.5 ± 0.10
0.20 S B
15.5 ± 0.10
INDEX MARK
0.20 S A
1.15 max.
0.10 S
S
0.40 ± 0.05
0.10 S
150−φ0.5 ± 0.05
B
φ0.12 M S A B
INDEX MARK
2.0
14.0
1.0
A
1.0
14.0
ECA-TS2-0427-01
Data Sheet E1819E20 (Ver. 2.0)
81
EDX1032BBBG
Package Pin Numbering
Figure 56 summarizes the x32 bits device package’s pin assignments.
Figure 56
x32 Package - Pin Numbering (top view)
R
not used when
width is x1,x2,x4
P
N
M
1
L
DQN25
DQ5
GND
DQ25
GND
1
DQN31
DQN19
DQN21
2
DQ31
DQ19
DQ21
not used when
width
isDQN15
x1
3
P
N
DQN3
DQN5
M
4
DQ15
DQ3
DQ5
GND
DQN9
DQ1
DQ9
L
GND
K
VDD
7
J
VDD
8
H
G
5
GND
GND
VDD
6
VDD
VDD
VTERM
9
10
VDD
VTERM
VDD
F
11
GND
GND
GND
E
12
DQN7
DQN11
DQN13
13
DQ7
DQ11
DQ13
14
DQN23
DQN27
DQN29
GND
2
K
DQ5N GND
3
J
H
4
VDD
G
GND
5
F
6E
D
VDD
VDD
DQ7N
GND
C
B
DQN24
DQ7
DQN20
DQN18
DQN30
MBa
DQ24
DQ20
DQ18
DQ30
SDI
DQN8
DQN4
not used when
is x1,x2
DQN2 width
DQN14
VTERM
VDD
RQ10
CFM
RQ3
DQ3N
DQ1N
VDD
RQ11
CFMN
RQ4
RQ0
VDD
RQ11
RQ10
GND
VDD
GND
GND
DQ3
DQ8
GND
VDD
RQ6
RQ7
GND
VREF
RQ4
CFMN
CFM
GND
RQ2
RQ5
GND
VTERM
VDD
GND
GND
DQN1
D
SD0
C
DQN17
GND
GND
VDD
GND
GND
GND
VDD
VDD
GND
GND
GND
VDD
GND
VREF
VDD
RQ1
RST
CMD
CMD
DQ1
SCK
DQ0
MBa
GND
RQ3
RQ0
RQ9
RQ7
RQ8
RQ6
RQ1
RQ5
RQ2
RST
SCK
SDO
DQ2N
MBa
DQ0N
VTERM
82
DQ2
DQ14
VDD
GND
GND
VTERM
VDD
VDD
VDD
VTERM
VDD
GND
GND
GND
DQN12
DQN10
DQN6
DQ12
DQ10
DQN28
DQN26
DQ28
DQ26
VDD
GND
GND
DQN0
SDI
DQ0
DQ2
DQN16
15
DQ29
DQ17
GND
VDD
GND
VDD VTERM
VDD
DQ16
GND
GND
VDD VDD
B
not
usedDQ23
when DQ27
width is x1,x2,x4
a. Mechanical Ball (Optional). Other vendor may have optional balls in E2, L14, E14. Elpida 1Gb XDR has no MBs.
DQ6N
DQ6
DQ4
DQ4N
Board layout must includeAsolder land pads at these locations.
Data Sheet E1819E20 (Ver. 2.0)
DQ4
GND
RQ9
VTERM
RQ8
VTERM
A when
not used
width is x1,x2,x4
7
not used
when
DQ6
width is x1,x2
DQN22
DQ22
not used
when
width is x1,x2,x4
EDX1032BBBG
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions
of the EDX1032BBBG.
Type of Surface Mount Device
EDX1032BBBG: 150-ball FBGA
< Lead free (Sn-Ag-Cu) >
Data Sheet E1819E20 (Ver. 2.0)
83
EDX1032BBBG
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E1819E20 (Ver. 2.0)
84
EDX1032BBBG
Rambus and the Rambus Logo are trademarks or registered trademarks of Rambus Inc. in the United States and other countries.
Rambus and other parties may also have trademark rights in other terms used herein.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, this product is not intended for use in the product in aerospace, aeronautics, nuclear power,
combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other
such application in which especially high quality and reliability is demanded or where its failure or
malfunction may directly threaten human life or cause risk of bodily injury. Customers are instructed to
contact Elpida Memory's sales office before using this product for such applications.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 ,
SO 2 , and NO x .
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E1007
Data Sheet E1819E20 (Ver. 2.0)
85