EM EM6125 Digitally programmable 65 and 81 multiplex rate lcd controller and driver Datasheet

EM MICROELECTRONIC - MARIN SA
EM6125
Digitally programmable 65 and 81 multiplex rate LCD
Controller and Driver
Features
Typical Applications
Slim IC for COG, COF and COB technologies
2
I C & Serial bus interface
Internal display data RAM
2 digitally programmable multiplex rates :
81 rows x 102 columns
65 rows x 118 columns
LCD supply voltage internally generated and digitally
programmable from 3V to 11V
Low operating current consumption: 120µA (typ)
No external components needed except one VLCD
capacitor
On chip
4 intermediate bias voltages generation
Oscillator for LCD refresh (no external components
required)
High noise immunity on inputs
Row and column drivers mirroring for COG or COF
connections flexibility
Partial display mode with 17 active rows for current
consumption reduction
Sleep mode for a nearly null current consumption
Wide VDD supply voltage from 1.8V to 5V.
Wide temperature range: -40°C to +85°C
Mobile phones
Smart cards
Automotive displays
Portable, battery operated products
Balances and scales, utility meters
Typical Operating Configuration
40 row drivers
41 row drivers
102 columns outputs
EM6125
VLCD
SCL SDA RES Vss1 Vss2 VDD1
VDD2
VHV
Figure 1
Pin Configuration
Description
The EM6125 is a bit map controller and driver for full dot
matrix monochrome STN LCD displays. The driving
capability is 81 rows x 102 columns (10 rows of
characters + one row of icons) or 65 rows x 118 columns
(8 rows of characters + one row of icons). There is a one
to one relation between LCD pixels and bits of the
Display Data RAM.
The EM6125 is extremely low power consumption LCD
controller and driver product. The typical current
consumption is about 120µA with no external component
except the capacitor connected to VLCD. One important
feature on EM6125 is the partial display mode, which
enables important current consumption reduction. With
this function selected, only 17 rows remain active,
needed VLCD decreases and the commutation
frequencies of row and column drivers are also
decreased. These three effects of partial display mode
reduce drastically current consumption.
Figure 2
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EM6125
Features
1
Description
1
Typical Applications
Typical Operating Configuration
Pin Configuration
1
1
1
1 Absolute Maximum Ratings
4
2 Handling Procedures
4
3 Operating Conditions
4
4 Electrical Characteristics
4
5 Timing Characteristics
5.1 Timing Waveforms
5
7
6 Block diagram
9
7 Pin description
10
8 Functional description
8.1 Selection of interface type
8.2 Serial interface
2
8.3 I C interface
8.3.1 Start and stop conditions
8.3.2 Bit transfer
8.3.3 Acknowledge
2
8.4 I C protocol
8.4.1 Write mode
8.4.2 Read Mode (RW = 1)
8.5 Display Data RAM
8.5.1 DDRAM description
8.5.2 DDRAM addressing
8.6 Initialization of EM6125
8.7 Description of instructions
8.7.1 Initialization 0
8.7.1.1 Mux Mode
8.7.1.2 TC[1:0]
8.7.1.3 Inv. Row
8.7.1.4 MX
8.7.1.5 Blank
8.7.1.6 Checker
8.7.1.7 Inv. Video
8.7.2 Initialization 1
8.7.2.1 X[6:0]
8.7.2.2 V
8.7.3 Initialization 2
8.7.3.1 Y[3:0]
8.7.3.2 Vlcd Dischg.
8.7.3.3 DEC
8.7.3.4 LSB
8.7.4 Initialization 3
8.7.4.1 Vlcd Level[7:0]
8.7.5 Initialization 4
8.7.5.1 Mult[1:0]
8.7.5.2 Partial Display
8.7.5.3 First Row PD[3:0]
11
11
11
13
13
13
13
13
13
14
14
14
18
23
24
24
24
24
25
26
26
26
26
28
28
28
28
28
28
28
28
28
28
29
29
29
29
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EM6125
8.7.5.4 Sleep
8.7.6 Test 0 to 3
8.8 LCD outputs
8.9 LCD refresh frequency
8.10 VLCD depending on VHV
8.11 LCD driver waveforms
8.11.1 Partial Display
29
29
30
31
31
32
34
9 Typical Application
35
10 Pad location
39
11 Ordering Information
42
12 Updates
43
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EM6125
1 Absolute Maximum Rating s
Parameter
Supply voltage range
Supply voltage range
Supply voltage range
All input voltages
Voltages at S0 to S184
Storage temperature
range
Electrostatic discharge
max. to MIL-STD-883C
method 3015
Maximum soldering
conditions
2 Handling Procedures
Symbol
VDD1,2
VHV
VLCD
VLOGIC
VDISPLAY
TSTO
Conditions
-0.3V to +6V
-0.3V to +6V
VHV-0.3V to +12V
-0.3V to VDD1,2+0.3V
-0.3V to VLCD + 0.3V
-65°C to +150 °C
VESD
1000V
TSMAX
250°C × 10 s
This device has built-in protection against high static
voltages or electric fields; however, anti-static
precautions should be taken as for any other CMOS
components. Unless otherwise specified, proper
operation can only occur when all terminal voltages are
kept within the supply voltage range.
3 Operating Conditions
Parameter
Operating
temperature
Logic supply
voltage
High voltage
generator
supply voltage
LCD supply
voltage
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond
specified electrical characteristics may affect device
reliability or cause malfunction.
Symbol
TA
Min.
-40
Typ.
Max.
+85
°C
VDD1,2
1.8
2.5
5.5
V
VHV
2.4 *
2.5
5.5
V
VLCD
3
8
11
V
* Lower VHV voltage is possible until the required VLCD voltage is reached.
4 Electrical Characteristics
VSS1,2 = 0V, VDD1 = VDD2 = 1.8V, VHV = 2.4V, unless otherwise specified. TA = -40°C to +85 °C unless otherwise specified.
Minimum required capacitor: 1µF on VLCD, 100nF on VDD1,2 and VHV.
Parameter
Symbol
Test conditions
Min.
Typ.
Max.
Units
Supply Current
Sleep mode
Sleep mode
Normal LCD refresh mode
Normal LCD refresh mode
Partial LCD refresh mode
Control Input Signals
IDD
IHV
IDD
IHV
IHV
Sleep = 1
Sleep = 1
(note 1)
(note 2)
(note 3)
Input leakage
Input capacitance
Low level input voltage
High level input voltage
LCD Outputs
Internally generated LCD
supply voltage
IIN
CIN
VIL
VIH
Vi = Vss1 or VDD1
10
0.5
15
124
50
-1
nA
21
180
87
1
8
0.3xVDD1
0.7xVDD1
µA
µA
µA
µA
µA
pF
V
V
VLCD 00000000b
3.02
V
VLCD 10001110b
8.02
V
35.2
mV
VLCD step between 2
consecutive programmed
VLCD Level
VLCD step
V bias tolerance
V bias tol.
(note 5)
-80
80
mV
Note 1: Measured on VDD1 + VDD2, all outputs open, SDA and SCL at VSS, RES at VDD1, multiplex rate 81, x5 voltage
multiplier, VLCD = 10001110b, DDRAM loaded with checker pattern
Note 2: Measured on VHV, same conditions as (note 1).
Note 3: Measured on VHV, all outputs open, SDA and SCL at VSS, RES at VDD1, partial display mode, × 2 voltage multiplier,
VLCD = 00101011b, DDRAM loaded with checker pattern.
Note 4: With internal voltage multiplier, the maximum VLCD voltage depends on VHV, programmed voltage multiplier and
display load.
Note 5: V1, V2, V3 and V4 bias levels measured with VLCD = 7V, on 1 LCD row driver output and 1 LCD column driver
output, multiplex rate 81, TA = 25 °C, load = ±10µA.
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EM6125
5 Timing Characteristics
VSS1,2 = 0V, VDD1 = VDD2 = 1.8V, VHV = 2.4V, TA = -40°C to +85 °C unless otherwise specified.
Parameter
Symbol
Internal frame frequency
for LCD refresh
fFR
Minimum reset pulse width
tRW
Test conditions
Min.
Typ.
Max.
75 x
mux
(note 1)
Units
Hz
70
ns
I2C timing characteristics
SCL frequency
fI2C
1600
kHz
SCL low period
tLOW
350
ns
SCL high period
tHIGH
100
ns
SDA setup time
tSUDAT
10
ns
SDA hold time
tHDDAT
20
ns
SCL and SDA rise time
tR
200
ns
SCL and SDA fall time
tF
200
ns
Setup time for a repeated
start condition
tSUSTA
20
ns
Hold time for a
start condition
tHDSTA
20
ns
Setup time for a
stop condition
tSUSTO
20
ns
Spike width on SCL and SDA
tSW
20
Time before a new transmission can start
tBUF
Capacitive bus line load
Cb
400
pF
SCL frequency
fSER
4
MHz
SCL low period
tCL
70
ns
SCL high period
tCH
130
ns
SDA setup time
tDS
20
ns
SDA hold time
tDH
50
ns
SCL rise time
tCR
200
ns
SCL fall time
tCF
200
ns
100
ns
ns
Serial bus timing characteristics
CS setup time
tSUCS
10
ns
CS hold time
tHDCS
130
ns
Time before a new transmission can
start, CS minimum high time.
tBUFCS
70
ns
Note 1: Measured on pad FR.
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EM6125
VSS1,2 = 0V, VDD1 = VDD2 = 2.5V, VHV = 2.4V, TA = -40°C to +85 °C unless otherwise specified.
Parameter
Minimum reset pulse width
Symbol
Test conditions
tRW
Min.
Typ.
Max.
Units
2100
kHz
50
I2C timing characteristics
SCL frequency
fSCL
SCL low period
tLOW
190
ns
SCL high period
tHIGH
60
ns
SDA setup time
tSUDAT
10
ns
SDA hold time
tHDDAT
20
ns
SCL and SDA rise time
tR
200
ns
SCL and SDA fall time
tF
200
ns
Setup time for a repeated
start condition
tSUSTA
20
ns
Hold time for a
start condition
tHDSTA
20
ns
Setup time for a
stop condition
tSUSTO
20
ns
Spike width on SCL and SDA
tSW
10
Time before a new transmission can start
tBUF
Capacitive bus line load
Cb
400
pF
SCL frequency
fSCL
5.2
MHz
SCL low period
tCL
50
ns
SCL high period
tCH
80
ns
SDA setup time
tDS
15
ns
SDA hold time
tDH
40
ns
SCL rise time
tCR
200
ns
SCL fall time
tCF
200
ns
40
ns
ns
Serial bus timing characteristics
CS setup time
tSUCS
10
ns
CS hold time
tHDCS
80
ns
Time before a new transmission can
start, CS minimum high time.
tBUFCS
50
ns
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EM6125
5.1 Timing Waveforms
SDA
SCL
Data line
stable, data
valid
Change of
data allowed
Figure 3: I2C 1 bit transfer
SDA
SCL
S
P
Start condition
Stop condition
Figure 4: I2C start and stop conditions
SDA
By transmitter
Not Acknowledge
SDA
By receiver
Acknowledge
SCL
1
2
8
9
S
Start condition
Clock pulse for
acknowledgement
Figure 5: Acknowledgement on the I2C bus
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EM6125
SDA
tBUF
tf
tLOW
SCL
tHIGH
tHDSTA
tr
tHDDAT
tSUDAT
SDA
tSUSTA
tSUSTO
Figure 6: I2C timing diagram.
Data stable, data valid
Change of data allowed
SDA
SDA sampled on SCL falling edge
SCL
Data input
setup time
Data input
hold time
Data input
setup time
Data input
hold time
Figure 7: Serial interface, 1 bit transfer.
tDH
tDS
SDA
tcf
tCL
SCL
tCH
tcr
tBUFCS
tSUCS
tHDCS
CS
Figure 8: Serial interface timing diagram.
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EM6125
6 Block diagram
S0 to S183
Voltage Multiplier
Intermediate
voltages generation
VHV
LCD levels selection
Gating
VLCD
1 uF external
capacitor
Internal Oscillator
Blank, Video, Checker
81 bits sequenceur
001000…000
Display Data RAM
1x118
8x(8x118)
2x(8x102)
VDD1
DB7 to DB0
VDD2
y-address
x-address
VSS
RES
I2C / serial 3 wires
interface
SDA
SCL
CS
x-address and y-address
generator
I
Figure 9: Block diagram.
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EM6125
7 Pin description
Symbol
Pad Type
Description
S0 to S183
Output
LCD driver outputs
S0 to S32 and S151 to S183
Output
LCD row driver outputs
S0 = S184
S33 to S40
and S143 to S150
S41 to S142
Output
Output
LCD row driver outputs when multiplex rate 81 is selected
LCD column driver outputs when multiplex rate 65 is selected
LCD column driver outputs
VHV
Positive power supply
Supply voltage for internal voltage multiplier
VDD1,2
Positive power supply
Supply voltage for logical and analog parts
VSS1,2
Ground power supply
Ground power supply
I
Input
Interface protocol selection input
RES
Input
External reset input, active low
CS
Input
Chip select input
FR
Input/output
Frame frequency input/output
TEST
Input/output
Test
SDA
Input/output
Serial data input
SCL
Input
Serial clock
VLCD
Positive power supply
LCD supply voltage
Table 1: Pin description
S0 to S183:
Connected to LCD electrodes, it should be left open if not used. S0 and S183 are internally connected
together.
VHV:
Supply voltage for internal voltage multiplier, it could be a different voltage value than for VDD1,2.
VDD1,2:
Logic and analog power supplies. VDD1 and VDD2 are not connected inside EM6125 but have to be
connected outside to the same potential. For chip on glass application, it is advised to keep VDD1 and VDD2
separated until their connection to 1 µF capacitor.
VSS1,2:
Ground supply for logic and high voltage generator. VSS1 is connected to substrate. Same precautions
than for VDD1,2 should be taken to connect these pads.
I:
Selects the chosen interface protocol. For chip on glass applications, it can be directly connected to VSS1
or VDD1 on glass.
RES:
External reset, a reset cycle must be applied at power on (reset at low level when power on).
CS:
Active low chip select, when serial interface is used it enables data transfer. If I C is used, it must be
connected at VSS1 or VDD1 pads.
FR:
Outputs LCD refresh frame frequency, used for test. It must be left open.
TEST:
Test pad, it must be left open.
SDA:
Serial data input used for I C interface as for 3 wires serial interface.
SCL:
Serial clock input used to latch SDA for I C interface as for 3 wires serial interface.
VLCD:
LCD voltage supply (generation of LCD waveforms applied to S0 to S183). It is normally internally
generated from VHV supply voltage. 1 µF capacitor is required between VLCD and VSS. External power
supply is also possible; in this configuration VLCD must be programmed at its lower value and VHV
connected to VSS2.
2
2
2
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EM6125
8 Functional description
8.1 Selection of interface type
There are two different serial interfaces available on EM6125. Selection depends on logical value applied on pad I.
If I = 0, serial interface is selected: 3 wires with Chip Select CS, Serial Clock SCL and Serial Data SDA.
2
If I = 1, I C protocol is selected: 2 wires with Serial Clock SCL and Serial Data SDA. CS must be connected to VSS
or VDD1.
I
0
1
Interface
3 wires serial interface
2
IC
Table 2: Interface selection
8.2 Serial interface
The serial interface consists of 3 wires: Chip Select CS, Serial Clock SCL and Serial Data SDA. The information is
exchanged byte-wide and is shifted serially in the LCD driver at SCL fall edge.
SDA
Data sampled on SCL fall edge
SCL
Data stable, data valid
Change of data allowed
Figure 10: Serial interface, 1 bit transfer
Transfer of data is unidirectional from micro controller to EM6125. When CS is activated at low level the communication is
enabled and must stay low for the rest of the transaction. Data transfer begins with one control byte. This control bytes is
transferred MSB first, it consists in:
MSB
C0
LSB
DC Test[2] Test[1] Test[0]
Ini[2]
Ini[1]
Ini[0]
C0 is the continuation bit:
If C0 = 1, the control byte is followed by 1 data byte only, the next byte is a new control byte.
If C0 = 0, all the following bytes are data bytes until data transfer is stopped.
DC selects data bytes or command bytes to be send after the control byte:
If DC = 1, the following data byte(s) is (are) written in the Display Data RAM. First data byte is stored at the
address specified by the x-address and y-address pointers. Data pointers are automatically updated for each byte
written in the DDRAM (see DDRAM description).
IF DC = 0, the following data byte is a command byte. It enables initialization of functions (multiplex rate, number
of voltage multiplier stages, VLCD programming, partial display settings…).
Bits ini2, ini1 and ini0 select the initialization register to be set by the following command byte (see Table 4: EM6125
instructions).
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EM6125
CS
start
Control Byte
C0 = 1
stop
Data Byte
Control Byte
Data Byte
Control Byte
Data Byte
Command byte
C0 = 1
DDRAM Data byte
C0 = 0
DDRAM Data byte
DC = 0
DC = 1
2n bytes
DC = 1
n bytes
2n bytes
Figure 11: serial interface protocol
Data byte is transferred with MSB bit first, LSB bit last:
MSB
LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
If CS goes high during a byte transfer, this byte is invalid but all previously transmitted data are valid. While CS is high the
serial interface is kept in reset that means internal interface counter and disables data transfer. To prevent transmission
errors, CS should be at high level when transfer is stopped.
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EM6125
2
8.3 I C interface
2
2
The EM6125 can be interfaced with a slave I C protocol (see description I2C protocol). The I C bus consists in 2 wires: SCL
(Serial Clock Line) and SDA (Serial Data Line). Both lines must be connected to VDD1,2 via a pull up resistor. EM6125 pad
SCL is input, pad SDA is bi-directional with pull down open drain. EM6125 supports initialization and RAM write and status
read access.
8.3.1 Start and stop conditions
2
Data transfer begins by a falling edge on SDA when SCL is at high level, this is the start condition (S), initiated by the I C
bus master. It is stopped with a rising edge on SDA and SCL at high level, this is the stop condition (P) (see Figure 4: I2C
start and stop conditions).
8.3.2 Bit transfer
One data bit is transferred during each SCL pulse. The data on the SDA line must remain stable during the high period of
SCL pulses, as any changes at this time would be interpreted as start or stop conditions. Data is always transferred with
MSB first.
8.3.3 Acknowledge
After a start condition, data bits are transferred to EM6125. Each byte is followed by an acknowledge bit: the transmitter let
the SDA line high (no pull down) and generates a high SCL pulse; if transfer concerns the EM6125 slave receiver and has
performed correctly, it generates a low SDA level (pull down activated). SDA remains stable during the high period of the
acknowledge related SCL pulse. After acknowledge, EM6125 let SDA line free, enabling the transmitter to continue transfer
or to generate a stop condition.
2
8.4 I C protocol
The EM6125 has a slave address, coded on 7 bits: 0000000.
After a start condition, the slave address + RW bit must be send first. If the slave address does not match with the EM6125
ones there is no acknowledge from LCD driver and the following data transfer will not affect the chip.
If the slave address corresponds to EM6125 slave address, it will acknowledge (pull SDA down to logical low level) and
data transfer is enabled.
The 8th bit RW sets the chip in write mode or read status mode, it is read for data transfer.
8.4.1 Write mode
If RW = 0, EM6125 is accessed by the micro controller.
Data transfer bytes can be either control bytes or data bytes. Data transfer always begins with a control byte (described in
fig.1). It sets bits C0, DC, ini2, ini1 and ini0.
C0 is the continuation bit:
If C0 = 1, the control byte is followed by 1 data byte only, the next byte is a new control byte.
If C0 = 0, all the following bytes are data bytes until data transfer is stopped.
DC selects data bytes or command bytes to be send after the control byte:
If DC = 1, the following data byte(s) is (are) written in the Display Data RAM. First data byte is stored at the
address specified by the x-address and y-address pointers. Data pointers are automatically updated for each byte
written in the DDRAM (see DDRAM description).
IF DC = 0, the following data byte is a command byte. It enables initialization of functions (multiplex rate, number
of voltage multiplier stages, VLCD programming, partial display settings…).
Bits ini2, ini1 and ini0 select the initialization register to be set by the following command byte (see Table 4: EM6125
instructions).
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EM6125
8.4.2 Read Mode (RW = 1)
EM6125 will output one status byte after slave address. This status byte consists in 8 initialization bits previously set by
command bytes or the reset cycle (see Table 4: EM6125 instructions).
First byte send:
Control Byte:
MSB
0
0
0
0
0
0
RW
0
Data Byte:
LSB
C0
MSB
DC Test[2]Test[1]Test[0] Ini[2] Ini[1] Ini[0]
A
LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A
EM6125
Slave Address
W rite mode:
Acknowledge
from EM 6125
S
0
0
0
0
0
0
0
0
A
Acknowledge
from EM 6125
Control Byte
1
Acknowledge
from EM6125
Data Byte
A
A
Acknowledge
from EM6125
Control Byte
0
2n ≥ 0 bytes
Slave
Address
1 byte
C0
A
Acknowledge
from EM6125
Data Byte
A
P
n ≥ 0 bytes
C0
W rite
M ode
Read mode:
Acknowledge
from EM6125
S
0
0
0
0
0
0
0
1
A
1
Acknowledge
from master
A
Status Byte
P
Slave
Address
Figure 12: I2C protocol description
8.5 Display Data RAM
The EM6125 contains a RAM, which stores the display data; there is a one to one correspondence between the bit stored in
the RAM and one LCD pixel.
8.5.1 DDRAM description
DDRAM consists in:
1 bank of 118 bits (row 0)
8 banks of 118 bytes (rows 1 to 64)
2 banks of 102 bytes (rows 65 to 80)
DDRAM is read row by row for display refresh. Each row corresponds to one pad, which is activated when the
corresponding row is read.
DDRAM is accessed via the interface. Bytes are stored at the column specified by x-address pointer and the bank specified
by y-address pointer. These pointers are set by the corresponding instruction “Initialization 1” and “Initialization 2” and are
automatically incremented or decrement after each byte written in the DDRAM (see
DDRAM addressing and Table 5: Internal functions after reset.)
For bank 0 only data byte 7 (DB7) is stored in row 0, DB6 to DB0 are not used. For bank 1 to 10 (y-address = 1 to 10), DBX
is stored at row ((8 x y-address)-X).
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EM6125
If Mux Mode = 0, the DDRAM provides a 65 rows and 118 columns matrix.
Bank 9 and 10 are not used for display refresh, the cells can not be addressed.
0
0
Bank 0
Bank 1
8
Bank 8
- - - - - - - - - - - - - - - - - - - - - - - x-address - - - - - - - - - - - - - - - - - - - - - - -
117
DB7 DB7 DB7
DB7 DB7 DB7 DB7
DB7 DB7 DB7
DB7
DB7
DB7 DB7 DB7
DB7 DB7 DB7 DB7
DB7 DB7 DB7
DB7 DB7 DB7
DB7 DB7 DB7 DB7
DB7 DB7 DB7
DB7
DB7
DB7 DB7 DB7
DB7 DB7 DB7 DB7
DB7 DB7 DB7
DB6 DB6 DB6
DB6 DB6 DB6 DB6
DB6 DB6 DB6
DB6
DB6
DB6 DB6 DB6
DB6 DB6 DB6 DB6
DB6 DB6 DB6
DB5 DB5 DB5
DB5 DB5 DB5 DB5
DB5 DB5 DB5
DB5
DB5
DB5 DB5 DB5
DB5 DB5 DB5 DB5
DB5 DB5 DB5
DB4 DB4 DB4
DB4 DB4 DB4 DB4
DB4 DB4 DB4
DB4
DB4
DB4 DB4 DB4
DB4 DB4 DB4 DB4
DB4 DB4 DB4
DB3 DB3 DB3
DB3 DB3 DB3 DB3
DB3 DB3 DB3
DB3
DB3
DB3 DB3 DB3
DB3 DB3 DB3 DB3
DB3 DB3 DB3
DB2 DB2 DB2
DB2 DB2 DB2 DB2
DB2 DB2 DB2
DB2
DB2
DB2 DB2 DB2
DB2 DB2 DB2 DB2
DB2 DB2 DB2
DB1 DB1 DB1
DB1 DB1 DB1 DB1
DB1 DB1 DB1
DB1
DB1
DB1 DB1 DB1
DB1 DB1 DB1 DB1
DB1 DB1 DB1
DB0 DB0 DB0
DB0 DB0 DB0 DB0
DB0 DB0 DB0
DB0
DB0
DB0 DB0 DB0
DB0 DB0 DB0 DB0
DB0 DB0 DB0
DB7 DB7 DB7
DB7 DB7 DB7 DB7
DB7 DB7 DB7
DB7
DB7
DB7 DB7 DB7
DB7 DB7 DB7 DB7
DB7 DB7 DB7
DB6 DB6 DB6
DB6 DB6 DB6 DB6
DB6 DB6 DB6
DB6
DB6
DB6 DB6 DB6
DB6 DB6 DB6 DB6
DB6 DB6 DB6
DB5 DB5 DB5
DB5 DB5 DB5 DB5
DB5 DB5 DB5
DB5
DB5
DB5 DB5 DB5
DB5 DB5 DB5 DB5
DB5 DB5 DB5
DB4 DB4 DB4
DB4 DB4 DB4 DB4
DB4 DB4 DB4
DB4
DB4
DB4 DB4 DB4
DB4 DB4 DB4 DB4
DB4 DB4 DB4
DB3 DB3 DB3
DB3 DB3 DB3 DB3
DB3 DB3 DB3
DB3
DB3
DB3 DB3 DB3
DB3 DB3 DB3 DB3
DB3 DB3 DB3
DB2 DB2 DB2
DB2 DB2 DB2 DB2
DB2 DB2 DB2
DB2
DB2
DB2 DB2 DB2
DB2 DB2 DB2 DB2
DB2 DB2 DB2
DB1 DB1 DB1
DB1 DB1 DB1 DB1
DB1 DB1 DB1
DB1
DB1
DB1 DB1 DB1
DB1 DB1 DB1 DB1
DB1 DB1 DB1
DB0 DB0 DB0
DB0 DB0 DB0 DB0
DB0 DB0 DB0
DB0
DB0
DB0 DB0 DB0
DB0 DB0 DB0 DB0
DB0 DB0 DB0
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 9
Row 10
Row 55
Row 56
Row 57
Row 58
Row 59
Row 60
Row 61
Row 62
Row 63
Row 64
Bank 9
Rows
not used
Bank 10
Rows
not used
Figure 13: DDRAM description with Mux Mode = 0 and LSB = 0
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If Mux Mode = 1, the DDRAM provides a 81 rows and 102 columns matrix.
8 columns on the left + 8 columns on the right are not used for display refresh, the cells can not be addressed.
0
- - - - x-address - - - -
101
Columns not used
0
Bank 0
Bank 1
Bank 8
Bank 9
10
Bank 10
Columns not used
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB6
DB6
DB6
DB6
DB6
DB6
DB5
DB5
DB5
DB5
DB5
DB5
DB4
DB4
DB4
DB4
DB4
DB4
DB3
DB3
DB3
DB3
DB3
DB3
DB2
DB2
DB2
DB2
DB2
DB2
DB1
DB1
DB1
DB1
DB1
DB1
DB0
DB0
DB0
DB0
DB0
DB0
DB7
DB7
DB7
DB7
DB7
DB7
DB6
DB6
DB6
DB6
DB6
DB6
DB5
DB5
DB5
DB5
DB5
DB5
DB4
DB4
DB4
DB4
DB4
DB4
DB3
DB3
DB3
DB3
DB3
DB3
DB2
DB2
DB2
DB2
DB2
DB2
DB1
DB1
DB1
DB1
DB1
DB1
DB0
DB0
DB0
DB0
DB0
DB0
DB7
DB7
DB7
DB7
DB7
DB7
DB6
DB6
DB6
DB6
DB6
DB6
DB5
DB5
DB5
DB5
DB5
DB5
DB4
DB4
DB4
DB4
DB4
DB4
DB3
DB3
DB3
DB3
DB3
DB3
DB2
DB2
DB2
DB2
DB2
DB2
DB1
DB1
DB1
DB1
DB1
DB1
DB0
DB0
DB0
DB0
DB0
DB0
DB7
DB7
DB7
DB7
DB7
DB7
DB6
DB6
DB6
DB6
DB6
DB6
DB5
DB5
DB5
DB5
DB5
DB5
DB4
DB4
DB4
DB4
DB4
DB4
DB3
DB3
DB3
DB3
DB3
DB3
DB2
DB2
DB2
DB2
DB2
DB2
DB1
DB1
DB1
DB1
DB1
DB1
DB0
DB0
DB0
DB0
DB0
DB0
DB7
DB7
DB7
DB7
DB7
DB7
DB6
DB6
DB6
DB6
DB6
DB6
DB5
DB5
DB5
DB5
DB5
DB5
DB4
DB4
DB4
DB4
DB4
DB4
DB3
DB3
DB3
DB3
DB3
DB3
DB2
DB2
DB2
DB2
DB2
DB2
DB1
DB1
DB1
DB1
DB1
DB1
DB0
DB0
DB0
DB0
DB0
DB0
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 9
Row 10
Row 55
Row 56
Row 57
Row 58
Row 59
Row 60
Row 61
Row 62
Row 63
Row 64
Row 65
Row 66
Row 67
Row 68
Row 69
Row 70
Row 71
Row 72
Row 73
Row 74
Row 75
Row 76
Row 77
Row 78
Row 79
Row 80
Figure 14: DDRAM description with Mux Mode = 1 and LSB = 0
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If Mux Mode = 1 and LSB=1.
0
- - - - x-address - - - -
101
Columns not used
0
Bank 0
Bank 1
Bank 8
Bank 9
10
Bank 10
Columns not used
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB1
DB1
DB1
DB1
DB1
DB1
DB2
DB2
DB2
DB2
DB2
DB2
DB3
DB3
DB3
DB3
DB3
DB3
DB4
DB4
DB4
DB4
DB4
DB4
DB5
DB5
DB5
DB5
DB5
DB5
DB6
DB6
DB6
DB6
DB6
DB6
DB7
DB7
DB7
DB7
DB7
DB7
DB0
DB0
DB0
DB0
DB0
DB0
DB1
DB1
DB1
DB1
DB1
DB1
DB2
DB2
DB2
DB2
DB2
DB2
DB3
DB3
DB3
DB3
DB3
DB3
DB4
DB4
DB4
DB4
DB4
DB4
DB5
DB5
DB5
DB5
DB5
DB5
DB6
DB6
DB6
DB6
DB6
DB6
DB7
DB7
DB7
DB7
DB7
DB7
DB0
DB0
DB0
DB0
DB0
DB0
DB1
DB1
DB1
DB1
DB1
DB1
DB2
DB2
DB2
DB2
DB2
DB2
DB3
DB3
DB3
DB3
DB3
DB3
DB4
DB4
DB4
DB4
DB4
DB4
DB5
DB5
DB5
DB5
DB5
DB5
DB6
DB6
DB6
DB6
DB6
DB6
DB7
DB7
DB7
DB7
DB7
DB7
DB0
DB0
DB0
DB0
DB0
DB0
DB1
DB1
DB1
DB1
DB1
DB1
DB2
DB2
DB2
DB2
DB2
DB2
DB3
DB3
DB3
DB3
DB3
DB3
DB4
DB4
DB4
DB4
DB4
DB4
DB5
DB5
DB5
DB5
DB5
DB5
DB6
DB6
DB6
DB6
DB6
DB6
DB7
DB7
DB7
DB7
DB7
DB7
DB0
DB0
DB0
DB0
DB0
DB0
DB1
DB1
DB1
DB1
DB1
DB1
DB2
DB2
DB2
DB2
DB2
DB2
DB3
DB3
DB3
DB3
DB3
DB3
DB4
DB4
DB4
DB4
DB4
DB4
DB5
DB5
DB5
DB5
DB5
DB5
DB6
DB6
DB6
DB6
DB6
DB6
DB7
DB7
DB7
DB7
DB7
DB7
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
Row 9
Row 10
Row 55
Row 56
Row 57
Row 58
Row 59
Row 60
Row 61
Row 62
Row 63
Row 64
Row 65
Row 66
Row 67
Row 68
Row 69
Row 70
Row 71
Row 72
Row 73
Row 74
Row 75
Row 76
Row 77
Row 78
Row 79
Row 80
Figure 15: DDRAM description with Mux Mode = 1 and LSB = 1
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EM6125
8.5.2 DDRAM addressing
The x-address and the y-address pointers are used to address RAM cells. They are set by instructions “initialization 1” and
“initialization 2”. As EM6125 offers 2 digitally programmable multiplex rates, number of row drivers and number of column
drivers are not fixed.
As DDRAM is an image of LCD display, address ranges also depend on multiplex rate (Mux Mode):
If Mux Mode = 0:
If Mux Mode = 1:
0 ≤ x-address ≤ 117
0 ≤ y-address ≤ 8
0 ≤ x-address ≤ 101
0 ≤ y-address ≤ 10
Addresses outside these ranges are not allowed.
There are three functions that affects the pointers: DEC, V and MX. They are set by instructions “initialization 1” and
“initialization 2” (see Table 4: EM6125 instructions).
Instruction DEC increment or decrement x-address:
If DEC = 0, x-address increments after each byte written to the RAM. After the last x-address, x-address
wraps around to 0 and y-address increments.
If DEC = 1, x-address decrements after each byte written to the RAM. After x-address=0, x-address wraps
around to the higher x-address for the select mux mode and y-address increments.
DEC allows write to the RAM in two ways right and left easily.
Instruction V horizontal or vertical mode addressing:
If V = 0 (horizontal mode addressing), x-address increments or decrements after each byte written to the
RAM. After the last x-address, x-address wraps around to 0 or to the higher x-address and y-address
increments.
If V = 1 (vertical mode addressing), y-address increments after each byte written to the RAM. After the last yaddress, y-address wraps around to 0 and x-address increments or decrements.
Instruction MX mirrored the DDRAM columns:
If MX = 0, x-address 0000000b corresponds to DDRAM column 0.
If MX = 1, x-address 0000000b corresponds to DDRAM column 117 or 101.
The table below represents the next address select after pointers are in the last allowed address:
Mux
Mode
0
1
0
1
DEC
0
0
1
1
Last allowed address
x-address
y-address
117
8
101
10
0
8
0
10
Next address
x-address
y-address
0
0
0
0
117
0
101
0
Table 3
The following tables represent the way that the pointers x-address and y-address are working according with the setting of
the instructions Mux Mode, V, MX and DEC.
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EM6125
Mux Mode = 0, V = 0, DEC =0, MX = 0:
0
1
2
3
--
--
x-a d d re ss
--
11 4
115
116
117
0
1
2
¦
y -a d d re ss
¦
6
7
8
Pad S33
Pad S150
Figure 16
Mux Mode = 0, V = 0, DEC =1, MX = 0:
0
1
2
3
--
--
x-a d d re ss
--
11 4
115
116
117
0
1
2
¦
y -a d d re ss
¦
6
7
8
Pad S33
Pad S150
Figure 17
Mux Mode = 1, V = 0, DEC =0, MX = 0:
0
1
2
3
--
--
x-a d d re ss
--
98
99
100
101
0
1
2
¦
y -a d d re ss
¦
8
9
10
Pad S41
Pad S142
Figure 18
Mux Mode = 1, V = 0, DEC =1, MX = 0:
0
1
2
3
--
--
x-a d d re ss
--
98
99
100
101
0
1
2
¦
y -a d d re ss
¦
8
9
10
Pad S41
Pad S142
Figure 19
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EM6125
Mux Mode = 0, V = 1, DEC =0,MX = 0:
0
1
2
3
--
--
x -a d d re s s
--
114
115
116
117
0
1
2
¦
y -a d d re s s
¦
6
7
8
Pad S33
Pad S150
Figure 20
Mux Mode = 0, V = 1, DEC =1,MX = 0:
0
1
2
3
--
--
x -a d d re s s
--
114
115
116
117
0
1
2
¦
y -a d d re s s
¦
6
7
8
Pad S33
Pad S150
Figure 21
Mux Mode = 1, V = 1, DEC =0, MX = 0:
0
1
2
3
--
--
x -a d d re s s
--
98
99
100
101
0
1
2
¦
y -a d d re s s
¦
8
9
10
Pad S41
Pad S142
Figure 22
Mux Mode = 1, V = 1, DEC =1, MX = 0:
0
1
2
3
--
--
x -a d d re s s
--
98
99
100
101
0
1
2
¦
y -a d d re s s
¦
8
9
10
Pad S41
Pad S142
Figure 23
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EM6125
Mux Mode = 0, V = 0, DEC =0, MX = 1:
117
116
115
114
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
6
7
8
Pad S33
Pad S150
Figure 24
Mux Mode = 0, V = 0, DEC =1, MX = 1:
117
116
115
114
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
6
7
8
Pad S33
Pad S150
Figure 25
Mux Mode = 1, V = 0, DEC =0, MX = 1:
101
100
99
98
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
8
9
10
Pad S41
Pad S142
Figure 26
Mux Mode = 1, V = 0, DEC =1, MX = 1:
101
100
99
98
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
8
9
10
Pad S41
Pad S142
Figure 27
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EM6125
Mux Mode = 0, V = 1, DEC =0,MX = 1:
117
116
115
114
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
6
7
8
Pad S33
Pad S150
Figure 28
Mux Mode = 0, V = 1, DEC =1,MX = 1:
117
116
115
114
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
6
7
8
Pad S33
Pad S150
Figure 29
Mux Mode = 1, V = 1, DEC =0, MX = 1:
101
100
99
98
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
8
9
10
Pad S41
Pad S142
Figure 30
Mux Mode = 1, V = 1, DEC =1, MX = 1:
101
100
99
98
--
--
x -a d d re s s
--
3
2
1
0
0
1
2
¦
y -a d d re s s
¦
8
9
10
Pad S41
Pad S142
Figure 31
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8.6 Initialization of EM6125
Data loaded in EM6125 can be divided in two parts:
The bits stored in the DDRAM, which are corresponding to LCD pixels.
The command bits, which are used to set functions of the LCD controller.
The way of addressing these bits is described in table below:
Control Byte
Control Byte
Instruction
Description
Inv.
Video
Set functions
X[0]
V
Set column adress for DDRAM write
access and vertical/horizontal
addressing
Vlcd
Dischg
DEC
LSB
Set bank adress for DDRAM write
access, increment /decrement
pointer and LSB/MSB mode
Vlcd
Level
[3]
Vlcd
Level
[2]
Vlcd
Level
[1]
Vlcd
Level
[0]
Programming the internally generated
LCD voltage supply VLCD
First
Row
PD
[3]
First
Row
PD
[2]
First
Row
PD
[1]
First
Row
PD
[0]
Sleep
Number of voltage multiplier stages
Partial display parameters
Sleep mode
Initialization 0
0
1
0
0
0
0
0
0
0
Mux
Mode
TC
[1]
TC
[0]
Inv.
Row
MX
Initialization 1
0
1
0
0
0
0
0
0
1
X[6]
X[5]
X[4]
X[3]
X[2]
X[1]
Initialization 2
0
1
0
0
0
0
0
1
0
Y[3]
Y[2]
Y[1]
Y[0]
0
Initialization 3
0
1
0
0
0
0
0
1
1
Vlcd
Level
[7]
Vlcd
Level
[6]
Vlcd
Level
[5]
Vlcd
Level
[4]
Mult
[0]
Partial
Display
Blank Checker
Initialization 4
0
1
0
0
0
0
1
0
0
Mult
[1]
Test 0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Byte test 0, all bits must be set to 0
Test 1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
Byte test 1, all bits must be set to 0
Test 2
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Byte test 2, all bits must be set to 0
Test 3
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
Byte test 3, all bits must be set to 0
Write 1 byte
in DDRAM
0
1/0
1
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write data byte to the
Display Data Ram
Read 1 byte
in initialization
1
-
-
-
-
-
-
-
-
Mux
Mode
TC
[1]
TC
[0]
Inv.
Row
MX
Blank Checker
Inv.
Video
Read Status Byte from EM6125
2
Status Byte = initialization 0 using I C
interface
Table 4: EM6125 instructions
Bits of instructions from Table 4 and active levels and state after reset:
Bits
Mux Mode
TC[1:0]
Inv. Row.
MX
Blank
Checker
Inv. Video
X[6:0]
V
Y[3:0]
VLCD Dischg
DEC
LSB
VLCD Level[7:0]
Mult[1:0]
Partial Display
First RowPD[3:0]
Sleep
0
1
Multiplex rate 65
Multiplex rate 81
Select VLCD Temperature Coefficient
Normal row drivers
Mirrored row drivers
Normal column drivers
Mirrored column drivers
Display DDRAM content
LCD blanked (all OFF)
Display DDRAM content
LCD = checker board
LCD = DDRAM
LCD = NOT (DDRAM)
x-address pointer. Selects DDRAM columns to be accessed
Horizontal addressing
Vertical addressing
y-address pointer. Selects DDRAM bank to be accessed
Normal Mode
Discharge Capacitor
x-address pointer incremented
x-address pointer decrement
DB7 copied to the higher row of the
DB0 copied to the higher row of the
selected bank
selected bank
Program the required LCD supply voltage
Number of voltage multiplier stages
Mux Mode multiplex rate
17 LCD rows active only
Position of first active row when partial display mode
Normal mode
No LCD pixel active, low power
consumption
State after reset
0
00b
0
0
0
0
0
0000000b
0
0000b
0b
0
0
00000000b
00b
0
0000b
0
Table 5: Internal functions after reset.
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8.7 Description of instructions
8.7.1 Initialization 0
8.7.1.1 Mux Mode
Set the multiplex rate.
Mux Mode
Multiplex rate
(number of row drivers)
Row drivers
Number of column drivers
Column drivers
Bias system
0
65
1
81
S0 → S32
S151 → S182
118
S33 → S150
1/9
Table 6
S0 → S40
S143 → S182
102
S41 → S142
1/10
The bias system sets the voltages V1, V2, V3 and V4 applied to row and column drivers. Assuming these voltages comes
from a resistive divider, we have:
VLCD
R
V1
R
The value of the corresponding bias system is:
V1/ VLCD = 1/(n+4).
It is chosen to optimize the value of the RMS voltage
applied to a LCD pixel ON divided by the RMS voltage
applied to a LCD pixel OFF: (VON)RMS/(VOFF)RMS.
This condition leads to:
V2
1
= 1
(n + 4)
(1 + MultiplexRate )
nR
V3
R
V4
R
VSS
bias systems ≊ 1/5 for multiplex rate 17 (partial
display mode)
bias systems ≊ 1/9 for multiplex rate 65
bias systems = 1/10 for multiplex rate 81
8.7.1.2 TC[1:0]
It sets the VLCD temperature compensation.
4 temperature coefficients are available for the internally generated voltage supply VLCD. One of these coefficients is chosen
depending one the LCD crystal needs. The temperature coefficient is proportional to VLCD.
VLCD Temperature Coefficients
8.800
TC[1]
TC[0]
0
0
1
1
0
1
0
1
VLCD Temperature
coefficient (mV/°C)
0
-0.39 × VLCD
-0.86 × VLCD
-1.34 × VLCD
8.600
8.400
8.200
8.000
Table 7
7.800
7.600
7.400
-20
-10
0
10
20
30
40
50
60
Temperature [°C]
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EM6125
8.7.1.3 Inv. Row
Row driver pads can be mirrored to give more flexibility for LCD interconnects.
This function acts on the row driver that is activated when a given DDRAM row is read: it becomes active with no need of
rewriting the RAM (see Table 8 and Figure 34: LCD output pads configuration depending on Mux Mode, Inv. Row and MX).
Read data when Inv. Row=0:
0
1
2
3
--
x -a d dr e s s
--
--
--
--
101 or 117
--
--
--
--
101 or 117
0
1
2
¦
y -a d d re ss
¦
¦
¦
8 or 10
Figure 32
Read data when Inv. Row=1:
0
1
2
3
--
x -a d dr e s s
0
1
2
¦
y -a d d re ss
¦
¦
¦
8 or 10
Figure 33
In v . R o w
M ux M ode
S0
S1
S32
S33
S34
S35
S36
S37
S38
S39
S40
S 4 1 to S 1 4 2
S 143
S 144
S 145
S 146
S 147
S 148
S 149
S 150
S 151
S 152
S 182
S 183 = S 0
0
0
Row 0
Row 1
1
0
Row 64
Row 63
R ow 32
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
=
=
=
=
=
=
=
=
Row 32
0
1
2
3
4
5
6
7
x -a d d re e s s = 8 to x -a d d re e s s = 1 0 9
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
x -a d d re e s s
R ow 64
R ow 63
R ow 33
Row 0
=
=
=
=
=
=
=
=
110
111
112
113
114
115
116
117
Row 0
Row 1
Row 31
Row 64
0
1
Row 0
Row 1
Row
Row
Row
Row
Row
Row
Row
Row
Row
32
33
34
35
36
37
38
39
40
1
1
R ow 80
R ow 79
Row
Row
Row
Row
Row
Row
Row
Row
Row
48
47
46
45
44
43
42
41
40
x -a d d re e s s = 0 to x -a d d re e s s = 1 0 1
Row
Row
Row
Row
Row
Row
Row
Row
Row
Row
80
79
78
77
76
75
74
73
72
71
Row 41
Row 0
Row
Row
Row
Row
Row
Row
Row
Row
Row
Row
0
1
2
3
4
5
6
7
8
9
R ow 39
R ow 80
Table 8
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EM6125
8.7.1.4 MX
Column driver pads can also be mirrored to give more flexibility for LCD interconnects.
This function change the x-address pointer to reverse columns of the DDRAM accessed during a write cycle: a rewrite cycle
is required to observe changes on outputs (see Figure 34: LCD output pads configuration depending on Mux Mode, Inv.
Row and MX)
Table 9 shows how the DDRAM is connected to LCD output pads, depending on bits Mux Mode, MX and Inv. Row.
MX
Mux Mode
S0
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44 to
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
0
0
1
0
0
1
Row 0
Row 0
Row 32
x-address = 0
x-address = 1
x-address = 2
x-address = 3
x-address = 4
x-address = 5
x-address = 6
x-address = 7
x-address = 8
x-address = 9
x-address = 10
x-address =11 to
x-address =106
x-address
x-address
x-address
x-address
x-address
x-address
x-address
x-address
x-address
x-address
x-address
=
=
=
=
=
=
=
=
=
=
=
x-address = 117
x-address = 116
x-address = 115
x-address = 114
x-address = 113
x-address = 112
x-address = 111
x-address = 110
x-address = 109
x-address = 108
x-address = 107
x-address =106 to
x-address =11
107
108
109
110
111
112
113
114
115
116
117
S182
S183 = S0
1
1
x-address = 10
x-address = 9
x-address = 8
x-address = 7
x-address = 6
x-address = 5
x-address = 4
x-address = 3
x-address = 2
x-address = 1
x-address = 0
Row
Row
Row
Row
Row
Row
Row
Row
Row
32
33
34
35
36
37
38
39
40
x-address = 0
x-address = 1
x-address = 2
x-address =3 to
x-address = 98
x-address = 101
x-address = 100
x-address = 99
x-address = 98 to
x-address = 3
x-address = 99
x-address = 100
x-address = 101
x-address = 2
x-address = 1
x-address = 0
Row 64
Row
Row
Row
Row
Row
Row
Row
Row
Row
80
79
78
77
76
75
74
73
72
Row 33
Row 0
Row 41
Row 0
Table 9: Relation between LCD output pads and row and columns of DDRAM
The combination of Mux Mode, Inv. Row and MX gives the following figures (next page) of output pads.
8.7.1.5 Blank
Sets all the LCD pixels OFF.
Every row drivers and column drivers are at VSS level.
DDRAM content is not affected by this instruction.
8.7.1.6 Checker
Sets all the LCD pixels in a checker mode, LCD displays alternately ON and OFF pixels.
DDRAM content is not affected by this instruction.
8.7.1.7 Inv. Video
Sets an inverse video mode.
If Inv. Video = 0, a logical 1 level stored in the DDRAM leads to a “ON” pixel displayed the LCD.
If Inv. Video = 1, a logical 1 level stored in the DDRAM leads to a “OFF” pixel displayed the LCD.
DDRAM content is not affected by this instruction.
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EM6125
Row 53
x-addr=106
Row 53
Row 11
x-addr=11
x-addr=106
Row 33
Row 0
Row 33
Row 0
Row 31
Row 64
Mux Mode = 0
Mux Mode = 0
Mux Mode = 0
Inv. Row = 0
Inv. Row = 1
Inv. Row = 0
MX. = 0
MX. = 0
MX = 1
Row 0
x-addr=11
x-addr=11
x-addr=106
Row 43
Row 21
Row 21
Row 61
Row 19
Row 61
x-addr=4
x-addr=98
x-addr=98
Row 0
Row 64
Row 41
Row 0
Row 39
Row 80
Row 41
Row 0
Mux Mode = 1
Mux Mode = 1
Mux Mode = 1
Inv. Row = 0
Inv. Row = 1
Inv. Row = 0
MX = 0
MX = 0
MX = 1
x-addr=3
Row 0
Row 80
Row 0
x-addr=3
x-addr=98
Row 59
Row 21
Row 21
Figure 34: LCD output pads configuration depending on Mux Mode, Inv. Row and MX
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EM6125
8.7.2 Initialization 1
8.7.2.1 X[6:0]
These 7 bits set the x-address pointer of the DDRAM.
Data are written in column “x-address” with: X[6] = MSB, X[0] = LSB.
As the number of column drivers depends on the chosen multiplex rate, the DDRAM x-address pointer should also satisfy
the following relationships:
If Mux Mode = 0 then 0 ≤ x-address ≤ 1110101b. (117).
If Mux Mode = 1 then 0 ≤ x-address ≤ 1100101b. (101).
8.7.2.2 V
Vertical addressing:
If V = 0, DDRAM x-address pointer is incremented or decrement after each data byte send.
If V = 1, DDRAM y-address pointer is incremented or decrement after each data byte send.
8.7.3 Initialization 2
8.7.3.1 Y[3:0]
These 4 bits set the y-address pointer of the DDRAM.
Data are written in bank “y-address” with Y[3]= MSB, Y[0]= LSB.
As the multiplex rate is digitally programmable, the DDRAM y-address pointer should also satisfy the following relationships:
If Mux Mode = 0 then 0 ≤ y-address ≤ 1000b.
If Mux Mode = 1 then 0 ≤ y-address ≤ 1010b.
8.7.3.2 Vlcd Dischg.
VLCD Discharge works to discharge the capacitor
connected to PAD VLCD. This operation becomes
necessary when programming Partial Display Mode. In
this case, a lower VLCD is required than the voltage used
for normal mux 65 or 81 operation, the display at
beginning of partial mode operation could be completely
‘ON’ until VLCD is low enough.
To avoid this, an internal pull down helps the VLCD
voltage to come down and hence reach the new optimum
value in a short time. This pull down is on until bit ‘Vlcd
Dischg’ is at 1L.
Typical use of ‘Vlcd Dischg’ command:
Normal mux 65 or mux 81 mode
VLCD = 8V
Blank = 1
Partial Display = 1
VLCD_Level = 2Bh (4.5V)
VLCD Dischg = 1
T ≅ 30ms, depending
on VLCD capacitor
VLCD Dischg = 0
Blank = 0
Using this command with external power supply on VLCD can damage the IC.
8.7.3.3 DEC
H controls the DDRAM writing direction:
If DEC = 0 then x-address pointer increments after each byte written to the DDRAM.
If DEC = 1 then x-address pointer decrements after each byte written to the DDRAM.
8.7.3.4 LSB
This instruction change the bytes send to the DDRAM before writing them. For instance, for bank 1 we have:
If LSB = 0 then DB7 is written on Row 1.
If LSB = 1 then DB0 is written on Row 1 (see Figure 14 and Figure 15).
8.7.4 Initialization 3
8.7.4.1 Vlcd Level[7:0]
Set the internally generated voltage level.
These 8 bits generate integer “VLCD Level”, VLCD Level [7] = MSB, VLCD Level [0] = LSB.
VLCD is given by the following formula:
VLCD = 3.02 + 0.0352 × VLCD _Level
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EM6125
8.7.5 Initialization 4
8.7.5.1 Mult[1:0]
Set the internal voltage multiplier factor.
These bits should be chosen depending on the VHV supply voltage level, the desired VLCD voltage and the current
consumption due to LCD load.
If low VLCD is required, for instance when partial display mode is enabled, lower voltage multiplier range can be used,
leading in current consumption reduction (improved voltage multiplier efficiency).
Mult1
0
0
Mult0
0
1
1
0
1
1
Voltage multiplier
Table 10
×2
×3
×4
×5
8.7.5.2 Partial Display
Set the partial display configuration of the driver (multiplex ratio 17).
In this configuration, 17 rows only are active:
The row which corresponds to RAM address 0.
16 other rows, first one is defined by First Row PD [3:0].
Multiplex rate
65 or 81 (depending on Mux Mode)
17
Partial Display
0
1
Table 11
8.7.5.3 First Row PD[3:0]
Partial display mode yields to a LCD with 2 banks activated only.
Row 0 is always active, it could be used to drive icons.
The 16 other active rows are chosen from 64 or 80 row as shown on table:
Mux
Mode
0 or 1
1
First
Row
PD[3]
0
0
0
0
0
0
0
0
1
First
Row
PD[2]
0
0
0
0
1
1
1
1
0
First
Row
PD[1]
0
0
1
1
0
0
1
1
0
First
Row
PD[0]
0
1
0
1
0
1
0
1
0
First active row
(DDRAM)
Last active row
(DDRAM)
Activated banks
Row 1
Row 9
Row 17
Row 25
Row 33
Row 41
Row 49
Row 57
Row 65
Row 16
Row 24
Row 32
Row 40
Row 48
Row 56
Row 64
Row 72
Row 80
0,1,2
0,2,3
0,3,4
0,4,5
0,5,6
0,6,7
0,7,8
0,8,9
0,9,10
Table 12
If Mux Mode = 0, 0 ≤ First_Row PD [3:0] ≤ 0110b.
If Mux Mode = 1, 0 ≤ First_Row PD [3:0] ≤ 1000b.
Values for “First_Row PD [3:0]” outside these ranges are not allowed.
8.7.5.4 Sleep
This function stops all functionality, internal oscillator and voltage multiplier are off, and LCD is blanked. It yields to a very
low current consumption with leakage currents only.
8.7.6 Test 0 to 3
All bits must be set to 0 (see example in typical application page 35).
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EM6125
8.8 LCD outputs
The LCD output pads are connected to LCD electrodes, signals and voltages are optimized for the best LCD contrast and a
null DC component of voltage applied to LCD pixels. Table 13 gives bias voltages referring to VLCD.
Multiplex Rate
VLCD
V1
V2
n
1
æ 1 ö
1− ç
è n +1
æ 2 ö
1− ç
÷
è n +1
81 (Mux Mode = 1)
1
0.90
65 (Mux Mode = 0)
1
17 (Partial Display = 1)
1
V3
V4
VSS
2
n +1
1
n +1
0
0.80
0.20
0.10
0
0.89
0.78
0.22
0.11
0
0.80
0.60
0.40
0.20
0
Table 13: Values of intermediate bias voltages
Table 14 gives values of VLCD in reference to RMS voltage applied to a pixel OFF and the contrast achieved between a ON
pixel and a OFF pixel. These values correspond to bias voltages described on Table 13.
VLCD
VOFF (RMS)
VON (RMS)
VOFF (RMS)
Programmed multiplex
rate
LCD Bias
configuration
81
6 levels
n ( n + 1)2
= 7.500
2( n − 1)
n +1
= 1.118
n −1
65
6 levels
n ( n + 1)2
= 6.847
2( n − 1)
n +1
= 1.133
n −1
17
6 levels
n ( n + 1)2
= 4.162
2( n − 1)
n +1
= 1.281
n −1
Table 14: Required LCD supply voltage and achieved LCD contrast
VLCD
gives the required VLCD voltage supply. We
VOFF (RMS)
can observe that the Partial Display mode decreases VLCD, leading to lower power consumption. Current consumption is
also decreased because lower VLCD leads to choose fewer stages for voltage multiplier and the efficiency is improved.
The chosen LCD gives the value of VOFF (RMS) and the value of
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EM6125
8.9 LCD refresh frequency
LCD refresh frequency depends on an internal RC oscillator. Pad FR outputs this frequency multiplied by the multiplex rate.
Following figures display typical variations depending on VDD power supply and temperature.
FR=f(VDD) @25°C
77
76
75
74
73
1.8
2.3
2.8
3.3
3.8
4.3
4.8
VDD
LCD refresh frequency depending on temperature
85
83
81
79
77
75
73
71
69
67
65
-20
-10
0
10
20
30
40
50
60
70
Temperature [°C]
8.10 VLCD depending on VHV
VLCD (VHV)
8.1
8.09
8.08
8.07
8.06
8.05
8.04
8.03
8.02
8.01
8
2.4
2.9
3.4
3.9
4.4
4.9
VHV [V¨]
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EM6125
8.11 LCD driver waveforms
Row and Column Multiplexing Waveform EM6125 (81)
frame n
frame n+1
Vstate1 (t)
Vstate2 (t)
VLCD
V1
V2
Row 1
Row 1
V3
V4
VSS
VLCD
V1
V2
Row 2
Row 2
V3
V4
VSS
VLCD
V1
V2
Col 0
Col 0
V3
V4
VSS
Col 1
VLCD
V1
V2
Col 1
V3
V4
VSS
VLCD
V2 – VSS
Vstate1 (t) = Col1 (t) – Row1 (t)
VLCD – V1
0V
V2 – V1
V3 – V4
0V
VSS – V4
Vstate1 (t)
V3 - VLCD
–VLCD
VLCD
V2 – VSS
Vstate2 (t) = Col1 (t) – Row2 (t)
VLCD – V1
0V
V2 – V1
V3 – V4
0V
VSS – V4
Vstate2 (t)
V3 - VLCD
–VLCD
0 1 2 3 4 5 6 7 8…
…80  0 1 2 3 4 5 6 7 8…
…80
Figure 35
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EM6125
Row and Column Multiplexing Waveform EM6125 (65)
frame n
frame n+1
Vstate1 (t)
Vstate2 (t)
VLCD
V1
V2
Row 1
Row 1
V3
V4
VSS
VLCD
V1
V2
Row 2
Row 2
V3
V4
VSS
VLCD
V1
V2
Col 1
Col 1
V3
V4
VSS
Col 2
VLCD
V1
V2
Col 2
V3
V4
VSS
VLCD
V2 – VSS
Vstate1 (t) = Col1 (t) – Row1 (t)
VLCD – V1
0V
V2 – V1
V3 – V4
0V
VSS – V4
Vstate1 (t)
V3 - VLCD
–VLCD
VLCD
V2 – VSS
Vstate2 (t) = Col2 (t) – Row2 (t)
VLCD – V1
0V
V2 – V1
V3 – V4
0V
VSS – V4
Vstate2 (t)
V3 - VLCD
–VLCD
0 1 2 3 4 5 6 7 8…
…64  0 1 2 3 4 5 6 7 8…
…64
Figure 36
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EM6125
8.11.1 Partial Display
Row and Column Multiplexing Waveform EM6125 (17)
frame n
frame n+1
Vstate1 (t)
Vstate2 (t)
VLCD
Row 1
V1
V2
Row 1
V3
V4
VSS
VLCD
V1
V2
Row 2
V3
Row 2
V4
VSS
VLCD
V1
Col 0
V2
V3
V4
Col 0
VSS
Col 1
VLCD
V1
Col 1
V2
V3
V4
VSS
VLCD
V2 – VSS
Vstate1 (t)
VLCD – V1
V3 – V4
0V
Vstate1 (t) = Col1 (t) – Row1 (t)
0V
V2 – V1
VSS – V4
V3 - VLCD
VLCD
–VLCD
V2 – VSS
Vstate2 (t)
VLCD – V1
V3 – V4
0V
Vstate2 (t) = Col1 (t) – Row2 (t)
0V
V2 – V1
VSS – V4
V3 - VLCD
–VLCD
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 37
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EM6125
9 Typical Application
2
This example gives typical programming steps for EM6125 with I C interface, for serial interface, start and stop conditions
should be replaced by CS at 0L and CS at 1L. LCD display is connected as described on Figure 38:
Example
Liquid Cristal Display
81 row x 102 columns
102 columns
41 rows
40 rows
Col 2
Col 99
Col 0
Col 101
Row 40
Row 80
EM6125
Row 21
Row 61
Figure 38: Connection between EM6125 and LCD for the application example
Step
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Comment
Power on
2
Reset
3
I2C start condition
Display
Undefined
A reset cycle must always follow the power
on
Blank
Blank
4
x
x
x
x
x
x
x
0
EM6125 slave address + write mode
Blank
5
1
0
0
0
0
0
0
0
Control byte for initialization 0
Blank
Blank
Blank
6
1
0
1
0
0
0
0
0
Data byte = initialization 0
Multiplex Rate = 81
Vlcd Temperature Coefficient
= -0.39 x Vlcd (mV/°C)
No row or column mirroring
No blank, Checker or Video functions.
7
1
0
0
0
0
0
1
1
Control byte for initialization 3
Data byte = initialization 3
Programmed Vlcd_level = 10001110b
(8Eh=142)
Vlcd = 3.02 + 142*0.0352 = 8.02V
Control byte for initialization 4
8
1
0
0
0
1
1
1
0
9
1
0
0
0
0
1
0
0
10
1
1
0
0
0
0
0
0
Data byte = initialization 4
x 5 Voltage Multiplier
No partial display mode. No sleep mode
11
1
0
1
0
0
0
0
0
Control byte for test 0
12
0
0
0
0
0
0
0
0
bits test must be set to 0L
13
1
0
1
0
1
0
0
0
Control byte for test 1
14
0
0
0
0
0
0
0
0
bits test must be set to 0L
15
1
0
1
1
0
0
0
0
Control byte for test 2
16
0
0
0
0
0
0
0
0
bits test must be set to 0L
17
1
0
1
1
1
0
0
0
Control byte for test 3
18
0
0
0
0
0
0
0
0
bits test must be set to 0L
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Blank
Blank
Undefined
Undefined
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EM6125
Step DB7
0
19
DB6
1
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
0
Comment
Last control byte
DDRAM write selected
Fisrt DDRAM byte stored at
x-address = 0, y-address = 0
Horizontal addressing is
selected (state after reset)
20
0
x
x
x
x
x
x
x
Only DB7 is stored at
row 0 of DDRAM, column 0
21 to
121
0
x
x
x
x
x
x
x
Only DB7 is stored at
row 0, columns 1 to 101
122
0
0
0
0
0
0
0
0
DB7 to DB0 are stored at
column 0, rows 1 to 8
123
1
1
1
1
1
1
1
0
DB7 to DB0 are stored at
column 1, rows 1 to 8
124
1
0
0
1
0
0
1
0
DB7 to DB0 are stored at
column 2, rows 1 to 8
125
1
0
0
1
0
0
1
0
DB7 to DB0 are stored at
column 3, rows 1 to 8
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Display
Undefined
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EM6125
Step DB7
1
126
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
0
Comment
DB7 to DB0 are stored at
column 4, rows 1 to 8
127 to
229
0
0
0
0
0
0
0
0
DB7 to DB0 are stored at
column 5 to 101, rows 1 to 8
column 0 to 5, rows 9 to 16
230
0
0
0
0
0
0
0
0
Write letter M
231
1
1
1
1
1
1
1
0
232
0
1
0
0
0
0
0
0
233
0
0
1
0
0
0
0
0
234
0
1
0
0
0
0
0
0
235
1
1
1
1
1
1
1
0
236 to
325
0
0
0
0
0
0
0
0
DB7 to DB0 are stored at
column 12 to 101, rows 9 to 16
326
Display
I2C stop condition + new start condition
Unchanged
327
x
x
x
x
x
x
x
0
EM6125 slave address + write mode
Unchanged
328
1
0
0
0
0
0
0
1
Control byte for initialization 1
Unchanged
329
0
0
0
1
1
0
0
0
x-address = 12 , Horizontal mode addressing
Unchanged
330
1
0
0
0
0
0
1
0
Control byte for initialization 2
Unchanged
331
332
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
y-address = 1
Write 6
Unchanged
333
0
1
1
1
1
1
0
0
334
1
0
0
1
0
0
1
0
335
1
0
0
1
0
0
1
0
336
1
0
0
1
0
0
1
0
337
0
1
0
0
1
1
0
0
338
x
x
x
x
x
x
x
x
Copyright  2001, EM Microelectronic-Marin SA
Continuation…
37
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EM6125
Step DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Comment
I2C start condition
1
Display
Previously set
2
x
x
x
x
x
x
x
0
EM6125 slave address + write mode
3
1
0
0
0
0
0
0
0
Control byte for initialization 0
4
1
0
1
0
0
1
0
0
Blank = 1
All pixels OFF
5
1
0
0
0
0
0
1
1
Control byte for initialization 3
All pixels OFF
6
0
0
1
0
1
0
1
1
Vlcd_level = 2Bh
All pixels OFF
7
1
0
0
0
0
0
1
0
Control byte for initialization 2
All pixels OFF
8
0
0
0
0
0
1
0
0
Vlcd_Dischg = 1
All pixels OFF
9
1
0
0
0
0
1
0
0
Control byte for initialization 4
All pixels OFF
10
1
1
1
0
0
0
0
0
Partial display on banks:
0, 1 and 2
All pixels OFF
11
1
0
0
0
0
0
1
0
12
0
0
0
0
0
0
0
0
Vlcd_Dischg = 0
All pixels OFF
All pixels OFF
Wait 30 ms
Control byte for initialization 32
13
1
0
0
0
0
0
0
0
Control byte for initialization 0
14
1
0
1
0
0
0
0
0
Blank = 0
Partial display on banks:
0, 1 and 2
15
1
0
0
0
0
1
0
0
Control byte for initialization 4
16
1
1
1
0
0
0
1
0
Partial display on banks:
0, 2 and 3
Unchanged
Unchanged
All pixels OFF
Remark:
This typical application example shows a LCD display ‘ON’ before the DDRAM is completely written, parts of the LCD are
undefined as DDRAM data is random at power on. However, blank function can remain active until DDRAM is completed to
avoid randomly ON or OFF pixels to appear on the LCD.
Copyright  2001, EM Microelectronic-Marin SA
38
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EM6125
10 Pad location
Figure 39
Mechanical Dimensions:
Typical value
70
50 × 100 × 17.5
102 × 102 × 17.5
50
380
7775 × 2175
Minimum pad pitch
Bump size pads from S[0] to S[183]
Bump size interface pads
Bump hardness
Wafer thickness
Chip Size
90 µm
90 µm
30 µm
30 µm
y center
30 µm
90 µm
y center
90 µm
30 µm
30 µm
x center
x center
MARK 1 : x = - 61, y = 209
Copyright  2001, EM Microelectronic-Marin SA
Unit
µm
µm
µm
Vickers
µm
µm
MARK 2 : x = 7397, y = 209
39
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EM6125
Pad
VHV
VHV
VDD2
VDD2
VDD1
VDD1
VSS2
VSS2
VSS1
VSS1
VSS1
VSS1
I
CS
RES
FR
TEST
SDA
SCL
VLCD
VLCD
VLCD
VLCD
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
Serial number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
x
5543
5383
5223
5063
4903
4743
4583
4423
4263
4103
3943
3783
3623
3463
3303
3143
2913
2683
2453
2271
2111
1951
1791
1545
1475
1405
1335
1265
1195
1125
1055
985
915
845
775
705
635
565
495
425
355
285
215
145
75
0
0
0
0
0
0
0
0
0
Copyright  2001, EM Microelectronic-Marin SA
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
362
432
502
572
642
712
782
852
922
Pad
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
40
Serial number
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
x
0
0
0
0
0
0
0
0
0
0
0
0
0
342
412
482
552
622
692
762
832
902
972
1042
1112
1182
1252
1322
1392
1462
1532
1602
1672
1742
1812
1882
1952
2022
2092
2162
2232
2302
2372
2442
2512
2582
2652
2722
2792
2862
2932
3002
3072
3142
y
992
1062
1132
1202
1272
1342
1412
1482
1552
1622
1692
1762
1832
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
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EM6125
Pad
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
Serial number
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
x
3212
3282
3352
3422
3492
3562
3632
3702
3772
3842
3912
3982
4052
4122
4192
4262
4332
4402
4472
4542
4612
4682
4752
4822
4892
4962
5032
5102
5172
5242
5312
5382
5452
5522
5592
5662
5732
5802
5872
5942
6012
6082
6152
6222
6292
6362
6432
6502
6572
6642
y
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
1785
Pad
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
S171
S172
S173
S174
S175
S176
S177
S178
S179
S180
S181
S182
S183
Serial number
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
x
6712
6782
6852
6922
6992
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7334
7259
7189
7119
7049
6979
6909
6839
6769
6699
6629
6559
6489
6419
6349
6279
6209
6139
6069
5999
5929
5859
5789
y
1785
1785
1785
1785
1785
1832
1762
1692
1622
1552
1482
1412
1342
1272
1202
1132
1062
992
922
852
782
712
642
572
502
432
362
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
Table 15: Pad location.
Copyright  2001, EM Microelectronic-Marin SA
41
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EM6125
11 Ordering Information
When ordering please specify the complete part number and package.
Part Number
Die Form & Thickness
Bumping
EM6125WS27
Sawn Wafer, 27mils
No bumps
EM6125WP15
Waffle pack, 15mils
No bumps
EM6125WP15E
Waffle pack, 15mils
Gold Bumps
Other delivery form might be available upon request and for a minimum order quantity. Please contact EM sales.
Copyright  2001, EM Microelectronic-Marin SA
42
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EM6125
12 Updates
Date ,Name
Version
22.11.01
02.04.02
Chapter
concerned
All
8.5.1
Fig13,14,15
Old Version (Text, Figure, etc.)
New Version (Text, Figure, etc.)
First version
Row 17
Row 18
Row 9
Row10
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry
entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to
change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the
information given has not been superseded by a more up-to-date version.
© EM Microelectronic-Marin SA, 04/02, Rev. B/454
Copyright  2001, EM Microelectronic-Marin SA
43
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