AD AD8122 Triple differential receiver Datasheet

Preliminary Technical Data
Triple Differential Receiver with
300m Adjustable Line Equalization
AD8122
FEATURES
Compensates cables to 300 meters for wideband video
60 MHz Equalized BW @ 300 meters of UTP Cable
120 MHz Equalized BW @ 150 meters of UTP Cable
Fast time domain performance
70 ns settling time to 1% with 300 meters of UTP cable
7 ns rise/fall times with 2 V step @ 300 meters of UTP cable
Three frequency response gain adjustment pins
High frequency peaking adjustment (VPEAK)
Output lowpass filter cutoff adjustment (VFILTER)
Broadband flat gain adjustment (VGAIN)
Selectable for UTP or coax compensation
DC output offset adjust (VOFFSET)
Low output offset voltage: ±4 mV @ G = 1
Compensates both RGB and YPbPr
Two on-chip comparators with hysteresis
Can be used for common-mode sync extraction
Available in 40-lead, 6 mm × 6 mm LFCSP
FUNCTIONAL BLOCK DIAGRAM
V PEAK VFILTER V OFFSET V GAIN
COAX/UTP
–INR
OUTR
+INR
GAIN R
–ING
OUTG
+ING
GAIN G
–INB
OUTB
+INB
GAIN B
–IN CMP1
OUTCMP1
+IN CMP1
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cables
Professional video projection and distribution
HD video
Security video
–IN CMP2
+IN CMP2
AD8122
OUTCMP2
Figure 1.
GENERAL DESCRIPTION
The AD8122 is a triple, high speed, differential receiver and
equalizer that compensates for the transmission losses of UTP
and coaxial cables up to 300 meters in length. Various gain
stages are summed together to best approximate the inverse
frequency response of the cable. Each channel features a high
impedance differential input that is ideal for interfacing directly
with the cable.
The AD8122 has two control inputs for optimal cable
compensation, one LPF control input, an input to select
between UTP and coax cable, and an output offset adjust input.
The cable compensation inputs are used to compensate for
different cable lengths; the VPEAK input controls the amount of high
frequency peaking and the VGAIN input adjusts the broadband
flat gain, which compensates for the flat cable loss. The VFILTER
input controls the cutoff frequency of output lowpass filters on
each channel. Selection between UTP and coaxial cable
compensation responses is determined by the binary
COAX/UTP input, which can be left floating in UTP
applications. The VOFFSET pin allows the dc voltage at the output
to be adjusted, which can be useful in dc-coupled systems.
For added flexibility, the gains of each channel can be set to x1
or x2 using the associated GAIN control pins.
The AD8122 is available in a 6 mm × 6 mm, 40-lead LFCSP and
is rated to operate over the extended temperature range of
−40°C to +85°C.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD8122
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Basic Operation .......................................................................... 10
Applications ....................................................................................... 1
Input Overdrive Recovery and Protection .............................. 10
Functional Block Diagram .............................................................. 1
Comparators ............................................................................... 10
General Description ......................................................................... 1
Sync Pulse Extraction Using Comparators ............................. 11
Revision History .......................... Error! Bookmark not defined.
Using the VPEAK, VGAIN, VFILTER, and VOFFSET Inputs ................. 11
Specifications..................................................................................... 3
Using the Coax/UTP Selector................................................... 12
Absolute Maximum Ratings ............................................................ 6
Driving High-Z and Capacitive Loads .................................... 12
Thermal Resistance ...................................................................... 6
Driving 75 Ω Cable With the AD8122 .................................... 12
ESD Caution .................................................................................. 6
Layout and Power Supply Decoupling Considerations ......... 12
Pin Configuration and Function Description .............................. 7
Input Common-Mode Range ................................................... 12
Theory of Operation ........................................................................ 9
Power-Down ............................................................................... 12
Input Single-Ended Voltage Range Considerations ................. 9
Outline Dimensions ....................................................................... 13
Applications Information .............................................................. 10
Rev. PrC | Page 2 of 13
Preliminary Technical Data
AD8122
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, G = 2, Belden Cable (BL-7987R), VOFFSET = 0 V, VPEAK and VGAIN are set to optimum settings, unless
otherwise noted.
Table 1.
Parameter
DYNAMIC AND NOISE PERFORMANCE
–3 dB Large Signal Bandwidth
Slew Rate
10% to 90% Rise/Fall Time
Settling Time to 1%
Integrated Output Voltage Noise
INPUT PERFORMANCE
Input Voltage Range
Maximum Differential Voltage Swing
Voltage Gain Error
Channel-to-Channel Gain Matching
Common-Mode Rejection (CMR)
Input Resistance
Input Capacitance
Input Bias Current
VOFFSET Pin Current
VGAIN Pin Current
VPEAK Pin Current
VFILTER Pin Current
COAX/UTP Pin Current
ADJUSTMENT PINS
VPEAK Input Voltage Range
VGAIN Input Voltage Range
VOFFSET to OUT Gain
Conditions
Min
Typ
Max
Unit
VOUT = 2 V p-p, AD8122 alone
VOUT = 2 V p-p, 150 meters Cat-5
VOUT = 2 V p-p, 300 meters Cat-5
VOUT = 1 V p-p, AD8122 alone, RL = 1 KΩ, G = 1
VOUT = 1 V p-p, 150 meters Cat-5, RL = 1 KΩ, G = 1
VOUT = 1 V p-p, 300 meters Cat-5, RL = 1 KΩ, G = 1
VOUT = 2 V p-p, AD8122 alone
VOUT = 2 V step, 150 meters Cat-5
VOUT = 2 V step, 300 meters Cat-5
VOUT = 1 V step, 150 meters Cat-5, RL = 1 KΩ, G = 1
VOUT = 1 V step, 300 meters Cat-5, RL = 1 KΩ, G = 1
VOUT = 2 V step, 150 meters Cat-5
VOUT = 2 V step, 300 meters Cat-5
VOUT = 1 V step, 150 meters Cat-5, RL = 1 KΩ, G = 1
VOUT = 1 V step, 300 meters Cat-5, RL = 1 KΩ, G = 1
150 meter setting, integrated to 160 MHz
300 meter setting, integrated to 160 MHz
155
110
57
260
120
60
Single-ended, −IN and +IN
±4.0
3
2
2
0.2
0.2
−92/−85
V
V p-p
%
%
%
%
dB
dB
−66/−60
dB
+4/+10
dB
Logic 0/Logic1
+8/+11
4.4
3.7
1.0
0.5
1.1
2.0
1.0
1.0
1.0
−1/24
dB
MΩ
MΩ
pF
pF
µA
µA
µA
µA
µA
µA
Relative to GND
Relative to GND
Range limited by output swing, G = 1, VGAIN = 0V
0 to 2
0 to 2
1
V
V
V/V
G = 1, ΔVO/VI, VGAIN set for 0 meters of cable
G = 2, ΔVO/VI, VGAIN set for 0 meters of cable
G = 1, VPEAK, VGAIN set for 300 meters of cable
G = 2, VPEAK, VGAIN set for 300 meters of cable
At dc, VPEAK = VGAIN = 0 V, G = 1/G = 2
At dc, VPEAK, VGAIN set for 300 meters of cable
At 1 MHz, VPEAK, VGAIN set for 300 meters of cable
G = 1/G = 2
At 50 MHz, VPEAK, VGAIN set for 300 meters of cable
G = 1/G = 2
At 100 MHz, VPEAK, VGAIN set for 300 meters of cable
G = 1/G = 2
Common mode
Differential
Common mode
Differential
Rev. PrC | Page 3 of 13
6
7
6
7
70
70
2.5
16
MHz
MHz
MHz
MHz
MHz
MHz
V/µsec
ns
ns
ns
ns
ns
ns
ns
ns
mV rms
mV rms
AD8122
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Offset Voltage
Output Offset Voltage Drift
POWER SUPPLY
Operating Voltage Range
Positive Quiescent Supply Current
Negative Quiescent Supply Current
Supply Current Drift, ICC/IEE
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Power Down, VIH (Minimum)
Power Down, VIL (Maximum)
Positive Supply Current, Powered Down
Negative Supply Current, Powered Down
COMPARATORS
Output Voltage Levels
Hysteresis
Propagation Delay
Rise/Fall Times
Output Resistance
OPERATING TEMPERATURE RANGE
Preliminary Technical Data
Conditions
Min
RL = 1 KΩ, G = 1
RTO, VPEAK = VGAIN = VFILTER = VOFFSET = 0 V, G = 1,
RL = 1 KΩ
RTO, Control inputs set for 300 meters of cable
RTO
Typ
Max
−3.9 to +3.9
V
V
±4
mV
mV
µV/°C
±4.5
±5.5
120
66
DC, referred to output
100 MHz, referred to output
DC, referred to output
100 MHz, referred to output
Minimum Logic 1 voltage
Maximum Logic 0 voltage
VPEAK = VGAIN = VPOLE = 0 V
VPEAK = VGAIN = VPOLE = 0 V
−70
−81
1.1
0.8
3.4
0.4
VOH/VOL
VHYST
tPD, LH/tPD, HL
tRISE/tFALL
3.33/0.33
73
14/10
10/7
−40
Rev. PrC | Page 4 of 13
Unit
+85
V
mA
mA
µA/°C
dB
dB
dB
dB
V
V
mA
mA
V
mV
ns
ns
Ω
°C
Preliminary Technical Data
AD8122
Figure 2. Equalized Frequency Response for Various Cable Lengths
Figure 3. Settling Time, G = 1, RL = 1KΩ
Rev. PrC | Page 5 of 13
AD8122
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Power Dissipation
Input Voltage (Any Input)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
11 V
See Figure 4
VS− − 0.3 V to VS+ + 0.3 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 3. Thermal Resistance with the Underside Pad
Connected to the Plane
Package Type/PCB Type
40-Lead LFCSP/4-Layer
θJA
TBD
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipation due to each load
current is calculated by multiplying the load current by the
voltage difference between the associated power supply and the
output voltage. The total power dissipation due to load currents
is then obtained by taking the sum of the individual power
dissipations. RMS output voltages must be used when dealing
with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces the θJA. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a solid plane (usually the
ground plane) to achieve the specified θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 40-lead LFCSP
(29°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
Unit
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8122 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8122. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. PrC | Page 6 of 13
Preliminary Technical Data
AD8122
PIN CONFIGURATION AND FUNCTION DESCRIPTION
AD8122
40 NC
39 AGND
38 –INB
37 +INB
36 AGND
35 –ING
34 +ING
33 AGND
32 –INR
31 +INR
TOP VIEW
( Not to Scale )
30
29
28
27
26
25
24
23
22
21
1
2
COAX / UTP
DVs+
PD
VFILTER
VPEAK
VGAIN
DGND
VOFFSET
DVsVs+
GAINB 11
OUTB 12
Vs+ 13
Vs– 14
GAING 15
OUTG 16
Vs+ 17
Vs– 18
GAINR 19
OUTR 20
NC 1
+INCMP1 2
–INCMP1 3
OUTCMP1 4
Vs+_CMP 5
Vs–_CMP 6
OUTCMP2 7
–INCMP2 8
+INCMP2 9
Vs– 10
NC = NO CONNECT
NOTES
1.
EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO A PCB GROUND PLANE TO
ACHIEVE SPECIFIED THERMAL RESISTANCE.
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 40
2
3
4
5
6
7
8
9
10, 14, 18
11
12
13, 17, 21
15
16
19
20
22
23
24
25
26
27
Mnemonic
NC
+INCMP1
−INCMP1
OUTCMP1
VS+_CMP
VS−_CMP
OUTCMP2
−INCMP2
+INCMP2
VS−
GAINB
OUTB
VS+
GAING
OUTG
GAINR
OUTR
DVS−
VOFFSET
DGND
VGAIN
VPEAK
VFILTER
Description
No Internal Connection.
Positive Input, Comparator 1.
Negative Input, Comparator 1.
Output, Comparator 1.
Positive Power Supply, Comparator. Connect to +5V.
Negative Power Supply, Comparator. Connect to −5V.
Output, Comparator 2.
Negative Input, Comparator 2.
Positive Input, Comparator 2.
Negative Power Supply, Equalizer Sections. Connect to −5V.
Blue Channel Gain. Connect to OUTB for G = 1; connect to GND for G = 2.
Output, Blue Channel.
Positive Power Supply, Equalizer Sections. Connect to +5V.
Green Channel Gain. Connect to OUTG for G = 1; connect to GND for G = 2.
Output, Green Channel.
Red Channel Gain. Connect to OUTR for G = 1; connect to GND for G = 2.
Output, Red Channel.
Negative Power Supply, Digital Control. Connect to −5V.
Output Offset Control Voltage.
Digital Ground Reference.
Broadband Flat Gain Control Voltage.
Equalizer High Frequency Boost Control Voltage.
Lowpass Filter Cutoff Frequency Adjustment Control Voltage.
Rev. PrC | Page 7 of 13
AD8122
28
29
30
31
32
33, 36, 39
34
35
37
38
Exposed Underside Pad
Preliminary Technical Data
PD
DVS+
COAX/UTP
+INR
−INR
AGND
+ING
−ING
+INB
−INB
Power Down.
Positive Power Supply, Digital Control. Connect to +5V.
Cable Compensation Control Input. Connect to Logic 1 for Coax, Logic 0 for UTP.
Positive Input, Red Channel.
Negative Input, Red Channel.
Analog Ground Reference
Positive Input, Green Channel.
Negative Input, Green Channel.
Positive Input, Blue Channel.
Negative Input, Blue Channel.
Thermal Plane Connection. Connect to any PCB plane with voltage between VS+ and VS−.
Rev. PrC | Page 8 of 13
Preliminary Technical Data
AD8122
THEORY OF OPERATION
The AD8122 is a triple, wideband, low noise analog line
equalizer that compensates for losses in UTP and coaxial cables
up to 300 meters in length. The 3-channel architecture is
targeted at high resolution RGB applications but can be used in
HD YPbPr applications as well. The transfer function of
theAD8122 can be pin-selected for UTP or coaxial cable, and
the gain of each channel can be set to 1 or 2.
Two comparators are provided on-chip that can be used for
sync pulse extraction in systems that use sync-on-common
mode encoding. Each comparator has very low output impedance
and can therefore be used in a source-only cable termination
scheme by placing a series resistor equal to the cable characteristic
impedance directly on the comparator output. Additional
details are provided in the Applications Information section.
Four continuously adjustable control voltages, common
to the RGB channels, are available to the designer to provide
compensation for various cable lengths as well as for variations
in the cable itself. The VPEAK input is used to control the amount
of high frequency peaking. VPEAK is the control that is used to
compensate for frequency and cable-length dependent, high
frequency losses that are present due to the skin effect of the
cable. A second control pin, VGAIN, is used to adjust broadband gain
to compensate for low frequency flat losses present in the cable.
A third control pin, VFILTER, is used to adjust the cutoff
frequency of the output lowpass filters. Finally, an output offset
adjust control, VOFFSET, allows the designer to shift the output dc
level.
INPUT SINGLE-ENDED VOLTAGE RANGE
CONSIDERATIONS
When using the AD8122 as a receiver, it is important to ensure
that its single-ended input voltages stay within their specified
ranges. The received single-ended level for each input is
calculated by adding the common-mode level of the driver, the
single-ended peak amplitude of the received signal, the
amplitude of any sync pulses, and the other induced commonmode signals, such as ground shifts between the driver and the
AD8122 and pickup from external sources, such as power lines
and fluorescent lights. See the Applications Information section
for more details.
The AD8122 has a high impedance differential input that makes
termination simple and allows dc-coupled signals to be received
directly from the cable. The AD8122 input can also be used in a
single-ended fashion in coaxial cable applications. For differential
systems that require very wide input common-mode range, the
AD8143 high-voltage triple differential receiver can be placed
in front of the AD8122.
The AD8122 has a low impedance output that is capable of
driving a 150 Ω load. For systems where the AD8122 has to
drive a high impedance capacitive load, it is recommended that
a small series resistor be placed between the output and load to
buffer the capacitance. The resistor should not be so large as to
reduce the overall bandwidth to an unacceptable level.
Rev. PrC | Page 9 of 13
AD8122
Preliminary Technical Data
APPLICATIONS INFORMATION
The AD8122 is easy to apply because it contains everything
on-chip needed for cable loss compensation. Figure 8 shows a
basic application circuit (power supplies not shown) with
common-mode sync pulse extraction that is compatible with
the common-mode sync pulse encoding technique used in the
AD8134, AD8142, AD8147, and AD8148 triple differential
drivers. If sync extraction is not required, the terminations can
be single 100 Ω resistors, and the comparator inputs can be left
floating.
INPUT OVERDRIVE RECOVERY AND PROTECTION
Occasional large differential transients can occur on the cable
due to a number of causes, such as ESD and switching. When
operating the AD8122 at G = 1, a differential input that exceeds
+3.4V or -3.4V will cause the output to “stick” at the associated
power supply rail (positive rail for positive overdrive, negative
rail for negative overdrive). The AD8122 recovers from this
condition when the magnitude of the differential input falls
below 200 mV. Most video signals return to nominally zero
volts during the blanking intervals, therefore recovery from the
overdriven condition in systems that use these signals would
occur during the first blanking interval that occurs after the
overdrive event has passed. In systems with G = 1 that employ
video signals that do not return to zero, such as those that
include DC offsets, it is necessary to prevent the overdrive
condition from occurring. In these cases the protection circuit
illustrated in Figure 6, which limits the differential input voltage
to a little over ±2V, should be placed between the termination
resistors and each AD8122 differential input. The overdrive
condition does not occur in applications with G = 2.
The comparator outputs have nearly 0 Ω output impedance and
are designed to drive source-terminated transmission lines. The
source termination technique uses a resistor in series with each
comparator output such that the sum of the comparator source
resistance (≈0 Ω) and the series resistor equals the transmission
line characteristic impedance. The load end of the transmission
line is high impedance. When the signal is launched into the source
termination, its initial value is one-half of its source value because
its amplitude is divided by two in the voltage divider formed by
the source termination and the transmission line. At the load,
the signal experiences nearly 100% positive reflection due to the
high impedance load and is restored to nearly its full value. This
technique is commonly used in PCB layouts that involve high
speed digital logic.
Figure 7 shows how to apply the comparators with source
termination when driving a 50 Ω transmission line that is high
impedance at its receive end.
49.9
1
2
3
HN2D02FUTW1T1
4
5
6
TERMINATION
RESISTORS
AD8122
INPUT
49.9
6
5
HN2D02FUTW1T1
4
3
2
1
Figure 6. Required Input Protection For Applications With G = 1
COMPARATORS
While the two on-chip comparators are most often used to
extract video sync pulses from the received common-mode
voltages as shown in Figure 8, they may also be used to recover
sync pulses in sync-on-color applications, to receive differential
digital information received on other channels such as the fourth
UTP pair , or as general purpose comparators. Built-in hysteresis
helps to eliminate false triggers from noise. The Sync Pulse
Extraction Using Comparators section describes the sync
extraction details.
Rev. PrC | Page 10 of 13
HIGH-Z
49.9Ω
Z0 = 50Ω
06814-021
BASIC OPERATION
Figure 7. Using Comparator with Source Termination
Preliminary Technical Data
ANALOG
CONTROL
INPUTS
POWER DOWN CONTROL
CABLE SELECT CONTROL
AD8122
26
25
27
23
28
30
V PEAK
V GAIN
V FILTER
V OFFSET
AD8122
PD
COAX/UTP
RED
RECEIVED
RED VIDEO
49.9Ω
49.9Ω
31
16
32
19
GREEN
RECEIVED
GREEN VIDEO
49.9Ω
49.9Ω
16
35
15
49.9Ω
49.9Ω
1kΩ
GREEN VIDEO OUT
GREEN GAIN
37
12
38
11
1kΩ
RED GAIN
34
BLUE
RECEIVED
BLUE VIDEO
RED VIDEO OUT
BLUE VIDEO OUT
BLUE GAIN
BLUE CMV 2
RED CMV 3
4
1
HSYNC OUT
9
GREEN
CMV
475Ω
47pF
8
7
2
VSYNC OUT
47pF
Figure 8. Basic Application Circuit with Common-Mode Sync Extraction (supplies and input protection not shown)
SYNC PULSE EXTRACTION USING COMPARATORS
The AD8122 is useful in many systems that transport computer
video signals, which are typically comprised of red, green, and
blue video signals and separate horizontal and vertical sync
signals (RGBHV). Because the sync signals are separate and not
embedded in the color signals, it is advantageous to transmit
them using a simple scheme that encodes them among the three
common-mode voltages of the RGB signals. The AD8134,
AD8142, AD8147, and AD8148 triple differential drivers are
natural complements to the AD8122 because they perform the
sync pulse encoding with the necessary circuitry on-chip.
The sync encoding equations follow:
Red VCM =
[
K
V −H
2
(1)
[
]
(2)
K
V +H
2
]
(3)
Green VCM =
Blue VCM =
]
K
−2 V
2
[
where:
Red VCM, Green VCM, and Blue VCM are the transmitted commonmode voltages of the respective color signals.
K is an adjustable gain constant that is set by the driver.
V and H are the vertical and horizontal sync pulses, defined
with a weight of −1 when the pulses are in their low states, and a
weight of +1 when they are in their high states.
The AD8134, AD8142 and AD8146/AD8147/AD8148 data
sheets contain further details regarding the encoding scheme.
Figure 8 illustrates how the AD8122 comparators can be used to
extract the horizontal and vertical sync pulses that are encoded
on the RGB common-mode voltages by the aforementioned
drivers.
USING THE VPEAK, VGAIN, VFILTER, AND VOFFSET INPUTS
The VPEAK input is the main peaking control and is used to
compensate for the low-pass roll-off in the cable response. The
VGAIN input controls the wideband flat gain and is used to
compensate for the cable loss that is nominally flat.
The output of each channel contains an on-chip adjustable
lowpass filter to reduce high frequency noise. In most
applications, the filter cutoff frequency control, VFILTER, is
connected directly to the VPEAK voltage in order to provide
maximum bandwidth and minimum noise for a given VPEAK
setting. External lowpass filters are generally not required.
The VOFFSET input is used to produce an offset at the AD8122
output. The output offset is equal to the voltage applied to the
VOFFSET input, limited by the output swing limits.
Rev. PrC | Page 11 of 13
AD8122
Preliminary Technical Data
USING THE COAX/UTP SELECTOR
Connect this input to Logic 1 (or +5V) for coaxial cable and
Logic 0 (or GND) for UTP cable. This input has an internal
pulldown resistor, and can therefore be left floating in UTP
applications.
ends). In many of these applications, the AD8122 input voltage
range of typically ±4 V is sufficient. If wider input range is
required, the AD8143 triple receiver (input common-mode
range equals ±10.5 V on ±12 V supplies) may be placed in front of
the AD8122. Figure 9 illustrates how this is done for one channel.
ONE AD8143 CHANNEL
POWER SUPPLIES = ±12V
DRIVING HIGH-Z AND CAPACITIVE LOADS
In many RGB-over-UTP applications, delay correction is
required to remove the skew that exists among the three pairs
used to carry the RGB signals. The AD8120 is ideally suited to
perform this skew correction, and can be placed immediately
following the AD8122 in the receiver signal chain. The AD8120
has a high input impedance, and a fixed gain of two. When
using the AD8120 with the AD8122, the AD8122 should be
configured for a gain of one by connecting each video output to
its respective “GAIN” pin.
When driving a high impedance capacitive input, it is necessary
to place a small series resistor between each of the three AD8122
video outputs and the load to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth.
DRIVING 75 Ω CABLE WITH THE AD8122
When the RGB outputs must drive a 75 Ω line rather than a
high impedance load, an additional gain of two is required to
make up for the double termination loss (75 Ω source and load
terminations). Each output of the AD8122 is easily configured
for a gain of two by grounding the respective “GAIN” pin.
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered
to when designing with the AD8122. A solid ground plane is
required and controlled impedance traces should be used when
interconnecting the high speed signals. Source termination
resistors on all of the outputs must be placed as close as possible
to the output pins.
The exposed paddle on the underside of the AD8122 must be
connected to a pad that connects to at least one PCB plane.
Several thermal vias should be used to make the connection
between the pad and the plane(s).
High quality 0.1 µF power supply decoupling capacitors should
be placed as close as possible to all of the supply pins. Small
surface-mount ceramic capacitors should be used for these, and
tantalum capacitors are recommended for bulk supply decoupling.
INPUT COMMON-MODE RANGE
Most applications that use the AD8122 as a receiver use a driver
(such as one from the AD8146/AD8147/AD8148 family, the
AD8133, or the AD8134) powered from ±5 V supplies. This
places the common-mode voltage on the line nominally at 0 V
relative to the ground potential at the driver and provides optimum
immunity from any common-mode anomalies picked up along
the cable (including ground shifts between the driver and receiver
ONE AD8122
INPUT
+5V
RECEIVED
SIGNAL
100Ω
2
49.9Ω
3
HBAT-540C 1
–5V
Figure 9. Optional Use of AD8143 in Front of AD8122 for
Wide Input Common-Mode Range
The Schottky diodes are required to protect the AD8122 from
any AD8143 outputs that may exceed the AD8122 input limits.
The 49.9 Ω resistor limits the fault current and produces a pole
at approximately 800 MHz with the effective diode capacitance of
3 pF and the AD8122 input capacitance of 1 pF. The pole drops
the response by only 0.07 dB at 100 MHz and therefore has a
negligible effect on the signal.
When using a single 5 V supply on the driver side, the commonmode voltage at the driver output is typically 2.5V, or fixed at 1.5V
in the case of the AD8142. The largest received differential video
signal is approximately 700 mV p-p, and this therefore adds 175
mVPEAK to each single-ended side of the differential signal,
resulting in a worst-case peak voltage of 2.675 V or 1.675 V on
an AD8122 single-ended input (presuming there is no ground shift
between driver and receiver). These levels are within the
AD8122 input voltage swing limits, and such a system works well
as long as the difference in ground potential between driver and
receiver does not cause the input voltage swing to exceed these
limits.
When used, common-mode sync signals are generally applied
with a peak deviation of 500 mV during the blanking intervals
(video = 0V), and thereby increase the common-mode level
from 2.5 V to 3.0 V, or 1.5V to 2.0V in the case of the AD8142.
These common-mode levels are below the upper input voltage
swing limit of 4 V, and therefore leave 1 V or 2 V margin for
ground shifts between driver and receiver. There are two ways
to increase the common-mode range of the overall system. One
is to power the driver from dual supplies (output commonmode voltage = 0 V) and the other is to place an AD8143 in
front of the AD8122, as shown in Figure 9. These techniques may
be combined or applied separately.
POWER-DOWN
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. The input
logic levels and supply current in power-down mode are presented
in the Power Supply section of Table 1.
Rev. PrC | Page 12 of 13
Preliminary Technical Data
AD8122
OUTLINE DIMENSIONS
Figure 10. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-12)
Dimensions shown in millimeters
Pubcode: PR10780-0-5/12(PrC)
Rev. PrC | Page 13 of 13