Cypress CY7C008V-20AC 3.3v 64k/128k x 8/9 dual-port static ram Datasheet

25/0251
CY7C008V/009V
CY7C018V/019V
3.3V 64K/128K x 8/9
Dual-Port Static RAM
Features
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 µA (typical)
Logic Block Diagram
R/WL
R/WR
CE0L
CE1L
CEL
CE0R
CE1R
CER
OEL
OER
[1]
8/9
I/O0R–I/O7/8R
I/O
Control
[2]
A0L–A15/16L
[2]
[1]
8/9
I/O0L–I/O7/8L
16/17
Address
Decode
I/O
Control
True Dual-Ported
RAM Array
16/17
A0L–A15/16L
CEL
OEL
R/WL
SEML
Address
Decode
16/17
[2]
A0R–A15/16R
16/17
Interrupt
Semaphore
Arbitration
[3]
[2]
A0R–A15/16R
CER
OER
R/WR
SEMR
[3]
BUSYL
INTL
BUSYR
INTR
M/S
Notes:
1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
2. A0–A15 for 64K devices; A0–A16 for 128K.
3. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06044 Rev. *B
Revised December 27, 2002
CY7C008V/009V
CY7C018V/019V
Functional Description
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip select (CE) pin.
The CY7C008V/009V and CY7018V/019V are low-power
CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
The CY7C008V/009V and CY7018V/019V are available in
100-pin Thin Quad Plastic Flatpacks (TQFP).
Pin Configurations
NC
NC
A6R
A5R
A4R
A3R
A1R
A2R
A0R
INTR
BUSYR
M/S
GND
INTL
BUSYL
A0L
NC
A2L
A1L
A3L
A4L
A5L
A6L
NC
NC
100-Pin TQFP
(Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
[4]
NC
1
75
NC
NC
2
74
NC
A7L
3
73
A7R
A8L
4
72
A8R
A9L
5
71
A9R
A10L
6
70
A10R
A11L
7
69
A11R
A12L
8
68
A12R
A13L
9
67
A13R
A14L
10
66
A14R
A15L
11
65
A15R
A16L
12
64
A16R [4]
VCC
13
63
GND
NC
14
62
NC
NC
15
61
NC
NC
16
60
NC
NC
17
59
NC
CE0L
18
58
CE0R
CE1L
19
57
CE1R
SEML
20
56
SEMR
R/WL
21
55
R/WR
OEL
22
54
OER
GND
23
53
GND
NC
24
52
GND
NC
25
51
NC
CY7C009V (128K x 8)
CY7C008V (64K x 8)
NC
NC
NC
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
VCC
I/O2R
I/01R
GND
I/O0R
VCC
I/O0L
GND
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
4. This pin is NC for CY7C008V.
Document #: 38-06044 Rev. *B
Page 2 of 18
CY7C008V/009V
CY7C018V/019V
Pin Configurations (continued)
NC
A6R
A5R
A4R
A3R
A2R
A1R
A0R
INTR
BUSYR
M/S
VCC
GND
GND
BUSYL
INTL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
NC
NC
100-Pin TQFP
(Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
1
75
NC
NC
2
74
NC
A7L
3
73
A7R
A8L
4
72
A8R
A9L
5
71
A9R
A10L
6
70
A10R
A11L
7
69
A11R
A12L
8
68
A12R
A13L
9
67
A13R
A14L
10
66
A14R
A15L
11
65
A15R
[5] A16L
12
64
A16R [5]
VCC
13
63
GND
NC
14
62
NC
NC
15
61
NC
NC
16
60
NC
NC
17
59
NC
CE0L
18
58
CE0R
CE1L
19
57
CE1R
SEML
20
56
SEMR
R/WL
21
55
R/WR
OEL
22
54
OER
GND
23
53
GND
NC
24
52
GND
NC
25
51
NC
CY7C019V (128K x 9)
CY7C018V (64K x 9)
NC
NC
I/O8R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
VCC
I/O2R
I/01R
I/O0R
GND
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
I/O8L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C008V/009V
CY7C018V/019V
-15
CY7C008V/009V
CY7C018V/019V
-20
CY7C008V/009V
CY7C018V/019V
-25
Maximum Access Time (ns)
15
20
25
Typical Operating Current (mA)
125
120
115
Typical Standby Current for ISB1 (mA)
(Both ports TTL level)
35
35
30
Typical Standby Current for ISB3 (µA)
(Both ports CMOS level)
10 µA
10 µA
10 µA
Note:
5. This pin is NC for CY7C018V.
Document #: 38-06044 Rev. *B
Page 3 of 18
CY7C008V/009V
CY7C018V/019V
Pin Definitions
Left Port
Right Port
Description
CE0L, CE1L
CER, CE1R
Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A16L
A0R–A16R
Address (A0–A15 for 64K devices and A0–A16 for 128K devices)
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9)
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
NC
No Connect
Maximum Ratings[6]
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Input Voltage ..................................... –0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >1100V
Storage Temperature .................................–65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 300 mV
Industrial[7]
–40°C to +85°C
3.3V ± 300 mV
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VCC+0.5V
Note:
6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
7. Industrial parts are available in CY7C009V and CY7C019V only.
Document #: 38-06044 Rev. *B
Page 4 of 18
CY7C008V/009V
CY7C018V/019V
Electrical Characteristics Over the Operating Range
CY7C008V/009V
CY7C018V/019V
-15
Parameter
Description
VOH
Output HIGH Voltage (VCC = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage (VCC = Min., IOH = +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
IOZ
Output Leakage Current
ICC
Operating Current (VCC=Max.
IOUT = 0 mA) Outputs Disabled
Com’l.
Standby Current (Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX
Com’l.
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Com’l.
ISB1
ISB2
-20
-25
Typ
Min.
.
Max. Min. Typ. Max. Min. Typ. Max. Unit
2.4
2.4
2.4
0.4
2.2
0.4
2.2
–10
–5
10
–10
5
–5
10
–10
125
185
35
50
45
55
80
120
75
110
Ind.[7]
Ind.[7]
120
175
140
195
35
45
85
120
ISB3
Standby Current (Both Ports CMOS Lev- Com’l.
el) CEL & CER ≥ VCC − 0.2V, f = 0
Ind.[7]
10
250
10
250
10
250
ISB4
Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX[8]
75
105
70
95
80
105
Ind.[7]
V
V
0.8
5
Ind.[7]
Com’l.
0.4
2.2
0.8
–5
V
0.8
V
5
µA
10
µA
115
165
mA
30
40
mA
65
95
10
250
µA
60
80
mA
mA
mA
mA
mA
µA
mA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
10
pF
10
pF
AC Test Loads and Waveforms
3.3V
3.3V
R1 = 590Ω
C = 30 pF
RTH = 250Ω
OUTPUT
OUTPUT
R1 = 590Ω
OUTPUT
C = 30pF
R2 = 435Ω
C = 5 pF
VTH = 1.4V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
GND
10%
≤ 3 ns
90%
R2 = 435Ω
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
90%
10%
≤ 3 ns
Notes:
8. fMAX=1/tRC=All inputs cycling at f=1/tRC (except output enable). f=0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06044 Rev. *B
Page 5 of 18
CY7C008V/009V
CY7C018V/019V
Switching Characteristics Over the Operating Range[10]
CY7C008V/009V
CY7C018V/019V
-15
Parameter
Description
Min.
-20
Max.
Min.
-25
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[11]
CE LOW to Data Valid
15
20
15
3
25
20
3
15
ns
25
ns
3
20
10
ns
25
tDOE
OE LOW to Data Valid
tLZOE[12, 13, 14]
OE LOW to Low Z
tHZOE[12, 13, 14]
OE HIGH to High Z
tLZCE[12, 13, 14]
CE LOW to Low Z
tHZCE[12, 13, 14]
CE HIGH to High Z
tPU[14]
CE LOW to Power-Up
tPD[14]
tABE[11]
CE HIGH to Power-Down
15
20
25
ns
Byte Enable Access Time
15
20
25
ns
3
12
ns
3
10
3
12
3
10
0
13
3
15
3
12
0
ns
ns
ns
ns
15
0
ns
ns
WRITE CYCLE
tWC
Write Cycle Time
15
20
25
ns
tSCE[11]
CE LOW to Write End
12
16
20
ns
tAW
Address Valid to Write End
12
16
20
ns
tHA
Address Hold From Write End
0
0
0
ns
tSA[11]
Address Set-Up to Write Start
0
0
0
ns
tPWE
Write Pulse Width
12
17
22
ns
tSD
Data Set-Up to Write End
10
12
15
ns
tHD
Data Hold From Write End
0
tHZWE[13, 14]
R/W LOW to High Z
tLZWE[13, 14]
R/W HIGH to Low Z
tWDD[15]
Write Pulse to Data Delay
30
tDDD[15]
Write Data Valid to Read Data Valid
0
10
0
ns
15
ns
40
50
ns
25
30
35
ns
3
12
3
3
ns
BUSY TIMING[16]
tBLA
BUSY LOW from Address Match
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
ns
tBLC
BUSY LOW from CE LOW
15
20
20
ns
tBHC
BUSY HIGH from CE HIGH
15
16
17
ns
tPS
Port Set-Up for Priority
5
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
13
tBDD[17]
BUSY HIGH to Data Valid
15
15
17
20
ns
25
ns
Notes:
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
11. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
12. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
13. Test conditions used are Load 2.
14. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading
port, refer to Read Timing with Busy waveform.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
16. Test conditions used are Load 1.
17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document #: 38-06044 Rev. *B
Page 6 of 18
CY7C008V/009V
CY7C018V/019V
Switching Characteristics Over the Operating Range[10] (continued)
CY7C008V/009V
CY7C018V/019V
-15
Parameter
INTERRUPT
Description
Min.
-20
Max.
Min.
-25
Max.
Min.
Max.
Unit
TIMING[16]
tINS
INT Set Time
15
20
20
ns
tINR
INT Reset Time
15
20
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
10
12
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tSPS
SEM Flag Contention Window
5
tSAA
SEM Address Access Time
Data Retention Mode
The CY7C008V/009V and CY7018V/019V are designed with
battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention:
5
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
ns
20
25
ns
Timing
Data Retention Mode
VCC
3.0V
1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
5
15
VCC > 2.0V
3.0V
VCC to VCC – 0.2V
CE
Parameter
ICCDR1
Test Conditions[18]
@ VCCDR = 2V
tRC
V
IH
Max.
Unit
50
µA
Note:
18. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06044 Rev. *B
Page 7 of 18
CY7C008V/009V
CY7C018V/019V
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[19, 20, 21]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No.2 (Either Port CE/OE Access)[19, 22, 23]
tACE
CE
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Read Cycle No. 3 (Either Port)[19, 21, 22, 23]
tRC
ADDRESS
tAA
tOHA
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes:
19. R/W is HIGH for read cycles.
20. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
21. OE = VIL.
22. Address valid prior to or coincident with CE transition LOW.
23. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06044 Rev. *B
Page 8 of 18
CY7C008V/009V
CY7C018V/019V
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[24, 25, 26, 27]
tWC
ADDRESS
tHZOE [29]
OE
tAW
CE
[28]
tPWE[27]
tSA
tHA
R/W
tHZWE[29]
DATA OUT
tLZWE
NOTE 30
NOTE 30
tSD
tHD
DATA IN
Write Cycle No. 2: CE Controlled Timing[24, 25, 26, 31]
tWC
ADDRESS
tAW
CE
[28]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes:
24. R/W must be HIGH during all address transitions.
25. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
26. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
28. To access RAM, CE = VIL, SEM = VIH.
29. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
30. During this period, the I/O pins are in the output state, and input signals must not be applied.
31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06044 Rev. *B
Page 9 of 18
CY7C008V/009V
CY7C018V/019V
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[32]
tSAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tOHA
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[33, 34, 35]
A0L –A 2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes:
32. CE = HIGH for the duration of the above timing (both write and read cycle).
33. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
34. Semaphores are reset (available to both ports) at cycle start.
35. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06044 Rev. *B
Page 10 of 18
CY7C008V/009V
CY7C018V/019V
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[36]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Note:
36. CEL = CER = LOW.
Document #: 38-06044 Rev. *B
Page 11 of 18
CY7C008V/009V
CY7C018V/019V
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[37]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER ValidFirst:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSYL
Busy Timing Diagram No. 2 (Address Arbitration)[37]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note:
37. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 38-06044 Rev. *B
Page 12 of 18
CY7C008V/009V
CY7C018V/019V
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE FFFF (1FFFF for CY7C009V/19V)
tHA[38]
CE L
R/W L
INT R
tINS [39]
Right Side Clears INT R :
tRC
READ FFFF
(1FFFF for CY7C009V/19V)
ADDRESSR
CE R
tINR [39]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE FFFE (1FFFF for CY7C009V/19V)
tHA[38]
CE R
R/W R
INT L
tINS[39]
Left Side Clears INT L:
tRC
READ 1FFE
(1FFFF for CY7C009V/19V)
ADDRESSR
CE L
tINR[39]
R/W L
OE L
INT L
Notes:
38. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
39. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06044 Rev. *B
Page 13 of 18
CY7C008V/009V
CY7C018V/019V
Architecture
The CY7C008V/009V and CY7018V/019V consist of an array
of 64K and 128K words of 8 and 9 bits each of dual-port RAM
cells, I/O and address lines, and control signals (CE, OE, R/W).
These control pins permit independent access for reads or writes to
any location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two interrupt
(INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources.
With the M/S pin, the devices can function as a master (BUSY pins
are outputs) or as a slave (BUSY pins are inputs). The devices also
have an automatic power-down feature controlled by CE. Each port
is provided with its own output enable control (OE), which allows data
to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the
CE pin (see Write Cycle No. 2 waveform). Required inputs for
non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the
port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must also
be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFFF for the
CY7C008/18, 1FFFF for the CY7C009/19) is the mailbox for
the right port and the second-highest memory location (FFFE
for the CY7C008/18, 1FFFE for the CY7C009/19) is the mailbox for the left port. When one port writes to the other port’s
mailbox, an interrupt is generated to the owner. The interrupt
is reset when the owner reads the contents of the mailbox. The
message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C008V/009V and CY7018V/019V provide on-chip arbitration to resolve simultaneous memory location access
Document #: 38-06044 Rev. *B
(contention). If both ports’ CEs are asserted and an address
match occurs within tPS of each other, the busy logic will determine
which port has access. If tPS is violated, one port will definitely gain
permission to the location, but it is not predictable which port will get
that permission. BUSY will be asserted tBLA after an address match
or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This will allow the
device to interface to a master device with no external components.
Writing to slave devices must be delayed until after the BUSY input
has settled (tBLC or tBLA), otherwise, the slave chip may begin a write
cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration outcome
to a slave.
Semaphore Operation
The CY7C008V/009V and CY7018V/019V provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the
left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing
to the semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value will be
available tSWRD + tDOE after the rising edge of the semaphore write.
If the left port was successful (reads a zero), it assumes control of the
shared resource, otherwise (reads a one) it assumes the right port
has control and continues to poll the semaphore. When the right side
has relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
remain HIGH during SEM LOW). A0–2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows sample
semaphore operations.
When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to
prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which side
will control the semaphore.
Page 14 of 18
CY7C008V/009V
CY7C018V/019V
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
SEM
H
X
X
H
High Z
Deselected: Power-Down
H
H
L
L
Data Out
Read Data in Semaphore Flag
X
X
H
X
High Z
I/O Lines Disabled
X
L
Data In
Write into Semaphore Flag
H
I/O0–I/O8
Operation
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[40]
Left Port
Function
Right Port
R/WL
CEL
OEL
A0L–16L
INTL
R/WR
CER
OER
A0R–16R
INTR
Set Right INTR Flag
L
L
X
FFFF (or 1FFFF)
X
X
X
X
X
L[42]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
FFFF (or 1FFFF)
H[41]
Set Left INTL Flag
X
X
X
X
L[41]
L
L
X
FFFE (or 1FFFE)
X
Reset Left INTL Flag
X
L
L
FFFE (or 1FFFE)
H[42]
X
X
X
X
X
Table 3. Semaphore Operation Example
I/O0–I/O8 Left
I/O0–I/O8Right
No action
Function
1
1
Semaphore free
Status
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Notes:
40. A0L–16L and A0R–16R, 1FFFF/1FFFE for the CY7C009V/19V.
41. If BUSYR=L, then no change.
42. If BUSYL=L, then no change.
Document #: 38-06044 Rev. *B
Page 15 of 18
CY7C008V/009V
CY7C018V/019V
Ordering Information
64K x8 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
15
CY7C008V-15AC
A100
100-Pin Thin Quad Flat Pack
Commercial
20
CY7C008V-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C008V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
64K x9 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
15
CY7C018V-15AC
A100
100-Pin Thin Quad Flat Pack
Commercial
20
CY7C018V-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C018V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
128K x8 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
15
CY7C009V-15AC
A100
100-Pin Thin Quad Flat Pack
20
CY7C009V-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C009V-20AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C009V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
Commercial
128K x9 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
15
CY7C019V-15AC
A100
100-Pin Thin Quad Flat Pack
20
CY7C019V-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C019V-20AI
A100
100-Pin Thin Quad Flat Pack
Industrial
CY7C019V-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
Document #: 38-06044 Rev. *B
Commercial
Page 16 of 18
CY7C008V/009V
CY7C018V/019V
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
Document #: 38-06044 Rev. *B
Page 17 of 18
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C008V/009V
CY7C018V/019V
Document Title: CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM
Document Number: 38-06044
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110192
09/29/01
SZV
Change from Spec number: 38-00669 to 38-06044
*A
113541
04/15/02
OOR
Change pin 85 from BUSYL to BUSYR (pg. 3)
*B
122294
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
Document #: 38-06044 Rev. *B
Page 18 of 18
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