AD AD7989-1 18-bit, 100 ksps/500 ksps pulsar adcs in msop/lfcsp Datasheet

18-Bit, 100 kSPS/500 kSPS
PulSAR ADCs in MSOP/LFCSP
AD7989-1/AD7989-5
Data Sheet
FEATURES
GENERAL DESCRIPTION
Low power dissipation
AD7989-1
400 μW at 100 kSPS (VDD only)
700 μW at 100 kSPS (total)
AD7989-5
2 mW at 500 kSPS (VDD only)
3.5 mW at 500 kSPS (total)
18-bit resolution with no missing codes
Throughput: 100 kSPS (AD7989-1)/500 kSPS (AD7989-5)
INL: ±1 LSB typical, 2 LSB maximum
SNR: 98 dB at 1 kHz, VREF = 5 V
SINAD: 97 dB at 1 kHz
THD: −120 dB at 10 kHz
Dynamic range: 99 dB, VREF = 5 V
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.4 V and 5.1 V
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Proprietary serial interface: SPI-/QSPI™-/MICROWIRE™-/DSPcompatible1
Ability to daisy-chain multiple ADCs
10-lead package: MSOP and 3 mm × 3 mm LFCSP
The AD7989-1/AD7989-5 are 18-bit, successive approximation,
analog-to-digital converters (ADCs) that operate from a single
power supply, VDD. They contain a low power, high speed,
18-bit sampling ADC and a versatile serial interface port. On
the CNV rising edge, the AD7989-1/AD7989-5 sample the
voltage difference between the IN+ and IN− pins. The voltages
on these pins usually swing in opposite phases between 0 V and
VREF. The reference voltage, REF, is applied externally and can
be set independent of the supply voltage, VDD. Its power scales
linearly with throughput.
The AD7989-1/AD7989-5 are serial peripheral interface (SPI)
compatible, which features the ability, using the SDI input, to
daisy-chain several ADCs on a single 3-wire bus. It is compatible
with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
The AD7989-1/AD7989-5 are available in a 10-lead MSOP or a
10-lead LFCSP with operation specified from −40°C to +85°C.
Table 1. MSOP, LFCSP 14-/16-/18-Bit PulSAR® ADCs
Bits
181
100 kSPS
AD7989-12
250 kSPS
400 kSPS to 500 kSPS
≥1000 kSPS
AD76912
AD76902
AD79822
AD7989-5
1
16
AD7684
AD7687
2
AD7688
2
AD79842
2
AD76932
16
APPLICATIONS
Battery-powered equipment
Data acquisition systems
Medical instruments
Seismic data acquisition systems
3
143
AD76852
AD7694
AD76862
AD79802
AD7683
AD7988-52
AD79832
AD7988-12
AD7940
AD79422
AD79462
AD7680
1
True differential.
Pin-for-pin compatible.
3
Pseudo differential.
2
TYPICAL APPLICATIONS CIRCUIT
2.5V TO 5V 2.5V
REF VDD VIO
SDI/CS
AD7989-1/ SCK
AD7989-5 SDO
±10V, ±5V, ..
IN–
ADA4941-1
GND
CNV
1.8V TO 5.5V
3- OR 4-WIRE
INTERFACE
(SPI, CS,
DAISY CHAIN)
10232-001
IN+
Figure 1.
1
Protected by U.S. Patent 6,703,961.
Rev. A
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AD7989-1/AD7989-5
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Inputs ............................................................................. 15
Applications ....................................................................................... 1
Driver Amplifier Choice ........................................................... 15
General Description ......................................................................... 1
Single-to-Differential Driver .................................................... 16
Typical Applications Circuit............................................................ 1
Voltage Reference Input ............................................................ 16
Revision History ............................................................................... 2
Power Supply............................................................................... 16
Specifications..................................................................................... 3
Digital Interface .......................................................................... 16
Timing Specifications .................................................................. 5
CS Mode, 3-Wire ........................................................................ 17
Absolute Maximum Ratings............................................................ 7
CS Mode, 4-Wire ........................................................................ 18
ESD Caution .................................................................................. 7
Chain Mode ................................................................................ 19
Pin Configurations and Function Descriptions ........................... 8
Applications Information .............................................................. 20
Typical Performance Characteristics ............................................. 9
Interfacing to Blackfin® DSP ..................................................... 20
Terminology .................................................................................... 12
Layout .......................................................................................... 20
Theory of Operation ...................................................................... 13
Evaluating AD7989-1/AD7989-5 Performance ..................... 21
Circuit Information .................................................................... 13
Outline Dimensions ....................................................................... 22
Converter Operation .................................................................. 13
Ordering Guide .......................................................................... 23
Typical Connection Diagram ................................................... 14
REVISION HISTORY
7/14—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 1
Changes to Table 8 .......................................................................... 15
1/14—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
AD7989-1/AD7989-5
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Nonlinearity Error
Integral Nonlinearity Error
Transition Noise
Gain Error, TMIN to TMAX 2
Gain Error Temperature Drift
Zero Error, TMIN to TMAX2
Zero Temperature Drift
Power Supply Rejection Ratio
THROUGHPUT
AD7989-1 Conversion Rate
AD7989-5 Conversion Rate
Transient Response
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range 4
Signal-to-Noise Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion 5
Signal-to-Noise-and-Distortion Ratio
Test Conditions/Comments
Min
18
Typ
IN+ − IN−
IN+, IN−
IN+, IN−
fIN = 450 kHz
Acquisition phase
−VREF
−0.1
VREF × 0.475
Max
Unit
Bits
+VREF
VREF + 0.1
VREF × 0.525
V
V
V
dB
nA
VREF × 0.5
67
200
See the Analog Inputs section
18
−0.85
−2
VREF = 5 V
−0.023
VDD = 2.5 V ± 5%
±0.5
±1
1.05
+0.004
±1
±100
0.5
90
0
0
97
95.5
+0.023
+700
100
500
400
Full-scale step
VREF = 5 V
VREF = 2.5 V
fO = 1 kSPS
fIN = 1 kHz, VREF = 5 V, TA = 25°C
fIN = 1 kHz, VREF = 2.5 V, TA = 25°C
fIN = 10 kHz
fIN = 10 kHz
fIN = 1 kHz, VREF = 5 V, TA = 25°C
+1.5
+2
99
93
126
98
92.5
−115
−120
97
Bits
LSB
LSB
LSB 1
% of FS
ppm/°C
µV
ppm/°C
dB
kSPS
kSPS
ns
dB 3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
LSB means least significant bit. With the ±5 V input range, 1 LSB is 38.15 µV.
See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
Dynamic range is obtained by oversampling the ADC running at a throughput, fS, of 500 kSPS followed by postdigital filtering with an output word rate of fO.
5
Tested fully in production at fIN = 1 kHz.
1
2
3
Rev. A | Page 3 of 24
AD7989-1/AD7989-5
Data Sheet
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
Test Conditions/Comments
VDD Only
REF Only
VIO Only
AD7989-5 Power Dissipation
Total
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
1
2
Typ
2.4
Max
Unit
5.1
VREF = 5 V
250
V
µA
VDD = 2.5 V
10
2
MHz
ns
VIO > 3 V
VIO ≤ 3 V
VIO > 3 V
VIO ≤ 3 V
–0.3
–0.3
0.7 × VIO
0.9 × VIO
−1
−1
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 1, 2
AD7989-1 Power Dissipation
Total
Min
+0.3 × VIO
+0.1 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
Serial, 18 bits, twos complement
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
ISINK = +500 µA
ISOURCE = −500 µA
Specified performance
Functional range
VDD and VIO = 2.5 V, 25°C
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
10 kSPS throughput
100 kSPS throughput
2.375
2.3
1.8
−40
With all digital inputs forced to VIO or ground as required.
During acquisition phase.
Rev. A | Page 4 of 24
V
V
2.625
5.5
5.5
V
V
V
µA
70
700
400
170
130
86
860
µW
µW
µW
µW
µW
3.5
2
0.85
0.65
7.0
4.3
mW
mW
mW
mW
nJ/sample
+85
°C
0.35
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
500 kSPS throughput
TMIN to TMAX
2.5
V
V
V
V
µA
µA
Data Sheet
AD7989-1/AD7989-5
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
AD7989-1
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
AD7989-5
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
Rev. A | Page 5 of 24
Symbol
tCONV
tACQ
tCYC
tCONV
tACQ
tCYC
tCNVH
tSCK
Min
Typ
Max
Unit
100
9500
kSPS
ns
ns
µs
500
1600
400
2
500
kSPS
ns
ns
μs
ns
10.5
12
13
15
ns
ns
ns
ns
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
500
10
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
9.5
11
12
14
ns
ns
ns
ns
10
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
5
2
5
5
2
3
AD7989-1/AD7989-5
Data Sheet
500µA
IOL
1.4V
TO SDO
500µA
10232-002
CL
20pF
IOH
Figure 2. Load Circuit for Digital Interface Timing
Y% VIO1
X% VIO1
tDELAY
VIH2
VIL2
VIH2
VIL2
1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS
IH
IL
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. A | Page 6 of 24
10232-003
tDELAY
Data Sheet
AD7989-1/AD7989-5
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs
IN+, IN− to GND 1
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Output to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
10-Lead MSOP
10-Lead LFCSP_WD
θJC Thermal Impedance
10-Lead MSOP
10-Lead LFCSP_WD
Reflow Soldering
1
Rating
−0.3 V to VREF + 0.3 V or ±130 mA
−0.3 V to +6.0 V
−0.3 V to +3.0 V
+3 V to −6 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
200°C/W
48.7°C/W
44°C/W
2.96°C/W
JEDEC Standard (J-STD-020)
See the Analog Inputs section for an explanation of IN+ and IN−.
Rev. A | Page 7 of 24
AD7989-1/AD7989-5
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
IN+ 3
10
VIO
AD7989-1/
AD7989-5
9
SDI/CS
IN+ 3
8
SCK
IN– 4
TOP VIEW
(Not to Scale)
7
SDO
6
CNV
VDD 2
GND 5
IN– 4
GND 5
10232-004
REF 1
10 VIO
AD7989-1/
AD7989-5
TOP VIEW
(Not to Scale)
9
SDI_CS
8
SCK
7
SDO
6
CNV
NOTES:
1. THE EXPOSED PAD CAN BE CONNECTED TO GND.
Figure 4. 10-Lead MSOP Pin Configuration
10232-005
VDD 2
Figure 5. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
AI
AI
P
DI
7
8
9
SDO
SCK
SDI/CS
DO
DI
DI
10
VIO
P
EP
Description
Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and should
be decoupled closely to the GND pin with a 10 µF capacitor.
Power Supply.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Conversion Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the device: chain mode or chip select (CS) mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data is read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
Serial Data Input/Chip Select. This input has multiple functions. It selects the interface mode of the ADC as
follows:
Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI/CS is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI/CS is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI/CS is high during the CNV rising edge. In this mode, either SDI/CS or CNV can
enable the serial output signals when low.
Input/Output Interface Digital Power. This pin is nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
Exposed Pad. For the lead frame chip scale package (LFCSP), the exposed pad can be connected to GND.
This connection is not required to meet the electrical performances.
AI = analog input, DI = digital input, DO = digital output, and P = power.
1
Rev. A | Page 8 of 24
Data Sheet
AD7989-1/AD7989-5
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V.
2.0
POSITIVE INL: +0.79 LSB
NEGATIVE INL: –0.68 LSB
1.5
1.5
1.0
1.0
0.5
0.5
DNL (LSB)
0
–0.5
–1.0
–1.0
–1.5
–1.5
0
65536
131072
CODE
196608
262144
–2.0
0
65536
Figure 6. Integral Nonlinearity vs. Code
44806
43239
45k
50k
40k
35k
40k
32476
COUNTS
COUNTS
262144
50k
50975
29064
30k
20k
30k
25k
20013
20k
16682
15k
10k
10k
9064
7795
5k
0
745
29
3FFF2
881
3FFF4
3FFF6
3FFF8
43
3FFFA
0
0
3FFFC
CODE IN HEX
0
7
145
0
1
2
3
4
5
6
7
8
9
222
7
0
0
A
B
C
D
Figure 10. Histogram of a DC Input at the Code Transition
0
0
fS = 500kSPS
fIN = 1kHz
fS = 100kSPS
fIN = 1kHz
SNR = 97.2634dB
SINAD = 97.145dB
THD = –112.7dB
–20
AMPLITUDE (dB OF FULL SCALE)
SNR = 97.4361dB
SINAD = 97.3577dB
THD = –114.42dB
–40
0
CODE IN HEX
Figure 7. Histogram of a DC Input at the Code Center
–20
3158
2793
0
10232-007
0
3FFF0
–60
–80
–100
–120
–140
–40
–60
–80
–100
–120
–140
–160
0
50
150
100
FREQUENCY (kHz)
200
250
10232-008
AMPLITUDE (dB OF FULL SCALE)
196608
Figure 9. Differential Nonlinearity vs. Code
60k
0
131072
CODE
10232-010
–2.0
10232-006
–0.5
10232-009
0
POSITIVE INL: +0.46 LSB
NEGATIVE INL: –0.49 LSB
Figure 8. AD7989-5 FFT Plot
–160
0
10
20
30
FREQUENCY (kHz)
Figure 11. AD7989-1 FFT Plot
Rev. A | Page 9 of 24
40
50
10232-111
INL (LSB)
2.0
AD7989-1/AD7989-5
Data Sheet
100
100
SNR (dB REFERRED TO FULL SCALE)
99
98
95
97
SINAD (dB)
96
95
94
90
93
85
92
–9
–8
–7
–5
–4
–3
–6
INPUT LEVEL (dB)
–2
–1
0
80
0.1
10232-011
90
–10
1
10
FREQUENCY (kHz)
100
1k
10232-014
91
Figure 15. SINAD vs. Frequency
Figure 12. SNR vs. Input Level
100
18
–100
130
–105
125
SNR, SINAD
17
–110
110
–120
85
THD
15
105
–125
2.75
14
5.25
4.75
3.25
3.75
4.25
REFERENCE VOLTAGE (V)
10232-012
–130
2.25
3.75
4.25
3.25
REFERENCE VOLTAGE (V)
100
5.25
4.75
Figure 16. THD, SFDR vs. Reference Voltage
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
–115
98
–117
96
–119
THD (dB)
100
94
92
–121
–123
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
–125
–55
10232-013
90
–55
2.75
Figure 14. SNR vs. Temperature
–35
–15
5
25
45
65
TEMPERATURE (°C)
Figure 17. THD vs. Temperature
Rev. A | Page 10 of 24
85
105
125
10232-016
80
2.25
SFDR (dB)
115
–115
10232-015
ENOB
THD (dB)
16
120
SFDR
ENOB (Bits)
90
SNR (dB)
SNR, SINAD (dB)
95
Data Sheet
AD7989-1/AD7989-5
0.14
0.7
IVDD
IVDD
0.12
OPERATING CURRENTS (mA)
0.5
0.4
0.3
IREF
0.2
IVIO
0.10
0.08
0.06
0.04
IVIO
2.425
2.475
2.525
2.575
2.625
VDD VOLTAGE (V)
0
2.375
10232-118
0
2.375
2.425
2.475
2.625
Figure 21. Operating Currents vs. VDD Voltage (AD7989-1)
8
–85
7
POWER-DOWN CURRENTS (µA)
–80
–90
–95
–100
–105
–110
–115
6
5
4
3
IVDD + IVIO
2
1
10
FREQUENCY (kHz)
100
1k
0
–55
10232-017
–125
0.1
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
10232-018
1
–120
Figure 22. Power-Down Currents vs. Temperature
Figure 19. THD vs. Frequency
0.7
0.14
IVDD
IVDD
0.6
OPERATING CURRENTS (mA)
0.12
0.5
0.4
0.3
IREF
0.2
IVIO
0.1
0.10
008
0.06
IREF
0.04
IVIO
0.02
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
10232-120
OPERATING CURRENTS (mA)
2.575
VDD VOLTAGE (V)
Figure 18. Operating Currents vs. VDD Voltage (AD7989-5)
0
–55
2.525
10232-121
0.02
0.1
THD (dB)
IREF
Figure 20. Operating Currents vs. Temperature (AD7989-5)
0
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 23. Operating Currents vs. Temperature (AD7989-1)
Rev. A | Page 11 of 24
10233-123
OPERATING CURRENTS (mA)
0.6
AD7989-1/AD7989-5
Data Sheet
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, and the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 … 00 to 100 …01) should occur
at a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) occurs for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the ±5 V range). The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition from
the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
and is expressed in bits.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dB so that it includes all noise
sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
Rev. A | Page 12 of 24
Data Sheet
AD7989-1/AD7989-5
THEORY OF OPERATION
IN+
SWITCHES CONTROL
LSB
MSB
REF
131,072C
65,536C
4C
2C
C
SW+
C
BUSY
COMP
GND
131,072C
65,536C
4C
2C
C
CONTROL
LOGIC
C
MSB
OUTPUT CODE
LSB
SW–
10232-020
CNV
IN–
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7989-1/AD7989-5 are high speed, low power, singlesupply, precise, 18-bit ADCs using a successive approximation
architecture.
The AD7989-5 is capable of converting 500,000 samples per
second (500 kSPS), whereas the AD7989-1 is capable of
converting 100,000 samples per second (100 kSPS), and they
power down between conversions. When operating at 100 kSPS,
the ADC typically consumes 700 µW, making the AD7989-1
ideal for battery-powered applications.
The AD7989-1/AD7989-5 provide the user with an on-chip
track-and-hold amplifier and do not exhibit any pipeline delay
or latency, making these devices ideal for multiple multiplexed
channel applications.
The AD7989-1/AD7989-5 can be interfaced to any 1.8 V to 5 V
digital logic family. It is available in a 10-lead MSOP or a tiny
10-lead LFCSP that allows space savings and flexible
configurations.
CONVERTER OPERATION
The AD7989-1/AD7989-5 are a successive approximation
ADCs based on a charge redistribution digital-to-analog
converter (DAC). Figure 24 shows the simplified schematic of
the ADC. The capacitive DAC consists of two identical arrays of
18 binary-weighted capacitors, which are connected to the two
comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the IN+ and IN− inputs captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4 ... VREF/262,144). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the device returns to the acquisition phase, and the control logic
generates the ADC output code.
Because the AD7989-1/AD7989-5 have an on-board conversion
clock, the serial clock, SCK, is not required for the conversion
process.
Rev. A | Page 13 of 24
AD7989-1/AD7989-5
Data Sheet
Transfer Functions
Table 7. Output Codes and Ideal Input Voltages
Analog Input
VREF = 5 V
+4.999962 V
+38.15 µV
0V
−38.15 µV
−4.999962 V
−5 V
Description
+FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
011...111
011...110
011...101
1
2
Digital Output
Code (Hex)
0x1FFFF1
0x00001
0x00000
0x3FFFF
0x20001
0x200002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
100...010
Figure 26 shows an example of the recommended connection
diagram for the AD7989-1/AD7989-5 when multiple supplies
are available.
100...001
100...000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
10232-021
Figure 25. ADC Ideal Transfer Function
V+
REF1
2.5V
10µF2
100nF
V+
1.8V TO 5.5V
20Ω
0V TO VREF
100nF
REF
2.7nF
VDD
IN+
V–
AD7989-1/
AD7989-5
4
V+
IN–
20Ω
VREF TO 0V
ADA4841-x2, 3
VIO
SDI/CS
SCK
SDO
3-WIRE INTERFACE
CNV
GND
2.7nF
V–
4
1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE THE RECOMMENDED LAYOUT IN FIGURE 39 AND FIGURE 40.
3SEE THE DRIVER AMPLIFIER CHOICE SECTION.
4OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.
Figure 26. Typical Application Diagram with Multiple Supplies
Rev. A | Page 14 of 24
10232-022
ADC CODE (TWOS COMPLEMENT)
The ideal transfer characteristic for the AD7989-1/AD7989-5 is
shown in Figure 25 and Table 7.
Data Sheet
AD7989-1/AD7989-5
ANALOG INPUTS
Figure 27 shows an equivalent circuit of the input structure of
the AD7989-1/AD7989-5.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the reference input
voltage (REF) by more than 0.3 V. If the analog input signal
exceeds this level, the diodes become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 130 mA maximum. However, if the supplies of the
input buffer (for example, the supplies of the ADA4841-x in
Figure 26) are different from those of REF, the analog input
signal may eventually exceed the supply rails by more than
0.3 V. In such a case (for example, an input buffer with a short
circuit), the current limitation can be used to protect the device.
When the source impedance of the driving circuit is low, the
AD7989-1/AD7989-5 can be driven directly. Large source
impedances significantly affect the ac performance, especially
THD. The dc performances are less sensitive to the input
impedance. The maximum source impedance depends on the
amount of THD that can be tolerated. The THD degrades as a
function of the source impedance and the maximum input
frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7989-1/AD7989-5 is easy to drive, the driver
amplifier must meet the following requirements:
•
REF
D1
RIN
CIN
IN+ OR IN–
D2
10232-023
CPIN
GND
Figure 27. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
SNRLOSS
•
90
85
CMRR (dB)
80
75
•
70
•
1
10
100
FREQUENCY (kHz)
1k
10k
10232-024
65
60
Figure 28. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
During the sampling phase, when the switches are closed, the input
impedance is limited to CPIN. RIN and CIN make a one-pole, lowpass filter that reduces undesirable aliasing effects and limits
noise.
The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7989-1/AD7989-5. The noise from
the driver is filtered by the one-pole, low-pass filter of the
AD7989-1/AD7989-5 analog input circuit made by RIN and
CIN or by the external filter, if one is used. Because the
typical noise of the AD7989-1/AD7989-5 is 40 µV rms, the
SNR degradation due to the amplifier is


40
= 20 log 

π
2
2
 40 + f − 3dB (NeN )
2







where:
f–3dB is the input bandwidth, in megahertz, of the AD7989-1/
AD7989-5 (10 MHz) or the cutoff frequency of the input
filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
For ac applications, use a driver with a THD performance
commensurate with the AD7989-1/AD7989-5.
For multichannel multiplexed applications, the driver
amplifier and the AD7989-1/AD7989-5 analog input
circuit must settle for a full-scale step onto the capacitor
array at an 18-bit level (0.0004%, 4 ppm). In the data sheet
of the amplifier, settling at 0.1% to 0.01% is more commonly
specified. This settling may differ significantly from the
settling time at an 18-bit level and must be verified prior to
driver selection.
Table 8. Recommended Driver Amplifiers1
Amplifier
ADA4941-1
ADA4841-1/
ADA4841-2
AD8021
AD8022
OP184
AD8655
AD8605, AD8615
1
Typical Application
Very low noise, low power, single to differential
Very low noise, small, and low power
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single supply, low noise
5 V single supply, low power
For the latest recommended drivers, see the product recommendations
listed on the product webpage.
Rev. A | Page 15 of 24
AD7989-1/AD7989-5
Data Sheet
SINGLE-TO-DIFFERENTIAL DRIVER
POWER SUPPLY
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-to-differential
driver allows a differential input to the device. The schematic is
shown in Figure 29.
The AD7989-1/AD7989-5 use two power supply pins: a core
supply (VDD) and a digital input/output interface supply (VIO).
VIO allows direct interface with any logic between 1.8 V and 5.5 V.
To reduce the number of supplies needed, VIO and VDD can be
tied together. The AD7989-1/AD7989-5 are independent of
power supply sequencing between VIO and VDD. Additionally,
they are insensitive to power supply variations over a wide
frequency range, as shown in Figure 30.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.
95
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. Make sure
that the common mode is close to VREF/2. For example, for the
±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ,
R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
R4
+5V REF
10µF
+5.2V
100nF
REF
OUTN
2.7nF
100nF
70
+2.5V
IN+
REF
VDD
AD7989-1/
AD7989-5
2.7nF
20Ω
IN
60
IN–
GND
10
100
FREQUENCY (kHz)
1k
The AD7989-1/AD7989-5 power down automatically at the end
of each conversion phase.
ADA4941
–0.2V
R2
10232-025
R1
1
Figure 30. PSRR vs. Frequency
FB
±10V,
±5V, ..
75
65
20Ω
OUTP
80
10232-026
R6
R3
85
PSRR (dB)
R5
90
CF
Figure 29. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7989-1/AD7989-5 voltage reference input, REF, has a
dynamic input impedance and must, therefore, be driven by a
low impedance source with efficient decoupling between the
REF and GND pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031 or the AD8605),
a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate
for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference decoupling capacitor with values as small
as 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
DIGITAL INTERFACE
Although the AD7989-1/AD7989-5 have a reduced number of
pins, they offer flexibility in their serial interface modes.
When in CS mode, the AD7989-1/AD7989-5 are compatible
with SPI, QSPI, digital hosts, and DSPs. In this mode, the
AD7989-1/AD7989-5 can use either a 3-wire or 4-wire interface.
A 3-wire interface using the CNV, SCK, and SDO signals
minimizes wiring connections, which is useful, for instance, in
isolated applications. A 4-wire interface using the SDI/CS, CNV,
SCK, and SDO signals allows CNV, which initiates the conversions,
to be independent of the readback timing (SDI). This is useful
in low jitter sampling or simultaneous sampling applications.
When in chain mode, the AD7989-1/AD7989-5 provide a daisychain feature using the SDI input for cascading multiple ADCs
on a single data line, similar to a shift register.
The mode in which the device operates depends on the SDI/CS
level when the CNV rising edge occurs. CS mode is selected if
SDI/CS is high, and chain mode is selected if SDI/CS is low. The
SDI/CS hold time is such that when SDI/CS and CNV are
connected together, chain mode is always selected. The user
must time out the maximum conversion time prior to readback.
Rev. A | Page 16 of 24
Data Sheet
AD7989-1/AD7989-5
CS MODE, 3-WIRE
AD7989-5 enter the acquisition phase and power down. When
CNV goes low, the MSB is output onto SDO. The remaining data
bits are clocked by subsequent SCK falling edges. The data is valid
on both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided that it has an acceptable hold
time. After the 18th SCK falling edge or when CNV goes high
(whichever occurs first), SDO returns to high impedance.
This mode is usually used when a single AD7989-1/AD7989-5
is connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 31, and the corresponding timing is
given in Figure 32.
With SDI/CS tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When the conversion is complete, the AD7989-1/
CONVERT
DIGITAL HOST
CNV
VIO
SDI/CS
AD7989-1/
AD7989-5
DATA IN
SDO
10232-027
SCK
CLK
Figure 31. CS Mode, 3-Wire Connection Diagram (SDI High)
SDI/CS = 1
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
16
tHSDO
18
tSCKH
tDSDO
tEN
SDO
17
D17
D16
D15
tDIS
D1
Figure 32. CS Mode, 3-Wire Serial Interface Timing (SDI High)
Rev. A | Page 17 of 24
D0
10232-028
SCK
AD7989-1/AD7989-5
Data Sheet
CS MODE, 4-WIRE
minimum conversion time elapses and then held high for the
maximum possible conversion time. When the conversion is
complete, the AD7989-1/AD7989-5 enter the acquisition phase
and power down. Each ADC result can be read by bringing its
SDI/CS input low, which consequently outputs the MSB onto
SDO. The remaining data bits are then clocked by subsequent
SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided that it has an acceptable hold time. After the 18th
SCK falling edge or when SDI/CS goes high (whichever occurs
first), SDO returns to high impedance and another AD7989-1/
AD7989-5 can be read.
This mode is usually used when multiple AD7989-1/AD7989-5
devices are connected to an SPI-compatible digital host.
A connection diagram example using two AD7989-1/AD7989-5
devices is shown in Figure 33, and the corresponding timing is
given in Figure 34.
With SDI high, a rising edge on CNV initiates a conversion,
selects SDI/CS mode, and forces SDO to high impedance. In
this mode, CNV must be held high during the conversion phase
and the subsequent data readback. (If SDI/CS and CNV are low,
SDO is driven low.) Prior to the minimum conversion time,
SDI/CS can be used to select other SPI devices, such as analog
multiplexers, but SDI/CS must be returned high before the
CS2
CS1
CONVERT
CNV
AD7989-1/
AD7989-5
SDO
SDI/CS
AD7989-1/
AD7989-5
SCK
DIGITAL HOST
SDO
SCK
10232-029
SDI/CS
CNV
DATA IN
CLK
Figure 33. CS Mode, 4-Wire Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI/CS (CS1)
tHSDICNV
SDI/CS (CS2)
tSCK
tSCKL
1
2
16
3
tHSDO
18
19
20
D1
D0
D17
D16
34
35
36
D1
D0
tDSDO
tEN
SDO
17
tSCKH
D17
D16
D15
tDIS
Figure 34. CS Mode, 4-Wire Serial Interface Timing
Rev. A | Page 18 of 24
10232-030
SCK
Data Sheet
AD7989-1/AD7989-5
CHAIN MODE
conversion phase and the subsequent data readback. When the
conversion is complete, the MSB is output onto SDO and the
AD7989-1/AD7989-5 enter the acquisition phase and power
down. The remaining data bits stored in the internal shift
register are clocked by subsequent SCK falling edges. For each
ADC, SDI feeds the input of the internal shift register and is
clocked by the SCK falling edge. Each ADC in the chain outputs
its data MSB first, and 18 × N clocks are required to read back
the N ADCs. The data is valid on both SCK edges. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and, consequently,
more AD7989-1/AD7989-5 devices in the chain, provided that
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
This mode can be used to daisy-chain multiple AD7989-1/
AD7989-5 devices on a 3-wire serial interface. This feature is
useful for reducing component count and wiring connections,
for example, in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using two AD7989-1/AD7989-5
devices is shown in Figure 35, and the corresponding timing is
given in Figure 36.
When SDI/CS and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, and selects the
chain mode. In this mode, CNV is held high during the
CONVERT
CNV
AD7989-1/
AD7989-5
SDO
SDI/CS
A
SCK
DIGITAL HOST
AD7989-1/
AD7989-5
SDO
DATA IN
B
SCK
10232-031
SDI/CS
CNV
CLK
Figure 35. Chain Mode Connection Diagram
SDI/CSA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
tHSCKCNV
2
3
16
17
tSSDISCK
18
19
20
DA17
DA16
34
35
36
DA1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDI/CSB
DA17
DA16
DA15
DA1
DA0
DB17
DB16
DB15
DB1
DB0
SDOB
Figure 36. Chain Mode Serial Interface Timing
Rev. A | Page 19 of 24
10232-032
tHSDO
tDSDO
AD7989-1/AD7989-5
Data Sheet
APPLICATIONS INFORMATION
INTERFACING TO BLACKFIN® DSP
LAYOUT
The AD7989-1/AD7989-5 can easily connect to a DSP SPI or
SPORT. The SPI configuration is straightforward using the
standard SPI interface, as shown in Figure 37.
Design the printed circuit board that houses the AD7989-1/
AD7989-5 so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7989-1/AD7989-5, with its analog signals on the left side
and its digital signals on the right side, eases this task.
SCK
SPI_MISO
SDO
SPI_MOSI
CNV
AD7989-1/
AD7989-5
10232-035
DSP
SPI_CLK
Figure 37. Typical Connection to Blackfin SPI Interface
Similarly, the SPORT interface can be used to interface to this
ADC. The SPORT interface has some benefits in that it can use
direct memory access (DMA) and provides a lower jitter CNV
signal generated from a hardware counter.
Some glue logic may be required between SPORT and the
AD7989-1/AD7989-5 interface. The evaluation board for the
AD7989-1/AD7989-5 interfaces directly to the SPORT of the
Blackfin-based (ADSP-BF527) SDP board. The configuration
used for the SPORT interface requires the addition of some glue
logic as shown in Figure 38. The SCK input to the ADC was
gated off when CNV was high to keep the SCK line static while
converting the data, thereby ensuring the best integrity of the
result. This approach uses an AND gate and a NOT gate for the
SCK path. The other logic gates used on the RSCLK and RFS
paths are for delay matching purposes and may not be
necessary when path lengths are short.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7989-1/AD7989-5 is used as a shield. Do not run fast
switching signals, such as CNV or clocks, near analog signal
paths. Avoid crossover of digital and analog signals.
Using at least one ground plane is recommended. It can be
common or split between the digital and analog sections. In the
latter case, join the planes underneath the AD7989-1/AD7989-5
devices.
The AD7989-1/AD7989-5 voltage reference input, REF, has a
dynamic input impedance. Decouple REF with minimal
parasitic inductances by placing the reference decoupling
ceramic capacitor close to, but ideally right up against, the REF
and GND pins and connecting them with wide, low impedance
traces.
Finally, decouple the power supplies of the AD7989-1/AD7989-5,
VDD and VIO, with ceramic capacitors, typically 100 nF, placed
close to the AD7989-1/AD7989-5 and connected using short,
wide traces to provide low impedance paths and to reduce the
effect of glitches on the power supply lines.
An example of a layout following these rules is shown in
Figure 39 and Figure 40.
This is one approach to using the SPORT interface for this
ADC; there may be other solutions similar to this approach.
VDRIVE
DR
SDO
RSCLK
TSCLK
SCK
RFS
AD7989-1/
AD7989-5
TFS
CNV
10232-045
BLACKFIN
DSP
Figure 38. Evaluation Board Connection to Blackfin Sport Interface
Rev. A | Page 20 of 24
Data Sheet
AD7989-1/AD7989-5
EVALUATING AD7989-1/AD7989-5
PERFORMANCE
Other recommended layouts for the AD7989-1/AD7989-5 are
outlined in UG-340, the user guide of the evaluation board for
the AD7989-1/AD7989-5 (EVAL-AD7989-5SDZ). The
evaluation board package includes a fully assembled and tested
evaluation board, the user guide, and software for controlling
the board from a PC via the EVAL-SDP-CB1Z.
10232-034
AD7989-1/
AD7989-5
10232-033
Figure 40. Recommended Layout of the AD7989-1/AD7989-5 (Bottom Layer)
Figure 39. Recommended Layout of the AD7989-1/AD7989-5 (Top Layer)
Rev. A | Page 21 of 24
AD7989-1/AD7989-5
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 41. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
Rev. A | Page 22 of 24
02-05-2013-C
PIN 1 INDEX
AREA
Data Sheet
AD7989-1/AD7989-5
ORDERING GUIDE
Model 1, 2, 3
AD7989-1BRMZ
AD7989-1BRMZ-RL7
AD7989-1BCPZ-RL7
AD7989-1BCPZ-R2
AD7989-5BRMZ
AD7989-5BRMZ-RL7
AD7989-5BCPZ-RL7
AD7989-5BCPZ-R2
EVAL-AD7989-5SDZ
EVAL-SDP-CB1Z
1
2
3
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP, Tube
10-Lead MSOP, 7” Tape and Reel
10-Lead LFCSP_WD, 7” Tape and Reel
10-Lead LFCSP_WD
10-Lead MSOP, Tube
10-Lead MSOP, 7” Tape and Reel
10-Lead LFCSP_WD, 7” Tape and Reel
10-Lead LFCSP_WD
Evaluation Board with AD7989-5 Populated; Use for
Evaluation of Both AD7989-1 and AD7989-5
System Demonstration Board, Used as a Controller
Board for Data Transfer via USB Interface to PC
Package
Option
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
Ordering
Quantity
50
1,000
1,500
250
50
1,000
1,500
250
Branding
C76
C76
C80
C80
C7N
C7N
C7Y
C7Y
Z = RoHS Compliant Part.
The EVAL-AD7989-5SDZ board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
The EVAL-SDP-CB1Z board allows a PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the SD designator.
Rev. A | Page 23 of 24
AD7989-1/AD7989-5
Data Sheet
NOTES
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10232-0-7/14(A)
Rev. A | Page 24 of 24