ACPL-570XL, ACPL-573XL, ACPL-177XL, 5962-08227 Hermetically Sealed 3.3V, Low IF, Wide VCC, High Gain Optocouplers Data Sheet Description Features These devices are single, dual, and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from DLA Drawing 5962-08227. All devices are manufactured and tested on a MIL-PRF-38534 certified line and are included in the DLA Qualified Products Database Supplemental Information Sheets QPDSIS-38534 as Hybrid Microcircuits. Low power consumption 3.3V Supply voltages Dual marked with device part number and DLA drawing number Manufactured and tested on a MIL-PRF-38534 Certified Line QPDSIS-38534, Class H and K Three hermetically sealed package configurations Performance guaranteed over full military temperature range: -55°C to +125°C Low input current requirement: 0.5 mA High current transfer ratio: 1500% typical @ IF = 0.5 mA Low output saturation voltage: 0.11 V typical 1500 Vdc withstand test voltage HCPL-4701/31, -070A/31 function compatibility Each channel contains a GaAsP light emitting diode which is optically coupled to an integrated high gain photon detector. The high gain output stage features an open collector output providing both lower saturation voltage and higher signaling speed than possible with conventional photo-Darlington optocouplers. The supply voltage can be operated as low as 3.0 V without adversely affecting the parametric performance. These devices have a 300% minimum CTR at an input current of only 0.5 mA making them ideal for use in low input current applications such as MOS, CMOS, low power logic interfaces or line receivers. Applications Military and aerospace High reliability systems Telephone ring detection Microprocessor system interface Transportation, medical, and life critical systems Isolated input line receiver EIA RS-232-C line receiver Voltage level shifting Isolated input line receiver Isolated output line driver Logic ground isolation Harsh industrial environments Current loop receiver System test equipment isolation Process control input/output isolation The connection of a 0.1 F bypass capacitor between VCC and GND is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Package styles for these parts are 8 and 16 pin DIP through hole (case outlines P and E respectively). Devices may be purchased with a variety of lead bend and plating options. See Selection Guide table for details. Standard Military Drawing (SMD) parts are available for each package and lead style. Functional Diagram Multiple Channel Devices Available 1 8 2 7 3 6 4 5 Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are similar for all parts except as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities justify the use of a common data base for die related reliability. Truth Table (Positive Logic) Input Output On (H) L Off (L) H Selection Guide – Package Styles and Lead Configuration Options Package 16 Pin DIP 8 Pin DIP 8 Pin DIP Lead Style Through Hole Through Hole Through Hole Channels 4 1 2 Common Channel Wiring VCC, GND None VCC, GND Commercial ACPL-1770L ACPL-5700L ACPL-5730L MIL-PRF-38534, Class H ACPL-1772L ACPL-5701L ACPL-5731L MIL-PRF-38534, Class K ACPL-177KL ACPL-570KL ACPL-573KL Standard Lead Finish Gold Plate Gold Plate Gold Plate Solder Dipped* Option -200 Option -200 Option -200 Butt Cut/Gold Plate Option -100 Option -100 Option -100 Gull Wing/Soldered* Option -300 Option -300 Option -300 Prescript for all below 5962- 5962- 5962- Gold Plate 0822703HEC 0822701HPC 0822702HPC Solder Dipped* 0822703HEA 0822701HPA 0822702HPA Butt Cut/Gold Plate 0822703HUC 0822701HYC 0822702HYC Butt Cut/Soldered* 0822703HUA 0822701HYA 0822702HYA Gull Wing/Soldered* 0822703HTA 0822701HXA 0822702HXA Prescript for all below 5962- 5962- 5962- Gold Plate 0822703KEC 0822701KPC 0822702KPC Solder Dipped* 0822703KEA 0822701KPA 0822702KPA Butt Cut/Gold Plate 0822703KUC 0822701KYC 0822702KYC Butt Cut/Soldered* 0822703KUA 0822701KYA 0822702KYA Gull Wing/Soldered* 0822703KTA 0822701KXA 0822702KXA Avago Part # & Options Class H SMD Part # Class K SMD Part # * Solder contains lead. 2 Functional Diagrams 16 pin DIP 8 pin DIP 8 pin DIP Through Hole Through Hole Through Hole 4 Channels 1 Channel 2 Channels 1 16 1 8 1 8 2 15 2 7 2 7 3 14 3 6 3 6 4 13 4 5 4 5 5 12 6 11 7 10 8 9 Outline Drawings 16 Pin DIP Through Hole, 4 Channels 20.06 (0.790) 0.89 (0.035) 20.83 (0.820) 1.65 (0.065) 8.13 (0.320) MAX. 4.45 (0.175) MAX. 0.51 (0.020) MIN. 3.81 (0.150) MIN. 2.29 (0.090) 2.79 (0.110) 7.36 (0.290) 7.87 (0.310) 0.51 (0.020) MAX. Device Marking Avago LOGO Avago P/N DLA SMD* DLA SMD* PIN ONE/ ESD IDENT 0.20 (0.008) 0.33 (0.013) 8 Pin DIP Through Hole, 1 and 2 Channel A QYYWWZ XXXXXX XXXXXXX XXX XXX t 50434 *QUALIFIED PARTS ONLY COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE* ANODE 2 IF VCC 8 ICC + VF CATHODE – IO 6 3 5 Note: Dimensions in Millimeters (Inches). 3 VO GND Hermetic Optocoupler Options Option Description 100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). 4.32 (0.170) MAX. 0.51 (0.020) MIN. 1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 4.32 (0.170) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.14 (0.045) 1.40 (0.055) 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MAX. 7.36 (0.290) 7.87 (0.310) Note: Dimensions in Millimeters (Inches). 200 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and 16 pin DIP. DLA Drawing part numbers contain provisions for lead finish. 300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped leads. 4.57 (0.180) MAX. 0.51 (0.020) MIN. 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 4.57 (0.180) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 4.57 (0.180) MAX. 5° MAX. 0.51 (0.020) MAX. Note: Dimensions in Millimeters (Inches). Solder contains lead. 4 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390) 1.07 (0.042) 1.32 (0.052) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -65 +150 °C Operating Temperature TA -55 +125 °C Case Temperature TC +170 °C Junction Temperature TJ +175 °C 260 for 10 sec °C 40 mA Lead Solder Temperature Notes Output Current (each channel) IO Output Voltage (each channel) VO -0.5 20 V 1 Supply Voltage VCC -0.5 20 V 1 Output Power Dissipation (each channel) 50 mW 2 Peak Input Current (each channel, <1 ms duration) 20 mA Average Input Current (each channel) IF 10 mA Reverse Input Voltage (each channel) VR 5 V Package Power Dissipation (each channel) PD 200 mW 3 8 Pin Ceramic DIP Single Channel Schematic ANODE 2 IF VCC 8 ICC + VF CATHODE – IO 6 3 5 VO GND ESD Classification (MIL-STD-883, Method 3015) ACPL-5700L/01L/0KL ( ), Class 2 ACPL-5730L/31L/3KL ( A), Class 3A ACPL-1770L/2L/KL ( B), Class 3B Recommended Operating Conditions Parameter Symbol Input Current, Low Level (Each Channel) IF(OFF) Input Current, High Level (Each Channel) IF(ON) Supply Voltage Output Voltage 5 Min. Max. Units 2.0 A 0.5 5 mA VCC 3.0 7.0 V VO 3.0 7.0 V Electrical Characteristics, TA = -55°C to +125°C, unless otherwise specified Min. Typ.* 1, 2, 3 300 1500 IF = 1.6 mA, VO = 0.4 V, VCC = 3.0 V 300 1300 IF =5 mA, VO = 0.4 V, VCC = 3.0 V 200 800 Parameter Symbol Test Conditions Current Transfer Ratio CTR IF = 0.5 mA, VO = 0.4 V, VCC = 3.0 V Logic Low Output Voltage VOL Logic High Output IOH Current IOHX Logic Low Supply Current Single Channel ICCL Limits Group A[13] Subgroup IF = 0.5 mA, IOL = 1.5 mA, VCC = 3.0 V 1, 2, 3 3 4, 5 V 2 4 0.4 4 IF =5 mA, IOL = 10 mA, VCC = 3.0 V 0.09 0.4 4 1.0 100 A 4 100 A 4, 6 0.8 2 mA IF =2 A, VO = 7 V, VCC = 7 V 1, 2, 3 IF =1.6 mA, VCC = 7 V 1, 2, 3 Quad Channel IF1 = IF2 =IF3 =IF4 =1.6 mA, VCC = 7 V 1.3 4 0.01 20 IF =0 mA, VCC = 7 V 1, 2, 3 IF1 =IF2 = 0 mA, VCC = 7 V 40 IF1 = IF2 =IF3 =IF4 =0 mA, VCC = 7 V 40 Input Forward Voltage VF IF = 1.6 mA 1, 2, 3 1.0 Input Reverse Breakdown Voltage BVR IR = 10 A 1, 2, 3 5 Input-Output II-O Insulation Leakage Current ≤65% Relative Humidity TA =25°C, t = 5 s, VI-O = 1500 VDC 1 Capacitance Between Input-Output f = 1 MHz, TA =25°C 4 6 % 0.06 4 CI-O Note IF = 1.6 mA, IOL = 4.8 mA, VCC = 3.0 V 0.8 Quad Channel Fig. 0.4 IF1 =IF2 = 1.6 mA, VCC = 7 V ICCH Units 0.05 Dual Channel Logic Single High Channel Supply Dual Current Channel * Max. All typical values are at VCC = 3.3 V, TA = 25°C. 1.4 1.8 4 A V 1 4 V 4 1.0 A 7, 12 4 pF 4, 8, 14 Electrical Characteristics (cont), TA = -55°C to +125°C, unless otherwise specified Parameter Symbol Propagation Delay tPHL Time to Logic Low at Output tPHL tPHL Propagation Delay tPLH Time to Logic High at Output tPLH tPLH Group A[13] Subgroup Test Conditions Limits Min. Typ.* Max. Units Fig. Note s 5, 6, 7, 8 4 IF = 0.5 mA, RL = 2.2 k, VCC = 3.3 V 9, 10, 11 40 100 IF = 1.6 mA, RL = 680 , VCC = 3.3 V 9, 10, 11 9 30 4 IF =5 mA, RL = 330 , VCC = 3.3 V 9 2 5 4 IF = 0.5 mA, RL = 2.2 k, VCC = 3.3 V 9, 10, 11 10 60 IF = 1.6 mA, RL = 680 , VCC = 3.3 V 9, 10, 11 8 50 4 IF =5 mA, RL = 330 , VCC = 3.3 V 9 6 20 4 10, 11 10 10, 11 s 5, 6, 7, 8 4 30 Common Mode Transient Immunity at Low Output Level |CML| VCC = 3.3 V, IF = 1.6 mA RL = 680 k |VCM|= 50 VP-P 9, 10, 11 500 1000 V/s 9 4, 10 11, 14 Common Mode Transient Immunity at High Output Level |CMH| VCC = 3.3 V , IF =0 mA RL = 680 k |VCM|= 50 VP-P 9, 10, 11 500 1000 V/s 9 4, 10 11, 14 * All typical values are at VCC = 3.3 V, TA = 25°C. Typical Characteristics, TA = 25°C Parameter Sym. Typ. Units Test Conditions Note Input Capacitance CIN 60 pF VF =0 V, f = 1 MHz 4 Input Diode Temperature Coefficient VF/TA -1.8 mV/°C IF = 1.6 mA 4 Resistance (Input-Output) RI-O 1012 VI-O = 500 V 4, 8 Capacitance (Input-Output) CI-O 2.0 pF f = 1 MHz 4, 8 Input-Input Leakage Current II-I 0.5 nA Relative Humidity = ≤65%, VI-I = 500 V, t = 5 s 9 Resistance (Input-Input) RI-I 1012 VI-I = 500 V 9 Capacitance (Input-Input) CI-I 1.0 pF f = 1 MHz 9 Dual and Quad Channel Product Only 7 Notes: 1. GND Pin should be the most negative voltage at the detector side. Keeping VCC as low as possible, but greater than 2.0 V, will provide lowest total IOH over temperature. 2. Output power is collector output power plus total supply power for the single channel device. For the dual channel device, output power is collector output power plus one half the total supply power. For the quad channel device, output power is collector output power plus one fourth of total supply power. Derate at 1.66 mW/°C above 110°C. 3. Derate IF at 0.33 mA/°C above 110°C. 4. Each channel. 5. CURRENT TRANSFER RATIO is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100%. 6. IOHX is the leakage current resulting from channel to channel optical crosstalk. IF = 2 μA for channel under test. For all other channels, IF = 10 mA. 7. All devices are considered two-terminal devices; measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 8. Measured between each input pair shorted together and all output connections for that channel shorted together. 9. Measured between adjacent input pairs shorted together for each multi-channel device. 10. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V). 8 11. In applications where dV/dt may exceed 50,000 V/s (such as a static discharge) a series resistor, RCC, should be included to protect the detector ICs from destructively high surge currents. The recommended value is: 1 (V) RCC = ————— k 0.15 IF (mA) for single channel; 1 (V) RCC = ————— k 0.3 IF (mA) for dual channel; 1 (V) RCC = ————— k 0.6 IF (mA) for quad channel. 12. This is a momentary withstand test, not an operating condition. 13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25,125, and -55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 14. Parameters tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits specified for all lots not specifically tested. IO - NOMINALIZED OUTPUT CURRENT 8 7 VCC = 3.3V TA = 25°C 5 4 3 1 1.5 0.4 0.6 0.8 1.0 1.2 1.4 Vo - OUTPUT VOLTAGE - V 1.6 1.8 2.0 100 TA = 0°C TA = 25°C 1.0 TA = 125°C NORMINALIZED AT: CTR AT IF = 0.5 mA TA = 25°C VCC = 3.3V VO = 0.4V ICC - NOMINALIZED SUPPLY CURRENT CTR-NORMINALIZED CURRENT TRANSFER RATIO tPHL - PROPAGATION DELAY TO LOGIC LOW μs 0.2 Figure 2. Normalized DC Transfer Characteristics. TA = 100°C 0.5 TA = 55°C 0.0 0.1 1 IF-INPUT DIODE FORWARD CURRENT mA 10 Figure 3. Normalized Current Transfer Ratio vs. Input Diode Forward Current. 100 10 1 VCC = 3.3V TA = 25°C WIDTH = 50 μs 0.1 0.1 IF = 0.5 mA, RL = 2.2 Kohm IF = 1.6 mA, RL = 680 ohm IF = 5.0 mA, RL = 330 ohm 1 10 100 T - INPUT PULSE PERIOD ms Figure 5. Propagation Delay to Logic Low vs. Input Pulse Period. 9 1.0 mA NOMINALIZED AT: IO AT IF = 0.5 mA IF = 0.5 mA 2 0 0.0 Figure 1. Input Diode Forward Current vs. Forward Voltage. 5.0 mA 4.5 mA 4.0 mA 3.5 mA 3.0 mA 2.5 mA 2.0 mA 1.5 mA 6 10 VCC = 18V 1 0.1 0.01 0.1 VCC = 3.3V NORMINALIZED AT: ICC AT IF = 1.6 mA (ALL CHANNELS) VCC = 18V TA = 25°C 1 10 IF - INPUT DIODE FORWARD CURRENT mA Figure 4. Normalized Supply Current vs. Input Diode Forward Current. 100 45 IF = 0.5mA, RL = 2.2kohm IF = 1.6mA, RL = 680ohm IF = 5.0mA, RL=330ohm 50 40 TPHL 40 tp - PROPAGATION DELAY s tp - PROPAGATION DELAY s 60 TPLH 30 TPLH 20 TPLH 10 TPHL TPHL 0 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 TA - TEMPERATURE°C Figure 6. Propagation Delay vs. Temperature. PULSE GEN. ZO = 50 tr, tf = 5.0 ns f = 100 Hz tPULSE = 0.5ms IF MONITOR Rm 35 30 25 20 15 tPLH, RL = 2.2Kohm 10 tPLH, RL = 680ohm tPLH, RL = 330ohm 5 0 0 RCC * 1 8 2 7 3 6 4 5 2 4 6 8 10 IF - INPUT DIODE FORWARD CURRENT mA 12 Figure 7. Propagation Delay vs. Input Diode Forward Current. IF IF VCC = 3.2V TA = 25°C PULSE WIDTH = 50 s PERIOD = 10ms tPHL, RL = 330ohm TO 2.2Kohm 56 1.0 F +3 V RCC * B 1 8 2 7 3 6 4 5 A RL 56 1.0 F +3 V RL VO CL** VFF + VCM – PULSE GEN. * SEE NOTE 11 ** CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 8. Switching Test Circuit. 10 * SEE NOTE 11 Figure 9. Test Circuit for Transient Immunity and Typical Waveforms. VO MIL-PRF-38534 Class H, Class K, and DLA SMD Test Program VCC R1 ILEAK 2.4 VF R2 ≥ IF VCC VF IF R2 R1 ≤ IF + ILEAK Avago’s Hi-Rel Optocouplers are in compliance with MILPRF-38534 Class H and K. Class H and Class K devices are also in compliance with DLA drawing 5962-08227. R2 1 8 2 7 3 6 4 5 Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534. VCC + 18 V (EACH INPUT) R2 MAY BE OMITTED IF ADDITIONAL FANOUT IS NOT USED. Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic. + VIN – 1 8 2 7 3 6 4 5 VOC 0.01 F (EACH OUTPUT) CONDITIONS: IF = 5 mA IO = 10 mA TA = +125°C * ALL CHANNELS TESTED SIMULTANEOUSLY. Figure 11. Operating Circuit for Burn-In and Steady State Life Tests. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-1819EN - October 2, 2012