OBSOLETE DS90CR583, DS90CR584 www.ti.com SNLS110B – JULY 1997 – REVISED APRIL 2013 DS90CR583/DS90CR584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz Check for Samples: DS90CR583, DS90CR584 FEATURES 1 • • • • • • • • • • • • • 2 20 to 65 MHz Shift clk Support Up to 227 Mbytes/s Bandwidth Cable Size is Reduced to Save Cost 290 mV Swing LVDS Devices for Low EMI Low Power CMOS Design (< 550 mW typ) Power-Down Mode Saves Power (< 0.25 mW) PLL Requires No External Components Low Profile 56-lead TSSOP Package Rising Edge Data Strobe Compatible with TIA/EIA-644 LVDS Standard Single Pixel Per Clock XGA (1024 x 768) Supports VGA, SVGA, XGA and Higher 1.8 Gbps Throughput DESCRIPTION The DS90CR583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR584 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CONTROL) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes per second. These devices are offered with rising edge data strobes for convenient interface with a variety of graphics and LCD panel controllers. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. BLOCK DIAGRAM Figure 1. DS90CR583 See Package Number DGG Figure 2. DS90CR584 See Package Number DGG 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2013, Texas Instruments Incorporated OBSOLETE DS90CR583, DS90CR584 SNLS110B – JULY 1997 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +6V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec) Maximum Power Dissipation @ 25°C +260°C DGG (TSSOP) Package: DS90CR583 Package Derating: 1.63W DS90CR584 1.61W DS90CR583 12.5 mW/°C above +25°C DS90CR584 12.4 mW/°C above +25°C This device does not meet 2000V ESD rating (3) . (1) (2) (3) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. ESD Rating: HBM (1.5 kΩ, 100 pF) PLL V CC ≥ 1000V All other pins ≥ 2000V EIAJ (0Ω, 200 pF) ≥ 150V Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC) 4.75 5.0 5.25 V Operating Free Air Temperature (TA) −10 +25 +70 °C 2.4 V 100 mVP-P Receiver Input Range 0 Supply Noise Voltage (VCC) ELECTRICAL CHARACTERISTICS over opeOver recommended operating supply and temperature ranges unless otherwise specifiedrating free-air temperature range (unless otherwise noted) Symb Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS VIH 2 High Level Input Voltage Submit Documentation Feedback 2.0 VCC V Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 OBSOLETE DS90CR583, DS90CR584 www.ti.com SNLS110B – JULY 1997 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) over opeOver recommended operating supply and temperature ranges unless otherwise specifiedrating free-air temperature range (unless otherwise noted) Symb Parameter Conditions VIL Low Level Input Voltage VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA VCL Input Clamp Voltage IIN IOS Min Typ GND 3.8 Max Units 0.8 V 4.9 V 0.1 0.3 ICL = −18 mA −0.79 −1.5 V V Input Current VIN = VCC, GND, 2.5V or 0.4V ±5.1 ±10 μA Output Short Circuit Current VOUT = 0V −120 mA 450 mV LVDS DRIVER DC SPECIFICATIONS VOD Differential Output Voltage R L = 100Ω 250 290 ΔV OD Change in VOD between Complementary Output States 35 mV ΔV CM Change in VCM between Complementary Output States 35 mV −2.9 −5 mA ±1 ±10 μA +100 mV VOL Low Level Output Voltage IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω 0.9 IOZ Output TRI-STATE Current Power Down = 0V, VOUT = 0V or VCC 1.01 V LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current V CM = +1.2V −100 VIN = +2.4V mV VCC = 5.5V VIN = 0V ±10 μA ±10 μA TRANSMITTER SUPPLY CURENT ICCTW ICCTG ICCTZ ICCRW ICCRG ICCRZ Transmitter Supply Current, Worst Case RL = 100Ω, CL = 5 pF, Worst Case Pattern (Figure 3, Figure 5) Transmitter Supply Current, 16 Grayscale RL = 100Ω, CL = 5 pF, 16 Grayscale Pattern (Figure 4, Figure 5) Transmitter Supply Current, Power Down Power Down = Low Receiver Supply Current, Worst Case CL = 8 pF, Worst Case Pattern (Figure 3, Figure 6) Receiver Supply Current, 16 Grayscale CL = 8 pF, 16 Grayscale Pattern (Figure 4, Figure 6) Receiver Supply Current, Power Down f = 32.5 MHz 49 63 mA f = 37.5 MHz 51 64 mA f = 65 MHz 70 84 mA f = 32.5 MHz 40 55 mA f = 37.5 MHz 41 55 mA f = 65 MHz 55 67 mA 1 10 µA f = 32.5 MHz 64 77 mA f = 37.5 MHz 70 85 mA f = 65 MHz 110 140 mA f = 32.5 MHz 35 55 mA f = 37.5 MHz 37 55 mA f = 65 MHz 55 67 mA 1 10 μA Typ Max Units Power Down = Low Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min LLHT LVDS Low-to-High Transition Time (Figure 5) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 5) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 7) 8 ns 350 ps 8.5 ns (1) TCCS TxOUT Channel-to-Channel Skew TCCD TxCLK IN to TxCLK OUT Delay @ 25°C, VCC = 5.0V (Figure 11) (1) (Figure 8) 3.5 This limit based on bench characterization. Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 Submit Documentation Feedback 3 OBSOLETE DS90CR583, DS90CR584 SNLS110B – JULY 1997 – REVISED APRIL 2013 www.ti.com Transmitter Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units TCIP TxCLK IN Period (Figure 9) 15 T 50 ns TCIH TxCLK IN High Time (Figure 9) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 9) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN (Figure 9 ) 5 3.5 THTC TxIN Hold to TxCLK IN (Figure 9) 2.5 1.5 TPDD Transmitter Powerdown Delay (Figure 20) 100 ns TPLLS Transmitter Phase Lock Loop Set (Figure 13) 10 ms TPPos0 Transmitter Output Pulse Position 0 (Figure 15) −0.30 0 0.30 ns TPPos1 Transmitter Output Pulse Position 1 1.70 1/7 Tclk 2.50 ns TPPos2 Transmitter Output Pulse Position 2 3.60 2/7 Tclk 4.50 ns TPPos3 Transmitter Output Pulse Position 3 5.90 3/7 Tclk 6.75 ns TPPos4 Transmitter Output Pulse Position 4 8.30 4/7 Tclk 9.00 ns TPPos5 Transmitter Output Pulse Position 5 10.40 5/7 Tclk 11.10 ns TPPos6 Transmitter Output Pulse Position 6 12.70 6/7 Tclk 13.40 ns f = 65 MHz ns ns Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Typ Max Units CLHT Symbol CMOS/TTL Low-to-High Transition Time (Figure 6) 2.5 4.0 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 6) 2.0 3.5 ns RCOP RxCLK OUT Period 15 T 50 ns RCOH RxCLK OUT High Time f = 65 MHz 3.8 5 ns RCOL RxCLK OUT Low Time f = 65 MHz 7.8 9 ns RSRC RxOUT Setup to RxCLK OUT f = 65 MHz 2.5 4.2 ns RHRC RxOUT Hold to RxCLK OUT f = 65 MHz 4.0 5.2 RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 5.0V (Figure 12) RPLLS Receiver Phase Lock Loop Set (Figure 14) RSKM RxIN Skew Margin (1) (Figure 16) RPDD Receiver Powerdown (Figure 19) (1) 4 Parameter Min 6.4 VCC = 5V, TA =25°C ns 10.7 ns 10 ms 1 μs 600 ps Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle) Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 OBSOLETE DS90CR583, DS90CR584 www.ti.com SNLS110B – JULY 1997 – REVISED APRIL 2013 AC Timing Diagrams Figure 3. “Worst Case” Test Pattern (1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. (2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. (3) Figure 3 and Figure 4 show a falling edge data strobe (TxCLK IN/RxCLK OUT). (4) Recommended pin to signal mapping. Customer may choose to define differently. Figure 4. “16 Grayscale” Test Pattern Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 Submit Documentation Feedback 5 OBSOLETE DS90CR583, DS90CR584 SNLS110B – JULY 1997 – REVISED APRIL 2013 www.ti.com Figure 5. DS90CR583 (Transmitter) LVDS Output Load and Transition Times Figure 6. DS90CR584 (Receiver) CMOS/TTL Output Load and Transition Times Figure 7. DS90CR583 (Transmitter) Input Clock Transition Time Note: Measurements at Vdiff = 0V Note: TCSS measured between earliest and latest LVDS edges. Note: TxCLK Differential High→Low Edge Figure 8. DS90CR583 (Transmitter) Channel-to-Channel Skew and Pulse Width 6 Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 OBSOLETE DS90CR583, DS90CR584 www.ti.com SNLS110B – JULY 1997 – REVISED APRIL 2013 Figure 9. DS90CR583 (Transmitter) Setup/Hold and High/Low Times Figure 10. DS90CR584 (Receiver) Clock In to Clock Out Delay Figure 11. DS90CR583 (Transmitter) Clock In to Clock Out Delay Figure 12. DS90CR584 (Receiver) Clock In to Clock Out Delay Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 Submit Documentation Feedback 7 OBSOLETE DS90CR583, DS90CR584 SNLS110B – JULY 1997 – REVISED APRIL 2013 www.ti.com Figure 13. DS90CR583 (Transmitter) Phase Lock Loop Set Time Figure 14. DS90CR584 (Receiver) Phase Lock Loop Set Time 8 Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 OBSOLETE DS90CR583, DS90CR584 www.ti.com SNLS110B – JULY 1997 – REVISED APRIL 2013 Figure 15. Transmitter LVDS Output Pulse Position Measurement SW—Setup and Hold Time (Internal Data Sampling Window) TCCS—Transmitter Output Skew RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) Cable Skew—typically 10 ps–40 ps per foot Figure 16. Receiver LVDS Input Skew Margin Figure 17. Seven Bits of LVDS in One Clock Cycle Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 Submit Documentation Feedback 9 OBSOLETE DS90CR583, DS90CR584 SNLS110B – JULY 1997 – REVISED APRIL 2013 www.ti.com Figure 18. Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR583) Figure 19. Receiver Powerdown Delay Figure 20. Transmitter Powerdown Delay DS90CR583 Pin Descriptions—FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL) TxOUT+ O 4 Positive LVDS differential data output TxOUT− O 4 Negative LVDS differential data output FPSHIFT IN I 1 TTL level clock input. The falling edge acts as data strobe TxCLK OUT+ O 1 Positive LVDS differential clock output TxCLK OUT− O 1 Negative LVDS differential clock output PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down VCC I 4 Power supply pins for TTL inputs GND I 5 Ground pins for TTL inputs 10 Description Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 OBSOLETE DS90CR583, DS90CR584 www.ti.com SNLS110B – JULY 1997 – REVISED APRIL 2013 DS90CR583 Pin Descriptions—FPD Link Transmitter (continued) I/O No. PLL VCC Pin Name I 1 Power supply pin for PLL Description PLL GND I 2 Ground pins for PLL LVDS VCC I 1 Power supply pin for LVDS outputs LVDS GND I 3 Ground pins for LVDS outputs I/O No. I 4 Positive LVDS differential data inputs DS90CR584 Pin Descriptions—FPD Link Receiver Pin Name RxIN+ Description RxIN− I 4 Negative LVDS differential data inputs RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL) RxCLK IN+ I 1 Positive LVDS differential clock input RxCLK IN− I 1 Negative LVDS differential clock input FPSHIFT OUT O 1 TTL level clock output. The falling edge acts as data strobe PWR DOWN I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state VCC I 4 Power supply pins for TTL outputs GND I 5 Ground pins for TTL outputs PLL VCC I 1 Power supply for PLL PLL GND I 2 Ground pin for PLL LVDS VCC I 1 Power supply pin for LVDS inputs LVDS GND I 3 Ground pins for LVDS inputs Connection Diagram Figure 21. 56 Pin TSSOP See Package Number DGG Figure 22. 56 Pin TSSOP See Package Number DGG Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 Submit Documentation Feedback 11 OBSOLETE DS90CR583, DS90CR584 SNLS110B – JULY 1997 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated Product Folder Links: DS90CR583 DS90CR584 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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