ALSC ASM5I9653AG-32-LR 3.3v 1:8 lvcmos pll clock generator Datasheet

ASM5I9653A
July 2005
rev 0.2
3.3V 1:8 LVCMOS PLL Clock Generator
Features
running at either 4x or 8x of the reference clock frequency.
The ASM5I9653A is guaranteed to lock in a low power PLL
ƒ
1:8 PLL based low-voltage clock generator
ƒ
Supports zero-delay operation
ƒ
3.3V power supply
ƒ
Generates clock signals up to 125MHz
ƒ
PLL guaranteed to lock down to 145MHz, output
mode in the high frequency range (VCO_SEL = 0) down to
PLL = 145 MHz or Fref = 36.25MHz.
The ASM5I9653A has a differential LVPECL reference
input long with an external feedback input. The device is
ideal for use as a zero delay, low skew fanout buffer. The
frequency = 36.25MHz
device performance has been tuned and optimized for zero
ƒ
Maximum output skew of 150 pS
ƒ
Differential LVPECL reference clock input
select the PLL bypass configuration for test and diagnosis.
ƒ
External PLL feedback
In this configuration, the selected input reference clock is
ƒ
Drives up to 16 clock lines
bypassing the PLL and routed either to the output dividers
ƒ
32 lead LQFP & TQFP Packages
or directly to the outputs. The PLL bypass configurations
ƒ
Ambient temperature range 0°C to +70°C
are
ƒ
Pin
and
function
compatible
delay performance. The PLL_EN and BYPASS controls
to
the
MPC953,MPC9653A and MPC9653
fully
static
and
the
minimum
clock
frequency
specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the
device reset by asserting the MR/OE pin. Asserting MR/OE
also causes the PLL to loose lock due to missing feedback
signal presence at FB_IN. Deasserting MR/OE will enable
Functional Description
The ASM5I9653A utilizes PLL technology to frequency lock
its outputs onto an input reference clock. Normal operation
of the ASM5I9653A requires the connection of the QFB
output to the feedback input to close the PLL feedback path
(external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device
and VCO_SEL selects the operating frequency range of 25
to 62.5MHz or 50 to 125MHz. The two available post-PLL
dividers selected by VCO_SEL (divide-by-4 or divide-by-8)
and the reference clock frequency determine the VCO
frequency. Both must be selected to match the VCO
the outputs and close the phase locked loop, enabling the
PLL to recover to normal operation. The ASM5I9653A is
fully 3.3V compatible and requires no external loop filter
components. The inputs (except PCLK) accept LVCMOS
except signals while the outputs provide LVCMOS
compatible levels with the capability to drive terminated
50Ω transmission lines. For series terminated transmission
lines, each of the ASM5I9653A outputs can drive one or
two traces giving the devices an effective fanout of 1:16.
The device is packaged in a 7x7 mm2 32-lead LQFP &
TQFP Packages.
frequency range. The internal VCO of the ASM5I9653A is
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM5I9653A
July 2005
rev 0.2
Block Diagram
Figure 1. ASM5I9653A Logic Diagram
Pin Configuration
ASM5I9653A
Figure 2. ASM5I9653A 32-Lead Package Pinout (Top View)
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
2 of 13
ASM5I9653A
July 2005
rev 0.2
Table 1: Pin Configuration
Pin #
Pin Name
8,9
I/O
Type
Function
Input
LVPECL
PECL reference clock signal
2
PCLK,
PCLK
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
32
VCO_SEL
Input
LVCMOS
Operating frequency range select
Input
LVCMOS
PLL and output divider bypass select
Input
LVCMOS
Input
LVCMOS
Output
LVCMOS
PLL enable/disable
Output enable/disable (high-impedance tristate) and
device reset
Clock outputs
31
BYPASS
PLL_EN
MR/OE
30
10
26,24,22,20,18,16,14,12
Q0-7
28
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
7,13,17,21,25,29
GND
Supply
Ground
VCC_PLL
Supply
VCC
VCC
Supply
VCC
Negative power supply (GND)
PLL positive power supply (analog power supply). It is
recommended to use an external RC filter for the analog
power supply pin VCC_PLL. Please see applications
section for details
Positive power supply for I/O and core. All VCC pins must
be connected to the positive power supply for correct
operation
-
-
1
11,15,19,23,27
3,4,5,6
NC
No Connect
Table 2: FUNCTION TABLE
Control
Default
0
1
Test mode with PLL bypassed. The reference
clock (PCLK) is substituted for the internal VCO
output. ASM5I9653A is fully static and no
minimum frequency limit applies. All PLL related
AC characteristics are not applicable.
Selects the VCO output1
BYPASS
1
Test mode with PLL and output dividers
bypassed. The reference clock (PCLK) is directly
routed to the outputs. ASM5I9653A is fully static
and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Selects the output dividers.
VCO_SEL
1
VCO ÷ 1 (High frequency range).
fREF =fQ0-7 =4 . fVCO
VCO ÷ 2 (Low output range).
fREF =fQ0-7 =8 . fVCO
Outputs enabled (active)
Outputs disabled (high-impedance state) and
reset of the device. During reset the PLL
feedback loop is open. The VCO is tied to its
lowest frequency. The length of the reset
pulse should be greater than one reference
clock cycle (PCLK).
PLL_EN
MR/OE
0
1
Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1.
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
3 of 13
ASM5I9653A
July 2005
rev 0.2
Table 3: GENERAL SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
Unit
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
Latch-Up Immunity
200
mA
LU
VCC÷2
Condition
V
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
Input Capacitance
4.0
pF
Inputs
Table 4: ABSOLUTE MAXIMUM RATINGS1
Symbol
Min
Max
Unit
VCC
Supply Voltage
-0.3
3.9
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VCC+0.3
V
±20
mA
±50
mA
125
°C
VOUT
IIN
Characteristics
DC Input Current
IOUT
DC Output Current
TS
Storage Temperature
-65
Condition
Table 5: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)
Symbol
VIL
VPP
VCMR
Characteristics
Min
Input high voltage
Input low voltage
VIH
2
Unit
V
V
Condition
LVCMOS
LVCMOS
Peak-to-peak input voltage
(PCLK)
300
mV
LVPECL
(PCLK)
1.0
V
LVPECL
V
IOH=-24 mA3
Output High Voltage
Output Low Voltage
ZOUT
Output impedance
ICC_PLL
ICCQ5
Max
VCC +0.3
0.8
Common Mode Range
VOH
VOL
IIN
Typ
2.0
Input Current
VCC-0.6
2.4
0.55
0.30
14 -17
4
Maximum PLL Supply Current
Maximum Quiescent Supply Current
10
VV
±200
Ω
µA
15
mA
15
mA
IOL=24mA
IOL=12mA
VIN=VCC or
GND
VCC_PLL Pin
All VCC Pins
1
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
2
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the VPP (DC) specification.
3
The ASM3P9653A is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. The
ASM3P9653A meets the VOH and VOL specification of the ASM3P953 (VOH > VCC-0.6V at IOH=-20mA and VOL > 0.6V at IOL=20mA).
4
Inputs have pull-down or pull-up resistors affecting the input current.
5
OE/MR=1 (outputs in high-impedance state).
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9653A
July 2005
rev 0.2
Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)6
Symbol
Characteristics
Input reference frequency
PLL mode, external feedback
fREF
Min
÷4 feedback7
8
÷8 feedback
9
fVCOlock
VPP
VCMR
13
Unit
125
62.5
MHz
MHz
200
MHz
500
MHz
÷4 feedback
÷8 feedback9
8
145
50
25
500
125
62.5
MHz
MHz
MHz
Peak-to-peak input voltage
PCLK
450
1000
mV
LVPECL
Common Mode Range
PCLK
1.2
VCC-0.75
V
LEPVCL
VCO lock frequency range
12
tPW,MIN
Input Reference Pulse Width14
t(Ø)
Propagation Delay (static phase offset)15 PCLK to FB_IN
2
-75
125
pS
1.2
3.0
3.3
7.0
150
1.5
55
1.0
7.0
6.0
nS
nS
pS
nS
%
nS
nS
nS
tsk(O)
tsk(PP)
DC
tR,tF
tPLZ, HZ
tPZL, LZ
tJIT(CC)
Cycle-to-cycle jitter
100
pS
tJIT(PER)
Period Jitter
18
I/O Phase Jitter
RMS (1 σ)
PLL closed loop bandwidth19
PLL mode, external feedback
Maximum PLL Lock Time
100
pS
25
pS
tJIT(Ø)
BW
tLOCK
8
÷ 4 feedback
÷8 feedback9
45
0.1
PLL locked
PLL locked
nS
Propagation Delay
PLL and divider bypass (BYPASS=0), PCLK to Q0-7
PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7
Output-to-output Skew16
Device-to-device Skew in PLL and divider bypass17
Output duty cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
tPD
Condition
PLL locked
PLL locked
0
Output Frequency
fMAX
Typ
200
Input reference frequency in PLL bypass mode
VCO operating frequency range10,11
fVCO
Max
50
25
50
0.8-4
0.5 -1.3
PLL locked
BYPASS=0
PLL locked
0.55 to 2.4V
MHz
10
mS
6
AC characteristics apply for parallel output termination of 50Ω to VTT.
÷4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
8
÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
9
In bypass mode, the ASM3P9653A divides the input reference clock.
10
The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
11
fVCO is frequency range where AC parameters are guaranteed.
12
fVCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO.
13
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
7
range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(Ø ).
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF . 100% and DCREF,MAX = 100% - DCREF,MIN. E.g. at
fREF=100 MHz the input duty cycle range is 20% < DC < 80%.
14
Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(Ø ) [ps] = 50 ps ± (1÷(120 . fREF)).
See application section for part-to-part skew calculation in PLL zero-delay mode.
17
For a specified temperature and voltage, includes output skew.
18
I/O phase jitter is reference frequency dependent. See application section for details.
19
-3 dB point of PLL transfer characteristics.
15
16
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9653A
July 2005
rev 0.2
APPLICATIONS INFORMATION
Driving Transmission Lines
The ASM5I9653A supports output clock frequencies from
25 to 125MHz. Two different feedback divider
configurations can be used to achieve the desired
frequency operation range. The feedback divider
(VCO_SEL) should be used to situate the VCO in the
frequency lock range between 200 and 500MHz for
BYPASS PLL_ EN VCO_ SEL
stable and optimal operation. Two operating frequency
ranges are supported : 25 to 62.5MHz and 50 to
125MHz. Table 9 illustrates the configurations supported
by the ASM5I9653A. PLL zero-delay is supported if
BYPASS=1, PLL_EN=1 and the input frequency is within
the specified PLL reference frequency range.
Frequency
Operation
Ratio
Output range (fQ0-7)
VCO
0
X
X
Test mode: PLL and divider bypass
fQ0-7 =fREF
0-200MHz
n/a
1
0
0
Test mode: PLL bypass
fQ0-7 =fREF ÷ 4
0-50MHz
n/a
1
0
1
Test mode: PLL bypass
fQ0-7 =fREF ÷ 8
0-25MHz
n/a
1
1
0
PLL mode (high frequency range)
fQ0-7 =fREF
50 to 125MHz
fVCO =fREF 4
1
1
1
PLL mode (low frequency range)
fQ0-7 =fREF
25 to 62.5MHz
fVCO =fREF 8
Power Supply Filtering
The ASM5I9653A is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCCA_PLL power supply impacts the
device characteristics, for instance I/O jitter. The
ASM5I9653A provides separate power supplies for the
output buffers (VCC) and the phase-locked loop
(VCCA_PLL) of the device. The purpose of this design
technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where
it is more difficult to minimize noise on the power supplies
a second level of isolation may be required. The simple
but effective form of isolation is a power supply filter on
the VCC_PLL pin for the ASM5I9653A. Figure 3
illustrates a typical power supply filter scheme. The
ASM5I9653A frequency and phase stability is most
susceptible to noise with spectral content in the 100kHz
to 20MHz range. Therefore the filter should be designed
to target this range. The key parameter that needs to be
met in the final filter design is the DC voltage drop across
the series filter resistor RF. From the data sheet the ICCA
current (the current sourced through the VCC_PLL pin) is
typically 10 mA (15 mA maximum), assuming that a
minimum of 2.985V must be maintained on the VCC_PLL
pin.
ASM5I9653A
Figure 3. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide attenuation greater than 40 dB for noise
whose spectral content is above 100kHz. In the example
RC filter shown in Figure 3. “VCC_PLL Power Supply
Filter”, the filter cut-off frequency is around 4 kHz and the
noise attenuation at 100kHz is better than 42 dB. As the
noise frequency crosses the series resonant point of an
individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a
low impedance path to ground exists for frequencies well
above the bandwidth of the PLL. Although the
ASM5I9653A has several design features to minimize the
susceptibility to power supply noise (isolated power and
grounds and fully differential PLL) there still may be
applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related
problems in most designs.
Using the ASM5I9653A in zero-delay applications
Nested clock trees are typical applications for the
ASM5I9653A. Designs using the ASM5I9653A as
LVCMOS PLL fanout buffer with zero insertion delay will
show significantly lower clock skew than clock
distributions developed from CMOS fanout buffers. The
external feedback option of the ASM5I9653A clock driver
allows for its use as a zero delay buffer. The PLL aligns
the feedback clock output edge with the clock input
reference edge resulting a near zero delay through the
device (the propagation delay through the device is
virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between
the reference clock input and any output. This effective
delay consists of the static phase offset, I/O jitter (phase
long-term jitter), feedback path delay and the output-tooutput skew error relative to the feedback output.
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
6 of 13
ASM5I9653A
July 2005
rev 0.2
Calculation of part-to-part skew
The ASM5I9653A zero delay buffer supports applications
where critical clock signal timing can be maintained
across several devices. If the reference clock inputs of
two or more ASM5I9653A are connected together, the
maximum overall timing uncertainty from the common
PCLK input to any output is: tSK(PP) = t(Ø) + tSK(O) +
tPD, LINE(FB) + tJIT(Ø) ¡ CF This maximum timing
uncertainty consist of 4 components: static phase offset,
output skew, feedback board trace delay and I/O (phase)
jitter:
resulting in a worst case timing uncertainty from input to
any output of -197 pS to 297 pS (at 125MHz reference
frequency) relative to PCLK:
tSK(PP) = [-17pS...117pS] + [-150pS...150pS] +
[(10pS . -3)...(10pS . 3)] + tPD, LINE(FB)
tSK(PP) = [-197pS...297pS] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure
5. .Max. I/O Jitter versus frequency. can be used for a
more precise timing performance analysis.
Figure 5. Maximum I/O Jitter vs Frequency
Driving Transmission Lines
Figure 4. ASM5I9653A max device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 10.
Table 10: Confidence Factor CF
± 1σ
Probability of clock edge within the
distribution
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
CF
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
The ASM5I9653A clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 20Ω the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the ASM5I9653A clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 6 “Single versus Dual Transmission Lines”
Illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme the fanout of the ASM5I9653A clock driver
is effectively doubled due to its capability to drive multiple
lines.
3.3V 1:8 LVCMOS PLL Clock Generator
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ASM5I9653A
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ASM5I9653A
OUTPUT BUFFER
IN
14Ω
ASM5I9653A
OUTPUT BUFFER
IN
Z0=15Ω
RS=36Ω
OUTA
Z0=15Ω
RS=36Ω
OUTB0
14Ω
RS=36Ω
Z0=15Ω
OUTB1
Figure 6. Single versus Dual Transmission Lines
The waveform plots in Figure 7 .Single versus Dual Line
Termination Waveforms show the simulation results of an
output driving a single line versus two lines. In both cases
the drive capability of the ASM5I9653A output buffer is
more than sufficient to drive 50Ω transmission lines on
the incident edge. Note from the delay measurements in
the simulations a delta of only 43ps exists between the
two differently loaded outputs. This suggests that the dual
line driving need not be used exclusively to maintain the
tight output-to-output skew of the ASM5I9653A. The
output waveform in Figure 7 Single versus Dual Line
Termination Waveforms shows a step in the waveform,
this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the
36Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances.
The voltage wave launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
VL = 3.0 ( 25 ⎟ (18+14+25)
= 1.31V
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 8 .Optimized Dual
Line Termination should be used. In this case the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
ASM5I9653A
OUTPUT BUFFER
IN
RS=22Ω
14Ω
RS=22Ω
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
Z0=15Ω
Z0=15Ω
14Ω + 22Ω _ 22Ω = 50Ω _ 50Ω
25Ω = 25Ω
Figure 8. Optimized Dual Line Termination
3.3V 1:8 LVCMOS PLL Clock Generator
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ASM5I9653A
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rev 0.2
ASM519653A
Figure 9. PCLK ASM5I9653A AC test reference
Figure 16. Output Transition Time Test Reference
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9653A
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rev 0.2
Package Diagram
32-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
10 of 13
ASM5I9653A
July 2005
rev 0.2
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9653A
July 2005
rev 0.2
Ordering Information
Part Number
Marking
Package Type
Operating Range
ASM5I9653A-32-ER
ASM5I9653A
32-pin TQFP
Industrial
ASM5I9653A-32-LR
ASM5I9653A
32-pin LQFP –Tape and Reel
Industrial
ASM5I9653AG-32-ER
ASM5I9653AG
32-pin TQFP, Green
Industrial
ASM5I9653AG-32-LR
ASM5I9653AG
32-pin LQFP –Tape and Reel, Green
Industrial
Device Ordering Information
A S M
5 I 9 6 5 3 A
F - 3 2 - L R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
12 of 13
ASM5I9653A
July 2005
rev 0.2
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5I9653A
Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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