Holtek BS66FV350 Enhanced touch voice a/d flash mcu Datasheet

Enhanced Touch Voice A/D Flash MCU
BS66FV340/BS66FV350/BS66FV360
Revision: V1.10
Date: �����������������
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Table of Contents
Features............................................................................................................. 7
CPU Features.......................................................................................................................... 7
Peripheral Features.................................................................................................................. 8
General Description.......................................................................................... 9
Selection Table.................................................................................................. 9
Block Diagram................................................................................................. 10
Pin Assignment............................................................................................... 10
Pin Descriptions............................................................................................. 14
Absolute Maximum Ratings........................................................................... 29
D.C. Characteristics........................................................................................ 29
A.C. Characteristics........................................................................................ 31
High Speed Internal Oscillator Frequency Accuracy.................................. 32
Low Speed Internal Oscillator Frequency Characteristics......................... 33
Low Speed Crystal Oscillator Characteristics............................................. 33
A/D Converter Characteristics....................................................................... 33
Temperature Sensor Electrical Characteristics........................................... 34
LVD/LVR Electrical Characteristics............................................................... 34
Touch Key Electrical Characteristics............................................................ 35
Software LCD Electrical Characteristics...................................................... 37
Audio D/A Converter Electrical Characteristics........................................... 37
Power Amplifier Electrical Characteristics................................................... 37
Power-on Reset Characteristics.................................................................... 38
System Architecture....................................................................................... 38
Clocking and Pipelining.......................................................................................................... 38
Program Counter.................................................................................................................... 39
Stack...................................................................................................................................... 40
Arithmetic and Logic Unit – ALU............................................................................................ 40
Flash Program Memory.................................................................................. 41
Structure................................................................................................................................. 41
Special Vectors...................................................................................................................... 41
Look-up Table......................................................................................................................... 42
Table Program Example......................................................................................................... 42
In Circuit Programming – ICP................................................................................................ 43
On-Chip Debug Support – OCDS.......................................................................................... 44
In Application Programming – IAP......................................................................................... 45
Data Memory................................................................................................... 55
Structure................................................................................................................................. 55
Data Memory Addressing....................................................................................................... 56
Rev. 1.10
2
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
General Purpose Data Memory............................................................................................. 56
Special Purpose Data Memory.............................................................................................. 56
Special Function Register Description......................................................... 60
Indirect Addressing Registers – IAR0, IAR1, IAR2................................................................ 60
Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L............................................................ 60
Program Memory Bank Pointer – PBP................................................................................... 62
Accumulator – ACC................................................................................................................ 62
Program Counter Low Register – PCL................................................................................... 62
Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 62
Status Register – STATUS..................................................................................................... 63
EEPROM Data Memory................................................................................... 65
EEPROM Data Memory Structure......................................................................................... 65
EEPROM Registers............................................................................................................... 65
Reading Data from the EEPROM.......................................................................................... 67
Writing Data to the EEPROM................................................................................................. 67
Write Protection...................................................................................................................... 67
EEPROM Interrupt................................................................................................................. 67
Programming Considerations................................................................................................. 68
Oscillator......................................................................................................... 69
Oscillator Overview................................................................................................................ 69
System Clock Configurations................................................................................................. 69
External Crystal/Ceramic Oscillator – HXT............................................................................ 70
Internal High Speed RC Oscillator – HIRC............................................................................ 71
External 32.768 kHz Crystal Oscillator – LXT........................................................................ 71
Internal 32kHz Oscillator – LIRC............................................................................................ 72
Operating Modes and System Clocks.......................................................... 73
System Clocks....................................................................................................................... 73
System Operation Modes....................................................................................................... 75
Control Registers................................................................................................................... 76
Operating Mode Switching..................................................................................................... 79
Standby Current Considerations............................................................................................ 83
Wake-up................................................................................................................................. 83
Watchdog Timer.............................................................................................. 84
Watchdog Timer Clock Source............................................................................................... 84
Watchdog Timer Control Register.......................................................................................... 84
Watchdog Timer Operation.................................................................................................... 85
Reset and Initialisation................................................................................... 86
Reset Functions..................................................................................................................... 86
Reset Initial Conditions.......................................................................................................... 89
Input/Output Ports.......................................................................................... 95
Pull-high Resistors................................................................................................................. 96
Port A Wake-up...................................................................................................................... 96
I/O Port Control Registers...................................................................................................... 96
I/O Port Source Current Control............................................................................................. 96
Rev. 1.10
3
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pin-shared Functions............................................................................................................. 98
I/O Pin Structures................................................................................................................. 105
Programming Considerations............................................................................................... 106
Timer Modules – TM..................................................................................... 107
Introduction.......................................................................................................................... 107
TM Operation....................................................................................................................... 107
TM Clock Source.................................................................................................................. 107
TM Interrupts........................................................................................................................ 108
TM External Pins.................................................................................................................. 108
TM Input/Output Pin Selection............................................................................................. 109
Programming Considerations................................................................................................110
Compact Type TM – CTM..............................................................................111
Compact TM Operation.........................................................................................................111
Compact Type TM Register Description...............................................................................112
Compact Type TM Operation Modes....................................................................................116
Standard Type TM – STM............................................................................. 122
Standard TM Operation........................................................................................................ 122
Standard Type TM Register Description.............................................................................. 123
Standard Type TM Operation Modes................................................................................... 127
Periodic Type TM – PTM............................................................................... 137
Periodic TM Operation......................................................................................................... 137
Periodic Type TM Register Description................................................................................ 138
Periodic Type TM Operation Modes..................................................................................... 142
Analog to Digital Converter......................................................................... 151
A/D Converter Overview...................................................................................................... 151
Registers Descriptions......................................................................................................... 152
A/D Converter Data Registers – SADOL, SADOH............................................................... 152
A/D Converter Control Registers – SADC0, SADC1, SADC2.............................................. 153
A/D Converter Operation...................................................................................................... 156
A/D Converter Reference Voltage........................................................................................ 157
A/D Converter Input Signals................................................................................................. 157
Conversion Rate and Timing Diagram................................................................................. 158
Summary of A/D Conversion Steps...................................................................................... 159
Programming Considerations............................................................................................... 160
A/D Conversion Transfer Function....................................................................................... 160
A/D Conversion Programming Examples............................................................................. 161
Serial Interface Module – SIM...................................................................... 163
SPI Interface........................................................................................................................ 163
I2C Interface......................................................................................................................... 169
UART Interface.............................................................................................. 179
UART External Pin............................................................................................................... 180
UART Data Transfer Scheme.............................................................................................. 180
UART Status and Control Registers.................................................................................... 180
Baud Rate Generator........................................................................................................... 185
Rev. 1.10
4
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
UART Setup and Control..................................................................................................... 186
UART Transmitter................................................................................................................ 187
UART Receiver.................................................................................................................... 189
Managing Receiver Errors................................................................................................... 190
UART Interrupt Structure..................................................................................................... 191
UART Power Down and Wake-up........................................................................................ 193
Serial Interface – SPIA.................................................................................. 194
SPIA Interface Operation..................................................................................................... 194
SPIA Communication........................................................................................................... 198
SPIA Bus Enable/Disable..................................................................................................... 200
SPIA Operation.................................................................................................................... 200
Error Detection..................................................................................................................... 201
Touch Key Function..................................................................................... 202
Touch Key Structure............................................................................................................. 202
Touch Key Register Definition.............................................................................................. 203
Touch Key Operation............................................................................................................ 210
Touch Key Interrupt.............................................................................................................. 216
Programming Considerations............................................................................................... 216
Low Voltage Detector – LVD........................................................................ 217
LVD Register........................................................................................................................ 217
LVD Operation...................................................................................................................... 218
Software LCD Driver..................................................................................... 219
LCD Control Registers......................................................................................................... 219
LCD Operation..................................................................................................................... 220
Voice Playing Controller.............................................................................. 222
Voice Controller Registers.................................................................................................... 222
Interrupts....................................................................................................... 225
Interrupt Registers................................................................................................................ 225
Interrupt Operation............................................................................................................... 231
External Interrupt.................................................................................................................. 232
Touch Key Interrupt.............................................................................................................. 233
UART Transfer Interrupt....................................................................................................... 233
A/D Converter Interrupt........................................................................................................ 233
Time Base Interrupt.............................................................................................................. 233
Multi-function Interrupt......................................................................................................... 235
TM Interrupt.......................................................................................................................... 235
LVD Interrupt........................................................................................................................ 236
EEPROM Interrupt............................................................................................................... 236
Serial Interface Module Interrupt.......................................................................................... 236
SPIA Interface Interrupt........................................................................................................ 236
Interrupt Wake-up Function.................................................................................................. 237
Programming Considerations............................................................................................... 237
Rev. 1.10
5
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Application Circuits...................................................................................... 238
5V Application...................................................................................................................... 238
3V Application...................................................................................................................... 239
Instruction Set............................................................................................... 240
Introduction.......................................................................................................................... 240
Instruction Timing................................................................................................................. 240
Moving and Transferring Data.............................................................................................. 240
Arithmetic Operations........................................................................................................... 240
Logical and Rotate Operation.............................................................................................. 241
Branches and Control Transfer............................................................................................ 241
Bit Operations...................................................................................................................... 241
Table Read Operations........................................................................................................ 241
Other Operations.................................................................................................................. 241
Instruction Set Summary............................................................................. 242
Table Conventions................................................................................................................ 242
Extended Instruction Set...................................................................................................... 244
Instruction Definition.................................................................................... 246
Extended Instruction Definition............................................................................................ 255
Package Information.................................................................................... 262
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions............................................ 263
48-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 264
Rev. 1.10
6
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Features
CPU Features
• Operating Voltage:
♦♦
fSYS=8MHz: 2.2V~5.5V
♦♦
fSYS=12MHz: 2.7V~5.5V
♦♦
fSYS=16MHz: 3.3V~5.5V
• Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Oscillator Type:
♦♦
External High Speed Crystal – HXT
♦♦
Internal High Speed RC – HIRC
♦♦
External 32.768kHz Crystal – LXT
♦♦
Internal 32kHz RC – LIRC
• Fully integrated internal 8/12/16 MHz oscillator requires no external components
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• All instructions executed in one to three instruction cycles
• Table read instructions
• 115 powerful instructions
• Up to 12-level subroutine nesting
• Bit manipulation instruction
Rev. 1.10
7
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Peripheral Features
• Program Memory: Up to 16K x 16
• Data Memory: Up to 1024 x 8
• True EEPROM Memory: 256 x 8
• Watchdog Timer function
• Up to 39 bidirectional I/O lines
• Programming I/O source current
• Software controlled 6-SCOM lines LCD driver with 1/3 bias
• Two external interrupt lines shared with I/O pins
• Multiple Timer Modules for time measure, input capture, compare match output, PWM output
function or single pulse output function
• Serial Interfaces Module – SIM for SPI or I2C
• Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART
• Serial Peripheral Interface – SPIA
• Dual Time-Base functions for generation of fixed time interrupt signals
• 8-channel 12-bit resolution A/D converter
• Temperature Sensor
• Up to 28 Touch Keys
• In Application Programming function – IAP
• Class AB power amplifier for speaker driving
• High performance 16-bit audio D/A converter
• Digital volume control for audio play function
• Low voltage reset function
• Low voltage detect function
• Flash program memory can be re-programmed up to 100,000 times
• Flash program memory data retention > 10 years
• True EEPROM data memory can be re-programmed up to 1,000,000 times
• True EEPROM data memory data retention > 10 years
• Package types: 44/48-pin LQFP
Rev. 1.10
8
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
General Description
The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture
microcontroller with fully integrated touch key functions. With all touch key functions provided
internally and with the convenience of Flash Memory multi-programming features, each device has
all the features to offer designers a reliable and easy means of implementing Touch Keys within their
products applications. A 16-bit D/A converter and a power amplifier are also integrated in this series
of devices. For the D/A converter, the device has a digital programmable volume control for a wide
range of applications.
The touch key functions are fully integrated completely eliminating the need for external
components. In addition to the flash program memory, other memory includes an area of RAM
Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as
serial numbers, calibration data, etc. Protective features such as an internal Watchdog Timer and
Low Voltage Reset functions coupled with excellent noise immunity and ESD protection ensure that
reliable operation is maintained in hostile electrical environments.
These devices also include fully integrated low and high speed oscillators which are flexibly used for
different applications. The ability to operate and switch dynamically between a range of operating
modes using different clock sources gives users the ability to optimise microcontroller operation
and minimise power consumption. Easy communication with the outside world is provided using
the internal UART, I2C and SPI interfaces, while the inclusion of flexible I/O programming features,
Timer modules and many other features further enhance device functionality and flexibility.
The touch key voice device will find excellent use in a huge range of modern Touch Key
product applications with voice playing function such as instrumentation, household appliances,
electronically controlled tools to name but a few.
Selection Table
Most features are common to all devices. The main features distinguishing them are Memory
capacity, Timer Module types, Touch Module and key number and stack capacity. The following
table summarises the main features of each device.
Part No.
Program
Memory
Data
Memory
Data
EEPROM
I/O
External
Interrupt
A/D
Temp.
Timer Module
Sensor
Time
Base
BS66FV340
4k x 16
512 x 8
128 x 8
39
2
12-bit x 8
√
10-bit CTM x 1
10-bit PTM x 2
16-bit STM x 1
2
BS66FV350
8k x 16
768 x 8
128 x 8
39
2
12-bit x 8
√
10-bit CTM x 2
10-bit PTM x 2
16-bit STM x 1
2
BS66FV360
16k x 16
1024 x 8
256 x 8
39
2
12-bit x 8
√
10-bit CTM x 2
10-bit PTM x 2
16-bit STM x 1
2
R-type LCD
(1/3 Bias)
D/A
Power
Amplifier
Package
Part No.
Stacks
Touch
Module
Touch
Key
BS66FV340
8
5
20
√
√
√
6(SCOM/SSEG)
+33SSEG6
√
√
44/48LQFP
BS66FV350
8
6
24
√
√
√
6(SCOM/SSEG)
+33SSEG
√
√
44/48LQFP
BS66FV360
12
7
28
√
√
√
6(SCOM/SSEG)
+33SSEG
√
√
44/48LQFP
SIM UART SPIA
Note: As devices exist in more than one package format, the table reflects the situation for the
package with the most pins.
Rev. 1.10
9
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Block Diagram
Wat�hdog
Ti�e�
Flash/EEPROM
P�og�a��ing Ci��uit�y
EEPROM
Data
Me�o�y
Flash
P�og�a�
Me�o�y
Inte�nal
HIRC/LIRC
Os�illato�s
Low
Voltage
Dete�t
IAP
Low
Voltage
Reset
RAM Data
Me�o�y
Reset
Ci��uit
8-�it
RISC
MCU
Co�e
Ti�e�
Modules
SIM
(SPI/I�C)
UART
SCOM/
SSEG
SPIA
Exte�nal
HXT/LXT
Os�illato�s
Tou�h Key
Modules
Ti�e
Base
Te�p.
Senso�
I/O
Inte��upt
Cont�olle�
Volu�e
Cont�ol
1�-�it A/D
Conve�te�
1�-�it D/A
Conve�te�
Powe� A�plifie�
Pin Assignment
SPAVSS_PA
AVDD_PA
SP+
AUD_IN
AUD
BIAS
VDD
PE7/XT�/SSEG1�
PE�/XT1/SSEG14
VSS
PE4/OSC1/AN4/SSEG1�
PE�/OSC�/AN�/SSEG13
PA4/AN0/SSEG�0
PA�/VREF/AN1/SSEG�1
PA�/SCK/SCL/AN�/SSEG��
PA7/SDI/SDA/AN3/SSEG�3
PB0/AN�/SSEG3�
PB4/STCK/KEY1/SSEG3�
PB�/PTCK0/KEY�/SSEG3�
PB�/CTP0B/KEY3/SSEG37
PB7/INT0/KEY4/SSEG38
44 43 4� 41 40 39 38 37 3� 3� 34
1
33
�
3�
3
31
4
30
�
BS66FV340/BS66VV340 �9
�
�8
44 LQFP-A
7
�7
8
��
9
��
10
�4
11
�3
1� 13 14 1� 1� 17 18 19 �0 �1 ��
PB�/CTCK0/VDDIO/SSEG34
PC7/SCSA/SSEG31
PC�/SDIA/SSEG30
PC�/SCKA/SSEG�9
PC4/SDOA/SSEG�8
PA3/SCS/SSEG19
PA�/SCS/SSEG18/ICPCK/OCDSCK
PA1/SDO/SSEG17
PA0/SDO/SSEG1�/ICPDA/OCDSDA
PE�/STPI/STP/KEY19/SSEG10
PE1/PTP1I/PTP1B/KEY18/SSEG9
PE0/PTP1I/PTP1/KEY17/SSEG8
PD�/KEY1�/SSEG�
PD�/KEY14/SCOM�/SSEG�
PD4/PTCK1/KEY13/SCOM4/SSEG4
PD3/KEY1�/SCOM3/SSEG3
PD�/KEY11/SCOM�/SSEG�
PD1/RX/KEY10/SCOM1/SSEG1
PD0/TX/KEY9/SCOM0/SSEG0
PC�/PTP0I/PTP0/KEY7/SSEG��
PC1/CTP0/KEY�/SSEG��
PC0/INT1/KEY�/SSEG�4
Rev. 1.10
10
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
PB�/CTCK0/VDDIO/SSEG34
SPAVSS_PA
AVDD_PA
SP+
AUD_IN
AUD
BIAS
VDD
PE7/XT�/SSEG1�
PE�/XT1/SSEG14
VSS
PE4/OSC1/AN4/SSEG1�
PE�/OSC�/AN�/SSEG13
PA4/AN0/SSEG�0
PA�/VREF/AN1/SSEG�1
PA�/SCK/SCL/AN�/SSEG��
PA7/SDI/SDA/AN3/SSEG�3
PB0/AN�/SSEG3�
PB1/AN7/SSEG33
PB4/STCK/KEY1/SSEG3�
PB�/PTCK0/KEY�/SSEG3�
PB�/CTP0B/KEY3/SSEG37
PB7/INT0/KEY4/SSEG38
48 47 4� 4� 44 43 4� 41 40 39 38 37
3�
1
3�
�
34
3
33
4
�
3�
BS66FV340/BS66VV340 31
�
7
30
48 LQFP-A
�9
8
�8
9
�7
10
��
11
��
1�
13 14 1� 1� 17 18 19 �0 �1 �� �3 �4
PC7/SCSA/SSEG31
PC�/SDIA/SSEG30
PC�/SCKA/SSEG�9
PC4/SDOA/SSEG�8
PA3/SCS/SSEG19
PA�/SCS/SSEG18/ICPCK/OCDSCK
PA1/SDO/SSEG17
PA0/SDO/SSEG1�/ICPDA/OCDSDA
PE3/STPI/STPB/KEY�0/SSEG11
PE�/STPI/STP/KEY19/SSEG10
PE1/PTP1/PTP1BI/KEY18/SSEG9
PE0/PTP1I/PTP1/KEY17/SSEG8
PD7/KEY1�/SSEG7
PD�/KEY1�/SSEG�
PD�/KEY14/SCOM�/SSEG�
PD4/PTCK1/KEY13/SCOM4/SSEG4
PD3/KEY1�/SCOM3/SSEG3
PD�/KEY11/SCOM�/SSEG�
PD1/RX/KEY10/SCOM1/SSEG1
PD0/TX/KEY9/SCOM0/SSEG0
PC3/PTP0I/PTP0B/KEY8/SSEG�7
PC�/PTP0I/PTP0/KEY7/SSEG��
PC1/CTP0/KEY�/SSEG��
PC0/INT1/KEY�/SSEG�4
SPAVSS_PA
AVDD_PA
SP+
AUD_IN
AUD
BIAS
VDD
PE7/XT�/SSEG1�
PE�/XT1/SSEG14
VSS
PE4/OSC1/AN4/SSEG1�
PE�/OSC�/AN�/SSEG13
PA4/AN0/SSEG�0
PA�/VREF/AN1/SSEG�1
PA�/SCK/SCL/AN�/SSEG��
PA7/SDI/SDA/AN3/SSEG�3
PB0/AN�/SSEG3�
PB4/STCK/KEY1/SSEG3�
PB�/PTCK0/KEY�/SSEG3�
PB�/CTP0B/KEY3/SSEG37
PB7/INT0/KEY4/SSEG38
44 43 4� 41 40 39 38 37 3� 3� 34
1
33
�
3�
3
31
4
30
�
BS66FV350/BS66VV350 �9
�
�8
44 LQFP-A
7
�7
8
��
9
��
10
�4
11
�3
1� 13 14 1� 1� 17 18 19 �0 �1 ��
PB�/CTCK0/VDDIO/SSEG34
PC7/SCSA/SSEG31
PC�/SDIA/SSEG30
PC�/SCKA/SSEG�9
PC4/SDOA/SSEG�8
PA3/SCS/KEY�4/SSEG19
PA�/SCS/KEY�3/SSEG18/ICPCK/OCDSCK
PA1/SDO/KEY��/SSEG17
PA0/SDO/KEY�1/SSEG1�/ICPDA/OCDSDA
PE�/STPI/STP/KEY19/SSEG10
PE1/PTP1I/PTP1B/KEY18/SSEG9
PE0/PTP1I/PTP1/KEY17/SSEG8
PD�/CTP1B/KEY1�/SSEG�
PD�/CTP1/KEY14/SCOM�/SSEG�
PD4/PTCK1/KEY13/SCOM4/SSEG4
PD3/KEY1�/SCOM3/SSEG3
PD�/KEY11/SCOM�/SSEG�
PD1/RX/KEY10/SCOM1/SSEG1
PD0/TXKEY9/SCOM0/SSEG0/
PC�/PTP0I/PTP0/KEY7/SSEG��
PC1/CTP0/KEY�/SSEG��
PC0/INT1/KEY�/SSEG�4
Rev. 1.10
11
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
PB�/CTCK0/VDDIO/SSEG34
SPAVSS_PA
AVDD_PA
SP+
AUD_IN
AUD
BIAS
VDD
PE7/XT�/SSEG1�
PE�/XT1/SSEG14
VSS
PE4/OSC1/AN4/SSEG1�
PE�/OSC�/AN�/SSEG13
PA4/AN0/SSEG�0
PA�/VREF/AN1/SSEG�1
PA�/SCK/SCL/AN�/SSEG��
PA7/SDI/SDA/AN3/SSEG�3
PB0/AN�/SSEG3�
PB1/AN7/SSEG33
PB4/STCK/KEY1/SSEG3�
PB�/PTCK0/KEY�/SSEG3�
PB�/CTP0B/KEY3/SSEG37
PB7/INT0/KEY4/SSEG38
48 47 4� 4� 44 43 4� 41 40 39 38 37
3�
1
3�
�
34
3
33
4
�
3�
BS66FV350/BS66VV350 31
�
7
30
48 LQFP-A
�9
8
�8
9
�7
10
��
11
��
1�
13 14 1� 1� 17 18 19 �0 �1 �� �3 �4
PC7/SCSA/SSEG31
PC�/SDIA/SSEG30
PC�/SCKA/SSEG�9
PC4/SDOA/SSEG�8
PA3/SCS/KEY�4/SSEG19
PA�/SCS/KEY�3/SSEG18/ICPCK/OCDSCK
PA1/SDO/KEY��/SSEG17
PA0/SDO/KEY�1/SSEG1�/ICPDA/OCDSDA
PE3/STPI/STPB/KEY�0/SSEG11
PE�/STPI/STP/KEY19/SSEG10
PE1/PTP1I/PTP1B/KEY18/SSEG9
PE0/PTP1I/PTP1/KEY17/SSEG8
PD7/CTCK1/KEY1�/SSEG7
PD�/CTP1B/KEY1�/SSEG�
PD�/CTP1/KEY14/SCOM�/SSEG�
PD4/PTCK1/KEY13/SCOM4/SSEG4
PD3/KEY1�/SCOM3/SSEG3
PD�/KEY11/SCOM�/SSEG�
PD1/RX/KEY10/SCOM1/SSEG1
PD0/TX/KEY9/SCOM0/SSEG0
PC3/PTP0I/PTP0B/KEY8/SSEG�7
PC�/PTP0I/PTP0/KEY7/SSEG��
PC1/CTP0/KEY�/SSEG��
PC0/INT1/KEY�/SSEG�4
SPAVSS_PA
AVDD_PA
SP+
AUD_IN
AUD
BIAS
VDD
PE7/XT�/SSEG1�
PE�/XT1/SSEG14
VSS
PE4/OSC1/AN4/SSEG1�
PE�/OSC�/AN�/SSEG13
PA4/AN0/SSEG�0
PA�/VREF/AN1/SSEG�1
PA�/SCK/SCL/AN�/SSEG��
PA7/SDI/SDA/AN3/SSEG�3
PB0/AN�/SSEG3�
PB4/STCK/KEY1/SSEG3�
PB�/PTCK0/KEY�/SSEG3�
PB�/CTP0B/KEY3/SSEG37
PB7/INT0/KEY4/SSEG38
44 43 4� 41 40 39 38 37 3� 3� 34
1
33
�
3�
3
31
4
30
�
BS66FV360/BS66VV360 �9
�
�8
44 LQFP-A
7
�7
8
��
9
��
10
�4
11
�3
1� 13 14 1� 1� 17 18 19 �0 �1 ��
PB�/CTCK0/VDDIO/SSEG34
PC7/SCSA/KEY�8/SSEG31
PC�/SDIA/KEY�7/SSEG30
PC�/SCKA/KEY��/SSEG�9
PC4/SDOA/KEY��/SSEG�8
PA3/SCS/KEY�4/SSEG19
PA�/SCS/KEY�3/SSEG18/ICPCK/OCDSCK
PA1/SDO/KEY��/SSEG17
PA0/SDO/KEY�1/SSEG1�/ICPDA/OCDSDA
PE�/STPI/STP/KEY19/SSEG10
PE1/PTP1I/PTP1B/KEY18/SSEG9
PE0/PTP1I/PTP1/KEY17/SSEG8
PD�/CTP1B/KEY1�/SSEG�
PD�/CTP1/KEY14/SCOM�/SSEG�
PD4/PTCK1/KEY13/SCOM4/SSEG4
PD3/KEY1�/SCOM3/SSEG3
PD�/KEY11/SCOM�/SSEG�
PD1/RX/KEY10/SCOM1/SSEG1
PD0/TX/KEY9/SCOM0/SSEG0
PC�/PTP0I/PTP0/KEY7/SSEG��
PC1/CTP0/KEY�/SSEG��
PC0/INT1/KEY�/SSEG�4
Rev. 1.10
12
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
PB�/CTCK0/VDDIO/SSEG34
SPAVSS_PA
AVDD_PA
SP+
AUD_IN
AUD
BIAS
VDD
PE7/XT�/SSEG1�
PE�/XT1/SSEG14
VSS
PE4/OSC1/AN4/SSEG1�
PE�/OSC�/AN�/SSEG13
PA4/AN0/SSEG�0
PA�/VREF/AN1/SSEG�1
PA�/SCK/SCL/AN�/SSEG��
PA7/SDI/SDA/AN3/SSEG�3
PB0/AN�/SSEG3�
PB1/AN7/SSEG33
PB4/STCK/KEY1/SSEG3�
PB�/PTCK0/KEY�/SSEG3�
PB�/CTP0B/KEY3/SSEG37
PB7/INT0/KEY4/SSEG38
48 47 4� 4� 44 43 4� 41 40 39 38 37
3�
1
3�
�
34
3
33
4
�
3�
BS66FV360/BS66VV360 31
�
7
30
48 LQFP-A
�9
8
�8
9
�7
10
��
11
��
1�
13 14 1� 1� 17 18 19 �0 �1 �� �3 �4
PC7/SCSA/KEY�8/SSEG31
PC�/SDIA/KEY�7/SSEG30
PC�/SCKA/KEY��/SSEG�9
PC4/SDOA/KEY��/SSEG�8
PA3/SCS/KEY�4/SSEG19
PA�/SCS/KEY�3/SSEG18/ICPCK/OCDSCK
PA1/SDO/KEY��/SSEG17
PA0/SDO/KEY�1/SSEG1�/ICPDA/OCDSDA
PE3/STPI/STPB/KEY�0/SSEG11
PE�/STPI/STP/KEY19/SSEG10
PE1/PTP1I/PTP1B/KEY18/SSEG9
PE0/PTP1I/PTP1/KEY17/SSEG8
PD7/CTCK1/KEY1�/SSEG7
PD�/CTP1B/KEY1�/SSEG�
PD�/CTP1/KEY14/SCOM�/SSEG�
PD4/PTCK1/KEY13/SCOM4/SSEG4
PD3/KEY1�/SCOM3/SSEG3
PD�/KEY11/SCOM�/SSEG�
PD1/RX/KEY10/SCOM1/SSEG1
PD0/TX/KEY9/SCOM0/SSEG0
PC3/PTP0I/PTP0B/KEY8/SSEG�7
PC�/PTP0I/PTP0/KEY7/SSEG��
PC1/CTP0/KEY�/SSEG��
PC0/INT1/KEY�/SSEG�4
Note: The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the BS66VV3x0
device which is the OCDS EV chip for the BS66FV3x0 device.
Rev. 1.10
13
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pin Descriptions
With the exception of the power pins and some relevant transformer control pins, all pins on these
devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O
function of the pins. However these Port pins are also shared with other function such as the Analog
to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table,
however the details behind how each pin is configured is contained in other sections of the datasheet.
BS66FV340
Pad Name
PA0/SDO/
SSEG16/
ICPDA/OCDSDA
PA1/SDO/
SSEG17
PA2/SCS/
SSEG18/
ICPCK/OCDSCK
PA3/SCS/
SSEG19
PA4/AN0/
SSEG20
PA5/VREF/AN1/
SSEG21
PA6/SCK/SCL/
AN2/SSEG22
Rev. 1.10
Function
OPT
I/T
O/T
PA0
PAWU
PAPU
PAS0
Description
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SDO
PAS0
—
CMOS
SPI data output
SSEG16
PAS0
—
CMOS
Software LCD SEG output
ICPDA
—
ST
CMOS
ICP Data/Address pin
OCDSDA
—
ST
CMOS
OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SDO
PAS0
—
CMOS
SPI data output
SSEG17
PAS0
—
CMOS
Software LCD SEG output
PA2
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCS
PAS0
IFS
ST
CMOS
SPI slave select
SSEG18
PAS0
—
CMOS
Software LCD SEG output
ICPCK
—
ST
CMOS
ICP Clock pin
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCS
PAS0
IFS
ST
CMOS
SPI slave select
SSEG19
PAS0
—
CMOS
Software LCD SEG output
PA4
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
OCDS Clock pin, for EV chip only.
AN0
PAS1
AN
—
A/D Converter analog input
SSEG20
PAS1
—
CMOS
Software LCD SEG output
PA5
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
VREF
PAS1
—
AN
A/D Converter reference voltage output
AN1
PAS1
AN
—
A/D Converter analog input
SSEG21
PAS1
—
CMOS
Software LCD SEG output
PA6
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCK
PAS1
ST
CMOS
SPI serial clock
SCL
PAS1
ST
NMOS
I2C clock line
AN2
PAS1
AN
—
A/D Converter analog input
SSEG22
PAS1
—
CMOS
Software LCD SEG output
14
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PA7/SDI/SDA/
AN3/SSEG23
PB0/AN6/
SSEG32
PB1/AN7/
SSEG33
PB2/CTCK0/
VDDIO/SSEG34
PB4/STCK/
KEY1/SSEG35
PB5/PTCK0/
KEY2/SSEG36
PB6/CTP0B/
KEY3/SSEG37
PB7/INT0/KEY4/
SSEG38
PC0/INT1/KEY5/
SSEG24
Rev. 1.10
Function
OPT
I/T
O/T
PA7
PAWU
PAPU
PAS1
ST
CMOS
SDI
PAS1
ST
—
SDA
PAS1
ST
NMOS
Description
General purpose I/O. Register enabled pull-up and
wake-up.
SPI data input
I2C data line
AN3
PAS1
AN
—
A/D Converter analog input
SSEG23
PAS1
—
CMOS
Software LCD SEG output
PB0
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN3
PBS0
AN
—
A/D Converter analog input
SSEG32
PBS0
—
CMOS
Software LCD SEG output
PB1
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN7
PBS0
AN
—
A/D Converter analog input
SSEG33
PBS0
—
CMOS
Software LCD SEG output
PB2
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTCK0
PBS0
ST
—
CTM0 clock input
VDDIO
PBS0
PWR
—
PC4~PC7 I/O power for level shift
SSEG34
PBS0
—
CMOS
Software LCD SEG output
PB4
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
STCK
PBS1
ST
—
STM clock input
KEY1
PBS1
AN
—
Touch key input
SSEG35
PBS1
—
CMOS
Software LCD SEG output
PB5
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK0
PBS1
ST
—
PTM0 clock input
KEY2
PBS1
AN
—
Touch key input
SSEG36
PBS1
—
CMOS
Software LCD SEG output
PB6
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTM0 inverted output
CTP0B
PBS1
—
CMOS
KEY3
PBS1
AN
—
SSEG37
PBS1
—
CMOS
Software LCD SEG output
PB7
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
INT0
PBS1
INTEG
INTC0
ST
—
External Interrupt 0
Touch key input
Touch key input
KEY4
PBS1
AN
—
SSEG38
PBS1
—
CMOS
Software LCD SEG output
PC0
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
INT1
PCS0
INTEG
INTC0
ST
—
External Interrupt 1
KEY5
PCS0
AN
—
Touch key input
SSEG24
PCS0
—
CMOS
15
Software LCD SEG output
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PC1/CTP0/KEY6/
SSEG25
PC2/PTP0I/
PTP0/KEY7/
SSEG26
PC3/PTP0I/
PTP0B/KEY8/
SSEG27
PC4/SDOA/
SSEG28
PC5/SCKA/
SSEG29
PC6/SDIA/
SSEG30
PC7/SCSA/
SSEG31
PD0/TX/KEY9/
SCOM0/SSEG0
PD1/RX/KEY10/
SCOM1/SSEG1
Rev. 1.10
Function
OPT
I/T
O/T
PC1
PCPU
PCS0
ST
CMOS
Description
General purpose I/O. Register enabled pull-up.
CTP0
PCS0
—
CMOS
KEY6
PCS0
AN
—
CTM0 output
SSEG25
PCS0
—
CMOS
Software LCD SEG output
PC2
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP0I
PCS0
IFS
ST
—
Touch key input
PTM0 capture input
PTP0
PCS0
—
CMOS
KEY7
PCS0
AN
—
PTM0 output
SSEG26
PCS0
—
CMOS
Software LCD SEG output
PC3
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP0I
PCS0
IFS
ST
—
Touch key input
PTM0 capture input
PTP0B
PCS0
—
CMOS
KEY8
PCS0
AN
—
PTM0 inverted output
SSEG27
PCS0
—
CMOS
Software LCD SEG output
PC4
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
Touch key input
SDOA
PCS1
—
CMOS
SPIA data output
SSEG28
PCS1
—
CMOS
Software LCD SEG output
PC5
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCKA
PCS1
ST
CMOS
SPIA serial clock
SSEG29
PCS1
—
CMOS
Software LCD SEG output
PC6
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SDIA
PCS1
ST
—
SSEG30
PCS1
—
CMOS
SPIA data input
Software LCD SEG output
PC7
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCSA
PCS1
ST
CMOS
SPIA slave select
SSEG31
PCS1
—
CMOS
Software LCD SEG output
PD0
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
TX
PDS0
—
CMOS
UART TX serial data output
KEY9
PDS0
AN
—
SCOM0
PDS0
—
CMOS
Touch key input
Software LCD COM output
SSEG0
PDS0
—
CMOS
Software LCD SEG output
PD1
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
RX
PDS0
ST
—
UART RX serial data input
Touch key input
KEY10
PDS0
AN
—
SCOM1
PDS0
—
CMOS
Software LCD COM output
SSEG1
PDS0
—
CMOS
Software LCD SEG output
16
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PD2/KEY11/
SCOM2/SSEG2
PD3/KEY12/
SCOM3/SSEG3
PD4/PTCK1/
KEY13/SCOM4/
SSEG4
PD5/KEY14/
SCOM5/SSEG5
PD6/KEY15/
SSEG6
PD7/KEY16/
SSEG7
PE0/PTP1I/
PTP1/KEY17/
SSEG8
PE1/PTP1I/
PTP1B/KEY18/
SSEG9
PE2/STPI/STP/
KEY19/SSEG10
Rev. 1.10
Function
OPT
I/T
O/T
PD2
PDPU
PDS0
Description
ST
CMOS
KEY11
PDS0
AN
—
SCOM2
PDS0
—
CMOS
Software LCD COM output
SSEG2
PDS0
—
CMOS
Software LCD SEG output
PD3
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
Touch key input
KEY12
PDS0
AN
—
SCOM3
PDS0
—
CMOS
Touch key input
Software LCD COM output
SSEG3
PDS0
—
CMOS
Software LCD SEG output
PD4
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK1
PDS1
ST
—
PTM1 clock input
KEY13
PDS1
AN
—
Touch key input
SCOM4
PDS1
—
CMOS
Software LCD COM output
SSEG4
PDS1
—
CMOS
Software LCD SEG output
PD5
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
KEY14
PDS1
AN
—
SCOM5
PDS1
—
CMOS
Software LCD COM output
SSEG5
PDS1
—
CMOS
Software LCD SEG output
PD6
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
Touch key input
KEY15
PDS1
AN
—
SSEG6
PDS1
—
CMOS
Touch key input
Software LCD SEG output
PD7
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
KEY16
PDS1
AN
—
SSEG7
PDS1
—
CMOS
Touch key input
Software LCD SEG output
PE0
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP1I
PES0
IFS
ST
—
PTM1 capture input
PTP1
PES0
—
CMOS
KEY17
PES0
AN
—
SSEG8
PES0
—
CMOS
Software LCD SEG output
PE1
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP1I
PES0
IFS
ST
—
PTP1B
PES0
—
CMOS
KEY18
PES0
AN
—
SSEG9
PES0
—
CMOS
Software LCD SEG output
PE2
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STPI
PES0
IFS
ST
—
STP
PES0
—
CMOS
KEY19
PES0
AN
—
SSEG10
PES0
—
CMOS
17
PTM1 output
Touch key input
PTM1 capture input
PTM1 inverted output
Touch key input
STM capture input
STM output
Touch key input
Software LCD SEG output
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PE3/STPI/STPB/
KEY20/SSEG11
PE4/OSC1/AN4/
SSEG12
PE5/OSC2/AN5/
SSEG13
PE6/XT1/
SSEG14
PE7/XT2/
SSEG15
Function
OPT
I/T
O/T
PE3
PEPU
PES0
ST
CMOS
STPI
PES0
IFS
ST
—
Description
General purpose I/O. Register enabled pull-up.
STM capture input
STPB
PES0
—
CMOS
KEY20
PES0
AN
—
STM inverted output
SSEG11
PES0
—
CMOS
Software LCD SEG output
PE4
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
OSC1
PES1
HXT
—
HXT oscillator pin
AN4
PES1
AN
—
A/D Converter analog input
SSEG12
PES1
—
CMOS
Software LCD SEG output
PE5
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
OSC2
PES1
—
HXT
AN5
PES1
AN
—
A/D Converter analog input
SSEG13
PES1
—
CMOS
Software LCD SEG output
PE6
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
Touch key input
HXT oscillator pin
XT1
PES1
LXT
—
SSEG14
PES1
—
CMOS
LXT oscillator pin
Software LCD SEG output
PE7
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
XT2
PES1
—
LXT
LXT oscillator pin
SSEG15
PES1
—
CMOS
SP+
SP+
—
—
AN
SP-
SP-
—
—
AN
Power amplifier output
AUD_IN
—
AN
—
Power amplifier input
AUD_IN
Software LCD SEG output
Power amplifier output
BIAS
BIAS
—
—
AN
Power amplifier voltage bias reference
AUD
AUD
—
—
AN
D/A converter output
AVDD_PA
AVDD_PA
—
PWR
—
Audio power amplifier positive power supply
AVSS_PA
AVSS_PA
—
PWR
—
Audio power amplifier negative power supply
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
Legend: I/T: Input type;
O/T: Output type;
PWR: Power;
AN: Analog signal;
CMOS: CMOS output;
NMOS: NMOS output;
HXT: High frequency crystal oscillator;
Rev. 1.10
18
OPT: Optional by register option;
ST: Schmitt Trigger input;
LXT: Low frequency crystal oscillator
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
BS66FV350
Pad Name
PA0/SDO/KEY21/
SSEG16/
ICPDA/OCDSDA
PA1/SDO/KEY22/
SSEG17
PA2/SCS/KEY23/
SSEG18/
ICPCK/OCDSCK
PA3/SCS/KEY24/
SSEG19
PA4/AN0/
SSEG20
PA5/VREF/AN1/
SSEG21
PA6/SCK/SCL/
AN2/SSEG22
Rev. 1.10
Function
OPT
I/T
O/T
PA0
PAWU
PAPU
PAS0
Description
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SDO
PAS0
—
CMOS
SPI data output
KEY21
PAS0
AN
—
Touch key input
SSEG16
PAS0
—
CMOS
Software LCD SEG output
ICPDA
—
ST
CMOS
ICP Data/Address pin
OCDSDA
—
ST
CMOS
OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SDO
PAS0
—
CMOS
SPI data output
KEY22
PAS0
AN
—
Touch key input
SSEG17
PAS0
—
CMOS
Software LCD SEG output
PA2
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCS
PAS0
IFS
ST
CMOS
SPI slave select
KEY23
PAS0
AN
—
Touch key input
SSEG18
PAS0
—
CMOS
Software LCD SEG output
ICPCK
—
ST
CMOS
ICP Clock pin
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCS
PAS0
IFS
ST
CMOS
SPI slave select
Touch key input
OCDS Clock pin, for EV chip only.
KEY24
PAS0
AN
—
SSEG19
PAS0
—
CMOS
Software LCD SEG output
PA4
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
AN0
PAS1
AN
—
A/D Converter analog input
SSEG20
PAS1
—
CMOS
Software LCD SEG output
PA5
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
VREF
PAS1
—
AN
A/D Converter reference voltage output
AN1
PAS1
AN
—
A/D Converter analog input
SSEG21
PAS1
—
CMOS
Software LCD SEG output
PA6
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCK
PAS1
ST
CMOS
SPI serial clock
SCL
PAS1
ST
NMOS
I2C clock line
AN2
PAS1
AN
—
A/D Converter analog input
SSEG22
PAS1
—
CMOS
Software LCD SEG output
19
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PA7/SDI/SDA/
AN3/SSEG23
PB0/AN6/
SSEG32
PB1/AN7/
SSEG33
PB2/CTCK0/
VDDIO/SSEG34
PB4/STCK/
KEY1/SSEG35
PB5/PTCK0/
KEY2/SSEG36
PB6/CTP0B/
KEY3/SSEG37
PB7/INT0/KEY4/
SSEG38
PC0/INT1/KEY5/
SSEG24
Rev. 1.10
Function
OPT
I/T
O/T
PA7
PAWU
PAPU
PAS1
ST
CMOS
SDI
PAS1
ST
—
SDA
PAS1
ST
NMOS
Description
General purpose I/O. Register enabled pull-up and
wake-up.
SPI data input
I2C data line
AN3
PAS1
AN
—
A/D Converter analog input
SSEG23
PAS1
—
CMOS
Software LCD SEG output
PB0
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN3
PBS0
AN
—
A/D Converter analog input
SSEG32
PBS0
—
CMOS
Software LCD SEG output
PB1
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN7
PBS0
AN
—
A/D Converter analog input
SSEG33
PBS0
—
CMOS
Software LCD SEG output
PB2
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTCK0
PBS0
ST
—
CTM0 clock input
VDDIO
PBS0
PWR
—
PC4~PC7 I/O power for level shift
SSEG34
PBS0
—
CMOS
Software LCD SEG output
PB4
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
STCK
PBS1
ST
—
STM clock input
KEY1
PBS1
AN
—
Touch key input
SSEG35
PBS1
—
CMOS
Software LCD SEG output
PB5
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK0
PBS1
ST
—
PTM0 clock input
KEY2
PBS1
AN
—
Touch key input
SSEG36
PBS1
—
CMOS
Software LCD SEG output
PB6
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTP0B
PBS1
—
CMOS
CTM0 inverted output
KEY3
PBS1
AN
—
SSEG37
PBS1
—
CMOS
Software LCD SEG output
PB7
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
INT0
PBS1
INTEG
INTC0
ST
—
External Interrupt 0
Touch key input
Touch key input
KEY4
PBS1
AN
—
SSEG38
PBS1
—
CMOS
Software LCD SEG output
PC0
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
INT1
PCS0
INTEG
INTC0
ST
—
External Interrupt 1
KEY5
PCS0
AN
—
Touch key input
SSEG24
PCS0
—
CMOS
20
Software LCD SEG output
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PC1/CTP0/KEY6/
SSEG25
PC2/PTP0I/
PTP0/KEY7/
SSEG26
PC3/PTP0I/
PTP0B/KEY8/
SSEG27
PC4/SDOA/
SSEG28
PC5/SCKA/
SSEG29
PC6/SDIA/
SSEG30
PC7/SCSA/
SSEG31
PD0/TX/KEY9/
SCOM0/SSEG0
PD1/RX/KEY10/
SCOM1/SSEG1
Rev. 1.10
Function
OPT
I/T
O/T
PC1
PCPU
PCS0
Description
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTM0 output
CTP0
PCS0
—
CMOS
KEY6
PCS0
AN
—
SSEG25
PCS0
—
CMOS
Software LCD SEG output
PC2
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP0I
PCS0
IFS
ST
—
Touch key input
PTM0 capture input
PTP0
PCS0
—
CMOS
KEY7
PCS0
AN
—
PTM0 output
SSEG26
PCS0
—
CMOS
Software LCD SEG output
PC3
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP0I
PCS0
IFS
ST
—
Touch key input
PTM0 capture input
PTP0B
PCS0
—
CMOS
KEY8
PCS0
AN
—
PTM0 inverted output
SSEG27
PCS0
—
CMOS
Software LCD SEG output
PC4
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
Touch key input
SDOA
PCS1
—
CMOS
SPIA data output
SSEG28
PCS1
—
CMOS
Software LCD SEG output
PC5
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCKA
PCS1
ST
CMOS
SPIA serial clock
SSEG29
PCS1
—
CMOS
Software LCD SEG output
PC6
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SDIA
PCS1
ST
—
SSEG30
PCS1
—
CMOS
SPIA data input
Software LCD SEG output
PC7
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCSA
PCS1
ST
CMOS
SPIA slave select
SSEG31
PCS1
—
CMOS
Software LCD SEG output
PD0
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
TX
PDS0
—
CMOS
UART TX serial data output
KEY9
PDS0
AN
—
SCOM0
PDS0
—
CMOS
Touch key input
Software LCD COM output
SSEG0
PDS0
—
CMOS
Software LCD SEG output
PD1
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
RX
PDS0
ST
—
UART RX serial data input
Touch key input
KEY10
PDS0
AN
—
SCOM1
PDS0
—
CMOS
Software LCD COM output
SSEG1
PDS0
—
CMOS
Software LCD SEG output
21
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PD2/KEY11/
SCOM2/SSEG2
PD3/KEY12/
SCOM3/SSEG3
PD4/PTCK1/
KEY13/SCOM4/
SSEG4
PD5/CTP1/
KEY14/SCOM5/
SSEG5
PD6/CTP1B/
KEY15/SSEG6
PD7/CTCK1/
KEY16/SSEG7
PE0/PTP1I/
PTP1/KEY17/
SSEG8
PE1/PTP1I/
PTP1B/KEY18/
SSEG9
Rev. 1.10
Function
OPT
I/T
O/T
PD2
PDPU
PDS0
Description
ST
CMOS
KEY11
PDS0
AN
—
SCOM2
PDS0
—
CMOS
Software LCD COM output
SSEG2
PDS0
—
CMOS
Software LCD SEG output
PD3
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
Touch key input
KEY12
PDS0
AN
—
SCOM3
PDS0
—
CMOS
Touch key input
Software LCD COM output
SSEG3
PDS0
—
CMOS
Software LCD SEG output
PD4
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK1
PDS1
ST
—
PTM1 clock input
KEY13
PDS1
AN
—
Touch key input
SCOM4
PDS1
—
CMOS
Software LCD COM output
SSEG4
PDS1
—
CMOS
Software LCD SEG output
PD5
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTP1
PDPU
PDS1
—
CMOS
CTM1 output
Touch key input
KEY14
PDS1
AN
—
SCOM5
PDS1
—
CMOS
Software LCD COM output
SSEG5
PDS1
—
CMOS
Software LCD SEG output
PD6
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTP1B
PDS1
—
CMOS
CTM1 inverted output
KEY15
PDS1
AN
—
SSEG6
PDS1
—
CMOS
Software LCD SEG output
PD7
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK1
PDS1
ST
—
CTM1 clock input
KEY16
PDS1
AN
—
Touch key input
SSEG7
PDS1
—
CMOS
Software LCD SEG output
PE0
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP1I
PES0
IFS
ST
—
Touch key input
PTM1 capture input
PTP1
PES0
—
CMOS
KEY17
PES0
AN
—
SSEG8
PES0
—
CMOS
Software LCD SEG output
PE1
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP1I
PES0
IFS
ST
—
PTP1B
PES0
—
CMOS
KEY18
PES0
AN
—
SSEG9
PES0
—
CMOS
22
PTM1 output
Touch key input
PTM1 capture input
PTM1 inverted output
Touch key input
Software LCD SEG output
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PE2/STPI/STP/
KEY19/SSEG10
PE3/STPI/STPB/
KEY20/SSEG11
PE4/OSC1/AN4/
SSEG12
PE5/OSC2/AN5/
SSEG13
PE6/XT1/
SSEG14
PE7/XT2/
SSEG15
SP+
SPAUD_IN
Function
OPT
I/T
O/T
PE2
PEPU
PES0
Description
ST
CMOS
STPI
PES0
IFS
ST
—
STP
PES0
—
CMOS
KEY19
PES0
AN
—
SSEG10
PES0
—
CMOS
Software LCD SEG output
PE3
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STPI
PES0
IFS
ST
—
STPB
PES0
—
CMOS
KEY20
PES0
AN
—
SSEG11
PES0
—
CMOS
Software LCD SEG output
PE4
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
OSC1
PES1
HXT
—
HXT oscillator pin
AN4
PES1
AN
—
A/D Converter analog input
SSEG12
PES1
—
CMOS
Software LCD SEG output
PE5
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
OSC2
PES1
—
HXT
AN5
PES1
AN
—
A/D Converter analog input
SSEG13
PES1
—
CMOS
Software LCD SEG output
PE6
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
STM capture input
STM output
Touch key input
STM capture input
STM inverted output
Touch key input
HXT oscillator pin
XT1
PES1
LXT
—
SSEG14
PES1
—
CMOS
LXT oscillator pin
Software LCD SEG output
PE7
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
XT2
PES1
—
LXT
SSEG15
PES1
—
CMOS
LXT oscillator pin
SP+
—
—
AN
Power amplifier output
Software LCD SEG output
SP-
—
—
AN
Power amplifier output
AUD_IN
—
AN
—
Power amplifier input
Power amplifier voltage bias reference
BIAS
BIAS
—
—
AN
AUD
AUD
—
—
AN
D/A converter output
AVDD_PA
AVDD_PA
—
PWR
—
Audio power amplifier positive power supply
AVSS_PA
AVSS_PA
—
PWR
—
Audio power amplifier negative power supply
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
Legend: I/T: Input type;
O/T: Output type;
PWR: Power;
AN: Analog signal;
CMOS: CMOS output;
NMOS: NMOS output;
HXT: High frequency crystal oscillator;
Rev. 1.10
23
OPT: Optional by register option;
ST: Schmitt Trigger input;
LXT: Low frequency crystal oscillator
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
BS66FV360
Pad Name
PA0/SDO/
KEY21/SSEG16/
ICPDA/OCDSDA
PA1/SDO/
KEY22/SSEG17
PA2/SCS/KEY23/
SSEG18/
ICPCK/OCDSCK
PA3/SCS/KEY24/
SSEG19
PA4/AN0/
SSEG20
PA5/VREF/AN1/
SSEG21
PA6/SCK/SCL/
AN2/SSEG22
Rev. 1.10
Function
OPT
I/T
O/T
PA0
PAWU
PAPU
PAS0
ST
CMOS
Description
General purpose I/O. Register enabled pull-up and
wake-up.
SDO
PAS0
—
CMOS
SPI data output
KEY21
PAS0
AN
—
Touch key input
SSEG16
PAS0
—
CMOS
Software LCD SEG output
ICPDA
—
ST
CMOS
ICP Data/Address pin
OCDSDA
—
ST
CMOS
OCDS Data/Address pin, for EV chip only.
PA1
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SDO
PAS0
—
CMOS
SPI data output
KEY22
PAS0
AN
—
Touch key input
SSEG17
PAS0
—
CMOS
Software LCD SEG output
PA2
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCS
PAS0
IFS
ST
CMOS
SPI slave select
KEY23
PAS0
AN
—
Touch key input
SSEG18
PAS0
—
CMOS
Software LCD SEG output
ICPCK
—
ST
CMOS
ICP Clock pin
OCDSCK
—
ST
—
PA3
PAWU
PAPU
PAS0
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCS
PAS0
IFS
ST
CMOS
SPI slave select
Touch key input
OCDS Clock pin, for EV chip only.
KEY24
PAS0
AN
—
SSEG19
PAS0
—
CMOS
Software LCD SEG output
PA4
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
AN0
PAS1
AN
—
A/D Converter analog input
SSEG20
PAS1
—
CMOS
Software LCD SEG output
PA5
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
VREF
PAS1
—
AN
A/D Converter reference voltage output
AN1
PAS1
AN
—
A/D Converter analog input
SSEG21
PAS1
—
CMOS
Software LCD SEG output
PA6
PAWU
PAPU
PAS1
ST
CMOS
General purpose I/O. Register enabled pull-up and
wake-up.
SCK
PAS1
ST
CMOS
SPI serial clock
SCL
PAS1
ST
NMOS
I2C clock line
AN2
PAS1
AN
—
A/D Converter analog input
SSEG22
PAS1
—
CMOS
Software LCD SEG output
24
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PA7/SDI/SDA/
AN3/SSEG23
PB0/AN6/
SSEG32
PB1/AN7/
SSEG33
PB2/CTCK0/
VDDIO/SSEG34
PB4/STCK/
KEY1/SSEG35
PB5/PTCK0/
KEY2/SSEG36
PB6/CTP0B/
KEY3/SSEG37
PB7/INT0/KEY4/
SSEG38
PC0/INT1/KEY5/
SSEG24
Rev. 1.10
Function
OPT
I/T
O/T
PA7
PAWU
PAPU
PAS1
ST
CMOS
SDI
PAS1
ST
—
SDA
PAS1
ST
NMOS
Description
General purpose I/O. Register enabled pull-up and
wake-up.
SPI data input
I2C data line
AN3
PAS1
AN
—
A/D Converter analog input
SSEG23
PAS1
—
CMOS
Software LCD SEG output
PB0
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN6
PBS0
AN
—
A/D Converter analog input
SSEG32
PBS0
—
CMOS
Software LCD SEG output
PB1
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
AN7
PBS0
AN
—
A/D Converter analog input
SSEG33
PBS0
—
CMOS
Software LCD SEG output
PB2
PBPU
PBS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTCK0
PBS0
ST
—
CTM0 clock input
VDDIO
PBS0
PWR
—
PC4~PC7 I/O power for level shift
SSEG34
PBS0
—
CMOS
Software LCD SEG output
PB4
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
STCK
PBS1
ST
—
STM clock input
KEY1
PBS1
AN
—
Touch key input
SSEG35
PBS1
—
CMOS
Software LCD SEG output
PB5
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK0
PBS1
ST
—
PTM0 clock input
KEY2
PBS1
AN
—
Touch key input
SSEG36
PBS1
—
CMOS
Software LCD SEG output
PB6
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTPB
PBS1
—
CMOS
CTM inverted output
KEY3
PBS1
AN
—
SSEG37
PBS1
—
CMOS
Software LCD SEG output
PB7
PBPU
PBS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
INT0
PBS1
INTEG
INTC0
ST
—
External Interrupt 0
Touch key input
Touch key input
KEY4
PBS1
AN
—
SSEG38
PBS1
—
CMOS
Software LCD SEG output
PC0
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
INT1
PCS0
INTEG
INTC0
ST
—
External Interrupt 1
KEY5
PCS0
AN
—
Touch key input
SSEG24
PCS0
—
CMOS
25
Software LCD SEG output
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PC1/CTP0/
KEY6/SSEG25
PC2/PTP0I/
PTP0/KEY7/
SSEG26
PC3/PTP0I/
PTP0B/KEY8/
SSEG27
PC4/SDOA/
KEY25/SSEG28
PC5/SCKA/
KEY26/SSEG29
PC6/SDIA/
KEY27/SSEG30
PC7/SCSA/
KEY28/SSEG31
PD0/TX/KEY9/
SCOM0/SSEG0
PD1/RX/KEY10/
SCOM1/SSEG1
Rev. 1.10
Function
OPT
I/T
O/T
PC1
PCPU
PCS0
Description
ST
CMOS
CTP0
PCS0
—
CMOS
KEY6
PCS0
AN
—
SSEG25
PCS0
—
CMOS
Software LCD SEG output
PC2
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP0I
PCS0
IFS
ST
—
PTP0
PCS0
—
CMOS
KEY7
PCS0
AN
—
SSEG26
PCS0
—
CMOS
Software LCD SEG output
PC3
PCPU
PCS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP0I
PCS0
IFS
ST
—
PTP0B
PCS0
—
CMOS
KEY8
PCS0
AN
—
SSEG27
PCS0
—
CMOS
Software LCD SEG output
PC4
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
CTM output
Touch key input
PTM0 capture input
PTM0 output
Touch key input
PTM0 capture input
PTM0 inverted output
Touch key input
SDOA
PCS1
—
CMOS
SPIA data output
KEY25
PCS1
AN
—
Touch key input
SSEG28
PCS1
—
CMOS
Software LCD SEG output
PC5
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SCKA
PCS1
ST
CMOS
SPIA serial clock
KEY26
PCS1
AN
—
Touch key input
SSEG29
PCS1
—
CMOS
Software LCD SEG output
PC6
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SDIA
PCS1
ST
—
SPIA data input
KEY27
PCS1
AN
—
Touch key input
SSEG30
PCS1
—
CMOS
Software LCD SEG output
PC7
PCPU
PCS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
SPIA slave select
SCSA
PCS1
ST
CMOS
KEY28
PCS1
AN
—
SSEG31
PCS1
—
CMOS
Software LCD SEG output
PD0
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
UART TX serial data output
Touch key input
TX
PDS0
—
CMOS
KEY9
PDS0
AN
—
SCOM0
PDS0
—
CMOS
Software LCD COM output
SSEG0
PDS0
—
CMOS
Software LCD SEG output
PD1
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
Touch key input
RX
PDS0
ST
—
UART RX serial data input
KEY10
PDS0
AN
—
Touch key input
SCOM1
PDS0
—
CMOS
Software LCD COM output
SSEG1
PDS0
—
CMOS
Software LCD SEG output
26
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PD2/KEY11/
SCOM2/SSEG2
PD3/KEY12/
SCOM3/SSEG3
PD4/PTCK1/
KEY13/SCOM4/
SSEG4
PD5/CTP1/
KEY14/SCOM5/
SSEG5
PD6/CTP1B/
KEY15/SSEG6
PD7/CTCK1/
KEY16/SSEG7
PE0/PTP1I/
PTP1/KEY17/
SSEG8
PE1/PTP1I/
PTP1B/KEY18/
SSEG9
Rev. 1.10
Function
OPT
I/T
O/T
PD2
PDPU
PDS0
Description
ST
CMOS
KEY11
PDS0
AN
—
SCOM2
PDS0
—
CMOS
Software LCD COM output
SSEG2
PDS0
—
CMOS
Software LCD SEG output
PD3
PDPU
PDS0
ST
CMOS
General purpose I/O. Register enabled pull-up.
General purpose I/O. Register enabled pull-up.
Touch key input
KEY12
PDS0
AN
—
SCOM3
PDS0
—
CMOS
Touch key input
Software LCD COM output
SSEG3
PDS0
—
CMOS
Software LCD SEG output
PD4
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTCK1
PDS1
ST
—
PTM1 clock input
KEY13
PDS1
AN
—
Touch key input
SCOM4
PDS1
—
CMOS
Software LCD COM output
SSEG4
PDS1
—
CMOS
Software LCD SEG output
PD5
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTP1
PDPU
PDS1
—
CMOS
CTM1 output
Touch key input
KEY14
PDS1
AN
—
SCOM5
PDS1
—
CMOS
Software LCD COM output
SSEG5
PDS1
—
CMOS
Software LCD SEG output
PD6
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
CTM1 inverted output
CTP1B
PDS1
—
CMOS
KEY15
PDS1
AN
—
SSEG6
PDS1
—
CMOS
Software LCD SEG output
PD7
PDPU
PDS1
ST
CMOS
General purpose I/O. Register enabled pull-up.
Touch key input
CTCK1
PDS1
ST
—
CTM1 clock input
KEY16
PDS1
AN
—
Touch key input
SSEG7
PDS1
—
CMOS
Software LCD SEG output
PE0
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP1I
PES0
IFS
ST
—
PTM1 capture input
PTP1
PES0
—
CMOS
KEY17
PES0
AN
—
SSEG8
PES0
—
CMOS
Software LCD SEG output
PE1
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
PTP1I
PES0
IFS
ST
—
PTP1B
PES0
—
CMOS
KEY18
PES0
AN
—
SSEG9
PES0
—
CMOS
27
PTM1 output
Touch key input
PTM1 capture input
PTM1 inverted output
Touch key input
Software LCD SEG output
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pad Name
PE2/STPI/STP/
KEY19/SSEG10
PE3/STPI/STPB/
KEY20/SSEG11
PE4/OSC1/AN4/
SSEG12
PE5/OSC2/AN5/
SSEG13
PE6/XT1/
SSEG14
PE7/XT2/
SSEG15
SP+
SP-
Function
OPT
I/T
O/T
PE2
PEPU
PES0
ST
CMOS
STPI
PES0
IFS
ST
—
Description
General purpose I/O. Register enabled pull-up.
STM capture input
STP
PES0
—
CMOS
KEY19
PES0
AN
—
STM output
SSEG10
PES0
—
CMOS
Software LCD SEG output
PE3
PEPU
PES0
ST
CMOS
General purpose I/O. Register enabled pull-up.
STPI
PES0
IFS
ST
—
Touch key input
STM capture input
STPB
PES0
—
CMOS
KEY20
PES0
AN
—
STM inverted output
SSEG11
PES0
—
CMOS
Software LCD SEG output
PE4
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
OSC1
PES1
HXT
—
HXT oscillator pin
AN4
PES1
AN
—
A/D Converter analog input
SSEG12
PES1
—
CMOS
Software LCD SEG output
PE5
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
OSC2
PES1
—
HXT
AN5
PES1
AN
—
A/D Converter analog input
SSEG13
PES1
—
CMOS
Software LCD SEG output
PE6
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
Touch key input
HXT oscillator pin
XT1
PES1
LXT
—
SSEG14
PES1
—
CMOS
LXT oscillator pin
Software LCD SEG output
PE7
PEPU
PES1
ST
CMOS
General purpose I/O. Register enabled pull-up.
XT2
PES1
—
LXT
SSEG15
PES1
—
CMOS
LXT oscillator pin
SP+
—
—
AN
Power amplifier output
Software LCD SEG output
SP-
—
—
AN
Power amplifier output
AUD_IN
—
AN
—
Power amplifier input
BIAS
BIAS
—
—
AN
Power amplifier voltage bias reference
AUD
AUD
—
—
AN
D/A converter output
AVDD_PA
AVDD_PA
—
PWR
—
Audio power amplifier positive power supply
AVSS_PA
AUD_IN
AVSS_PA
—
PWR
—
Audio power amplifier negative power supply
VDD
VDD
—
PWR
—
Positive power supply
VSS
VSS
—
PWR
—
Negative power supply, ground.
Legend: I/T: Input type;
O/T: Output type;
PWR: Power;
AN: Analog signal;
CMOS: CMOS output;
NMOS: NMOS output;
HXT: High frequency crystal oscillator;
Rev. 1.10
28
OPT: Optional by register option;
ST: Schmitt Trigger input;
LXT: Low frequency crystal oscillator
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
IOL Total...................................................................................................................................... 80mA
IOH Total.....................................................................................................................................-80mA
Total Power Dissipation.......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.
D.C. Characteristics
Ta=25°C
Symbol
Parameter
Operating Voltage (HXT)
Test Conditions
—
VDD
Operating Voltage (HIRC)
—
3V
5V
3V
Operating Current (HXT)
5V
3V
5V
5V
3V
IDD
5V
Operating Current (HIRC)
3V
5V
5V
Operating Current (LXT)
Operating Current (LIRC)
Rev. 1.10
Conditions
VDD
3V
5V
3V
5V
Min.
Typ.
Max.
Unit
fSYS=8MHz
2.2
—
5.5
V
fSYS=12MHz
2.7
—
5.5
V
fSYS=16MHz
3.3
—
5.5
V
fSYS=8MHz
2.2
—
5.5
V
fSYS=12MHz
2.7
—
5.5
V
fSYS=16MHz
3.3
—
5.5
V
fSYS=fH=4MHz
No load, all peripherals off
—
0.5
0.75
mA
—
1.0
1.5
mA
fSYS=fH=8MHz
No load, all peripherals off
—
1.0
1.5
mA
—
2.0
3.0
mA
fSYS=fH=12MHz
No load, all peripherals off
—
1.5
2.75
mA
—
3.0
4.5
mA
—
4
6
mA
fSYS=fH=8MHz
No load, all peripherals off
—
0.8
1.2
mA
—
1.6
2.4
mA
fSYS=fH=12MHz
No load, all peripherals off
—
1.2
1.8
mA
—
2.4
3.6
mA
—
3.2
4.8
mA
fSYS=fSUB=fLXT=32.768kHz
No load, all peripherals off
—
10
20
μA
—
30
50
μA
fSYS=fSUB=fLIRC=32kHz
No load, all peripherals off
—
10
20
μA
—
30
50
μA
fSYS=fH=16MHz, no load, all
peripherals off
fSYS=fH=16MHz, no load, all
peripherals off
29
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Symbol
Parameter
Standby Current (SLEEP
Mode)
Standby Current (IDLE0 Mode)
Test Conditions
3V
5V
3V
5V
3V
5V
3V
ISTB
Standby Current (IDLE1 Mode)
Min.
Typ.
Max.
Unit
fSYS off, fSUB off, No load, all
peripherals off, WDT enabled
—
1.5
3
μA
—
3
5
μA
fSYS off, fSUB on, No load, all
peripherals off, WDT enabled
—
3
5
μA
—
5
10
μA
fSYS= fHXT= 4MHz on, fSUB on
No load, all peripherals off,
WDT enabled
—
180
250
μA
—
400
600
μA
fSYS=fHXT or fHIRC=8MHz on,
fSUB on, No load, all peripherals
off, WDT enabled
—
360
500
μA
—
600
800
μA
fSYS=fHXT or fHIRC=12MHz on,
fSUB on, No load, all peripherals
off, WDT enabled
—
540
750
μA
—
800
1200
μA
—
1.4
2.0
mA
Conditions
VDD
5V
3V
5V
5V
fSYS=fHXT or fHIRC=16MHz on,
fSUB on, No load, all peripherals
off, WDT enabled
Input Low Voltage for I/O Ports
or Input Pins
5V
—
0
—
1.5
V
—
—
0
—
0.2VDD
V
VIH
Input High Voltage for I/O Ports
or Input Pins
5V
—
3.5
—
5.0
V
—
—
0.8VDD
—
VDD
V
IOL
Sink Current for I/O Pins
16
32
—
mA
32
65
—
mA
VOH=0.9VDD, PxPS[n+1:n]=00,
x=A, B, C, D or E, n=0, 2, 4 or 6
-0.7
-1.5
—
mA
-1.5
-2.9
—
mA
VOH=0.9VDD, PxPS[n+1:n]=01,
x=A, B, C, D or E, n=0, 2, 4 or 6
-1.3
-2.5
—
mA
-2.5
-5.1
—
mA
VOH=0.9VDD, PxPS[n+1:n]=10,
x=A, B, C, D or E, n=0, 2, 4 or 6
-1.8
-3.6
—
mA
-3.6
-7.3
—
mA
VOH=0.9VDD, PxPS[n+1:n]=11,
x=A, B, C, D or E, n=0, 2, 4 or 6
-4
-8
—
mA
5V
-8
-16
—
mA
3V
IOL=17mA
—
—
0.3
V
5V
IOL=34mA
—
—
0.5
V
V
VIL
3V
5V
3V
5V
3V
IOH
Source Current for I/O Pins
5V
3V
5V
3V
VOL=0.1VDD
VOL
Output low voltage for I/O ports
VOH
Output high voltage for I/O
ports
3V
IOL=5.5mA
2.7
—
—
5V
IOL=11mA
4.5
—
—
V
RPH
Pull-high Resistance for I/O
Ports
3V
—
20
60
100
kΩ
—
10
30
50
kΩ
ILEAK
Input leakage current
5V
—
—
±1
μA
VDR
RAM data retention voltage
—
1.0
—
—
V
Rev. 1.10
5V
VIN=VDD or VIN=VSS
—
30
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
A.C. Characteristics
Ta=25°C
Symbol
Parameter
System Clock (HXT)
fSYS
System Clock (HIRC)
Test Condition
VDD
Condition
Min.
Typ.
Max. Unit
2.2~5.5V fSYS=fHXT=8MHz
—
8
—
MHz
2.7~5.5V fSYS=fHXT=12MHz
—
12
—
MHz
3.3~5.5V fSYS=fHXT=16MHz
—
16
—
MHz
2.2~5.5V fSYS=fHIRC=8MHz
—
8
—
MHz
2.7~5.5V fSYS=fHIRC=12MHz
—
12
—
MHz
3.3~5.5V fSYS=fHIRC=16MHz
—
16
—
MHz
System Clock (LXT)
2.2~5.5V fSYS=fLXT=32.768kHz
—
32.768
—
kHz
System Clock (LIRC)
2.2~5.5V fSYS=fLIRC=32kHz
—
32
—
kHz
tTPI
STPI, PTPnI pin Minimum Input
Pulse Width
—
—
0.3
—
—
μs
tTCK
CTCKn, STCK, PTCKn pin
Minimum Input Pulse Width
—
—
0.3
—
—
μs
tINT
Interrupt Pin Minimum Input Pulse
Width
—
—
10
—
—
μs
tSST
System Start-up Timer Period
(Wake-up from power down mode
and fSYS off)
—
fSYS=fH=fHXT~fHXT/64
128
—
—
tHXT
—
fSYS=fH=fHIRC~fHIRC/64
16
—
—
tHIRC
—
fSYS=fSUB=fLXT
1024
—
—
tLXT
—
fSYS=fSUB=fLIRC
2
—
—
tLIRC
System Start-up Timer Period
(Wake-up from power down mode
and fSYS on)
—
fSYS=fH~fH/64, fH=fHXT or fHIRC
2
—
—
tH
—
fSYS=fSUB=fLXT or fLIRC
2
—
—
tSUB
—
fHXT off → on (HXTF=1)
1024
—
—
tHXT
—
fHIRC off → on (HIRCF=1)
16
—
—
tHIRC
—
fLXT off → on (LXTF=1)
1024
—
—
tLXT
System Start-up Timer period
(SLOW mode → NORMAL mode)
(NORMAL mode → SLOW mode)
System Start-up Timer period
(WDT hardware reset)
—
—
0
—
—
tSYS
System Reset Delay Time
(Power-on reset, LVR hardware
reset, LVRC/WDTC/RSTC software
reset)
—
—
25
50
100
ms
System Reset Delay Time
(WDT hardware reset)
—
—
8.3
16.7
33.3
ms
tEERD
EEPROM Read Time
—
—
—
—
4
tSYS
tEEWR
EEPROM Write Time
—
—
—
2
4
ms
tRSTD
System Frequency for I2C Standard
Mode (100kHz)
fI2C
System Frequency for I2C Fast
Mode (400kHz)
—
No clock debounce
2
—
—
MHz
—
2 system clocks debounce
4
—
—
MHz
—
4 system clocks debounce
8
—
—
MHz
—
No clock debounce
5
—
—
MHz
—
2 system clocks debounce
10
—
—
MHz
—
4 system clocks debounce
20
—
—
MHz
Note: tSYS=1/fSYS
Rev. 1.10
31
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
High Speed Internal Oscillator Frequency Accuracy
Ta=25°C
Trim 8MHz at VDD=3V
Symbol
Parameter
Test Conditions
3V
High Speed Internal RC Oscillator
(HIRC)
fHIRC
Conditions
VDD
Ta=25°C
Min.
Typ.
Max.
Unit
-1%
8
+1%
MHz
-1.5%
8
+1.5%
MHz
Ta= -40°C to 85°C
-2%
8
+2%
MHz
2.2V~5.5V Ta= -40°C to 85°C
-3%
8
+3%
MHz
-20%
12
+20%
MHz
Min.
Typ.
Max.
Unit
2.2V~5.5V Ta=25°C
3V
3V
Ta=25°C
Trim 8MHz at VDD=5V
Symbol
Parameter
Test Conditions
Conditions
VDD
5V
Ta=25°C
2.2V~5.5V Ta=25°C
5V
Ta= -40°C to 85°C
High Speed Internal RC Oscillator
(HIRC)
2.2V~5.5V Ta= -40°C to 85°C
fHIRC
-1%
8
+1%
MHz
-1.5%
8
+1.5%
MHz
-2%
8
+2%
MHz
-3%
8
+3%
MHz
5V
Ta=25°C
-20%
12
+20%
MHz
5V
Ta=25°C
-20%
16
+20%
MHz
Min.
Typ.
Max.
Unit
Trim 12MHz at VDD=3V
Symbol
Parameter
Test Conditions
3V
High Speed Internal RC Oscillator
(HIRC)
fHIRC
Conditions
VDD
Ta=25°C
-1%
12
+1%
MHz
-1.5%
12
+1.5%
MHz
Ta= -40°C to 85°C
-2%
12
+2%
MHz
2.7V~5.5V Ta= -40°C to 85°C
-3%
12
+3%
MHz
-20%
8
+20%
MHz
Min.
Typ.
Max.
Unit
2.7V~5.5V Ta=25°C
3V
3V
Ta=25°C
Trim 12MHz at VDD=5V
Symbol
Parameter
Test Conditions
Conditions
VDD
5V
Ta=25°C
2.7V~5.5V Ta=25°C
5V
Ta= -40°C to 85°C
High Speed Internal RC Oscillator
(HIRC)
2.7V~5.5V Ta= -40°C to 85°C
fHIRC
-1%
12
+1%
MHz
-1.5%
12
+1.5%
MHz
-2%
12
+2%
MHz
-3%
12
+3%
MHz
5V
Ta=25°C
-20%
8
+20%
MHz
5V
Ta=25°C
-20%
16
+20%
MHz
Min.
Typ.
Max.
Unit
Trim 16MHz at VDD=5V
Symbol
Parameter
Test Conditions
Conditions
VDD
5V
Ta=25°C
3.3V~5.5V Ta=25°C
fHIRC
Rev. 1.10
5V
Ta= -40°C to 85°C
High Speed Internal RC Oscillator
(HIRC)
3.3V~5.5V Ta= -40°C to 85°C
-1%
16
+1%
MHz
-1.5%
16
+1.5%
MHz
-2%
16
+2%
MHz
-3%
16
+3%
MHz
5V
Ta=25°C
-20%
8
+20%
MHz
5V
Ta=25°C
-20%
12
+20%
MHz
32
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Low Speed Internal Oscillator Frequency Characteristics
Ta=25°C
Symbol
fLIRC
Parameter
Low Speed Internal RC Oscillator
(LIRC)
Duty Cycle Duty Cycle
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
5V
Ta=25°C
-10%
32
+10%
kHz
5V
Ta= -40°C to 85°C
-40%
32
+40%
kHz
2.2V~5.5V Ta= -40°C to 85°C
-50%
32
+60%
kHz
10
—
90
%
—
—
Low Speed Crystal Oscillator Characteristics
Ta=25°C
Symbol
Parameter
fLXT
Low Speed Crystal Oscillator (LXT)
RNEG
Negative Resistance *
Test Conditions
Conditions
VDD
2.2~5.5V
2.2V
Min.
Typ.
—
32.768
—
kHz
3*ESR
—
—
Ω
fSYS=fLXT=32.768kHz
—
Max. Unit
*: C1, C2 and RP are external components. C1=C2=10pF. RP=10MΩ. CL=7pF. ESR=30kΩ.
A/D Converter Characteristics
Operating Temperature: -40°C~85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Conditions
VDD
Min. Typ. Max. Unit
VDD
Operating Voltage
—
—
2.7
—
5.5
V
VADI
Input Voltage
—
—
0
—
VREF
V
VREF
Reference Voltage
—
—
2
—
VDD
V
VREF=VDD, tADCK=0.5μs or 10μs
—
—
±3
LSB
VREF=VDD, tADCK=0.5μs or 10μs
—
—
±4
LSB
—
1.0
2.0
mA
—
1.5
3.0
mA
μs
DNL
Differential Non-linearity
INL
Integral Non-linearity
IADC
Additional Current Consumption
for A/D Converter Enable
tADCK
Clock Period
3V
5V
3V
5V
3V
5V
No load, tADCK=0.5μs
—
AN≠Temperature sensor output
0.5
—
10
—
AN=Temperature sensor output
1
—
2
μs
tADC
Conversion Time
(Including A/D Sample and Hold Time)
—
AN≠Temperature sensor output
—
16
—
tADCK
—
AN=Temperature sensor output
—
56
—
tADCK
tON2ST
A/D Converter On-to-Start Time
—
—
4
—
—
μs
Rev. 1.10
33
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Temperature Sensor Electrical Characteristics
Ta=25°C, Operating Temperature: -40°C~85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
VDD
Conditions
—
Min. Typ. Max. Unit
VDD
Operating Voltage
—
VTSVREF
Temperature Sensor Reference
Voltage
3V Ta=25°C, Trim @VDD=3V,
5V K_VPTAT=0, K_REFO=0
-5%
3V Ta=25°C, VREF=VTSVREF, G5XEN=1,
5V AN=Temperature sensor output
1990 2250 2600 LSB
3V Ta=90°C, VREF=VTSVREF, G5XEN=1,
5V AN=Temperature sensor output
3400 3850 4250 LSB
3V Ta= -40°C, VREF=VTSVREF, G5XEN=1,
5V AN=Temperature sensor output
550
720
995
LSB
—
—
5
μs
CodeTS
tTSS
A/D Conversion Code Range
Temperature Sensor Turn on
Stable Time
3V
2.7
—
5V
—
5.5
2.01 +5%
V
V
LVD/LVR Electrical Characteristics
Ta=25°C
Symbol
VLVR
VLVD
Parameter
Low Voltage Reset Voltage
Low Voltage Detector Voltage
Test Conditions
VDD
—
—
Conditions
Min.
LVR Enable, voltage select 2.1V
2.1
LVR Enable, voltage select 2.55V
2.55
LVR Enable, voltage select 3.15V
- 5%
Bandgap Reference Voltage
IOP
LVD/LVR Operating Current
tBGS
VBG Turn on Stable Time
tLVDS
3.15
LVR Enable, voltage select 3.8V
3.8
LVD Enable, voltage select 2.0V
2.0
LVD Enable, voltage select 2.2V
2.2
LVD Enable, voltage select 2.4V
2.4
LVD Enable, voltage select 2.7V
LVD Enable, voltage select 3.0V
- 5%
2.7
3.0
LVD Enable, voltage select 3.3V
3.3
LVD Enable, voltage select 3.6V
3.6
LVD Enable, voltage select 4.0V
VBG
Typ.
—
—
Max.
Unit
+ 5%
V
+ 5%
V
+ 5%
V
4.0
- 5%
1.04
5V
LVD/LVR Enable, VBGEN=0
—
20
25
μA
5V
LVD/LVR Enable, VBGEN=1
—
180
200
μA
—
No load
—
—
150
μs
—
For LVR enable, VBGEN=0,
LVD off → on
—
—
15
μs
—
For LVR disable, VBGEN=0,
LVD off → on
—
—
150
μs
LVDO stable time
tLVR
Minimum Low Voltage Width to
Reset
—
—
120
240
480
μs
tLVD
Minimum Low Voltage Width to
Interrupt
—
—
60
120
240
μs
Rev. 1.10
34
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Touch Key Electrical Characteristics
Ta=25°C
Touch Key RC Oscillator 500kHz Mode Selected
Symbol
Parameter
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
IREFOSC
Only Reference Oscillator
Operating Current
Test Conditions
VDD
3V
5V
3V
5V
3V
5V
Conditions
*fSENOSC=500kHz
*fREFOSC=500kHz, MnTSS=0
*fREFOSC=500kHz, MnTSS=1
Min.
Typ. Max. Unit
—
30
60
—
60
120
—
30
60
—
60
120
—
30
60
—
60
120
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator
External Capacitor
3V
*fSENOSC=500kHz
3
10
30
pF
5V
*fSENOSC=500kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal
Capacitor
3V
*fREFOSC=500kHz
3
10
30
pF
5V
*fREFOSC=500kHz
5
10
20
pF
fKEYOSC
Sensor (KEY) Oscillator
Operating Frequency
3V
*CEXT=7, 8, 9, 10, 11, 12, 13, … 50pF 100
500
1000
kHz
5V
*CEXT=7, 8, 9, 10, 11, 12, 13, … 50pF 100
500
1000
kHz
Reference Oscillator Operating
Frequency
3V
*CEXT=7, 8, 9, 10, 11, 12, 13, … 50pF 100
500
1000
kHz
5V
*CEXT=7, 8, 9, 10, 11, 12, 13, … 50pF 100
500
1000
kHz
fREFOSC
Note: 1. fSENOSC = 500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 500kHz.
2. fREFOSC = 500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 500kHz.
Touch Key RC Oscillator 1000kHz Mode Selected
Symbol
Parameter
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
IREFOSC
Only Reference Oscillator
Operating Current
Test Conditions
VDD
3V
5V
3V
5V
3V
5V
Conditions
*fSENOSC=1000kHz
*fREFOSC=1000kHz, MnTSS=0
*fREFOSC=1000kHz, MnTSS=1
Min.
Typ. Max. Unit
—
40
80
—
80
160
—
40
80
—
80
160
—
40
80
—
80
160
μA
μA
μA
CKEYOSC
Sensor (KEY) Oscillator
External Capacitor
3V
*fSENOSC=1000kHz
3
10
25
pF
5V
*fSENOSC=1000kHz
5
10
20
pF
CREFOSC
Reference Oscillator Internal
Capacitor
3V
*fREFOSC=1000kHz
3
10
25
pF
5V
*fREFOSC=1000kHz
5
10
20
fKEYOSC
Sensor (KEY) Oscillator
Operating Frequency
3V
*CEXT=3, 4, 5, 6, 7, 8, 9, 10, … , 50pF
150
1000 2000
kHz
5V
*CEXT=3, 4, 5, 6, 7, 8, 9, 10, … , 50pF
150
1000 2000
kHz
Reference Oscillator Operating
Frequency
3V
*CEXT=3, 4, 5, 6, 7, 8, 9, 10, … , 50pF
150
1000 2000
kHz
5V
*CEXT=3, 4, 5, 6, 7, 8, 9, 10, … , 50pF
150
1000 2000
kHz
fREFOSC
pF
Note: 1. fSENOSC = 1000kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 1000kHz.
2. fREFOSC = 1000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 1000kHz.
Rev. 1.10
35
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Touch Key RC Oscillator 1500kHz Mode Selected
Symbol
Parameter
Only Sensor (KEY) Oscillator
Operating Current
IKEYOSC
Test Conditions
VDD
3V
5V
3V
Only Reference Oscillator
Operating Current
IREFOSC
5V
3V
5V
CKEYOSC
Sensor (KEY) Oscillator External
Capacitor
3V
CREFOSC
Reference Oscillator Internal
Capacitor
3V
fKEYOSC
Sensor (KEY) Oscillator
Operating Frequency
3V
Reference Oscillator Operating
Frequency
3V
fREFOSC
5V
5V
5V
5V
Conditions
*fSENOSC=1500kHz
*fREFOSC=1500kHz, MnTSS=0
*fREFOSC=1500kHz, MnTSS=1
*fSENOSC=1500kHz
*fREFOSC=1500kHz
*CEXT=3, 4, 5, 6, 7, 8, … , 50pF
*CINT=3, 4, 5, 6, 7, 8, … , 50pF
Min.
Typ.
Max.
Unit
—
60
120
—
120
240
—
60
120
—
120
240
—
60
120
—
120
240
4
8
20
pF
5
10
20
pF
4
8
20
pF
5
10
20
pF
150
1500
3000
kHz
150
1500
3000
kHz
150
1500
3000
kHz
150
1500
3000
kHz
μA
μA
μA
Note: 1. fSENOSC = 1500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 1500kHz.
2. fREFOSC = 1500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 1500kHz.
Touch Key RC Oscillator 2000kHz Mode selected
Symbol
Parameter
IKEYOSC
Only Sensor (KEY) Oscillator
Operating Current
IREFOSC
Only Reference Oscillator
Operating Current
Test Conditions
VDD
3V
5V
3V
5V
3V
5V
CKEYOSC
Sensor (KEY) Oscillator External
Capacitor
3V
CREFOSC
Reference Oscillator Internal
Capacitor
3V
fKEYOSC
Sensor (KEY) Oscillator
Operating Frequency
3V
Reference Oscillator Operating
Frequency
3V
fREFOSC
5V
5V
5V
5V
Conditions
*fSENOSC=2000kHz
*fREFOSC=2000kHz, MnTSS=0
*fREFOSC=2000kHz, MnTSS=1
*fSENOSC=2000kHz
*fREFOSC=2000kHz
*CEXT=3, 4, 5, 6, 7, 8, … , 50pF
*CINT=3, 4, 5, 6, 7, 8, … , 50pF
Min.
Typ.
Max.
Unit
—
80
160
—
160
320
—
80
160
—
160
320
—
80
160
—
160
320
4
8
20
pF
5
10
20
pF
4
8
20
pF
5
10
20
pF
150
2000
4000
kHz
150
2000
4000
kHz
150
2000
4000
kHz
150
2000
4000
kHz
μA
μA
μA
Note: 1. fSENOSC = 2000kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is
equal to 2000kHz.
2. fREFOSC = 2000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator
frequency is equal to 2000kHz.
Rev. 1.10
36
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Software LCD Electrical Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
3V
5V
3V
IBIAS
LCD Bias Current
5V
3V
5V
3V
5V
Conditions
ISEL[1:0]=00
ISEL[1:0]=01
ISEL[1:0]=10
ISEL[1:0]=11
Min.
Typ.
Max.
Unit
3.2
6.4
9.6
μA
4.2
8.3
13
μA
5.3
10.5
16
μA
8.3
16.7
25
μA
15.4
30.9
46.4
μA
25
50
75
μA
30.4
60.8
91.2
μA
50
100
150
μA
VSCOM_L
LCD COM 1/3 Bias Level Output
—
No load
0.3135VDD
0.33VDD
0.3465VDD
V
VSCOM_H
LCD COM 2/3 Bias Level Output
—
No load
0.627VDD
0.66VDD
0.693VDD
V
VSSEG_L
LCD SEG 1/3 Bias Level Output
—
No load
0.3135VDD
0.33VDD
0.3465VDD
V
VSSEG_H
LCD SEG 2/3 Bias Level Output
—
No load
0.627VDD
0.66VDD
0.693VDD
V
Audio D/A Converter Electrical Characteristics
Ta=25°C
Symbol
VDD
Parameter
Operating Voltage
(THD+N)/S (THD+N)/S(Note)
Test Conditions
VDD
Conditions
—
—
Min.
Typ.
Max.
Unit
2.2
—
5.5
V
3V
10kΩ load
—
-50
—
dB
5V
10kΩ load
—
-55
—
dB
Note: sine wave input @ 1kHz, -6dB.
Power Amplifier Electrical Characteristics
Ta=25°C
Symbol
AVDD_PA
Parameter
Audio Power Amplifier Operating
Voltage
(THD+N)/S (THD+N)/S(Note)
Test Conditions
Typ.
Max.
Unit
2.2
—
5.5
V
8Ω load,
Output power= 500mW
—
0.2
—
%
8Ω Load, (THD+N)/S=1%
—
410
—
mW
8Ω Load, (THD+N)/S=10%
—
550
—
mW
8Ω Load, (THD+N)/S=1%
—
1200
—
mW
8Ω Load, (THD+N)/S=10%
—
1500
—
mW
Conditions
—
—
5V
3V
POUT
Min.
VDD
Output Power
5V
Note: sine wave input @ 1kHz, -6dB.
Rev. 1.10
37
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Power-on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
—
—
—
100
mV
RRPOR
VDD Rising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to
Ensure Power-on Reset
—
—
1
—
—
ms
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set
operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplified by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O and A/D control system with maximum reliability and flexibility. This makes these
devices suitable for low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided
into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented
at the beginning of the T1 clock during which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock
cycle forms one instruction cycle. Although the fetching and execution of instructions takes place
in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that
instructions are effectively executed in one instruction cycle. The exception to this are instructions
where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
Rev. 1.10
38
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU


 
 
  
System Clocking and Pipelining
     
  
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. For the device whose memory capacity is greater than 8K
words the Program Memory address may be located in a certain program memory bank which is
selected by the program memory bank pointer bit, PMBP0. Only the lower 8 bits, known as the
Program Counter Low Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading
the required address into the Program Counter. For conditional skip instructions, once the condition
has been met, the next instruction, which has already been fetched during the present instruction
execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Program Counter
Device
High Byte
Low Byte (PCL)
BS66FV340
PC11~PC8
PC7~PC0
BS66FV350
PC12~PC8
PC7~PC0
BS66FV360
PBP0, PC12~PC8
PC7~PC0
Program Counter
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly; however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Rev. 1.10
39
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack has multiple levels and is neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
If the stack is overflow, the first Program Counter save in the stack will be lost.
P�og�a� Counte�
Top of Sta�k
Sta�k Level 1
Sta�k Level �
Sta�k
Pointe�
Sta�k Level 3
Botto� of Sta�k
Sta�k Level N
:
:
:
P�og�a� Me�o�y
Note: N=8 for BS66FV340/BS66FV350 while N=12 for BS66FV360
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations:
ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA
• Logic operations:
AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA
• Rotation:
RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC
• Increment and Decrement:
INCA, INC, DECA, DEC
LINCA, LINC, LDECA, LDEC
• Branch decision:
JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA
Rev. 1.10
40
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For these devices
series the Program Memory are Flash type, which means it can be programmed and re-programmed
a large number of times, allowing the user the convenience of code modification on the same
device. By using the appropriate programming tools, these Flash devices offer users the flexibility to
conveniently debug and develop their applications while also offering a means of field programming
and updating.
Device
Capacity
Banks
BS66FV340
4K x 16
—
BS66FV350
8K x 16
—
BS66FV360
16K x 16
0~1
Structure
The Program Memory has a capacity of 4K×16 to 16K×16 bits. The Program Memory is addressed
by the Program Counter and also contains data, table information and interrupt entries. Table data,
which can be setup in any location within the Program Memory, is addressed by a separate table
pointer registers.
000H
BS66FV340
BS66FV350
BS66FV360
Initialisation Ve�to�
Initialisation Ve�to�
Initialisation Ve�to�
Inte��upt Ve�to�s
Inte��upt Ve�to�s
Inte��upt Ve�to�s
Look-up Ta�le
Look-up Ta�le
Look-up Ta�le
1� �its
1� �its
004H
0�CH
n00H
nFFH
FFFH
1� �its
1FFFH
�000H
Bank 1
3FFFH
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by these devices reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Rev. 1.10
41
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the "TABRD [m]" or "TABRDL [m]" instructions respectively when the memory [m] is located in
sector 0. If the memory [m] is located in other sectors except sector 0, the data can be retrieved from
the program memory using the corresponding extended table read instruction such as "LTABRD [m]"
or "LTABRDL [m]" respectively. When the instruction is executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified
in the instruction. The higher order table data byte from the Program Memory will be transferred to
the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0".
The accompanying diagram illustrates the addressing data flow of the look-up table.
Program Memory
Add�ess
Last Page o�
TBHP Registe�
TBLP Registe�
Data
1� �its
Registe� TBLH
Use� Sele�ted
Registe�
High Byte
Low Byte
Table Program Example
The accompanying example shows how the table pointer and table data is defined and retrieved from
the device. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is "0F00H" which refers to the start address of
the last page within the 4K Program Memory of the device. The table pointer low byte register is
setup here to have an initial value of "06H". This will ensure that the first data read from the data
table will be at the Program Memory address "0F06H" or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address of the present page pointed
by the TBHP register if the "TABRD [m]" instruction is being used. The high byte of the table data
which in this case is equal to zero will be transferred to the TBLH register automatically when the
"TABRD [m] instruction is executed.
Because the TBLH register is a read/write register and can be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Rev. 1.10
42
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a ; to the last page or the page that tbhp pointed
mov a,0fh ; initialise high table pointer
mov tbhp,a
:
tabrd
tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address "0F06H" transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd
tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address "0F05H" transferred to tempreg2 and TBLH in this
; example the data "1AH" is transferred to tempreg1 and data "0FH" to
; register tempreg2
:
org 0F00h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
In Circuit Programming – ICP
The provision of Flash type Program Memory provides the user with a means of convenient and
easy upgrades and modifications to their programs on the same device.
As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing
their circuit boards complete with a programmed or un-programmed microcontroller, and then
programming or upgrading the program at a later stage. This enables product manufacturers to easily
keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device.
Holtek Writer Pins
MCU Programming Pins
Pin Description
ICPDA
PA0
Programming Serial Data/Address
ICPCK
PA2
Programming Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
The Program Memory and EEPROM data memory can be programmed serially in-circuit using this
4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line
for the clock. Two additional lines are required for the power supply. The technical details regarding
the in-circuit programming of the device are beyond the scope of this document and will be supplied
in supplementary literature.
During the programming process, the user must take care of the ICPDA and ICPCK pins for data
and clock programming purposes to ensure that no other outputs are connected to these two pins.
Rev. 1.10
43
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
W r ite r C o n n e c to r
S ig n a ls
M C U
W r ite r _ V D D
V D D
IC P D A
P A 0
IC P C K
P A 2
W r ite r _ V S S
V S S
*
P r o g r a m m in g
P in s
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance
of * must be less than 1nF.
On-Chip Debug Support – OCDS
There is an EV chip named BS66VV3x0 which is used to emulate the real MCU device named
BS66FV3x0. The EV chip device also provides the "On-Chip Debug" function to debug the real
MCU device during development process. The EV chip and real MCU devices, BS66VV3x0 and
BS66FV3x0, are almost functional compatible except the "On-Chip Debug" function. Users can
use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA
and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS
Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users
use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA
and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two
OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory
programming pins for ICP. For more detailed OCDS information, refer to the corresponding
document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide".
Holtek e-Link Pins
Rev. 1.10
EV Chip OCDS Pins
Pin Description
OCDSDA
OCDSDA
On-Chip Debug Support Data/Address input/output
OCDSCK
OCDSCK
On-Chip Debug Support Clock input
VDD
VDD
Power Supply
VSS
VSS
Ground
44
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
In Application Programming – IAP
These devices offer IAP function to update data or application program to flash ROM. Users can
define any ROM location for IAP, but there are some features which user must notice in using IAP
function. Note that the BS66FV340 device supports the "Block Erase" function instead of the "Page
Erase" function.
BS66FV340 Configurations
BS66FV350 Configurations
BS66FV360 Configurations
Erase Block
256 words/block
Erase Page
32 words/page
Erase Page
64 words/page
Writing Word
4 words/time
Writing Word
32 words/time
Writing Word
64 words/time
Reading Word
1 word/time
Reading Word
1 word/time
Reading Word
1 word/time
In Application Programming Control Registers
The Address register, FARL and FARH, the Data registers, FD0L/FD0H, FD1L/FD1H, FD2L/FD2H
and FD3L/FD3H, and the Control registers, FC0, FC1 and FC2, are the corresponding Flash access
registers located in Data Memory sector 0 for IAP. If using the indirect addressing method to access
the FC0, FC1 and FC2 registers, all read and write operations to the registers must be performed
using the Indirect Addressing Register, IAR1 or IAR2, and the Memory Pointer pair, MP1L/MP1H
or MP2L/MP2H. Because the FC0, FC1 and FC2 control registers are located at the address of
50H~52H in Data Memory sector 0, the desired value ranged from 50H to 52H must first be written
into the MP1L or MP2L Memory Pointer low byte and the value "00H" must also be written into the
MP1H or MP2H Memory Pointer high byte.
Register
Name
FC0
Bit
7
6
5
4
3
CFWEN FMOD2 FMOD1 FMOD0 FWPEN
2
1
0
FWT
FRDEN
FRD
FC1
D7
D6
D5
D4
D3
D2
D1
D0
FC2
(BS66FV350/360)
—
—
—
—
—
—
—
CLWB
FARL
A7
A6
A5
A4
A3
A2
A1
A0
FARH (BS66FV340)
—
—
—
—
A11
A10
A9
A8
FARH (BS66FV350)
—
—
—
A12
A11
A10
A9
A8
FARH (BS66FV360)
—
—
A13
A12
A11
A10
A9
A8
FD0L
D7
D6
D5
D4
D3
D2
D1
D0
FD0H
D15
D14
D13
D12
D11
D10
D9
D8
D0
FD1L
D7
D6
D5
D4
D3
D2
D1
FD1H
D15
D14
D13
D12
D11
D10
D9
D8
FD2L
D7
D6
D5
D4
D3
D2
D1
D0
FD2H
D15
D14
D13
D12
D11
D10
D9
D8
FD3L
D7
D6
D5
D4
D3
D2
D1
D0
FD3H
D15
D14
D13
D12
D11
D10
D9
D8
IAP Registers List
Rev. 1.10
45
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• FC0 Register
Bit
7
6
5
4
3
2
1
0
Name
CFWEN
FMOD2
FMOD1
FMOD0
FWPEN
FWT
FRDEN
FRD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
1
1
0
0
0
0
Bit 7
CFWEN: Flash Memory Write enable control
0: Flash memory write function is disabled
1: Flash memory write function has been successfully enabled
When this bit is cleared to 0 by application program, the Flash memory write function
is disabled. Note that writing a "1" into this bit results in no action. This bit is used
to indicate that the Flash memory write function status. When this bit is set to 1 by
hardware, it means that the Flash memory write function is enabled successfully.
Otherwise, the Flash memory write function is disabled as the bit content is zero.
Bit 6~4
FMOD2~FMOD0: Mode selection
000: Write program memory
001: Block/Page erase program memory
010: Reserved
011: Read program memory
10x: Reserved
110: FWEN mode – Flash memory Write function Enabled mode
111: Reserved
When these bits are set to "001", the "Block erase" mode is selected for BS66FV340
while the "Page erase" mode is selected for BS66FV350/BS66FV360.
Bit 3
FWPEN: Flash memory Write Procedure Enable control
0: Disable
1: Enable
When this bit is set to 1 and the FMOD field is set to "110", the IAP controller will
execute the "Flash memory write function enable" procedure. Once the Flash memory
write function is successfully enabled, it is not necessary to set the FWPEN bit any
more.
Bit 2
FWT: Flash memory Write Initiate control
0: Do not initiate Flash memory write or Flash memory write process is completed
1: Initiate Flash memory write process
This bit is set by software and cleared by hardware when the Flash memory write
process is completed.
Bit 1
FRDEN: Flash memory Read Enable control
0: Flash memory read disable
1: Flash memory read enable
Bit 0
FRD: Flash memory Read Initiate control
0: Do not initiate Flash memory read or Flash memory read process is completed
1: Initiate Flash memory read process
This bit is set by software and cleared by hardware when the Flash memory read
process is completed.
• FC1 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.10
D7~D0: Whole chip reset pattern
When user writes a specific value of "55H" to this register, it will generate a reset
signal to reset whole chip.
46
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• FC2 Register – BS66FV350/BS66FV360
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
CLWB
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Unimplemented, read as 0.
Bit 0
CLWB: Flash memory Write Buffer Clear control
0: Do not initiate Write Buffer Clear process or Write Buffer Clear process is
completed
1: Initiate Write Buffer Clear process
This bit is set by software and cleared by hardware when the Write Buffer Clear
process is completed.
• FARL Register
Bit
7
6
5
4
3
2
1
0
Name
A7
A6
A5
A4
A3
A2
A1
A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Flash Memory Address bit 7 ~ bit 0
• FARH Register – BS66FV340
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
A11
A10
A9
A8
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as 0.
Bit 3~0
Flash Memory Address bit 11 ~ bit 8
• FARH Register – BS66FV350
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
A12
A11
A10
A9
A8
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7~5
Unimplemented, read as 0.
Bit 4~0
Flash Memory Address bit 12 ~ bit 8
• FARH Register – BS66FV360
Bit
7
6
5
4
3
2
1
0
Name
—
—
A13
A12
A11
A10
A9
A8
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as 0.
Bit 5~0
Flash Memory Address bit 13 ~ bit 8
• FD0L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.10
The first Flash Memory data bit 7 ~ bit 0
47
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• FD0H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The first Flash Memory data bit 15 ~ bit 8
• FD1L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
The second Flash Memory data bit 7 ~ bit 0
• FD1H Register
Bit
7
6
5
4
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The second Flash Memory data bit 15 ~ bit 8
• FD2L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The third Flash Memory data bit 7 ~ bit 0
• FD2H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The third Flash Memory data bit 15 ~ bit 8
• FD3L Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
The fourth Flash Memory data bit 7 ~ bit 0
• FD3H Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.10
The fourth Flash Memory data bit 15 ~ bit 8
48
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Flash Memory Write Function Enable Procedure
In order to allow users to change the Flash memory data through the IAP control registers, users
must first enable the Flash memory write operation by the following procedure:
Step 1. Write "110" into the FMOD2~FMOD0 bits to select the FWEN mode.
Step 2. Set the FWPEN bit to "1". The step 1 and step 2 can be executed simultaneously.
Step 3. The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written
into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively.
Step 4. A counter with a time-out period of 300μs will be activated to allow users writing the correct
pattern data into the FD1L/FD1H ~ FD3L/FD3H register pairs. The counter clock is derived
from LIRC oscillator.
Step 5. If the counter overflows or the pattern data is incorrect, the Flash memory write operation
will not be enabled and users must again repeat the above procedure. Then the FWPEN bit
will automatically be cleared to 0 by hardware.
Step 6. If the pattern data is correct before the counter overflows, the Flash memory write operation
will be enabled and the FWPEN bit will automatically be cleared to 0 by hardware. The
CFWEN bit will also be set to 1 by hardware to indicate that the Flash memory write
operation is successfully enabled.
Step 7. Once the Flash memory write operation is enabled, the user can change the Flash ROM data
through the Flash control register.
Step 8. To disable the Flash memory write operation, the user can clear the CFWEN bit to 0.
Is �ounte�
ove�flow ?
Flash Me�o�y
W�ite Fun�tion
Ena�le P�o�edu�e
No
Yes
FWPEN=0
Set FMOD [�:0] =110 & FWPEN=1
Sele�t FWEN �ode & Sta�t Flash w�ite
Ha�dwa�e a�tivate a �ounte�
Is patte�n
�o��e�t ?
W�tie the following patte�n to Flash Data �egiste�s
FD1L= 00h � FD1H = 04h
FD�L= 0Dh � FD�H = 09h
FD3L= C3h � FD3H = 40h
No
Yes
CFWEN = 1
CFWEN=0
Success
Failed
END
Flash Memory Write Function Enable Procedure
Rev. 1.10
49
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Flash Memory Read/Write Procedure
After the Flash memory write function is successfully enabled through the preceding IAP procedure,
users must first erase the corresponding Flash memory block or page and then initiate the Flash
memory write operation. For the BS66FV340 device the number of the block erase operation is
256 words per block, the available block erase address is only specified by FARH register and
the content in the FARL register is not used to specify the block address. For the BS66FV350
and BS66FV360 devices the number of the page erase operation is 32 and 64 words per page
respectively, the available page erase address is specified by FARH register and the content of FARL
[7:5] and FARL [7:6] bit field respectively.
Erase Block
FARH [3:0]
FARL [7:0]
0
0000
xxxx xxxx
1
0001
xxxx xxxx
2
0010
xxxx xxxx
3
0011
xxxx xxxx
4
0100
xxxx xxxx
5
0101
xxxx xxxx
6
0110
xxxx xxxx
7
0111
xxxx xxxx
8
1000
xxxx xxxx
9
1001
xxxx xxxx
10
1010
xxxx xxxx
11
1011
xxxx xxxx
12
1100
xxxx xxxx
13
1101
xxxx xxxx
14
1110
xxxx xxxx
15
1111
xxxx xxxx
"x": don’t care
BS66FV340 Erase Block Number and Selection
Rev. 1.10
50
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Erase Page
FARH
FARL [7:5]
0
0000 0000
000
FARL [4:0]
x xxxx
1
0000 0000
001
x xxxx
2
0000 0000
010
x xxxx
3
0000 0000
011
x xxxx
4
0000 0000
100
x xxxx
5
0000 0000
101
x xxxx
6
0000 0000
110
x xxxx
7
0000 0000
111
x xxxx
8
0000 0001
000
x xxxx
9
0000 0001
001
x xxxx
:
:
:
:
:
:
:
:
126
0 0 0 0 1111
110
x xxxx
127
0 0 0 0 1111
111
x xxxx
128
0001 0000
000
x xxxx
129
0001 0000
001
x xxxx
:
:
:
:
:
:
:
:
254
0 0 0 1 1111
110
x xxxx
255
0 0 0 1 1111
111
x xxxx
"x": don’t care
BS66FV350 Erase Page Number and Selection
Erase Page
FARH
FARL [7:6]
0
0000 0000
00
FARL [5:0]
xx xxxx
1
0000 0000
01
xx xxxx
2
0000 0000
10
xx xxxx
3
0000 0000
11
xx xxxx
4
0000 0001
00
xx xxxx
5
0000 0001
01
xx xxxx
:
:
:
:
:
:
:
:
126
0 0 0 1 1111
10
xx xxxx
127
0 0 0 1 1111
11
xx xxxx
128
0010 0000
00
xx xxxx
129
0010 0000
01
xx xxxx
:
:
:
:
:
:
:
:
254
0 0 11 1111
10
xx xxxx
255
0 0 11 1111
11
xx xxxx
"x": don’t care
BS66FV360 Erase Page Number and Selection
Rev. 1.10
51
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Read
Flash Me�o�y
Set FMOD [�:0]=011
& FRDEN=1
Set Flash Add�ess �egiste�s
FARH=xxh� FARL=xxh
Set FRD=1
No
FRD=0 ?
Yes
Read data value:
FD0L=xxh� FD0H=xxh
Read Finish ?
No
Yes
Clea� FRDEN �it
END
Read Flash Memory Procedure
Rev. 1.10
52
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
W�ite
Flash Me�o�y
Flash Me�o�y
W�ite Fun�tion
Ena�le P�o�edu�e
Set Blo�k E�ase add�ess: FARH/FARL
Set FMOD [�:0]=001 & FWT=1
Sele�t “Blo�k E�ase �ode”
& Initiate w�ite ope�ation
No
FWT=0 ?
Yes
Set FMOD [�:0]=000
Sele�t “W�ite Flash Mode”
Set W�ite sta�ting add�ess: FARH/FARL
W�ite data to data �egiste�:
FD0L/FD0H� FD1L/FD1H�
FD�L/FD�H� FD3L/FD3H�
Set FWT=1
No
FWT=0 ?
Yes
W�ite Finish ?
No
Yes
Clea� CFWEN=0
END
Write Flash Memory Procedure – BS66FV340
Rev. 1.10
53
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
W�ite
Flash Me�o�y
Flash Me�o�y
W�ite Fun�tion
Ena�le P�o�edu�e
Set Page E�ase add�ess: FARH/FARL
Set FMOD [�:0]=001 & FWT=1
Sele�t “Page E�ase �ode”
& Initiate w�ite ope�ation
No
FWT=0 ?
Yes
Set FMOD [�:0]=000
Sele�t “W�ite Flash Mode”
Set W�ite sta�ting add�ess: FARH/FARL
W�ite data to data �egiste�: FD0L/FD0H
No
Page data
W�ite finish
Yes
Set FWT=1
No
FWT=0 ?
Yes
W�ite Finish ?
No
Yes
Clea� CFWEN=0
END
Write Flash Memory Procedure – BS66FV350/BS66FV360
Note: When the FWT or FRD bit is set to 1, the MCU is stopped.
Rev. 1.10
54
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Data Memory
The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary
information is stored.
Divided into two types, the first of Data Memory is an area of RAM where special function registers
are located. These registers have fixed locations and are necessary for correct operation of the
device. Many of these registers can be read from and written to directly under program control,
however, some remain protected from user manipulation. The second area of Data Memory is
reserved for general purpose use. All locations within this area are read and write accessible under
program control.
Switching between the different Data Memory sectors is achieved by properly setting the Memory
Pointers to correct value.
Structure
The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide
Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data
Memory and the General Purpose Data Memory.
The address range of the Special Purpose Data Memory for the device is from 00H to 7FH. The
General Purpose Data Memory address range is from 80H to FFH except the Touch Key Module
Data Memory. The Touch Key Module Data Memory is located in sector 5 and sector 6 respectively
with a start address of 00H.
Device
Special Purpose
Data Memory
General Purpose
Data Memory
Located Sectors
Touch Key
Module
Data Memory
Capacity
Sector : Address
Sector : Address
5: 00H~27H
6: 00H~27H
BS66FV340
0, 1
512 x 8
0: 80H~FFH
1: 80H~FFH
2: 80H~FFH
3: 80H~FFH
BS66FV350
0, 1
768 x 8
0: 80H~FFH
1: 80H~FFH
:
5: 80H~FFH
5: 00H~2FH
6: 00H~2FH
BS66FV360
0, 1
1024 x 8
0: 80H~FFH
1: 80H~FFH
:
7: 80H~FFH
5: 00H~37H
6: 00H~37H
Data Memory Summary
Rev. 1.10
55
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
00H
Spe�ial Pu�pose
Data Me�o�y
(Se�to� 0 ~ Se�to� 1)
Tou�h Key Module
Data Me�o�y
7FH
80H
(Se�to� �~Se�to� �)
Gene�al Pu�pose
Data Me�o�y
(Se�to� 0 ~ Se�to� N)
FFH
Se�to� 0
Se�to� 1
Se�to� N
Note: N=3 fo� BS�7FV340;
N=� fo� BS�7FV3�0;
N=7 fo� BS�7FV3�0;
Data Memory Structure
Data Memory Addressing
For these devices that support the extended instructions, there is no Bank Pointer for Data Memory.
The Bank Pointer, PBP, is only available for Program Memory. For Data Memory the desired Sector
is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected
sector is specified by the MP1L or MP2L register when using indirect addressing access.
Direct Addressing can be used in all sectors using the corresponding instruction which can address
all available data memory space. For the accessed data memory which is located in any data
memory sectors except sector 0, the extended instructions can be used to access the data memory
instead of using the indirect addressing access. The main difference between standard instructions
and extended instructions is that the data memory address "m" in the extended instructions can be
from 10 bits to 11 bits depending upon which device is selected, the high byte indicates a sector and
the low byte indicates a specific address.
General Purpose Data Memory
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user programming for both
reading and writing operations. By using the bit operation instructions individual bits can be set or
reset under program control giving the user a large range of flexibility for bit manipulation in the
Data Memory.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value "00H".
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
INTEG
SCC
HIRCC
HXTC
LXTC
LVDC
LVRC
WDTC
RSTC
PC
PCC
PCPU
PD
PDC
PDPU
MFI0
MFI1
MFI2
MFI3
SADOL
SADOH
SADC0
SADC1
PSCR0
TB0C
TB1C
SIMC0
SIMC1
SIMA/SIMC2
SIMD
SIMTOC
CTM0C0
CTM0C1
CTM0DL
CTM0DH
CTM0AL
CTM0AH
Sector 1
TKTMR
TKC0
TK16DL
TK16DH
TKC1
TKM016DL
TKM016DH
TKM0ROL
TKM0ROH
TKM0C0
TKM0C1
TKM0C2
TKM116DL
TKM116DH
TKM1ROL
TKM1ROH
TKM1C0
TKM1C1
TKM1C2
TKM216DL
TKM216DH
TKM2ROL
TKM2ROH
TKM2C0
TKM2C1
TKM2C2
TKM316DL
TKM316DH
TKM3ROL
TKM3ROH
TKM3C0
TKM3C1
TKM3C2
TKM416DL
TKM416DH
TKM4ROL
TKM4ROH
TKM4C0
TKM4C1
TKM4C2
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
Sector 0
EEA
EED
PSCR1
SLEDC0
SLEDC1
SLEDC2
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
FC0
FC1
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
STMRP
69H
6AH
6BH
SADC2
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
PE
PEC
PEPU
SPIAC0
SPIAC1
SPIAD
USR
UCR1
UCR2
TXR_RXR
BRG
USVC
PLAC
PLADL
PLADH
Sector 1
EEC
IFS
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
SLCDC0
SLCDC1
: Unused, read as 00H
Special Purpose Data Memory Structure – BS66FV340
Rev. 1.10
57
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
INTEG
SCC
HIRCC
HXTC
LXTC
LVDC
LVRC
WDTC
RSTC
PC
PCC
PCPU
PD
PDC
PDPU
MFI0
MFI1
MFI2
MFI3
SADOL
SADOH
SADC0
SADC1
PSCR0
TB0C
TB1C
SIMC0
SIMC1
SIMA/SIMC2
SIMD
SIMTOC
CTM0C0
CTM0C1
CTM0DL
CTM0DH
CTM0AL
CTM0AH
Sector 1
TKTMR
TKC0
TK16DL
TK16DH
TKC1
TKM016DL
TKM016DH
TKM0ROL
TKM0ROH
TKM0C0
TKM0C1
TKM0C2
TKM116DL
TKM116DH
TKM1ROL
TKM1ROH
TKM1C0
TKM1C1
TKM1C2
TKM216DL
TKM216DH
TKM2ROL
TKM2ROH
TKM2C0
TKM2C1
TKM2C2
TKM316DL
TKM316DH
TKM3ROL
TKM3ROH
TKM3C0
TKM3C1
TKM3C2
TKM416DL
TKM416DH
TKM4ROL
TKM4ROH
TKM4C0
TKM4C1
TKM4C2
TKM516DL
TKM516DH
TKM5ROL
TKM5ROH
TKM5C0
TKM5C1
TKM5C2
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
Sector 0
EEA
EED
PSCR1
SLDEC0
SLDEC1
SLDEC2
PTMC0
PTMC1
PTMDL
PTMDH
PTMAL
PTMAH
PTMRPL
PTMRPH
FC0
FC1
FC2
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
STMRP
CTM1C0
CTM1C1
CTM1DL
CTM1DH
CTM1AL
CTM1AH
SADC2
Sector 1
EEC
IFS
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
SLCDC0
SLCDC1
PE
PEC
PEPU
SPIAC0
SPIAC1
SPIAD
USR
UCR1
UCR2
TXR_RXR
BRG
USVC
PLAC
PLADL
PLADH
: Unused, read as 00H
Special Purpose Data Memory Structure – BS66FV350
Rev. 1.10
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December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Sector 0
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
PBP
IAR2
MP2L
MP2H
RSTFC
INTC0
INTC1
INTC2
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
INTEG
SCC
HIRCC
HXTC
LXTC
LVDC
LVRC
WDTC
RSTC
PC
PCC
PCPU
PD
PDC
PDPU
MFI0
MFI1
MFI2
MFI3
SADOL
SADOH
SADC0
SADC1
PSCR0
TB0C
TB1C
SIMC0
SIMC1
SIMA/SIMC2
SIMD
SIMTOC
CTM0C0
CTM0C1
CTM0DL
CTM0DH
CTM0AL
CTM0AH
Sector 1
TKTMR
TKC0
TK16DL
TK16DH
TKC1
TKM016DL
TKM016DH
TKM0ROL
TKM0ROH
TKM0C0
TKM0C1
TKM0C2
TKM116DL
TKM116DH
TKM1ROL
TKM1ROH
TKM1C0
TKM1C1
TKM1C2
TKM216DL
TKM216DH
TKM2ROL
TKM2ROH
TKM2C0
TKM2C1
TKM2C2
TKM316DL
TKM316DH
TKM3ROL
TKM3ROH
TKM3C0
TKM3C1
TKM3C2
TKM416DL
TKM416DH
TKM4ROL
TKM4ROH
TKM4C0
TKM4C1
TKM4C2
TKM516DL
TKM516DH
TKM5ROL
TKM5ROH
TKM5C0
TKM5C1
TKM5C2
TKM616DL
TKM616DH
TKM6ROL
TKM6ROH
TKM6C0
TKM6C1
TKM6C2
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
Sector 0
EEA
EED
PSCR1
SLEDC0
SLEDC1
SLEDC2
PTM0C0
PTM0C1
PTM0DL
PTM0DH
PTM0AL
PTM0AH
PTM0RPL
PTM0RPH
FC0
FC1
FC2
FARL
FARH
FD0L
FD0H
FD1L
FD1H
FD2L
FD2H
FD3L
FD3H
STMC0
STMC1
STMDL
STMDH
STMAL
STMAH
STMRP
CTM1C0
CTM1C1
CTM1DL
CTM1DH
CTM1AL
CTM1AH
SADC2
Sector 1
EEC
IFS
PAS0
PAS1
PBS0
PBS1
PCS0
PCS1
PDS0
PDS1
PES0
PES1
PTM1C0
PTM1C1
PTM1DL
PTM1DH
PTM1AL
PTM1AH
PTM1RPL
PTM1RPH
SLCDC0
SLCDC1
PE
PEC
PEPU
SPIAC0
SPIAC1
SPIAD
USR
UCR1
UCR2
TXR_RXR
BRG
USVC
PLAC
PLADL
PLADH
: Unused, read as 00H
Special Purpose Data Memory Structure – BS66FV360
Rev. 1.10
59
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section.
However, several registers require a separate description in this section.
Indirect Addressing Registers – IAR0, IAR1, IAR2
The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal
RAM register space, do not actually physically exist as normal registers. The method of indirect
addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers,
in contrast to direct memory addressing, where the actual memory address is specified. Actions on
the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers
but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/
MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector
0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with
MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing
Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will
return a result of "00H" and writing to the registers indirectly will result in no operation.
Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L
Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These
Memory Pointers are physically implemented in the Data Memory and can be manipulated in the
same way as normal registers providing a convenient way with which to address and track data. When
any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the
microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together
with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H
together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors
according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data
sectors using the corresponding instruction which can address all available data memory space.
Indirect Addressing Program Example
• Example 1
data .section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org 00h
start:
mov a,04h ;
mov block,a
mov a,offset adres1 ;
mov mp0,a ;
loop:
clr IAR0 ;
inc mp0;
sdz block ;
jmp loop
continue:
:
Rev. 1.10
setup size of block
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by MP0
increment memory pointer
check if last memory location has been cleared
60
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• Example 2
data .section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ‘code’
org 00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,01h ; setup the memory sector
mov mp1h,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp1l,a ; setup memory pointer with first RAM address
loop:
clr IAR1 ; clear the data at address defined by MP1
inc mp1l ; increment memory pointer MP1L
sdz block ; check if last memory location has been cleared
jmp loop
continue:
:
The important point to note here is that in the example shown above, no reference is made to specific
RAM addresses.
Direct Addressing Program Example using extended instructions
data .section ‘data’
temp db ?
code .section at 0 code
org 00h
start:
lmov a,[m]; move [m] data to acc
lsub a, [m+1] ; compare [m] and [m+1] data
snz c; [m]>[m+1]?
jmp continue; no
lmov a,[m] ; yes, exchange [m] and [m+1] data
mov temp,a
lmov a,[m+1]
lmov [m],a
mov a,temp
lmov [m+1],a
continue:
:
Note: Here "m" is a data memory address located in any data memory sectors. For example,
m=1F0H, it indicates address 0F0H in Sector 1.
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Program Memory Bank Pointer – PBP
For the BS66FV360 device the Program Memory is divided into several banks. Selecting the
required Program Memory area is achieved using the Program Memory Bank Pointer, PBP. The
PBP register should be properly configured before the device executes the "Branch" operation using
the "JMP" or "CALL" instruction. After that a jump to a non-consecutive Program Memory address
which is located in a certain bank selected by the program memory bank pointer bits will occur.
PBP Register – BS66FV360
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
PBP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~1
D7~D1: General data bits and can be read or written.
Bit 0
PBP0: Program Memory Bank Point bit 0
0: Bank 0
1: Bank 1
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location;
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which
is stored in the Program Memory. The TBLP and TBHP registers are the table pointer pair and
indicates the location where the table data is located. Their value must be setup before any table
read commands are executed. Their value can be changed, for example using the "INC" or "DEC"
instructions, allowing for easy table data pointing and reading. TBLH is the location where the high
order byte of the table data is stored after a table read data instruction has been executed. Note that
the lower order table data byte is transferred to a user defined location.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/
logical operation and system management flags are used to record the status and operation of the
microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing
the "HALT" or "CLR WDT" instruction or during a system power-up.
The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by
executing the "HALT" instruction.
• TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is
set by a WDT time-out.
• SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the
current instruction operation result.
• CZ is the operational result of different flags for different instructions. Refer to register
definitions for more details.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
SC
CZ
TO
PDF
OV
Z
AC
C
R/W
R
R
R
R
R/W
R/W
R/W
R/W
POR
x
x
0
0
x
x
x
x
"x": unknown
Rev. 1.10
Bit 7
SC: The result of the "XOR" operation which is performed by the OV flag and the
MSB of the instruction operation result.
Bit 6
CZ: The operational result of different flags for different instructions.
For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag.
For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the "AND" operation
result which is performed by the previous operation CZ flag and current operation zero
flag. For other instructions, the CZ flag will not be affected.
Bit 5
TO: Watchdog Time-out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred
Bit 4
PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3
OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa
Bit 2
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1
AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles, in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0
C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
The "C" flag is also affected by a rotate through carry instruction.
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Enhanced Touch Voice A/D Flash MCU
EEPROM Data Memory
These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for
Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form
of re-programmable memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are made
available to the designer. The availability of EEPROM storage allows information such as product
identification numbers, calibration values, specific user data, system setup data or other product
information to be stored directly within the product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced to a very trivial affair.
Device
BS66FV340
BS66FV350
BS66FV360
Capacity
Address
128 x 8
00H ~ 7FH
256 x 8
00H ~ FFH
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is up to 256×8 bits for the series of devices. Unlike the
Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped
into memory space and is therefore not directly addressable in the same way as the other types of
memory. Read and Write operations to the EEPROM are carried out in single byte operations using
an address and data register in sector 0 and a single control register in sector 1.
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in sector 0, they can be directly accessed in the same was as any other
Special Function Register. The EEC register, however, being located in sector 1, can be read from
or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect
Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H
in sector 1, the Memory Pointer low byte register, MP1L or MP2L, must first be set to the value
40H and the Memory Pointer high byte register, MP1H or MP2H, set to the value, 01H, before any
operations on the EEC register are executed.
Register Name
Bit
7
6
5
4
3
2
1
0
—
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
EEA7
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
EEA
EEA
(for BS66FV360 only)
EEPROM Registers List
EEA Register – BS66FV340/BS66FV350
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0".
Bit 6~0
EEA6~EEA0: Data EEPROM address bit 6 ~ bit0
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Enhanced Touch Voice A/D Flash MCU
EEA Register – BS66FV360
Bit
7
6
5
4
3
2
1
0
Name
EEA7
EEA6
EEA5
EEA4
EEA3
EEA2
EEA1
EEA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
EEA7~EEA0: Data EEPROM address bit 7 ~ bit0
EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
D7~D0: Data EEPROM data bit 7~bit0
EEC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as "0".
Bit 3
WREN: Data EEPROM write enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2
WR: EEPROM write control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1
RDEN: Data EEPROM read enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0
RD: EEPROM read control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The
WR and RD can not be set to "1" at the same time.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM
To write data to the EEPROM, the EEPROM address of the data to be written must first be placed
in the EEA register and the data placed in the EED register. Then the write enable bit, WREN,
in the EEC register must first be set high to enable the write function. After this, the WR bit in
the EEC register must be immediately set high to initiate a write cycle. These two instructions
must be executed consecutively. The global interrupt bit EMI should also first be cleared before
implementing any write operations, and then set again after the write cycle has started. Note that
setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the
EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to
microcontroller system clock, a certain time will elapse before the data will have been written into
the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the
WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates,
the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the
data has been written to the EEPROM. The application program can therefore poll the WR bit to
determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered on, the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be
reset to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control
register is located in sector 1, this adds a further measure of protection against spurious write
operations. During normal program operation, ensuring that the Write Enable bit in the control
register is cleared will safeguard against incorrect write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However, as
the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic
by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory
Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1
where the EEPROM control register exist. Although certainly not necessary, consideration might be
given in the application program to the checking of the validity of new write data by a simple read
back process. When writing data the WR bit must be set high immediately after the WREN bit has
been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also
be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that
the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is
totally complete. Otherwise, the EEPROM read or write operation will fail.
Programming Example
• Reading data from the EEPROM – polling method
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, 040H
MOV MP1L, A
MOV A, 01H
MOV MP1H, A
SET IAR1.1
SET IAR1.0
BACK:
SZ IAR1.0
JMP BACK
CLR IAR1
CLR MP1H
MOV A, EED
MOV READ_DATA, A
; user defined address
; setup memory pointer low byte MP1L
; MP1L points to EEC register
; setup Memory Pointer high byte MP1H
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM write
; move read data to register
• Writing Data to the EEPROM - polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA
MOV EED, A
MOV A, 040H
MOV MP1L, A
MOV A, 01H
MOV MP1H, A
CLR EMI
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ IAR1.2
JMP BACK
CLR IAR1
CLR MP1H
Rev. 1.10
; user defined address
; user defined data
; setup memory pointer low byte MP1L
; MP1L points to EEC register
; setup Memory Pointer high byte MP1H
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM write
68
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Oscillator
Various oscillator types offer the user a wide range of functions according to their various application
requirements. The flexible features of the oscillator functions ensure that the best optimisation can
be achieved in terms of speed and power saving. Oscillator selections and operation are selected
through a combination of application program and relevant control registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external
components as well as fully integrated internal oscillators, requiring no external components, are
provided to form a wide range of both fast and slow system oscillators. All oscillator options are
selected through register programming. The higher frequency oscillators provide higher performance
but carry with it the disadvantage of higher power requirements, while the opposite is of course true
for the lower frequency oscillators. With the capability of dynamically switching between fast and
slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature
especially important in power sensitive portable applications.
Type
Name
Frequency
Pins
External High Speed Crystal
HXT
400 kHz~20 MHz
OSC1/OSC2
Internal High Speed RC
HIRC
8/12/16 MHz
—
External Low Speed Crystal
LXT
32.768 kHz
XT1/XT2
Internal Low Speed RC
LIRC
32 kHz
—
Oscillator Types
System Clock Configurations
There are four methods of generating the system clock, two high speed oscillators and two low
speed oscillators for all devices. The high speed oscillator is the external crystal/ceramic oscillator,
HXT, and the internal 8/12/16 MHz RC oscillator, HIRC. The two low speed oscillators are the
internal 32 kHz RC oscillator, LIRC, and the external 32.768 kHz crystal oscillator, LXT. Selecting
whether the low or high speed oscillator is used as the system oscillator is implemented using the
CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected.
The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC
register while for the high speed oscillator the source clock is selected by the FHS bit in the SCC
register. The frequency of the slow speed or high speed system clock is determined using the
CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one
high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection
for either the high or low speed oscillator.
Rev. 1.10
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December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
fH
High Speed
Os�illato�
FHS
fH/�
fH/4
HIRC
HIRCEN
HXTEN
fH/8
P�es�ale�
fH
HXT
fSYS
fH/1�
fH/3�
fH/�4
Low Speed
Os�illato�
FSS
CKS�~CKS0
LXTEN
LXT
fSUB
LIRC
fSUB
fLIRC
fLIRC
System Clock Configurations
External Crystal/Ceramic Oscillator – HXT
The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the
default oscillator clock source after power on. For most crystal oscillator configurations, the simple
connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer’s specification.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
     Crystal/Resonator Oscillator
HXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0 pF
0 pF
8MHz
0 pF
0 pF
4MHz
0 pF
0 pF
1MHz
100 pF
100 pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Internal High Speed RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 8/12/16 MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 3V or 5V and at a temperature
of 25°C degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 1%. Note
that if this internal system clock option is selected, as it requires no external pins for its operation, I/
O pins are free for use as normal I/O pins.
External 32.768 kHz Crystal Oscillator – LXT
The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices,
which is selected via a software control bit, FSS. This clock source has a fixed frequency of 32.768
kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external
resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide
oscillation. For applications where precise frequencies are essential, these components may be
required to provide frequency compensation due to different crystal manufacturing tolerances. After
the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated with the
LXT oscillator waiting for it to start-up.
When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. However, in many microcontroller applications it
may be necessary to keep the internal timers operational even when the microcontroller is in the
SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided.
However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary
to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be
selected in consultation with the crystal or resonator manufacturer’s specification. The external
parallel feedback resistor, Rp, is required.
The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator
or as I/O or other pin-shared functional pins.
• If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/
O or other pin-shared functional pins.
• If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to
the XT1/XT2 pins.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
‚   
­ €
  ‚ 
External LXT Oscillator
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the Speed-Up Mode and the Low-Power
Mode. The mode selection is executed using the LXTSP bit in the LXTC register.
LXTSP
LXT Operating Mode
0
Low-Power
1
Speed-Up
When the LXTSP bit is set to high, the LXT Quick Start Mode will be enabled. In the Speed-Up
Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has
fully powered up, it can be placed into the Low-Power Mode by clearing the LXTSP bit to zero and
the oscillator will continue to run but with reduced current consumption. It is important to note that
the LXT operating mode switching must be properly controlled before the LXT oscillator clock is
selected as the system clock source. Once the LXT oscillator clock is selected as the system clock
source using the CKS bit field and FSS bit in the SCC register, the LXT oscillator operating mode
can not be changed.
It should be note that no matter what condition the LXTSP is set to the LXT oscillator will always
function normally. The only difference is that it will take more time to start up if in the Low Power
Mode.
Internal 32kHz Oscillator – LIRC
The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is
selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency
of 32 kHz at 5V, requiring no external components for its implementation. Device trimming during
the manufacturing process and the inclusion of internal frequency compensation circuits are used
to ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of
25˚C degrees, the fixed oscillation frequency of 32 kHz will have a tolerance within 10%.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa lower speed clocks reduce
current consumption. As Holtek has provided these devices with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
Each device has different clock sources for both the CPU and peripheral function operation. By
providing the user with a wide range of clock selections using register programming, a clock system
can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source,
and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is
sourced from an HXT or HIRC oscillator, selected via configuring the FHS bit in the SCC register.
The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected
then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in
the SCC register. The other choice, which is a divided version of the high speed system oscillator
has a range of fH/2~fH/64.
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
fH
High Speed
Os�illato�
HIRCEN
HXTEN
FHS
fH/�
fH/4
HIRC
fH/8
P�es�ale�
fH
HXT
fSYS
fH/1�
fH/3�
fH/�4
FSS
LXTEN
CKS�~CKS0
LXT
fSUB
LIRC
fSUB
fLIRC
fSYS
fPSC0
fSYS/4
Low Speed
Os�illato�
fSUB
P�es�ale� 0
Ti�e Base 0
TB0[�:0]
CLKSEL0[1:0]
fSYS
fPSC1
fSYS/4
fSUB
CLKSEL1[1:0]
fLIRC
fLIRC
P�es�ale� 1
Ti�e Base 1
TB1[�:0]
WDT
LVR
Device Clock Configurations
Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation
can be stopped to conserve the power or continue to oscillate to provide the clock source,
fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding
high speed oscillator enable control bit.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP,
IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve
power.
Operation
Mode
CPU
NORMAL
On
SLOW
On
Register Setting
FHIDEN
x
x
FSIDEN CKS2~CKS0
x
x
IDLE0
Off
0
1
IDLE1
Off
1
1
IDLE2
Off
1
0
SLEEP
Off
0
0
000~110
fSYS
fH
fH~fH/64
On
111
fSUB
000~110
Off
111
On
xxx
On
000~110
On
111
Off
xxx
Off
fSUB
fLIRC
On
On
On
On
Off
On
On
On
On
On
On
Off
On
Off
Off
On/Off
(1)
On
(2)
Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable
bit in the SLOW mode.
2. The fLIRC clock will be switched on since the WDT function is always enabled.
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by one of the high speed oscillators.
This mode operates allowing the microcontroller to operate normally with a clock source will come
from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator
will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by
the CKS2~CKS0 bits in the SCC register. Although a high speed oscillator is used, running the
microcontroller at a divided clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the
LIRC or LXT oscillator.
SLEEP Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and
FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. However the fLIRC clock still
continues to operate since the WDT function is always enabled.
IDLE0 Mode
The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in
the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the
CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral
functions.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
IDLE1 Mode
The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU
will be switched off but both the high and low speed oscillators will be turned on to provide a clock
source to keep some peripheral functions operational.
IDLE2 Mode
The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU
will be switched off but the high speed oscillator will be turned on to provide a clock source to keep
some peripheral functions operational.
Control Registers
The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the
corresponding oscillator configurations.
Bit
Register
Name
7
6
5
4
3
2
1
0
SCC
CKS2
CKS1
CKS0
—
FHS
FSS
FHIDEN
FSIDEN
HIRCC
—
—
—
—
HIRC1
HIRC0
HIRCF
HIRCEN
HXTC
—
—
—
—
—
HXTM
HXTF
HXTEN
LXTC
—
—
—
—
—
LXTSP
LXTF
LXTEN
System Operating Mode Control Registers List
SCC Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
—
FHS
FSS
FHIDEN
FSIDEN
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
POR
0
0
0
—
0
0
0
0
Bit 7~5
Bit 4
Unimplemented, read as 0.
Bit 3
FHS: High Frequency clock selection
0: HIRC
1: HXT
Bit 2
FSS: Low Frequency clock selection
0: LIRC
1: LXT
FHIDEN: High Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the high speed oscillator is activated or stopped
when the CPU is switched off by executing an "HALT" instruction.
Bit 1
Rev. 1.10
CKS2~CKS0: System clock selection
000: fH
001: fH/2
010: fH/4
011: fH/8
100: fH/16
101: fH/32
110: fH/64
111: fSUB
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source directly derived from fH or fSUB, a divided version
of the high speed system oscillator can also be chosen as the system clock source.
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Enhanced Touch Voice A/D Flash MCU
Bit 0
FSIDEN: Low Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the low speed oscillator is activated or stopped
when the CPU is switched off by executing an "HALT" instruction. The LIRC
oscillator is controlled by this bit together with the WDT function enable control when
the LIRC is selected to be the low speed oscillator clock source or the WDT function
is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the
LIRC oscillator will also be enabled.
HIRCC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
HIRC1
HIRC0
HIRCF
HIRCEN
R/W
—
—
—
—
R/W
R/W
R
R/W
POR
—
—
—
—
0
0
0
1
Bit 7~4
Bit 3~2
Bit 1
Bit 0
Unimplemented, read as 0.
HIRC1~HIRC0: HIRC frequency selection
00: 8 MHz
01: 12 MHz
10: 16 MHz
11: 8 MHz
When the HIRC oscillator is enabled or the HIRC frequency selection is changed
by application program, the clock frequency will automatically be changed after the
HIRCF flag is set to 1.
HIRCF: HIRC oscillator stable flag
0: HIRC unstable
1: HIRC stable
This bit is used to indicate whether the HIRC oscillator is stable or not. When the
HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection
is changed by application program, the HIRCF bit will first be cleared to 0 and then
set to 1 after the HIRC oscillator is stable.
HIRCEN: HIRC oscillator enable control
0: Disable
1: Enable
HXTC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
HXTM
HXTF
HXTEN
R/W
—
—
—
—
—
R/W
R
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Bit 2
Bit 1
Rev. 1.10
Unimplemented, read as 0.
HXTM: HXT mode selection
0: HXT frequency ≤ 10 MHz
1: HXT frequency >10 MHz
This bit is used to select the HXT oscillator operating mode. Note that this bit must
be properly configured before the HXT is enabled. When the OSC1 and OSC2 pins
are enabled and the HXTEN bit is set to 1 to enable the HXT oscillator, it is invalid to
change the value of this bit. Otherwise, this bit value can be changed with no operation
on the HXT function.
HXTF: HXT oscillator stable flag
0: HXT unstable
1: HXT stable
This bit is used to indicate whether the HXT oscillator is stable or not. When the
HXTEN bit is set to 1 to enable the HXT oscillator, the HXTF bit will first be cleared
to 0 and then set to 1 after the HXT oscillator is stable.
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Enhanced Touch Voice A/D Flash MCU
Bit 0
HXTEN: HXT oscillator enable control
0: Disable
1: Enable
LXTC Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
LXTSP
LXTF
LXTEN
R/W
—
—
—
—
—
RW
R
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Unimplemented, read as 0.
Bit 2
LXTSP: LXT oscillator speed-up control
0: Disable – Low power
1: Enable – Speed up
This bit is used to control whether the LXT oscillator is operating in the low power
or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate
quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator
will consume less power but take longer time to stablise. It is important to note that
this bit can not be changed after the LXT oscillator is selected as the system clock
source using the CKS2~CKS0 and FSS bits in the SCC register.
Bit 1
LXTF: LXT oscillator stable flag
0: LXT unstable
1: LXT stable
This bit is used to indicate whether the LXT oscillator is stable or not. When the
LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared
to 0 and then set to 1 after the LXT oscillator is stable.
Bit 0
LXTEN: LXT oscillator enable control
0: Disable
1: Enable
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Enhanced Touch Voice A/D Flash MCU
Operating Mode Switching
These devices can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using
the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes
to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is
executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the
condition of the FHIDEN and FSIDEN bits in the SCC register.
NORMAL
fSYS=fH~fH/�4
fH on
CPU �un
fSYS on
fSUB on
SLOW
fSYS=fSUB
fSUB on
CPU �un
fSYS on
fH on/off
SLEEP
HALT inst�u�tion exe�uted
CPU stop
FHIDEN=0
FSIDEN=0
fH off
fSUB off
IDLE0
HALT inst�u�tion exe�uted
CPU stop
FHIDEN=0
FSIDEN=1
fH off
fSUB on
IDLE2
HALT inst�u�tion exe�uted
CPU stop
FHIDEN=1
FSIDEN=0
fH on
fSUB off
Rev. 1.10
79
IDLE1
HALT inst�u�tion exe�uted
CPU stop
FHIDEN=1
FSIDEN=1
fH on
fSUB on
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by set the
CKS2~CKS0 bits to "111" in the SCC register. This will then use the low speed system oscillator
which will consume less power. Users may decide to do this for certain operations which do not
require high performance and can subsequently reduce power consumption.
The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC
register and therefore requires this oscillator to be stable before full mode switching occurs.
NORMAL Mode
CKS�~CKS0 = 111
SLOW Mode
FHIDEN=0� FSIDEN=0
HALT inst�u�tion is exe�uted
SLEEP Mode
FHIDEN=0� FSIDEN=1
HALT inst�u�tion is exe�uted
IDLE0 Mode
FHIDEN=1� FSIDEN=1
HALT inst�u�tion is exe�uted
IDLE1 Mode
FHIDEN=1� FSIDEN=0
HALT inst�u�tion is exe�uted
IDLE2 Mode
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
SLOW Mode to NORMAL Mode Switching
In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the
NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to "000" ~"110" and then the system
clock will respectively be switched to fH~ fH/64.
However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is
monitored using the HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register. The
time duration required for the high speed system oscillator stabilization is specified in the A.C.
characteristics.
SLOW Mode
CKS�~CKS0 = 000~110
NORMAL Mode
FHIDEN=0� FSIDEN=0
HALT inst�u�tion is exe�uted
SLEEP Mode
FHIDEN=0� FSIDEN=1
HALT inst�u�tion is exe�uted
IDLE0 Mode
FHIDEN=1� FSIDEN=1
HALT inst�u�tion is exe�uted
IDLE1 Mode
FHIDEN=1� FSIDEN=0
HALT inst�u�tion is exe�uted
IDLE2 Mode
Entering the SLEEP Mode
There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT"
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to "0". In this mode all the clocks and functions will be switched off except the WDT function.
When this instruction is executed under the conditions described above, the following will occur:
• The system clock will be stopped and the application program will stop at the "HALT"
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT"
instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the
FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be stopped and the application program will stop at the "HALT" instruction, but
the fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT"
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to "1". When this instruction is executed under the conditions described above, the following
will occur:
• The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
Entering the IDLE2 Mode
There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT"
instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the
FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be on but the fSUB clock will be off and the application program will stop at the
"HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting as the WDT function is always enabled.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by
the circuit designer if the power consumption is to be minimised. Special attention must be made
to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed
high or low level as any floating input pins could create internal oscillations and result in increased
current consumption. This also applies to devices which have different package types, as there may
be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high
resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.
These should be placed in a condition in which minimum current is drawn or connected only to
external circuits that do not draw current, such as other CMOS inputs. Also note that additional
standby current will also be required if the LIRC oscillator has enabled.
In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock
source is derived from the high speed oscillator, the additional standby current will also be perhaps
in the order of several hundred micro-amps.
Wake-up
To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the
CPU will be switched off. However, when the device is woken up again, it will take a considerable
time for the original system oscillator to restart, stabilise and allow normal operation to resume.
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
When the device executes the "HALT" instruction, the PDF flag will be set to 1. The PDF flag will
be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer
instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated
and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up
that only resets the Program Counter and Stack Pointer, other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the "HALT" instruction. In this situation, the interrupt which woke up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal RC oscillator, fLIRC. The LIRC internal
oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary
with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided
by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0
bits in the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register controls the overall operation of the Watchdog Timer.
WDTC Register
Bit
Register
Name
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3
Bit 2~0
WE4~WE0: WDT function enable control
10101 or 01010: Enabled
Other values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the
WRF bit in the RSTFC register will be set to 1.
WS2~WS0: WDT time-out period selection
000: 28/fLIRC
001: 210/fLIRC
010: 212/fLIRC
011: 214/fLIRC
100: 215/fLIRC
101: 216/fLIRC
110: 217/fLIRC
111: 218/fLIRC
These three bits determine the division ratio of the watchdog timer source clock,
which in turn determines the time-out period.
RSTFC Register
Bit
Register
Name
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
"x": unknown
Rev. 1.10
Bit 7~4
Unimplemented, read as "0"
Bit 3
RSTF: Reset control register software reset flag
Described elsewhere.
Bit 2
LVRF: LVR function reset flag
Described elsewhere.
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Enhanced Touch Voice A/D Flash MCU
Bit 1
LRF: LVR control register software reset flag
Described elsewhere.
Bit 0
WRF: WDT control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the WDT control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear instruction will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to
the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register
to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will
be enabled when the WE4~WE0 bits are set to a value of 01010B or 10101B. If the WE4~WE0 bits
are set to any other values other than 01010B and 10101B, it will reset the device after 2~3 fLIRC
clock cycles. After power on these bits will have a value of 01010B.
WE4 ~ WE0 Bits
WDT Function
10101B or 01010B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value except 01010B and 10101B written into the
WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is
via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single "CLR WDT" instruction to clear the WDT contents.
The maximum time out period is when the 218 division ratio is selected. As an example, with a 32
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
second for the 218 division ratio and a minimum timeout of 7.8ms for the 28 division ration.
WDTC WE4~WE0 �its
Registe�
Reset MCU
CLR
“HALT”Inst�u�tion
“CLR WDT”Inst�u�tion
LIRC
fLIRC
8-stage Divide�
fLIRC/�8
WS�~WS0
(fLIRC/�8 ~ fLIRC/�18)
WDT P�es�ale�
8-to-1 MUX
WDT Ti�e-out
(�8/fLIRC ~ �18/fLIRC)
Watchdog Timer
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR,
where a full reset is implemented in situations where the power supply voltage falls below a
certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the
microcontroller. All types of reset operations result in different register conditions being setup.
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally.
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
VDD
Powe�-on Reset
tRSTD
SST Ti�e-out
Note: tRSTD is power-on delay with typical time = 50 ms
Power-On Reset Timing Chart
Internal Reset Control
There is an internal reset control register, RSTC, which is used to provide a reset when the device
operates abnormally due to the environmental noise interference. If the content of the RSTC register
is set to any value other than 01010101B or 10101010B, it will reset the device after 2~3 fLIRC clock
cycles. After power on the register will have a value of 01010101B.
RSTC7 ~ RSTC0 Bits
Reset Function
01010101B
No operation
10101010B
No operation
Any other value
Reset MCU
Internal Reset Function Control
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• RSTC Register
Bit
Register
Name
7
6
5
4
3
2
1
0
Name
RSTC7
RSTC6
RSTC5
RSTC4
RSTC3
RSTC2
RSTC1
RSTC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0
RSTC7~RSTC0: Reset function control
01010101: No operation
10101010: No operation
Other values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the
RSTF bit in the RSTFC register will be set to 1.
• RSTFC Register
Bit
Register
Name
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
"x": unknown
Bit 7~4
Unimplemented, read as "0"
Bit 3
RSTF: Reset control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the RSTC control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Bit 2
LVRF: LVR function reset flag
Described elsewhere.
Bit 1
LRF: LVR control register software reset flag
Described elsewhere.
Bit 0
WRF: WDT control register software reset flag
Described elsewhere.
Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage
of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery,
the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will
also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~ VLVR must exist for a time greater than that specified by tLVR in the LVD/LVR characteristics.
If the low supply voltage state does not exceed this value, the LVR will ignore the low supply
voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS
bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which may perhaps occur
due to adverse environmental conditions such as noise, the LVR will reset the device after 2~3 fLIRC
clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power
on the register will have the value of 01010101B. Note that the LVR function will be automatically
disabled when the device enters the power down mode.
Rev. 1.10
87
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
LVR
tRSTD + tSST
Inte�nal Reset
Note: tRSTD is power-on delay with typical time = 50 ms
Low Voltage Reset Timing Chart
• LVRC Register
Bit
Register
Name
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0
LVS7~LVS0: LVR voltage select
01010101: 2.1V
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
Other values: Generates a MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the four defined
LVR voltage value above, an MCU reset will generated. The reset operation will be
activated after 2~3 fLIRC clock cycles. In this situation the register contents will remain
the same after such a reset occurs.
Any register value, other than the four defined register values above, will also result
in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC
clock cycles. However in this situation the register contents will be reset to the POR
value.
• RSTFC Register
Bit
Register
Name
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF
LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
"x": unknown
Rev. 1.10
Bit 7~4
Unimplemented, read as "0"
Bit 3
RSTF: Reset control register software reset flag
Described elsewhere.
Bit 2
LVRF: LVR function reset flag
0: Not occurred
1: Occurred
This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit
can only be cleared to 0 by the application program.
Bit 1
LRF: LVR control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the LVRC control register contains any undefined LVR voltage
register values. This in effect acts like a software-reset function. Note that this bit can
only be cleared to 0 by the application program.
Bit 0
WRF: WDT control register software reset flag
Described elsewhere.
88
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as the hardware Low Voltage
Reset except that the Watchdog time-out flag TO will be set to "1".
WDT Ti�e-out
tRSTD + tSST
Inte�nal Reset
Note: tRSTD is power-on delay with typical time = 16.7 ms
WDT Time-out Reset during NORMAL Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset.
Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details.
WDT Ti�e-out
tSST
Inte�nal Reset
WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
Reset Function
0
0
Power-on reset
u
u
LVR reset during NORMAL or SLOW Mode operation
1
u
WDT time-out reset during NORMAL or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
"u" stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Reset Function
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT, Time Base
Clear after reset, WDT begins counting
Timer Modules
Timer Modules will be turned off
Input/Output Ports
I/O ports will be setup as inputs
Stack pointer
Stack pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects the microcontroller internal registers.
Rev. 1.10
89
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
BS66FV340
BS66FV350
BS66FV360
Reset
(Power On)
IAR0
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
IAR1
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP1H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
●
---- xxxx
---- uuuu
---- uuuu
---- uuuu
---x xxxx
---u uuuu
---u uuuu
---u uuuu
●
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
●
xx00 xxxx
uuuu uuuu
xx1u uuuu
u u 11 u u u u
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
Register
TBHP
●
TBHP
STATUS
●
●
PBP
LVR Reset
WDT Time-out
(Normal Operation) (Normal Operation)
WDT Time-out
(IDLE or SLEEP)*
IAR2
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP2L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
MP2H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
RSTFC
●
●
●
---- 0x00
---- u1uu
---- uuuu
---- uuuu
INTC0
●
●
●
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PA
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PB
●
●
●
1111 - 111
1111 - 111
1111 - 111
uuuu -uuu
PBC
●
●
●
1111 - 111
1111 - 111
1111 - 111
uuuu -uuu
PBPU
●
●
●
0000 -000
0000 -000
0000 -000
uuuu -uuu
INTEG
●
●
●
---- 0000
---- 0000
---- 0000
---- uuuu
SCC
●
●
●
000- 0000
000- 0000
000- 0000
uuu- uuuu
HIRCC
●
●
●
---- 0001
---- 0001
---- 0001
---- uuuu
HXTC
●
●
●
---- -000
---- -000
---- -000
---- -uuu
LXTC
●
●
●
---- -000
---- -000
---- -000
---- -uuu
LVDC
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
LVRC
●
●
●
0101 0101
0101 0101
0101 0101
uuuu uuuu
WDTC
●
●
●
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
RSTC
●
●
●
0101 0101
0101 0101
0101 0101
uuuu uuuu
PC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCPU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PD
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDPU
●
●
●
0000 0000
0000 0000
0000 0000
0uuuu uuuu
MFI0
●
●
●
--00 --00
--00 --00
--00 --00
--uu --uu
Rev. 1.10
90
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
BS66FV360
BS66FV350
MFI1
BS66FV340
Register
●
MFI1
Reset
(Power On)
00-- 00--
LVR Reset
WDT Time-out
(Normal Operation) (Normal Operation)
00-- 00--
00-- 00--
WDT Time-out
(IDLE or SLEEP)*
uu-- uu--
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFI2
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
MFI3
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
SADOL
(ADRFS=0)
●
●
●
xxxx ----
xxxx ----
xxxx ----
uuuu ----
SADOL
(ADRFS=1)
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
SADOH
(ADRFS=0)
●
●
●
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
SADOH
(ADRFS=1)
●
●
●
---- xxxx
---- uuuu
---- uuuu
---- uuuu
SADC0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
SADC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PSCR0
●
●
●
---- --00
---- --00
---- --00
---- --uu
TB0C
●
●
●
0--- -000
0--- -000
0--- -000
u--- -uuu
TB1C
●
●
●
0--- -000
0--- -000
0--- -000
u--- -uuu
SIMC0
(SPI mode)
●
●
●
111 - - - 0 0
111 - - - 0 0
111 - - - 0 0
uuu- --uu
SIMC0
(I2C mode)
●
●
●
111 - 0 0 0 -
111 - 0 0 0 -
111 - 0 0 0 -
uuu- uuu-
SIMC1
●
●
●
1000 0001
1000 0001
1000 0001
uuuu uuuu
SIMA/SIMC2
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
SIMD
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
SIMTOC
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0C0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0C1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0DH
●
●
●
---- --00
---- --00
---- --00
---- --uu
CTM0AL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM0AH
●
●
●
---- --00
---- --00
---- --00
---- --uu
EEA
●
●
-000 0000
-000 0000
-000 0000
-uuu uuuu
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
EEA
EED
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PSCR1
●
●
●
---- --00
---- --00
---- --00
---- --uu
SLEDC0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
SLEDC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
SLEDC2
●
●
●
---- 0000
---- 0000
---- 0000
---- uuuu
PTM0C0
●
●
●
0000 0---
0000 0---
0000 0---
uuuu u---
PTM0C1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM0DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM0DH
●
●
●
---- --00
---- --00
---- --00
---- --uu
PTM0AL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM0AH
●
●
●
---- --00
---- --00
---- --00
---- --uu
PTM0RPL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.10
91
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
BS66FV340
BS66FV350
BS66FV360
Reset
(Power On)
PTM0RPH
●
●
●
---- --00
---- --00
---- --00
---- --uu
FC0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
●
●
---- ---0
---- ---0
---- ---0
---- ---u
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
---- 0000
---- 0000
---- 0000
---- uuuu
---0 0000
---0 0000
---0 0000
---u uuuu
●
--00 0000
--00 0000
--00 0000
--uu uuuu
Register
FC2
FARL
●
FARH
●
FARH
●
FARH
LVR Reset
WDT Time-out
(Normal Operation) (Normal Operation)
WDT Time-out
(IDLE or SLEEP)*
FD0L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD0H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD1L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD1H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD2L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD2H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD3L
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
FD3H
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMC0
●
●
●
0000 0---
0000 0---
0000 0---
uuuu u---
STMC1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMDL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMDH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMAL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMAH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
STMRP
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1C0
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1C1
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1DL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1DH
●
●
---- --00
---- --00
---- --00
---- --uu
CTM1AL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTM1AH
●
●
---- --00
---- --00
---- --00
---- --uu
SADC2
●
●
●
---- --10
---- --10
---- --10
---- --uu
PE
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
●
●
●
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEPU
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
SPIAC0
●
●
●
111 - - - 0 0
111 - - - 0 0
111 - - - 0 0
uuu- --uu
SPIAC1
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
SPIAD
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
USR
●
●
●
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
uuuu uuuu
UCR1
●
●
●
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
UCR2
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TXR_RXR
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRG
●
●
●
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
USVC
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PLAC
●
●
●
---- --00
---- --00
---- --00
---- --uu
PLADL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
Rev. 1.10
92
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
BS66FV340
BS66FV350
BS66FV360
Reset
(Power On)
PLADH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKTMR
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKC0
●
●
●
0000 0-00
0000 0-00
0000 0-00
uuuu u-uu
TK16DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TK16DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKC1
●
●
●
0 0 0 0 0 0 11
0 0 0 0 0 0 11
0 0 0 0 0 0 11
uuuu uuuu
TKM016DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM016DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM0ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM0ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM0C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM0C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM0C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM116DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM116DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM1ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM1ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM1C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM1C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM1C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM216DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM216DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM2ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM2ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM2C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM2C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM2C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM316DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM316DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM3ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM3ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM3C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM3C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM3C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM416DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM416DH
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM4ROL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM4ROH
●
●
●
---- --00
---- --00
---- --00
---- --uu
TKM4C0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM4C1
●
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM4C2
●
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM516DL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM516DH
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM5ROL
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
Register
Rev. 1.10
LVR Reset
WDT Time-out
(Normal Operation) (Normal Operation)
93
WDT Time-out
(IDLE or SLEEP)*
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
BS66FV350
BS66FV360
BS66FV340
Reset
(Power On)
TKM5ROH
●
●
---- --00
---- --00
---- --00
---- --uu
TKM5C0
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM5C1
●
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM5C2
●
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
TKM616DL
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM616DH
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM6ROL
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
TKM6ROH
●
---- --00
---- --00
---- --00
---- --uu
TKM6C0
●
--00 0000
--00 0000
--00 0000
--uu uuuu
TKM6C1
●
0-00 0000
0-00 0000
0-00 0000
u-uu uuuu
TKM6C2
●
111 0 0 1 0 0
111 0 0 1 0 0
111 0 0 1 0 0
uuuu uuuu
Register
LVR Reset
WDT Time-out
(Normal Operation) (Normal Operation)
WDT Time-out
(IDLE or SLEEP)*
EEC
●
●
●
---- 0000
---- 0000
---- 0000
---- uuuu
IFS
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAS0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAS1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PBS0
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
PBS1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PCS0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PCS1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PDS0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PDS1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PES0
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PES1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1C0
●
●
●
0000 0---
0000 0---
0000 0---
uuuu u---
PTM1C1
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1DL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1DH
●
●
●
---- --00
---- --00
---- --00
---- --uu
PTM1AL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1AH
●
●
●
---- --00
---- --00
---- --00
---- --uu
PTM1RPL
●
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
PTM1RPH
●
●
●
---- --00
---- --00
---- --00
---- --uu
SLCDC0
●
●
●
0000 ----
0000 ----
0000 ----
uuuu ----
SLCDC1
●
●
●
--00 0000
--00 0000
--00 0000
--uu uuuu
Note: "u" stands for unchanged
"x" stands for "unknown"
"-" stands for unimplemented
Rev. 1.10
94
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
These devices provide bidirectional input/output lines labeled with port names PA~PE. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
Register
Name
Bit
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PAWU0
PB
PB7
PB6
PB5
PB4
—
PB2
PB1
PB0
PBC
PBC7
PBC6
PBC5
PBC4
—
PBC2
PBC1
PBC0
PBPU
PBPU7
PBPU6
PBPU5
PBPU4
—
PBPU2
PBPU1
PBPU0
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDC
PDC7
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
PDPU7
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PE
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PEC
PEC7
PEC6
PEC5
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU
PEPU7
PEPU6
PEPU5
PEPU4
PEPU3
PEPU2
PEPU1
PEPU0
I/O Registers List
"—": Unimplemented, read as "0".
PAWUn: Port A Pin wake-up function control
0: Disable
1: Enable
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn: I/O Pin pull-high function control
0: Disable
1: Enable
PAn/PBn/PCn/PDn/PEn: I/O Port Data bit
0: Data 0
1: Data 1
PACn/PBCn/PCCn/PDCn/PECn: I/O Pin type selection
0: Output
1: Input
Rev. 1.10
95
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using the relevant pull-high control registers and are implemented
using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant
pull-high control register only when the pin-shared functional pin is selected as an input or NMOS
output. Otherwise, the pull-high resistors can not be enabled.
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register. Note that the wake-up function can be controlled by the wake-up control
registers only when the pin-shared functional pin is selected as general purpose input/output and the
MCU enters the Power down mode.
I/O Port Control Registers
Each Port has its own control register, known as PAC~PEC, which controls the input/output
configuration. With this control register, each I/O pin with or without pull-high resistors can be
reconfigured dynamically under software control. For the I/O pin to function as an input, the
corresponding bit of the control register must be written as a "1". This will then allow the logic state
of the input pin to be directly read by instructions. When the corresponding bit of the control register
is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an
output, instructions can still be used to read the output register.
However, it should be noted that the program will in fact only read the status of the output data latch
and not the actual logic status of the output pin.
I/O Port Source Current Control
These devices support different source current driving capability for each I/O port. With the
selection register, SLEDCn, specific I/O port can support four levels of the source current driving
capability. Users should refer to the D.C. characteristics section to select the desired source current
for different applications.
Bit
Register
Name
7
6
5
4
3
2
1
0
SLEDC0
PBPS3
PBPS2
PBPS1
PBPS0
PAPS3
PAPS2
PAPS1
PAPS0
SLEDC1
PDPS3
PDPS2
PDPS1
PDPS0
PCPS3
PCPS2
PCPS1
PCPS0
SLEDC2
—
—
—
—
PEPS3
PEPS2
PEPS1
PEPS0
I/O Port Source Current Control Registers List
Rev. 1.10
96
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
SLEDC0 Register
Bit
7
6
5
4
3
2
1
0
Name
PBPS3
PBPS2
PBPS1
PBPS0
PAPS3
PAPS2
PAPS1
PAPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PBPS3~PBPS2: PB7~PB4 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Bit 5~4
PBPS1~PBPS0: PB2~PB0 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Bit 3~2
PAPS3~PAPS2: PA7~PA4 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Bit 1~0
PAPS1~PAPS0: PA3~PA0 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
SLEDC1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
PDPS3
PDPS2
PDPS1
PDPS0
PCPS3
PCPS2
PCPS1
PCPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PDPS3~PDPS2: PD7~PD4 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Bit 5~4
PDPS1~PDPS0: PD3~PD0 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Bit 3~2
PCPS3~PCPS2: PC7~PC4 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Bit 1~0
PCPS1~PCPS0: PC3~PC0 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
97
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
SLEDC2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
PEPS3
PEPS2
PEPS1
PEPS0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as 0.
Bit 3~2
PEPS3~PEPS2: PE7~PE4 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Bit 1~0
PEPS1~PEPS0: PE3~PE0 source current selection
00: source current = Level 0 (min.)
01: source current = Level 1
10: source current = Level 2
11: source current = Level 3 (max.)
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the
desired function of the multi-function I/O pins is selected by a series of registers via the application
program control.
Pin-shared Function Selection Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes. Each device includes Port "x" output function Selection
register "n", labeled as PxSn, and Input Function Selection register, labeled as IFS, which can select
the desired functions of the multi-function pin-shared pins.
When the pin-shared input function is selected to be used, the corresponding input and output
functions selection should be properly managed. For example, if the I2C SDA line is used, the
corresponding output pin-shared function should be configured as the SDI/SDA function by
configuring the PxSn register and the SDA signal input should be properly selected using the IFS
register. However, if the external interrupt function is selected to be used, the relevant output pinshared function should be selected as an I/O function and the interrupt input signal should be
selected.
The most important point to note is to make sure that the desired pin-shared function is properly
selected and also deselected. To select the desired pin-shared function, the pin-shared function
should first be correctly selected using the corresponding pin-shared control register. After that the
corresponding peripheral functional setting should be configured and then the peripheral function
can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be
disabled and then the corresponding pin-shared function control register can be modified to select
other pin-shared functions.
Rev. 1.10
98
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Bit
Register
Name
7
6
5
4
3
2
1
0
PAS0
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
PAS1
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
PBS0
—
—
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
PBS1
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
PCS0
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
PCS10
PCS1
PCS17
PCS16
PCS15
PCS14
PCS13
PCS12
PCS11
PDS0
PDS07
PDS06
PDS05
PDS04
PDS03
PDS02
PDS01
PDS00
PDS1
PDS17
PDS16
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
PES0
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
PES1
PES17
PES16
PES15
PES14
PES13
PES12
PES11
PES10
IFS
IFS7
IFS6
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
Pin-shared Function Selection Registers List
• PAS0 Register
Bit
7
6
5
4
3
2
1
0
Name
PAS07
PAS06
PAS05
PAS04
PAS03
PAS02
PAS01
PAS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 5~4
PAS07~PAS06: PA3 pin function selection
PAS0[7:6]
BS66FV340
00
PA3
PA3
01
SCS
SCS
10
PA3
KEY24
11
SSEG19
SSEG19
PAS05~PAS04: PA2 pin function selection
PAS0[5:4]
Bit 3~2
Bit 1~0
Rev. 1.10
BS66FV350/BS66FV360
BS66FV340
BS66FV350/BS66FV360
00
PA2
PA2
01
SCS
SCS
10
PA2
KEY23
11
SSEG18
SSEG18
PAS03~PAS02: PA1 pin function selection
PAS0[3:2]
BS66FV340
00
PA1
BS66FV350/BS66FV360
PA1
01
SDO
SDO
10
PA1
KEY22
11
SSEG17
SSEG17
PAS01~PAS00: PA0 pin function selection
PAS0[1:0]
BS66FV340
00
PA0
BS66FV350/BS66FV360
PA0
01
SDO
SDO
10
PA0
KEY21
11
SSEG16
SSEG16
99
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• PAS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PAS17
PAS16
PAS15
PAS14
PAS13
PAS12
PAS11
PAS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PAS17~PAS16: PA7 pin function selection
00: PA7
01: SDI/SDA
10: AN3
11: SSEG23
Bit 5~4
PAS15~PAS14: PA6 pin function selection
00: PA6
01: SCK/SCL
10: AN2
11: SSEG22
Bit 3~2
PAS13~PAS12: PA5 pin function selection
00: PA5
01: VREF
10: AN1
11: SSEG21
Bit 1~0
PAS11~PAS10: PA4 pin function selection
0x: PA4
10: AN0
11: SSEG20
• PBS0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
PBS05
PBS04
PBS03
PBS02
PBS01
PBS00
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as 0.
Bit 5~4
PBS05~PBS04: PB2 pin function selection
0x: PB2/CTCK0
10: VDDIO
11: SSEG34
Bit 3~2
PBS03~PBS02: PB1 pin function selection
0x: PB1
10: AN7
11: SSEG33
Bit 1~0
PBS01~PBS00: PB0 pin function selection
0x: PB0
10: AN6
11: SSEG32
100
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• PBS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PBS17
PBS16
PBS15
PBS14
PBS13
PBS12
PBS11
PBS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PBS17~PBS16: PB7 pin function selection
00/01: PB7/INT0
10: KEY4
11: SSEG38
Bit 5~4
PBS15~PBS14: PB6 pin function selection
00: PB6
01: CTP0B
10: KEY3
11: SSEG37
Bit 3~2
PBS13~PBS12: PB5 pin function selection
0x: PB5/PTCK0
10: KEY2
11: SSEG36
Bit 1~0
PBS11~PBS10: PB4 pin function selection
0x: PB4/STCK
10: KEY1
11: SSEG35
• PCS0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
PCS07
PCS06
PCS05
PCS04
PCS03
PCS02
PCS01
PCS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PCS07~PCS06: PC3 pin function selection
00: PC3/PTP0I
01: PTP0B
10: KEY8
11: SSEG27
Bit 5~4
PCS05~PCS04: PC2 pin function selection
00: PC2/PTP0I
01: PTP0
10: KEY7
11: SSEG26
Bit 3~2
PCS03~PCS02: PC1 pin function selection
00: PC1
01: CTM0
10: KEY6
11: SSEG25
Bit 1~0
PCS01~PCS00: PC0 pin function selection
0x: PC0/INT1
10: KEY5
11: SSEG24
101
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
PCS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PCS17
PCS16
PCS15
PCS14
PCS13
PCS12
PCS11
PCS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PCS17~PCS16: PC7 pin function selection
PCS1[7:6]
Bit 5~4
Bit 3~2
Bit 1~0
BS66FV340/ BS66FV350
BS66FV360
00
PC7
PC7
01
SCSA
SCSA
10
PC7
KEY28
11
SSEG31
SSEG31
PCS15~PCS14: PC6 pin function selection
PCS1[5:4]
BS66FV340/ BS66FV350
00
PC6
BS66FV360
PC6
01
SDIA
SDIA
10
PC6
KEY27
11
SSEG30
SSEG30
PCS13~PCS12: PC5 pin function selection
PCS1[3:2]
BS66FV340/ BS66FV350
00
PC5
BS66FV360
PC5
01
SCKA
SCKA
10
PC5
KEY26
11
SSEG29
SSEG29
PCS11~PCS10: PC4 pin function selection
PCS1[1:0]
BS66FV340/ BS66FV350
BS66FV360
00
PC4
PC4
01
SDOA
SDOA
10
PC4
KEY25
11
SSEG28
SSEG28
• PDS0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
PDS07
PDS06
PDS05
PDS04
PDS03
PDS02
PDS01
PDS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PDS07~PDS06: PD3 pin function selection
0x: PD3
10: KEY12
11: SCOM3/SSEG3
Bit 5~4
PDS05~PDS04: PD2 pin function selection
0x: PD2
10: KEY11
11: SCOM2/SSEG2
Bit 3~2
PDS03~PDS02: PD1 pin function selection
00: PD1
01: RX
10: KEY10
11: SCOM1/SSEG1
102
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Bit 1~0
PDS01~PDS00: PD0 pin function selection
00: PD0
01: TX
10: KEY9
11: SCOM0/SSEG0
• PDS1 Register
Bit
7
6
5
4
3
2
1
0
Name
PDS17
PDS16
PDS15
PDS14
PDS13
PDS12
PDS11
PDS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 5~4
Bit 3~2
Bit 1~0
PDS17~PDS16: PD7 pin function selection
PDS1[7:6]
BS66FV340
BS66FV350/BS66FV360
00
PD7
PD7/CTCK1
01
PD7
PD7/CTCK1
10
KEY16
KEY16
11
SSEG7
SSEG7
PDS15~PDS14: PD6 pin function selection
PDS1[5:4]
BS66FV340
00
PD6
BS66FV350/BS66FV360
PD6
01
PD6
CTP1B
10
KEY15
KEY15
11
SSEG6
SSEG6
PDS13~PDS12: PD5 pin function selection
PDS1[3:2]
BS66FV340
BS66FV350/BS66FV360
00
PD5
PD5
01
PD5
CTP1
10
KEY14
KEY14
11
SCOM5/SSEG5
SCOM5/SSEG5
PDS11~PDS10: PD4 pin function selection
0x: PD4/PTCK1
10: KEY13
11: SCOM4/SSEG4
• PES0 Register
Bit
7
6
5
4
3
2
1
0
Name
PES07
PES06
PES05
PES04
PES03
PES02
PES01
PES00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Rev. 1.10
PES07~PES06: PE3 pin function selection
00: PE3/STPI
01: STPB
10: KEY20
11: SSEG11
103
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Bit 5~4
PES05~PES04: PE2 pin function selection
00: PE2/STPI
01: STP
10: KEY19
11: SSEG10
Bit 3~2
PES03~PES02: PE1 pin function selection
00: PE1/PTP1I
01: PTP1B
10: KEY18
11: SSEG9
Bit 1~0
PES01~PES00: PE0 pin function selection
00: PE0/PTP1I
01: PTP1
10: KEY17
11: SSEG8
• PES1 Register
Bit
7
6
5
4
3
2
1
0
Name
PES17
PES16
PES15
PES14
PES13
PES12
PES11
PES10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
PES17~PES16: PE7 pin function selection
0x: PE7
10: XT2
11: SSEG15
Bit 5~4
PES15~PES14: PE6 pin function selection
0x: PE6
10: XT1
11: SSEG14
Bit 3~2
PES13~PES12: PE5 pin function selection
00: PE5
01: OSC2
10: AN5
11: SSEG13
Bit 1~0
PES11~PES10: PE4 pin function selection
00: PE4
01: OSC1
10: AN4
11: SSEG12
• IFS Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
IFS7
IFS6
IFS5
IFS4
IFS3
IFS2
IFS1
IFS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
IFS7~IFS6: PTP1I input source pin selection
x0: PE0
x1: PE1
Bit 5~4
IFS5~IFS4: SCS input source pin selection
x0: PA2
x1: PA3
104
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Bit 3~2
IFS3~IFS2: PTP0I input source pin selection
x0: PC2
x1: PC3
Bit 1~0
IFS1~IFS0: STPI input source pin selection
x0: PE2
x1: PE3
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
    
  Generic Input/Output Structure
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A/D Input/Output Structure
Rev. 1.10
105
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Programming Considerations
Within the user program, one of the things first to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set to high. This means that all I/O pins will be
defaulted to an input state, the level of which depends on the other connected circuitry and whether
pull-high selections have been chosen. If the port control registers are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated
port data registers are first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct values into the appropriate port control register or
by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i"
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Rev. 1.10
106
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Timer Modules – TM
One of the most fundamental functions in any microcontroller devices is the ability to control and
measure time. To implement time related functions the device includes several Timer Modules,
generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
interrupts. The addition of input and output pins for each TM ensures that users are provided with
timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Compact, Standard and Periodic TM sections.
Introduction
These devices contain up to five TMs and each individual TM can be categorised as a certain type,
namely Compact Type TM, Standard Type TM or Periodic Type TM. Although similar in nature,
the different TM types vary in their feature complexity. The common features to all of the Compact,
Standard and Periodic TMs will be described in this section and the detailed operation regarding
each of the TM types will be described in separate sections. The main features and differences
between the three types of TMs are summarised in the accompanying table.
CTM
STM
PTM
Timer/Counter
TM Function
√
√
√
Input Capture
—
√
√
Compare Match Output
√
√
√
PWM Channels
1
1
1
Single Pulse Output
—
1
1
Edge
Edge
Edge
Duty or Period
Duty or Period
Duty or Period
PWM Alignment
PWM Adjustment Period & Duty
TM Function Summary
TM Operation
The different types of TM offer a diverse range of functions, from simple timing operations to PWM
signal generation. The key to understanding how the TM operates is to see it in terms of a free
running count-up counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running count-up counter has the same value as the pre-programmed
comparator, known as a compare match situation, a TM interrupt signal will be generated which
can clear the counter and perhaps also change the condition of the TM output pin. The internal TM
counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources. The
selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn
control registers, where "x" stands for C, S or P type TM and "n" stands for the specific TM serial
number. For STM there is no serial number "n" in the relevant pin or control bits since there is only
one STM respectively in the series of devices, The clock source can be a ratio of the system clock,
fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin
clock source is used to allow an external signal to drive the TM as an external clock source for event
counting.
Rev. 1.10
107
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
TM Interrupts
The Compact, Standard or Periodic type TM has two internal interrupt, one for each of the internal
comparator A or comparator P, which generate a TM interrupt when a compare match condition
occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the
state of the TM output pin.
TM External Pins
Each of the TMs, irrespective of what type, has one or two TM input pins, with the label xTCKn and
xTPnI respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is
selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows
an external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either
a rising or falling active edge. The STCK and PTCKn pins are also used as the external trigger input
pin in single pulse output mode for the STM and PTMn respectively.
The other xTM input pin, STPI or PTPnI, is the capture input whose active edge can be a rising
edge, a falling edge or both rising and falling edges and the active edge transition type is selected
using the STIO1~STIO0 or PTnIO1~PTnIO0 bits in the STMC1 or PTMnC1 register respectively.
There is another capture input, PTCKn, for PTMn capture input mode, which can be used as the
external trigger input source except the PTPnI pin.
The TMs each have two output pins, xTPn and xTPnB. The xTPnB is the inverted signal of the
xTPn output. The TM output pins can be selected using the corresponding pin-shared function
selection bits described in the Pin-shared Function section. When the TM is in the Compare Match
Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle
when a compare match situation occurs. The external xTPn or xTPnB output pin is also the pin
where the TM generates the PWM output waveform. As the TM output pins are pin-shared with
other functions, the TM output function must first be setup using relevant pin-shared function
selection register.
Device
CTM
Input
STM
Output
Input
PTM
Output
Input
Output
BS66FV340
CTCK0
CTP0, CTP0B
STCK, STPI
PTCK0, PTP0I PTP0, PTP0B
STP, STPB
PTCK1, PTP1I PTP1, PTP1B
BS66FV350
BS66FV360
CTCK0
CTCK1
CTP0, CTP0B
CTP1, CTP1B
STCK, STPI
STP, STPB
PTCK0, PTP0I PTP0, PTP0B
PTCK1, PTP1I PTP1, PTP1B
TM External Pins
Rev. 1.10
108
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
TM Input/Output Pin Selection
Selecting to have a TM input/output or whether to retain its other shared function is implemented
using the relevant pin-shared function selection registers, with the corresponding selection bits in
each pin-shared function register corresponding to a TM input/output pin. Configuring the selection
bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared
function selection are described in the pin-shared function section.
CTCKn
CTMn
CCR output
CTPn
CTPnB
CTM Function Pin Control Block Diagram – n = 0 or 1
STCK
CCR �aptu�e input
STPI
STM
CCR output
STP
STPB
STM Function Pin Control Block Diagram
PTCKn
CCR �aptu�e input
PTPnI
PTM
CCR output
PTPn
PTPnB
PTM Function Pin Control Block Diagram – n = 0 or 1
Rev. 1.10
109
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low
and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be
accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in
a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its
related low byte only takes place when a write or read operation to its corresponding high byte is
executed.
As the CCRA and CCRP registers are implemented in the way shown in the following diagram and
accessing these register pairs is carried out in a specific way as described above, it is recommended
to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL
and PTMnRPL, using the following access procedures. Accessing the CCRA or CCRB low byte
registers without following these access procedures will result in unpredictable values.
xTMn Counte� Registe� (Read only)
xTMnDL
xTMnDH
8-�it Buffe�
xTMnAL
xTMnAH
xTMn CCRA Registe� (Read/W�ite)
PTMnRPL PTMnRPH
PTMn CCRP Registe� (Read/W�ite)
Data Bus
The following steps show the read and write procedures:
• Writing Data to CCRA or CCRP
♦♦
Step 1. Write data to Low Byte xTMnAL or PTMnRPL
––note that here data is only written to the 8-bit buffer.
♦♦
Step 2. Write data to High Byte xTMnAH or PTMnRPH
––here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA or CCRP
Rev. 1.10
♦♦
Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH
––here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦
Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL
––this step reads data from the 8-bit buffer.
110
December 15, 2016
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Enhanced Touch Voice A/D Flash MCU
Compact Type TM – CTM
Although the simplest form of the TM types, the Compact TM type still contains three operating
modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The
Compact TM can also be controlled with an external input pin and can drive two external output pin.
Device
CTM Core
CTM Input Pin
CTM Output Pin
Note
BS66FV340
10-bit CTM
(CTM0)
CTCK0
CTP0, CTP0B
n=0
BS66FV350
BS66FV360
10-bit CTM
(CTM0, CTM1)
CTCK0, CTCK1
CTP0, CTP0B
CTP1, CTP1B
n=0~1
CCRP
fSYS/4
fSYS
fH/1�
fH/�4
fSUB
fSUB
3-�it Co�pa�ato� P
001
�7~�9
011
10-�it Count-up Counte�
100
101
111
CTnON
CTnPAU
�0~�9
10-�it Co�pa�ato� A
CTMnPF Inte��upt
CTnOC
010
110
CTCKn
Co�pa�ato� P Mat�h
000
Counte� Clea�
0
1
CTnCCLR
Co�pa�ato� A Mat�h
Output
Cont�ol
Pola�ity
Cont�ol
Pin
Cont�ol
CTnM1� CTnM0
CTnIO1� CTnIO0
CTnPOL
PxSn
CTPn
CTPnB
CTMnAF Inte��upt
CTnCK�~CTnCK0
CCRA
Compact Type TM Block Diagram – n = 0 or 1
Compact TM Operation
The Compact TM core is a 10-bit count-up counter which is driven by a user selectable internal or
external clock source. There are also two internal comparators with the names, Comparator A and
Comparator P. These comparators will compare the value in the counter with CCRP and CCRA
registers. The CCRP is three-bit wide whose value is compared with the highest three bits in the
counter while the CCRA is ten-bit wide and therefore compares with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the CTnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Compact
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
Rev. 1.10
111
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Compact Type TM Register Description
Overall operation of the Compact TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes and as well as the three CCRP bits.
Bit
Register
Name
7
6
5
4
3
CTMnC0
CTnPAU
CTnCK2
CTnCK1
CTnCK0
CTnON
CTnRP2 CTnRP1
CTMnC1
CTnM1
CTnM0
CTnIO1
CTnIO0
CTnOC
CTnPOL CTnDPX CTnCCLR
CTMnDL
D7
D6
D5
D4
D3
D2
D1
D0
CTMnDH
—
—
—
—
—
—
D9
D8
CTMnAL
D7
D6
D5
D4
D3
D2
D1
D0
CTMnAH
—
—
—
—
—
—
D9
D8
2
1
0
CTnRP0
10-bit Compact TM Registers List – n = 0 or 1
CTMnDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
CTMn Counter Low Byte Register bit 7 ~ bit 0
CTMn 10-bit Counter bit 7 ~ bit 0
CTMnDH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
CTMn Counter High Byte Register bit 1 ~ bit 0
CTMn 10-bit Counter bit 9 ~ bit 8
CTMnAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
1
0
Bit 7~0
CTMn CCRA Low Byte Register bit 7 ~ bit 0
CTMn 10-bit CCRA bit 7 ~ bit 0
CTMnAH Register
Rev. 1.10
Bit
7
6
5
4
3
2
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
CTMn CCRA High Byte Register bit 1 ~ bit 0
CTMn 10-bit CCRA bit 9 ~ bit 8
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December 15, 2016
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Enhanced Touch Voice A/D Flash MCU
CTMnC0 Register
Bit
7
6
5
4
3
2
1
0
Name
CTnPAU
CTnCK2
CTnCK1
CTnCK0
CTnON
CTnRP2
CTnRP1
CTnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
CTnPAU: CTMn Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the CTMn will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4
CTnCK2~CTnCK0: Select CTMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: CTCKn rising edge clock
111: CTCKn falling edge clock
These three bits are used to select the clock source for the CTMn. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which
can be found in the oscillator section.
Bit 3
CTnON: CTMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the CTMn. Setting the bit high enables
the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero
will stop the counter from counting and turn off the CTMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value will
be reset to zero, however when the bit changes from high to low, the internal counter will
retain its residual value until the bit returns high again. If the CTMn is in the Compare
Match Output Mode then the CTMn output pin will be reset to its initial condition, as
specified by the CTnOC bit, when the CTnON bit changes from low to high.
CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn Counter
bit 9 ~ bit 7
000: 1024 CTMn clocks
001: 128 CTMn clocks
010: 256 CTMn clocks
011: 384 CTMn clocks
100: 512 CTMn clocks
101: 640 CTMn clocks
110: 768 CTMn clocks
111: 896 CTMn clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter’s highest three bits. The result of this
comparison can be selected to clear the internal counter if the CTnCCLR bit is set to
zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
Bit 2~0
Rev. 1.10
113
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
CTMnC1 Register
Rev. 1.10
Bit
7
6
5
4
3
Name
CTnM1
CTnM0
CTnIO1
CTnIO0
CTnOC
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
CTnPOL CTnDPX CTnCCLR
Bit 7~6
CTnM1~CTnM0: Select CTMn Operating Mode
00: Compare Match Output Mode
01: Undefined
10: PWM Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the CTMn. To ensure reliable
operation the CTMn should be switched off before any changes are made to the
CTnM1 and CTnM0 bits. In the Timer/Counter Mode, the CTMn output pin control
will be disabled.
Bit 5~4
CTnIO1~CTnIO0: Select CTMn external pin (CTPn) function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Undefined
Timer/Counter Mode
Unused
These two bits are used to determine how the CTMn output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the CTMn is running.
In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the
CTMn output pin changes state when a compare match occurs from the Comparator A.
The CTMn output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the CTMn
output pin should be setup using the CTnOC bit in the CTMnC1 register. Note that
the output level requested by the CTnIO1 and CTnIO0 bits must be different from the
initial value setup using the CTnOC bit otherwise no change will occur on the CTMn
output pin when a compare match occurs. After the CTMn output pin changes state,
it can be reset to its initial level by changing the level of the CTnON bit from low to
high.
In the PWM Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output
pin changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to only change the
values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched off.
Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed
when the CTMn is running.
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Rev. 1.10
Bit 3
CTnOC: CTPn Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode
0: Active low
1: Active high
This is the output control bit for the CTMn output pin. Its operation depends upon
whether CTMn is being used in the Compare Match Output Mode or in the PWM
Mode. It has no effect if the CTMn is in the Timer/Counter Mode. In the Compare
Match Output Mode it determines the logic level of the CTMn output pin before a
compare match occurs. In the PWM Mode it determines if the PWM signal is active
high or active low.
Bit 2
CTnPOL: CTPn Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the CTPn output pin. When the bit is set high the
CTMn output pin will be inverted and not inverted when the bit is zero. It has no effect
if the TM is in the Timer/Counter Mode.
Bit 1
CTnDPX: CTMn PWM duty/period control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0
CTnCCLR: CTMn Counter Clear condition selection
0: CTMn Comparator P match
1: CTMn Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the CTnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The CTnCCLR bit is not
used in the PWM Mode.
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Compact Type TM Operation Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Mode or Timer/Counter Mode. The operating mode is selected using the CTnM1 and CTnM0
bits in the CTMnC1 register.
Compare Match Output Mode
To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register, should be set to "00"
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the CTnCCLR bit is low, there are two ways in which the counter can
be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP
bits are all zero which allows the counter to overflow. Here both CTMnAF and CTMnPF interrupt
request flags for the Comparator A and Comparator P respectively, will both be generated.
If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the CTMnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
CTnCCLR is high no CTMnPF interrupt request flag will be generated. If the CCRA bits are all
zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here
the CTMnAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the CTMn output pin will change
state. The CTMn output pin condition however only changes state when a CTMnAF interrupt
request flag is generated after a compare match occurs from Comparator A. The CTMnPF interrupt
request flag, generated from a compare match occurs from Comparator P, will have no effect on
the CTMn output pin. The way in which the CTMn output pin changes state are determined by
the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register. The CTMn output pin can
be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present
condition when a compare match occurs from Comparator A. The initial condition of the CTMn
output pin, which is setup after the CTnON bit changes from low to high, is setup using the CTnOC
bit. Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place.
Rev. 1.10
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Counter Value
Counter overflow
CCRP=0
0x3FF
CTnCCLR = 0; CTnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
CTnON
CTnPAU
CTnPOL
CCRP Int. flag
CTMnPF
CCRA Int. flag
CTMnAF
CTMn O/P Pin
Output pin set to
initial Level Low
if CTnOC=0
Output not affected by CTMnAF
flag. Remains High until reset by
CTnON bit
Output Toggle with
CTMnAF flag
Here CTnIO [1:0] = 11
Toggle Output select
Note CTnIO [1:0] = 10
Active High Output select
Output Inverts
when CTnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – CTnCCLR = 0
Note: 1. With CTnCCLR = 0, a Comparator P match will clear the counter
2. The CTMn output pin controlled only by CTMnAF flag
3. The output pin is reset to its initial state by CTnON bit rising edge
4. n = 0 or 1
Rev. 1.10
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Counter Value
CTnCCLR = 1; CTnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
Resume
CCRA
Pause
CCRA=0
Stop
Counter Restart
CCRP
Time
CTnON
CTnPAU
CTnPOL
No CTMnAF flag
generated on
CCRA overflow
CCRA Int. flag
CTMnAF
CCRP Int. flag
CTMnPF
CTMn
O/P Pin
CTMnPF not
generated
Output pin set to
initial Level Low
if CTnOC=0
Output does
not change
Output not affected by
CTMnAF flag. Remains High
until reset by CTnON bit
Output Toggle with
CTMnAF flag
Here CTnIO [1:0] = 11
Toggle Output select
Note CTnIO [1:0] = 10
Active High Output select
Output Inverts
when CTnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – CTnCCLR = 1
Note: 1. With CTnCCLR = 1, a Comparator A match will clear the counter
2. The CTMn output pin is controlled only by CTMnAF flag
3. The CTMn output pin is reset to initial state by CTnON rising edge
4. The CTMnPF flags is not generated when CTnCCLR = 1
5. n = 0 or 1
Rev. 1.10
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Timer/Counter Mode
To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
CTMn output pin is not used. Therefore the above description and Timing Diagrams for the
Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not
used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 10
respectively. The PWM function within the CTMn is useful for applications which require functions
such as motor control, heating control, illumination control etc. By providing a signal of fixed
frequency but of varying duty cycle on the CTMn output pin, a square wave AC waveform can be
generated with varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the CTnCCLR bit has no effect on the PWM
operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the CTnDPX bit in the CTMnC1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The CTnOC bit in the CTMnC1 register is used
to select the required polarity of the PWM waveform while the two CTnIO1 and CTnIO0 bits are
used to enable the PWM output or to force the TM output pin to a fixed high or low level. The
CTnPOL bit is used to reverse the polarity of the PWM output waveform.
• 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=0
CCRP
1~7
Period
CCRPx128
Duty
0
1024
CCRA
If fSYS = 16MHz, CTMn clock source is fSYS/4, CCRP = 2 and CCRA = 128,
The CTMn PWM output frequency = (fSYS/4)/(2x128) = fSYS/1024 = 16 kHz, duty = 128/(2x128)= 50%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=1
CCRP
1~7
Period
0
CCRA
CCRPx128
Duty
1024
The PWM output period is determined by the CCRA register value together with the CTMn clock
while the PWM duty cycle is defined by the CCRP register value.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Counter Value
CTnDPX = 0; CTnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
CTnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
CTnON bit low
Time
CTnON
CTnPAU
CTnPOL
CCRA Int. flag
CTMnAF
CCRP Int. flag
CTMnPF
CTMn O/P Pin
(CTnOC=1)
CTMn O/P Pin
(CTnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when CTnPOL = 1
PWM Output Mode – CTnDXP = 0
Note: 1. Here CTnDPX = 0 – Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues even when CTnIO1, CTnIO0 = 00 or 01
4. The CTnCCLR bit has no influence on PWM operation
5. n = 0 or 1
Rev. 1.10
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Counter Value
CTnDPX = 1; CTnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
CTnON returns high
CCRA
Pause Resume
CCRP
Counter Stop if
CTnON bit low
Time
CTnON
CTnPAU
CTnPOL
CCRP Int.
flag CTMnPF
CCRA Int.
flag CTMnAF
CTMn O/P
Pin (CTnOC=1)
CTMn O/P
Pin (CTnOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when CTnPOL = 1
PWM Output Mode – CTnDXP = 1
Note: 1. Here CTnDPX = 1 – Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when CTnIO [1:0] = 00 or 01
4. The CTnCCLR bit has no influence on PWM operation
5. n = 0 or 1
Rev. 1.10
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Standard Type TM – STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can
also be controlled with two external input pins and can drive two external output pin.
Device
STM Core
STM Input Pin
STM Output Pin
BS66FV340
BS66FV350
BS66FV360
16-bit STM
(STM)
STCK, STPI
STP, STPB
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fSUB
8-bit Comparator P
001
STMPF Interrupt
STOC
b8~b15
010
011
16-bit Count-up Counter
100
101
110
STCK
Comparator P Match
000
STON
STPAU
Counter Clear
0
1
STCCLR
b0~b15
111
STCK2~STCK0
16-bit Comparator A
Output
Control
Polarity
Control
Pin
Control
STM1, STM0
STIO1, STIO0
STPOL
PxSn
Comparator A Match
STP
STPB
STMAF Interrupt
STIO1, STIO0
Edge
Detector
CCRA
STPI
Standard Type TM Block Diagram
Standard TM Operation
The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by
a user selectable internal or external clock source. There are also two internal comparators with the
names, Comparator A and Comparator P. These comparators will compare the value in the counter
with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the
with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all
counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the STON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a STM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. The STMRP register is used to store the 8-bit CCRP value. The
remaining two registers are control registers which setup the different operating and control modes.
Bit
Register
Name
7
6
5
4
3
2
1
0
STMC0
STPAU
STCK2
STCK1
STCK0
STON
—
—
—
STMC1
STM1
STM0
STIO1
STIO0
STOC
STPOL
STDPX
STCCLR
STMDL
D7
D6
D5
D4
D3
D2
D1
D0
STMDH
D15
D14
D13
D12
D11
D10
D9
D8
STMAL
D7
D6
D5
D4
D3
D2
D1
D0
STMAH
D15
D14
D13
D12
D11
D10
D9
D8
STMRP
STRP7
STRP6
STRP5
STRP4
STRP3
STRP2
STRP1
STRP0
16-bit Standard TM Registers List
STMDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
STM Counter Low Byte Register bit 7 ~ bit 0
STM 16-bit Counter bit 7 ~ bit 0
STMDH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
STM Counter High Byte Register bit 7 ~ bit 0
STM 16-bit Counter bit 15 ~ bit 8
STMAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
STM CCRA Low Byte Register bit 7 ~ bit 0
STM 16-bit CCRA bit 7 ~ bit 0
STMAH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.10
STM CCRA High Byte Register bit 7 ~ bit 0
STM 16-bit CCRA bit 15 ~ bit 8
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Enhanced Touch Voice A/D Flash MCU
STMC0 Register
Bit
7
6
5
4
3
2
1
0
Name
STPAU
STCK2
STCK1
STCK0
STON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
STPAU: STM Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the STM will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4
STCK2~STCK0: Select STM Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: STCK rising edge clock
111: STCK falling edge clock
These three bits are used to select the clock source for the STM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fSUB are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3
STON: STM Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the STM. Setting the bit high enables
the counter to run while clearing the bit disables the STM. Clearing this bit to zero
will stop the counter from counting and turn off the STM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the STM is in
the Compare Match Output Mode then the STM output pin will be reset to its initial
condition, as specified by the STOC bit, when the STON bit changes from low to high.
Bit 2~0
Unimplemented, read as "0"
STMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
STM1
STM0
STIO1
STIO0
STOC
STPOL
STDPX
STCCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Rev. 1.10
STM1~STM0: Select STM Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the STM. To ensure reliable operation
the STM should be switched off before any changes are made to the STM1 and STM0
bits. In the Timer/Counter Mode, the STM output pin control will be disabled.
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Rev. 1.10
Bit 5~4
STIO1~STIO0: Select STM external pin (STP or STPI) function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single Pulse Output
Capture Input Mode
00: Input capture at rising edge of STPI
01: Input capture at falling edge of STPI
10: Input capture at rising/falling edge of STPI
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the STM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the STM is running.
In the Compare Match Output Mode, the STIO1 and STIO0 bits determine how the
STM output pin changes state when a compare match occurs from the Comparator
A. The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the STM output
pin should be setup using the STOC bit in the STMC1 register. Note that the output
level requested by the STIO1 and STIO0 bits must be different from the initial value
setup using the STOC bit otherwise no change will occur on the STM output pin when
a compare match occurs. After the STM output pin changes state, it can be reset to its
initial level by changing the level of the STON bit from low to high.
In the PWM Mode, the STIO1 and STIO0 bits determine how the STM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to only change the
values of the STIO1 and STIO0 bits only after the STM has been switched off.
Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed
when the STM is running.
Bit 3
STOC: STM STP Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the STM output pin. Its operation depends upon
whether STM is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the STM
output pin before a compare match occurs. In the PWM Mode/Single Pulse Output
Mode it determines if the PWM signal is active high or active low.
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Bit 2
STPOL: STM STP Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the STP output pin. When the bit is set high the STM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
STM is in the Timer/Counter Mode.
Bit 1
STDPX: STM PWM duty/period control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0
STCCLR: STM Counter Clear condition selection
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the STCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
STMRP Register
Bit
7
6
5
4
3
2
1
0
Name
STRP7
STRP6
STRP5
STRP4
STRP3
STRP2
STRP1
STRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.10
STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit 15~bit 8
Comparator P match period =
0: 65536 STM clocks
1~255: (1~255) x 256 STM clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the STCCLR bit is set to
zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
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Enhanced Touch Voice A/D Flash MCU
Standard Type TM Operation Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the STM1 and STM0 bits in the STMC1 register.
Compare Match Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to "0".
As the name of the mode suggests, after a comparison is made, the STM output pin, will change
state. The STM output pin condition however only changes state when a STMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STM
output pin. The way in which the STM output pin changes state are determined by the condition of
the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the
STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the STM output pin, which is setup after
the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and
STIO0 bits are zero then no pin change will take place.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Counter Value
Counter overflow
CCRP=0
0xFFFF
STCCLR = 0; STM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
STON
STPAU
STPOL
CCRP Int.
flag STMPF
CCRA Int.
flag STMAF
STM O/P Pin
Output pin set to
initial Level Low
if STOC=0
Output not affected by STMAF
flag. Remains High until reset by
STON bit
Output Toggle with
STMAF flag
Here STIO [1:0] = 11
Toggle Output select
Note STIO [1:0] = 10
Active High Output select
Output Inverts
when STPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – STCCLR = 0
Note: 1. With STCCLR=0 a Comparator P match will clear the counter
2. The STMn output pin is controlled only by the STMAF flag
3. The output pin is reset to its initial state by a STON bit rising edge
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Counter Value
STCCLR = 1; STM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0xFFFF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
STON
STPAU
STPOL
No STMAF flag
generated on
CCRA overflow
CCRA Int.
flag STMAF
CCRP Int.
flag STMPF
STM O/P Pin
STMPF not
generated
Output pin set to
initial Level Low
if STOC=0
Output does
not change
Output Toggle with
STMAF flag
Here STIO [1:0] = 11
Toggle Output select
Output not affected by
STMAF flag. Remains High
until reset by STON bit
Note STIO [1:0] = 10
Active High Output select
Output Inverts
when STPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode –STCCLR = 1
Note: 1. With STCCLR=1 a Comparator A match will clear the counter
2. The STM output pin is controlled only by the STMAF flag
3. The output pin is reset to its initial state by a STON bit rising edge
4. A STMPF flag is not generated when STCCLR=1
Rev. 1.10
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Timer/Counter Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM
output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively
and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within
the STM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty
cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to
select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to
enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit
is used to reverse the polarity of the PWM output waveform.
• 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0
CCRP
1~255
0
Period
CCRPx256
65536
Duty
CCRA
If fSYS = 16MHz, STM clock source is fSYS/4, CCRP = 2 and CCRA = 128,
The STM PWM output frequency = (fSYS/4) / (2x256) = fSYS/2048 = 8 kHz, duty = 128/(2x256)= 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1
CCRP
1~255
Period
0
CCRA
CCRPx256
Duty
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is
equal to 0.
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Enhanced Touch Voice A/D Flash MCU
Counter Value
STDPX = 0; STM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
STON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
STON bit low
Time
STON
STPAU
STPOL
CCRA Int.
flag STMAF
CCRP Int.
flag STMPF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when STPOL = 1
PWM Output Mode – STDXP = 0
Note: 1. Here STDPX=0 – Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when STIO [1:0] = 00 or 01
4. The STCCLR bit has no influence on PWM operation
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Counter Value
STDPX = 1; STM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
STON returns high
CCRA
Pause Resume
CCRP
Counter Stop if
STON bit low
Time
STON
STPAU
STPOL
CCRP Int.
flag STMPF
CCRA Int.
flag STMAF
STM O/P
Pin (STOC=1)
STM O/P
Pin (STOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when STPOL = 1
PWM Output Mode – STDXP = 1
Note: 1. Here STDPX=1 – Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when STIO [1:0] = 00 or 01
4. The STCCLR bit has no influence on PWM operation
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Single Pulse Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively
and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode,
as the name suggests, will generate a single shot pulse on the STM output pin.
The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the STON bit
can also be made to automatically change from low to high using the external STCK pin, which will
in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The STON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
STON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the STON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter
can only be reset back to zero when the STON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in
this Mode.
S/W Command
SET“STON”
or
STCK Pin
Transition
CCRA
Leading Edge
CCRA
Trailing Edge
STON bit
0à1
STON bit
1à0
S/W Command
CLR“STON”
or
CCRA Compare
Match
STP Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Counter Value
STM [1:0] = 10 ; STIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
STON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
STON
Software
Trigger
Auto. set by
STCK pin
Cleared by
CCRA match
STCK pin
Software
Trigger
Software
Clear
Software
Trigger
Software
Trigger
STCK pin
Trigger
STPAU
STPOL
No CCRP Interrupts
generated
CCRP Int. Flag
STMPF
CCRA Int. Flag
STMAF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
Output Inverts
when STPOL = 1
Pulse Width
set by CCRA
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse triggered by the STCK pin or by setting the STON bit high
4. A STCK pin active edge will automatically set the STON bit high.
5. In the Single Pulse Mode, STIO [1:0] must be set to "11" and can not be changed.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Capture Input Mode
To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal
is supplied on the STPI pin, whose active edge can be a rising edge, a falling edge or both rising
and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in
the STMC1 register. The counter is started when the STON bit changes from low to high which is
initiated using the application program.
When the required edge transition appears on the STPI pin the present value in the counter will be
latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur
on the STPI pin the counter will continue to free run until the STON bit changes from high to low.
When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP
value can be used to control the maximum counter value. When a CCRP compare match occurs
from Comparator P, a STM interrupt will also be generated. Counting the number of overflow
interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1
and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or
both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take
place irrespective of what happens on the STPI pin, however it must be noted that the counter will
continue to run. The STCCLR and STDPX bits are not used in this Mode.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Counter Value
STM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
STON
STPAU
Active
edge
Active
edge
Active edge
STM capture
pin STPI
CCRA Int. Flag
STMAF
CCRP Int. Flag
STMPF
CCRA
Value
STIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. STM [1:0] = 01 and active edge set by the STIO [1:0] bits
2. A STM Capture input pin active edge transfers the counter value to CCRA
3. STCCLR bit not used
4. No output function -- STOC and STPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when
CCRP is equal to zero.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Periodic Type TM – PTM
The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
also be controlled with two external input pins and can drive two external output pin.
Device
PTM Core
PTM Input Pin
PTM Output Pin
BS66FV340
BS66FV350
BS66FV360
10-bit PTM
(PTM0, PTM1)
PTCK0, PTP0I
PTCK1, PTP1I
PTP0, PTP0B
PTP1, PTP1B
CCRP
fSYS/4
fSYS
fH/1�
fH/�4
fSUB
fSUB
10-�it Co�pa�ato� P
001
PTMnPF Inte��upt
PTnOC
�0~�9
010
011
10-�it Count-up Counte�
100
101
110
PTCKn
Co�pa�ato� P Mat�h
000
PTnON
PTnPAU
�0~�9
111
PTnCK�~PTnCK0
10-�it Co�pa�ato� A
CCRA
Counte� Clea�
Output
Cont�ol
Pola�ity
Cont�ol
Pin
Cont�ol
PTnM1� PTnM0
PTnIO1� PTnIO0
PTnPOL
PxSn
0
1
PTnCCLR
Co�pa�ato� A Mat�h
PTPn
PTPnB
PTMnAF Inte��upt
IFS
PTnIO1� PTnIO0
PTnCAPTS
Edge
Dete�to�
0
1
Pin
Cont�ol
PTPnI
Periodic Type TM Block Diagram – n = 0 or 1
Periodic TM Operation
The size of Periodic TM is 16-bit wide and its core is a 10-bit count-up counter which is driven by
a user selectable internal or external clock source. There are also two internal comparators with the
names, Comparator A and Comparator P. These comparators will compare the value in the counter
with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is
respectively compared with all counter bits.
The only way of changing the value of the 10-bit counter using the application program is to
clear the counter by changing the PTnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pins. All operating setup conditions
are selected using relevant internal registers.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Periodic Type TM Register Description
Overall operation of the Periodic TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which
setup the different operating and control modes.
Bit
Register
Name
7
6
5
4
3
2
1
0
PTMnC0
PTnPAU PTnCK2
PTnCK1
PTnCK0
PTnON
—
—
—
PTMnC1
PTnM1
PTnM0
PTnIO1
PTnIO0
PTnOC
PTMnDL
D7
D6
D5
D4
D3
PTnPOL PTnCAPTS PTnCCLR
D2
D1
D0
D8
PTMnDH
—
—
—
—
—
—
D9
PTMnAL
D7
D6
D5
D4
D3
D2
D1
D0
PTMnAH
—
—
—
—
—
—
D9
D8
PTMnRPL
PTnRP7
PTnRP6
PTnRP5
PTnRP4
PTMnRPH
—
—
—
—
PTnRP3 PTnRP2
—
—
PTnRP1
PTnRP0
PTnRP9
PTnRP8
Periodic TM Registers List – n = 0 or 1
PTMnDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTMn Counter Low Byte Register bit 7 ~ bit 0
PTMn 10-bit Counter bit 7 ~ bit 0
PTMnDH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
PTMn Counter High Byte Register bit 1 ~ bit 0
PTMn 10-bit Counter bit 9 ~ bit 8
PTMnAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.10
PTMn CCRA Low Byte Register bit 7 ~ bit 0
PTMn 10-bit CCRA bit 7 ~ bit 0
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Enhanced Touch Voice A/D Flash MCU
PTMnAH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Bit 1~0
Unimplemented, read as "0"
PTMn CCRA High Byte Register bit 1 ~ bit 0
PTMn 10-bit CCRA bit 9 ~ bit 8
PTMnRPL Register
Bit
7
6
5
4
3
2
1
0
Name
PTnRP7
PTnRP6
PTnRP5
PTnRP4
PTnRP3
PTnRP2
PTnRP1
PTnRP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTnRP7~PTnRP0: PTMn CCRP Low Byte Register bit 7 ~ bit 0
PTMn 10-bit CCRP bit 7 ~ bit 0
PTMnRPH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PTnRP9
PTnRP8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
PTnRP9~PTnRP8: PTMn CCRP High Byte Register bit 1 ~ bit 0
PTMn 10-bit CCRP bit 9 ~ bit 8
PTMnC0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
PTnPAU
PTnCK2
PTnCK1
PTnCK0
PTnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
PTnPAU: PTMn Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the PTMn will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4
PTnCK2~PTnCK0: Select PTMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fSUB
110: PTCKn rising edge clock
111: PTCKn falling edge clock
These three bits are used to select the clock source for the PTMn. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which
can be found in the oscillator section.
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Enhanced Touch Voice A/D Flash MCU
Bit 3
PTnON: PTMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the PTMn. Setting the bit high enables
the counter to run while clearing the bit disables the PTMn. Clearing this bit to zero
will stop the counter from counting and turn off the PTMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value will
be reset to zero, however when the bit changes from high to low, the internal counter will
retain its residual value until the bit returns high again. If the PTMn is in the Compare
Match Output Mode then the PTMn output pin will be reset to its initial condition, as
specified by the PTnOC bit, when the PTnON bit changes from low to high.
Bit 2~0
Unimplemented, read as "0"
PTMnC1 Register
Rev. 1.10
Bit
7
6
5
4
3
Name
PTnM1
PTnM0
PTnIO1
PTnIO0
PTnOC
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PTnPOL PTnCAPTS
0
PTnCCLR
Bit 7~6
PTnM1~PTnM0: Select PTMn Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the PTMn. To ensure reliable
operation the PTMn should be switched off before any changes are made to the
PTnM1 and PTnM0 bits. In the Timer/Counter Mode, the PTMn output pin control
will be disabled.
Bit 5~4
PTnIO1~PTnIO0: Select PTMn external pin PTPn or PTPnI function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single Pulse Output
Capture Input Mode
00: Input capture at rising edge of PTPnI or PTCKn
01: Input capture at falling edge of PTPnI or PTCKn
10: Input capture at rising/falling edge of PTPnI or PTCKn
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the PTMn output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the PTMn is running.
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In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the
PTMn output pin changes state when a compare match occurs from the Comparator A.
The PTMn output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the PTMn
output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that
the output level requested by the PTnIO1 and PTnIO0 bits must be different from the
initial value setup using the PTnOC bit otherwise no change will occur on the PTMn
output pin when a compare match occurs. After the PTMn output pin changes state,
it can be reset to its initial level by changing the level of the PTnON bit from low to
high.
In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PTMn output
function is modified by changing these two bits. It is necessary to only change the
values of the PTnIO1 and PTnIO0 bits only after the PTMn has been switched off.
Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed
when the PTMn is running.
Rev. 1.10
Bit 3
PTnOC: PTMn PTPn Output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the PTMn output pin. Its operation depends upon
whether PTMn is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the PTMn is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the PTMn
output pin before a compare match occurs. In the PWM Mode/Single Pulse Output
Mode it determines if the PWM signal is active high or active low.
Bit 2
PTnPOL: PTMn PTPn Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the PTPn output pin. When the bit is set high the
PTMn output pin will be inverted and not inverted when the bit is zero. It has no effect
if the PTMn is in the Timer/Counter Mode.
Bit 1
PTnCAPTS: PTMn Capture Trigger Source selection
0: From PTPnI pin
1: From PTCKn pin
Bit 0
PTnCCLR: PTMn Counter Clear condition selection
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the PTnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
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Periodic Type TM Operation Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register.
Compare Match Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both PTMnAF and PTMnPF interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMnAF interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match
Output Mode, the CCRA can not be set to "0".
As the name of the mode suggests, after a comparison is made, the PTMn output pin will change
state. The PTMn output pin condition however only changes state when a PTMnAF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the PTMn
output pin. The way in which the PTMn output pin changes state are determined by the condition of
the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The PTMn output pin can be selected using
the PTnIO1 and PTnIO0 bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the PTMn output pin, which is
setup after the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the
PTnIO1 and PTnIO0 bits are zero then no pin change will take place.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Counter Value
Counter overflow
CCRP=0
0x3FF
PTnCCLR = 0; PTnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
PTnON
PTnPAU
PTnPOL
CCRP Int. Flag
PTMnPF
CCRA Int. Flag
PTMnAF
PTMn
O/P Pin
Output pin set to
initial Level Low
if PTnOC=0
Output not affected by
PTMnAF flag. Remains High
until reset by PTnON bit
Output Toggle with
PTMnAF flag
Here PTnIO [1:0] = 11
Toggle Output select
Note PTnIO [1:0] = 10
Active High Output select
Output Inverts
when PTnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – PTnCCLR = 0
Note: 1. With PTnCCLR=0, a Comparator P match will clear the counter
2. The PTMn output pin is controlled only by the PTMnAF flag
3. The output pin is reset to its initial state by a PTnON bit rising edge
4. n = 0 or 1
Rev. 1.10
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Counter Value
PTnCCLR = 1; PTnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
PTnON
PTnPAU
PTnPOL
No PTMnAF flag
generated on
CCRA overflow
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
PTMn
O/P Pin
PTMPF not
generated
Output pin set to
initial Level Low
if PTnOC=0
Output does
not change
Output Toggle with
PTMnAF flag
Here PTnIO [1:0] = 11
Toggle Output select
Output not affected by PTMnAF
flag. Remains High until reset
by PTnON bit
Note PTnIO [1:0] = 10
Active High Output select
Output Inverts
when PTnPOL is
Output Pin
high
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – PTnCCLR = 1
Note: 1. With PTnCCLR=1, a Comparator A match will clear the counter
2. The PTMn output pin is controlled only by the PTMnAF flag
3. The output pin is reset to its initial state by a PTnON bit rising edge
4. A PTMnPF flag is not generated when PTnCCLR =1
5. n = 0 or 1
Rev. 1.10
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Timer/Counter Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
PTMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the PTMn output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively
and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within
the PTMn is useful for applications which require functions such as motor control, heating control,
illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the
PTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the PTnCCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore
be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used
to select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are
used to enable the PWM output or to force the PTMn output pin to a fixed high or low level. The
PTnPOL bit is used to reverse the polarity of the PWM output waveform.
• 10-bit PTMn, PWM Mode,
CCRP
1~1023
Period
1~1023
Duty
0
1024
CCRA
If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128,
The PTMn PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 8kHz, duty=128/512=25%,
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
Rev. 1.10
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Counter Value
PTnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
PTnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
PTnON bit low
Time
PTnON
PTnPAU
PTnPOL
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
PTMn O/P Pin
(PTnOC=1)
PTMn O/P Pin
(PTnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
When PTnPOL = 1
PWM Mode
Note: 1. The counter is cleared by CCRP.
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PTnIO [1:0] = 00 or 01
4. The PTnCCLR bit has no influence on PWM operation
5. n = 0 or 1
Rev. 1.10
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Single Pulse Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10
respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin.
The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the PTnON
bit can also be made to automatically change from low to high using the external PTCKn pin,
which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The PTnON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the PTnON bit is cleared to zero, which can be implemented using the application program or
when a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PTnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter
can only be reset back to zero when the PTnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR is not used in this Mode.
S/W Command
SET“PTnON”
or
PTCKn Pin
Transition
CCRA
Leading Edge
CCRA
Trailing Edge
PTnON bit
0à1
PTnON bit
1à0
S/W Command
CLR“PTnON”
or
CCRA Compare
Match
PTPn Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.10
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Counter Value
PTnM [1:0] = 10 ; PTnIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
PTnON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
PTnON
Software
Trigger
Auto. set by
PTCKn pin
Cleared by
CCRA match
PTCKn pin
Software
Trigger
Software
Trigger
Software
Clear
Software
Trigger
PTCKn pin
Trigger
PTnPAU
PTnPOL
No CCRP Interrupts
generated
CCRP Int. Flag
PTMnPF
CCRA Int. Flag
PTMnAF
PTMn O/P Pin
(PTnOC=1)
PTMn O/P Pin
(PTnOC=0)
Pulse Width
set by CCRA
Output Inverts
when PTnPOL = 1
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse triggered by the PTCKn pin or by setting the PTnON bit high
4. A PTCKn pin active edge will automatically set the PTnON bit high.
5. In the Single Pulse Mode, PTnIO [1:0] must be set to "11" and can not be changed.
6. n = 0 or 1
Rev. 1.10
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Capture Input Mode
To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the PTPnI or PTCKn pin, selected by the PTnCAPTS bit in the PTMnC1 register. The
input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the
active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register.
The counter is started when the PTnON bit changes from low to high which is initiated using the
application program.
When the required edge transition appears on the PTPnI or PTCKn pin the present value in the
counter will be latched into the CCRA registers and a PTMn interrupt generated. Irrespective of
what events occur on the PTPnI or PTCKn pin the counter will continue to free run until the PTnON
bit changes from high to low. When a CCRP compare match occurs the counter will reset back to
zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP
compare match occurs from Comparator P, a PTMn interrupt will also be generated. Counting the
number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse
widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin
to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high,
then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin,
however it must be noted that the counter will continue to run.
As the PTPnI or PTCKn pin is pin shared with other functions, care must be taken if the PTMn is in
the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this
pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits
are not used in this Mode.
Rev. 1.10
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Counter Value
PTnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
PTnON
PTnPAU
Active
edge
Active
edge
Active edge
PTMn capture pin
PTPnI or PTCKn
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
CCRA
Value
PTnIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. PTnM [1:0] = 01 and active edge set by the PTnIO [1:0] bits
2. A PTMn Capture input pin active edge transfers the counter value to CCRA
3. PTnCCLR bit not used
4. No output function – PTnOC and PTnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when
CCRP is equal to zero.
6. n = 0 or 1
Rev. 1.10
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Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Converter Overview
These devices contain a multi-channel analog to digital converter which can directly interface to
external analog signals, such as that from sensors or other control signals and convert these signals
directly into a 12-bit digital value. It also can convert the internal signals, such as the temperature
sensor output, into a 12-bit digital value. The external or internal analog signal to be converted is
determined by the SAINS and SACS bit fields. Note that when the internal analog signal is to be
converted, the corresponding pin-shared control bits should first be properly configured and then
the desired internal analog signal should be selected using the SAINS and SACS bit fields. More
detailed information about the A/D input signal selection will be described in the "A/D Converter
Control Registers" and "A/D Converter Input Signals sections respectively.
This A/D converter also includes a temperature sensor circuitry which contains a temperature
sensor, operational amplifiers and an internal reference voltage. The temperature sensor will detect
the temperature and output a voltage proportional to the temperature. The output voltage can be
amplified by the OPA and then converted to a 12-bit digital data using the A/D converter.
The accompanying block diagram shows the internal structure of the A/D converter with temperature
sensor together with its associated registers and control bits.
Device
External Input Channels
Internal Signal
A/D Signal Select
BS66FV340
BS66FV350
BS66FV360
8: AN0~AN7
2: VBG, VTSO
SAINS2~SAINS0
SACS3~SACS0
VDD
fSYS
SACKS�~SACKS0
Pin-sha�ed
Sele�tion SACS3~SACS0
÷ �N
(N=0~7)
ADCEN
VSS
A/D Clo�k
AN0
AN1
SADOL
A/D Conve�te�
AN7
SADOH
VVREF
SAINS�~SAINS0
ADBZ
START
A/D Data
Registe�s
ADRFS
A/D Conve�te�
Refe�en�e Voltage
VBG
VTSO
Gain=1.�7�
VTSVRI
Te�p.
Senso�
OPA1
VTSVREF
VDD
TSEN
OPA�
G�XEN
SAVRS1�
SAVRS0
VTSO
VREF
Pin-sha�ed
Sele�tion
Gain=4 o� �
A/D Converter with Temperature Sensor
Rev. 1.10
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Registers Descriptions
Overall operation of the A/D converter with Temperature sensor is controlled using five registers.
A read only register pair exists to store the A/D Converter data 12-bit value. Two registers, SADC0
and SADC1, are the control registers which setup the operating and control function of the A/
D converter. The SADC2 register is the temperature sensor control register which control the
temperature sensor and operational amplifier functions together with the gain selection.
Bit
Register
Name
7
6
5
4
3
2
1
0
SADOL
(ADRFS=0)
D3
D2
D1
D0
—
—
—
—
SADOL
(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
SADOH
(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
SADOH
(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
SADC0
START
ADBZ
ADCEN
ADRFS
SACS3
SACS2
SACS1
SACS0
SADC1
SAINS2
SAINS1
SAINS0
SAVRS1
SAVRS0
SADC2
—
—
—
—
—
SACKS2 SACKS1 SACKS0
—
G5XEN
TSEN
A/D Converter with Temperature Sensor Registers List
A/D Converter Data Registers – SADOL, SADOH
As these devices contain an internal 12-bit A/D converter, it requires two data registers to store the
converted value. These are a high byte register, known as SADOH, and a low byte register, known
as SADOL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits.
Any unused bits will be read as zero. The A/D data registers contents will be unchanged if the A/D
converter is disabled.
ADRFS
0
1
SADOH
7
6
D11 D10
0
0
SADOL
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Converter Data Registers
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
A/D Converter Control Registers – SADC0, SADC1, SADC2
To control the function and operation of the A/D converter, two control registers known as SADC0
and SADC1 are provided. These 8-bit registers define functions such as the selection of which
analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock
source as well as controlling the start function and monitoring the A/D converter busy status. As
these devices contain only one actual analog to digital converter hardware circuit, each of the
external and internal analog signals must be routed to the converter. The SACS3~SACS0 bits in
the SADC0 register are used to determine which external channel input is selected to be converted.
The SAINS2~SAINS0 bits in the SADC1 register are used to determine that the analog signal to be
converted comes from the external channel input or internal analog signal. If the SAINS2~SAINS0
bits are set to "000", the external channel input is selected to be converted and the SACS3~SACS0
bits can determine which external channel is selected. If the internal analog signal is selected to be
converted, the SACS3~SACS0 bits must be set to "1xxx" to switch off the external channel input.
Otherwise, the external channel input will be connected to the internal analog signal. This will result
in unpredictable situations.
SAINS [2:0]
SACS [3:0]
Input Signals
0000~0111
AN0~AN7
000, 101, 110
Description
External channel analog input
1xxx
—
Floating, no external channel is selected.
001
1xxx
VBG
Internal Bandgap reference voltage, VBG.
010
1xxx
VTSO
Temperature Sensor output voltage, VTSO.
011, 100
1xxx
GND
Connected to the ground.
111
xxxx
—
Forbidden to be used.
A/D Converter Input Signal Selection
The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog
inputs for the A/D converter input and which pins are not. When the pin is selected to be an A/
D input, its original function whether it is an I/O or other pin-shared function will be removed. In
addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin
is selected to be an A/D converter input.
SADC0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
START
ADBZ
ADCEN
ADRFS
SACS3
SACS2
SACS1
SACS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
START: Start the A/D Conversion
0→1→0: Start
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
Bit 6
ADBZ: A/D Converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to 0 after the A/D conversion is complete.
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Bit 5
ADCEN: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set to one to enable
the A/D converter. If the bit is set low, then the A/D converter will be switched off
reducing the device power consumption. When the A/D converter function is disabled,
the contents of the A/D data register pair known as SADOH and SADOL will be
unchanged.
Bit 4
ADRFS: A/D conversion data format select
0: A/D converter data format → SADOH = D [11:4]; SADOL = D [3:0]
1: A/D converter data format → SADOH = D [11:8]; SADOL = D [7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Bit 3~0
SACS3~SACS0: A/D converter external analog input channel select
0000: External AN0 input
0001: External AN1 input
0010: External AN2 input
0011: External AN3 input
0100: External AN4 input
0101: External AN5 input
0110: External AN6 input
0111: External AN7 input
1xxx: Undefined, input floating.
These bits are used to select which external analog input channel is to be converted.
When the external analog input channel is selected, the SAINS bit field must set to
"000", "101" or "110". Details are summarized in the "A/D Converter Input Signal
Selection" table.
SADC1 Register
Bit
7
6
5
4
3
2
1
0
Name
SAINS2
SAINS1
SAINS0
SAVRS1
SAVRS0
SACKS2
SACKS1
SACKS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
Rev. 1.10
SAINS2~SAINS0: A/D converter input signal select
000: External source – External analog channel intput
001: Internal source – Internal Bandgap reference voltage, VBG.
010: Internal source – Internal Temperature sensor output voltage, VTSO.
011, 100: Internal source – Ground.
101, 110: External source – External analog channel input
111: Forbidden to be used
Care must be taken if the SAINS2~SAINS0 bits are set to "001", "010", "011" or
"100" to select the internal analog signal to be converted. When the internal analog
signal is selected to be converted, the SACS3~SACS0 bits must be set to "1xxx" to
make sure that the external analog channel input is floating. Otherwise, the external
channel input will be connected together with the internal analog signal. This will
result in unpredictable situations and irreversible damage.
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Bit 4~3
SAVRS1~SAVRS0: A/D converter reference voltage select
00: External VREF pin
01: Internal A/D converter power, VDD.
10: Internal temperature sensor reference voltage, VTSVREF.
11: Internal A/D converter power, VDD.
These bits are used to select the A/D converter reference voltage source. Care must
be taken if the SAVRS bit field is set to any other values except "00" to select the
internal reference voltage source. When the internal reference voltage source is
selected, the external VREF pin can not be configured as the A/D converter external
reference voltage input by properly selecting the pin-shared function. Otherwise, the
A/D converter internal reference voltage source will be connected together with the
external reference voltage input on the VREF pin. This will result in unpredictable
situations.
Bit 2~0
SACKS2~SACKS0: A/D conversion clock source select
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: fSYS/128
These bits are used to select the clock source for the A/D converter. It is recommended
that the A/D conversion clock frequency should be in the range from 500 kHz to
1MHz by properly configuring the SACKS2~SACKS0 bits.
SADC2 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
G5XEN
TSEN
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
1
0
Bit 7~2
Unimplemented, read as "0"
Bit 1
G5XEN: OPA2 gain select
0: Gain=4
1: Gain=5
This bit controls the OPA2 gain selection. This bit should be properly selected for
different temperature range applications to avoid the saturated code.
Bit 0
TSEN: Temperature sensor circuitry enable control
0: Disable
1: Enable
This bit controls the internal temperature sensor circuitry. When the temperature sensor
is enabled by setting the TSEN bit to 1, a time named as tTSS should be allowed for
the temperature sensor circuit to stabilise before implementing relevant temperature
sensor operation.
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A/D Converter Operation
The START bit in the SADC0 register is used to start the AD conversion. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be
initiated.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an
A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ bit will
be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an internal interrupt signal will be generated. This
A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt
address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the
ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative method of
detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the
system clock fSYS and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D
clock source speed that can be selected. As the recommended range of permissible A/D clock period,
tADCK, is from 0.5μs to 10μ, care must be taken for system clock frequencies. For example, if the
system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000,
001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period
which may result in inaccurate A/D conversion values. Refer to the following table for examples,
where values marked with an asterisk * show where, depending upon the device, special care must
be taken, as the values may be less than the specified minimum A/D Clock Period.
However, the recommended A/D clock period is from 1μs to 2μ if the input signal to be converted is
the temperature sensor output voltage.
A/D Clock Period (tADCK)
SACKS[2:0]
= 000
(fSYS)
SACKS[2:0]
= 001
(fSYS/2)
SACKS[2:0]
= 010
(fSYS/4)
SACKS[2:0]
= 011
(fSYS/8)
SACKS[2:0]
= 100
(fSYS/16)
SACKS[2:0]
= 101
(fSYS/32)
SACKS[2:0]
= 110
(fSYS/64)
SACKS[2:0]
= 111
(fSYS/128)
1 MHz
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
128μs *
2 MHz
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
64μs *
4 MHz
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
32μs *
8 MHz
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
16μs *
12 MHz
83ns *
167ns *
333ns *
667ns
1.33μs
2.67μs
5.33μs
10.67μs *
16 MHz
62.5ns *
125ns *
250ns *
500ns
1μs
2μs
4μs
8μs
20 MHz
50ns *
100ns *
200ns *
400ns *
800ns
1.6μs
3.2μs
6.4μs
fSYS
A/D Clock Period Examples for External Analog Inputs
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When
the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be
consumed. In power conscious applications it is therefore recommended that the ADCEN is set low
to reduce power consumption when the A/D converter function is not being used.
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A/D Converter Reference Voltage
The reference voltage supply to the A/D Converter can be supplied from the positive power supply
pin, VDD, an external reference source supplied on pin VREF or an internal temperature sensor
reference voltage VTSVREF determined by the SAVRS1~SAVRS0 bits in the SADC1 register. The
internal temperature sensor reference voltage is amplified through a programmable gain amplifier,
PGA. The PGA gain is equal to 1.675. As the VREF pin is pin-shared with other functions, when
the VREF pin is selected as the reference voltage supply pin, the VREF pin-shared function control
bits should first be properly configured to disable other pin-shared functions. However, if the VDD
or VTSVREF is selected as the reference voltage supply source, the VREF pin function should be
deselected using the pin-shared function control bits to avoid that the internal reference voltage
source is connected to the external VREF voltage.
A/D Converter Input Signals
All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions.
The corresponding pin-shared function selection bits in the PxS1 and PxS0 registers, determine
whether the external input pins are setup as A/D converter analog channel inputs or whether they
have other functions. If the corresponding pin is setup to be an A/D converter analog channel input,
the original pin function will be disabled. In this way, pins can be changed under program control
to change their function between A/D inputs and other functions. All pull-high resistors, which are
setup through register programming, will be automatically disconnected if the pins are setup as A/D
inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register
to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input,
the status of the port control register will be overridden.
There are two internal analog signals, the Bandgap reference voltage V BG or temperature
sensor output VTSO, which can be connected to the A/D converter as the analog input signal by
configuring the SAINS2~SAINS0 bits. If the internal analog signal is selected to be converted, the
SACS3~SACS0 bits must be configured as "1xxx" to switch off the external analog channel input.
Otherwise, the internal analog signal will be connected together with the external channel input.
This will result in unpredictable situations.
The A/D converter has its own reference voltage pin, VREF. However, the reference voltage can also
be supplied from the power supply pin or the internal temperature sensor reference voltage, a choice
which is made through the SAVRS1~SAVRS0 bits in the SADC1 register. Note that the analog input
signal values must not be allowed to exceed the value of the selected A/D reference voltage.
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Conversion Rate and Timing Diagram
A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D
clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is
defined as tADC are necessary. However, an A/D conversion for an internal temperature sensor signal
will take a total of 56 A/D clock cycles.
Maximum single A/D conversion rate = A/D clock period/16 (External channel input signal)
Maximum single A/D conversion rate = A/D clock period/56 (Internal Temperature sensor signal)
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period.
tON�ST
ADCEN
off
on
off
A/D sa�pling ti�e
tADS
A/D sa�pling ti�e
tADS
Sta�t of A/D �onve�sion
Sta�t of A/D �onve�sion
on
START
ADBZ
SACS[3:0]
(SAINS=000)
End of A/D
�onve�sion
0011B
A/D �hannel
swit�h
End of A/D
�onve�sion
0010B
tADC
A/D �onve�sion ti�e
Sta�t of A/D �onve�sion
0000B
tADC
A/D �onve�sion ti�e
0001B
tADC
A/D �onve�sion ti�e
A/D Conversion Timing – External Channel Input
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Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by properly programming the SACKS2~SACKS0 bits
in the SADC1 register.
• Step 2
Enable the A/D converter by setting the ADCEN bit in the SADC0 register to one.
• Step 3
Select which signal is to be connected to the internal A/D converter by correctly configuring the
SACS and SAINS bit fields
Selecting the external channel input to be converted, go to Step 4.
Selecting the internal analog signal to be converted, go to Step 5.
• Step 4
If the SAINS field is 000, 101 or 110, the external channel input can be selected. The desired
external channel input is selected by configuring the SACS field from 0000 to 0111, When the A/D
input signal comes from the external channel input, the corresponding pin should be configured
as an A/D input function by selecting the relevant pin-shared function control bits. Then go to
Step 6.
• Step 5
If the SAINS field is 001 or 010, the relevant internal analog signal will be selected. When the
internal analog signal is selected to be converted, the SACS field should be set to 1xxx. Then go
to Step 6.
• Step 6
Select the A/D converter output data format by configuring the ADRFS bit.
Step 7
Select the A/D converter reference voltage source by configuring the SAVRS bit field.
• Step 8
If A/D conversion interrupt is used, the interrupt control registers must be correctly configured
to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D
conversion interrupt control bit, ADE, must both be set high in advance.
• Step 9
The A/D conversion procedure can now be initialized by setting the START bit from low to high
and then low again.
• Step 10
If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion
process is complete, the ADBZ flag will go low and then the output data can be read from
SADOH and SADOL registers.
Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit
in the SADC0 register is used, the interrupt enable step above can be omitted.
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Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by setting bit ADCEN low in the
SADC0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.
A/D Conversion Transfer Function
As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the reference voltage, this gives a single bit
analog input value of reference voltage value divided by 4096.
1 LSB = VREF ÷ 4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage = A/D output digital value × VREF ÷ 4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VREF level.
   

   
 
  Ideal A/D Transfer Function
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A/D Conversion Programming Examples
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an ADBZ polling method to detect the end of conversion
clr ADE; disable ADC interrupt
mov a,03H; select fSYS/8 as A/D clock and A/D external VREF pin voltage
mov SADC1,a ; as reference voltage
set ADCEN
mov a,02H ; setup PAS1 to configure pin AN0
mov PAS1,a
mov a,20H
mov SADC0,a ; enable and connect AN0 channel to A/D converter
:
start_conversion:
clr START ; high pulse on start bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
:
polling_EOC:
sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
:
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
jmp start_conversion ; start next A/D conversion
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Example: using the interrupt method to detect the end of conversion
clr ADE; disable ADC interrupt
mov a,03H; select fSYS/8 as A/D clock and A/D external VREF pin voltage
mov SADC1,a ; as reference voltage
set ADCEN
mov a,02h ; setup PAS1 to configure pin AN0
mov PAS1,a
mov a,20h
mov SADC0,a ; enable and connect AN0 channel to A/D converter
:
Start_conversion:
clr START ; high pulse on START bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set ADE; enable ADC interrupt
set EMI ; enable global interrupt
:
:
ADC_ISR: ; ADC interrupt service routine
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti
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Serial Interface Module – SIM
These devices contain a Serial Interface Module, which includes both the four-line SPI interface or
two-line I2C interface types, to allow an easy method of communication with external peripheral
hardware. Having relatively simple communication protocols, these serial interface types allow
the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or
EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the
SIM interface functional pins must first be selected using the corresponding pin-shared function
selection bits. As both interface types share the same pins and registers, the choice of whether the
SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in
the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pullhigh control registers when the SIM function is enabled and the corresponding pins are used as SIM
input pins.
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the devices can be
either master or slave. Although the SPI interface specification can control multiple slave devices
from a single master, these devices provided only one SCS pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pin to select the slave devices.
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data
Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins
are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first
be selected by configuring the pin-shared function selection bits and setting the correct bits in the
SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or
enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected
to the SPI interface is carried out in a slave/master mode with all data transfer initiations being
implemented by the master. The Master also controls the clock signal. As the device only contains
a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set
CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state.
The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN and
SIMEN.
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SPI Master/Slave Connection
  ­   

€ ‚ ƒ „
  
  SPI Block Diagram
SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These are
the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only
used by the I2C interface.
Bit
Register
Name
7
6
5
4
3
2
1
0
SIMC0
SIM2
SIM1
SIM0
—
—
—
SIMEN
SIMICF
SIMC2
D7
D6
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
SIMD
D7
D6
D5
D4
D3
D2
D1
D0
SPI Registers List
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• SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2
register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used
by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable
function and to set the data transmission clock frequency. Register SIMC2 is used for other control
functions such as LSB/MSB selection, write collision flag, etc.
• SIMC0 Register
Bit
7
6
5
4
3
2
1
0
Name
SIM2
SIM1
SIM0
—
—
—
SIMEN
SIMICF
R/W
R/W
R/W
R/W
—
—
—
R/W
R/W
POR
1
1
1
—
—
—
0
0
Bit 7~5
Rev. 1.10
SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS /4
001: SPI master mode; SPI clock is fSYS /16
010: SPI master mode; SPI clock is fSYS /64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a ratio of the system clock but can
also be chosen to be sourced from CTM0. If the SPI Slave Mode is selected then the
clock will be supplied by an external Master device.
Bit 4~2
Unimplemented, read as "0"
Bit 1
SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. If the
SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents
of the SPI control registers will remain at the previous settings when the SIMEN bit
changes from low to high and should therefore be first initialised by the application
program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0
bits and the SIMEN bit changes from low to high, the contents of the I2C control bits
such as HTX and TXAK will remain at the previous settings and should therefore be
first initialised by the application program while the relevant I2C flags such as HCF,
HAAS, HBB, SRW and RXAK will be set to their default states.
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Bit 0
SIMICF: SIM SPI slave mode Incomplete Transfer Flag
0: SIM SPI slave mode incomplete condition not occurred
1: SIM SPI slave mode incomplete condition occurred
This bit is only available when the SIM is configured to operate in an SPI slave mode.
If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set
to 1 but the SCS line is pulled high by the external master device before the SPI data
transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF
bit. When this condition occurs, the corresponding interrupt will occur if the interrupt
function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set
to 1 by software application program.
• SIMC2 Register
Bit
6
5
4
3
2
1
0
Name
D7
D6
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Rev. 1.10
7
Undefined bits
These bits can be read or written by the application program.
CKPOLB: SPI clock line base condition selection
0: The SCK line will be high when the clock is inactive.
1: The SCK line will be low when the clock is inactive.
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
CKEG: SPI SCK clock active edge type selection
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive. The CKEG bit determines active clock
edge type which depends upon the condition of CKPOLB bit.
MLS: SPI data shift order
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
CSEN: SPI SCS pin control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the
SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the
bit is high, the SCS pin will be enabled and used as a select pin.
WCOL: SPI write collision flag
0: No collision
1: Collision
The WCOL flag is used to detect whether a data collision has occurred or not. If this
bit is high, it means that data has been attempted to be written to the SIMD register
during a data transfer operation. This writing operation will be ignored if data is being
transferred. This bit can be cleared by the application program.
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Enhanced Touch Voice A/D Flash MCU
TRF: SPI Transmit/Receive complete flag
0: SPI data is being transferred
1: SPI data transfer is completed
The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when
an SPI data transfer is completed, but must cleared to 0 by the application program. It
can be used to generate an interrupt.
Bit 0
SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the TRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into
the SIMD register. The master should output a SCS signal to enable the slave devices before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG
bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal
for various configurations of the CKPOLB and CKEG bits.
The SPI will continue to function even in the IDLE Mode.
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SPI Slave Mode Timing – CKEG = 0
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
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Rev. 1.10
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I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Master/Slave Bus Connection
I2C interface Operation
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I2C bus is identified by a unique address which
will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data;
however, it is the master device that has overall control of the bus. For these devices, which only
operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
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      „ ­ ­ ­ ­ I2C Block Diagram
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
S T A R T s ig n a l
fro m M a s te r
S e n d s la v e a d d r e s s
a n d R /W b it fr o m M a s te r
A c k n o w le d g e
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S e n d d a ta b y te
fro m M a s te r
A c k n o w le d g e
fr o m s la v e
S T O P s ig n a l
fro m M a s te r
The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses
the system clock to in effect add a debounce time to the external clock to reduce the possibility
of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be
chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there
exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C
Standard or Fast mode operation, users must take care of the selected system clock frequency and
the configured debounce time to match the criterion shown in the following table.
I2C Debounce Time Selection
I2C Standard Mode (100kHz)
I2C Fast Mode (400kHz)
No Devounce
fSYS > 2 MHz
fSYS > 5 MHz
2 system clock debounce
fSYS > 4 MHz
fSYS > 10 MHz
4 system clock debounce
fSYS > 8 MHz
fSYS > 20 MHz
I2C Minimum fSYS Frequency
I2C Registers
There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA, and one
data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store
the data being transmitted and received on the I2C bus. Before the microcontroller writes data to
the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is
received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission
or reception of data from the I2C bus must be made via the SIMD register.
Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN
and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface.
Bit
Register
Name
7
6
5
4
SIMC0
SIM2
SIM1
SIM0
—
SIMC1
HCF
HAAS
HBB
HTX
TXAK
SIMA
IICA6
IICA5
IICA4
IICA3
IICA2
SIMD
D7
D6
D5
D4
D3
D2
SIMTOC SIMTOEN
3
2
1
0
SIMEN
—
SRW
IAMWU
RXAK
IICA1
IICA0
—
D1
D0
SIMDEB1 SIMDEB0
SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
I2C Registers List
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
• SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the
device can read it from the SIMD register. Any transmission or reception of data from the I2C bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
• SIMA Register
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is
the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register
define the device slave address. Bit 0 is not implemented.
When a master device, which is connected to the I2C bus, sends out an address, which matches the
slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is
the same register address as SIMC2 which is used by the SPI interface.
Bit
7
6
5
4
3
2
1
0
Name
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
POR
x
x
x
x
x
x
x
—
"x": unknown
Bit 7~1
IICA6~IICA0: I2C slave address
IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0
Bit 0
Unimplemented, read as "0".
There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0
is used to control the enable/disable function and to set the data transmission clock frequency. The
SIMC1 register contains the relevant flags which are used to indicate the I2C communication status.
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Enhanced Touch Voice A/D Flash MCU
• SIMC0 Register
Bit
7
6
5
4
Name
SIM2
SIM1
SIM0
—
R/W
R/W
R/W
R/W
—
R/W
POR
1
1
1
—
0
Bit 7~5
Bit 4
Bit 3~2
Bit 1
Bit 0
Rev. 1.10
3
2
1
0
SIMEN
—
R/W
R/W
—
0
0
—
SIMDEB1 SIMDEB0
SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS /4
001: SPI master mode; SPI clock is fSYS /16
010: SPI master mode; SPI clock is fSYS /64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a ratio of the system clock but can
also be chosen to be sourced from CTM0. If the SPI Slave Mode is selected then the
clock will be supplied by an external Master device.
Unimplemented, read as "0"
SIMDEB1~SIMDEB0: I2C Debounce Time Selection
00: No debounce
01: 2 system clock debounce
1x: 4 system clock debounce
SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I2C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I2C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Unimplemented, read as "0"
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• SIMC1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
HCF
HAAS
HBB
HTX
TXAK
SRW
IAMWU
RXAK
R/W
R
R
R
R/W
R/W
R/W
R/W
R
POR
1
0
0
0
0
0
0
1
Bit 7
HCF: I2C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
Bit 6
HAAS: I2C Address match flag
0: Not address match
1: Address match
The HAAS flag is the address match flag. This flag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match then
this bit will be high, if there is no match then the flag will be low.
Bit 5
HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which
will occur when a START signal is detected. The flag will be set to "0" when the bus is
free which will occur when a STOP signal is detected.
Bit 4
HTX: I2C slave device transmitter/receiver selection
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3
TXAK: I2C bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave does not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits
of data, this bit will be transmitted to the bus on the 9th clock from the slave device.
The slave device must always set TXAK bit to "0" before further data is received.
Bit 2
SRW: I2C slave read/write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus. When the
transmitted address and slave address is match, that is when the HAAS flag is set high,
the slave device will check the SRW flag to determine whether it should be in transmit
mode or receive mode. If the SRW flag is high, the master is requesting to read data
from the bus, so the slave device should be in transmit mode. When the SRW flag
is zero, the master will write data to the bus, therefore the slave device should be in
receive mode to read this data.
Bit 1
IAMWU: I2C Address Match Wake-Up control
0: Disable
1: Enable – must be cleared by the application program after wake-up
This bit should be set to 1 to enable the I2C address match wake up from the SLEEP
or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or
IDLE mode to enable the I2C address match wake up, then this bit must be cleared by
the application program after wake-up to ensure correction device operation.
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Bit 0
RXAK: I2C bus receive acknowledge flag
0: Slave receives acknowledge flag
1: Slave does not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it
means that a acknowledge signal has been received at the 9th clock, after 8 bits of data
have been transmitted. When the slave device in the transmit mode, the slave device
checks the RXAK flag to determine if the master receiver wishes to receive the next
byte. The slave transmitter will therefore continue sending out data until the RXAK
flag is "1". When this occurs, the slave transmitter will release the SDA line to allow
the master to send a STOP signal to release the I2C Bus.
I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of
data on the bus. The first seven bits of the data will be the slave address with the first bit being the
MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the
SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service
routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine
whether the interrupt source originates from an address match, 8-bit data transfer completion or
I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been
transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in
the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or
receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise
the bus; the following are steps to achieve this:
• Step 1
Set the SIM2~SIM0 bits to "110" and SIMEN bit to "1" in the SIMC0 register to enable the I2C bus.
• Step 2
Write the slave address of the device to the I2C bus address register SIMA.
• Step 3
Set the SIME and SIM Multi-Function interrupt enable bit of the interrupt control register to
enable the SIM interrupt and Multi-function interrupt.
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I2C Bus Initialisation Flow Chart
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the slave device. This START signal will be detected by all devices connected to the I2C bus. When
detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
I2C Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the
read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then
transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the
status flag HAAS when the addresses match.
As an I2C bus interrupt can come from three sources, when the program enters the interrupt
subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source has
come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out
occurrence. When a slave address is matched, the devices must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a dummy
read from the SIMD register to release the SCL line.
I2C Bus Read/Write Signal
The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the
I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to
be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes
to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as
a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C
bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. The
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the HAAS flag is high, the addresses have matched and the slave
device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag
is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register
should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as
a receiver and the HTX bit in the SIMC1 register should be set to "0".
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Enhanced Touch Voice A/D Flash MCU
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before
it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master
to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD
register. If setup as a transmitter, the slave device must first write the data to be transmitted into the
SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD
register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the SIMC1 register to determine if it is to send another data byte, if not then it will release the
SDA line and await the receipt of a STOP signal from the master.
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and then write data to the SIMD register, or in the receive mode where it must implement a
dummy read from the SIMD register to release the SCL line.
I2C Communication Timing Diagram
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
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    I2C Bus ISR Flow Chart
I2C Time-out Control
In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out
function is provided. If the clock source connected to the I2C bus is not received for a while, then the
I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts
to count on an I2C bus "START" & "address match" condition, and is cleared by an SCL falling
edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period
specified by the SIMTOC register, then a time-out condition will occur. The time-out function will
stop when an I2C "STOP" condition occurs.
When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will
be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has
occurred. The time-out condition will also generate an interrupt which uses the I2C interrupt vector.
When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset
into the following condition:
Register
After I2C Time-out
SIMD, SIMA, SIMC0
No change
SIMC1
Reset to POR condition
I2C Register after Time-out
The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections
which can be selected using the SIMTOS bits in the SIMTOC register. The time-out duration is
calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from
about 1ms to 64ms.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
S ta rt
S C L
IIC S R W
S la v e A d d r e s s
0
1
S D A
1
1
0
1
0
A C K
1
0
I2 C t i m e - o u t
c o u n te r s ta rt
S to p
S C L
1
0
0
1
0
1
0
0
S D A
I2 C t im e - o u t c o u n t e r r e s e t
o n S C L n e g a tiv e tr a n s itio n
I2C Time-out
• SIMTOC Register
Bit
Name
7
6
5
4
3
2
1
0
SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
SIMTOEN: SIM I C Time-out control
0: Disable
1: Enable
Bit 6
SIMTOF: SIM I2C Time-out flag
0: No time-out occurred
1: Time-out occurred
Bit 5~0
SIMTOS5~SIMTOS0: SIM I2C Time-out period selection
I2C Time-out clock source is fSUB/32
2
32
I2C Time-out period is equal to SIMTOS 5 : 0  1 f
SUB
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
UART Interface
These devices contain an integrated full-duplex asynchronous serial communications UART
interface that enables communication with external devices that contain a serial interface. The
UART function has many features and can transmit and receive data serially by transferring a frame
of data with eight or nine data bits per transmission as well as being able to detect errors when the
data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt
which can be used to indicate when a reception occurs or when a transmission terminates.
The integrated UART function contains the following features:
• Full-duplex, asynchronous communication
• 8 or 9 bits character length
• Even, odd or no parity options
• One or two stop bits
• Baud rate generator with 8-bit prescaler
• Parity, framing, noise and overrun error detection
• Support for interrupt on address detect (last character bit=1)
• Separately enabled transmitter and receiver
• 2-byte Deep FIFO Receive Data Buffer
• RX pin wake-up function
• Transmit and receive interrupts
•
Interrupts can be initialized by the following conditions:
♦♦
Transmitter Empty
♦♦
Transmitter Idle
♦♦
Receiver Full
♦♦
Receiver Overrun
♦♦
Address Mode Detect
T�ans�itte� Shift Registe� (TSR)
MSB ………………………… LSB
TX Pin
TX Registe� (TXR)
RX Pin
Re�eive� Shift Registe� (RSR)
MSB ………………………… LSB
RX Registe� (RXR)
Buffe�
Baud Rate
Gene�ato�
fSYS
Data to �e t�ans�itted
Data �e�eived
MCU Data Bus
UART Data Transfer Block Diagram
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
UART External Pin
To communicate with an external serial interface, the internal UART has two external pins known
as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The
TX and RX pin function should first be selected by the corresponding pin-shared function selection
register before the UART function is used. Along with the UARTEN bit, the TXEN and RXEN
bits, if set, will automatically setup the TX and RX pins to their respective TX output and RX input
conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When
the TX or RX pin function is disabled by clearing the UARTEN, TXEN or RXEN bit, the TX or RX
pin will be set to a floating state. At this time whether the internal pull-high resistor is connected to
the TX or RX pin or not is determined by the corresponding I/O pull-high function control bit.
UART Data Transfer Scheme
The above diagram shows the overall data transfer structure arrangement for the UART interface.
The actual data to be transmitted from the MCU is first transferred to the TXR register by the
application program. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only
the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped
and is therefore inaccessible to the application program.
Data to be received by the UART is accepted on the external RX pin, from where it is shifted in,
LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When
the shift register is full, the data will then be transferred from the shift register to the internal RXR
register, where it is buffered and can be manipulated by the application program. Only the TXR
register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is
therefore inaccessible to the application program.
It should be noted that the actual register for data transmission and reception, although referred to
in the text, and in application programs, as separate TXR and RXR registers, only exists as a single
shared register in the Data Memory. This shared register known as the TXR_RXR register is used
for both data transmission and data reception.
UART Status and Control Registers
There are five control registers associated with the UART function. The USR, UCR1 and UCR2
registers control the overall function of the UART, while the BRG register controls the Baud rate.
The actual data to be transmitted and received on the serial interface is managed through the TXR_
RXR data registers.
TXR_RXR Register
The TXR_RXR register is the data register which is used to store the data to be transmitted on the
TX pin or being received from the RX pin.
Bit
7
6
5
4
3
2
1
0
Name
TXRX7
TXRX6
TXRX5
TXRX4
TXRX3
TXRX2
TXRX1
TXRX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
Bit 7~0
Rev. 1.10
TXRX7~TXRX0: UART Transmit/Receive Data bits
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Enhanced Touch Voice A/D Flash MCU
USR Register
The USR register is the status register for the UART, which can be read by the program to
determine the present status of the UART. All flags within the USR register are read only and further
explanations are given below.
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
PERR
NF
FERR
OERR
RIDLE
RXIF
TIDLE
TXIF
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
1
0
1
1
Bit 7
PERR: Parity error flag
0: No parity error is detected
1: Parity error is detected
The PERR flag is the parity error flag. When this read only flag is "0", it indicates a
parity error has not been detected. When the flag is "1", it indicates that the parity of
the received word is incorrect. This error flag is applicable only if Parity mode (odd or
even) is selected. The flag can also be cleared by a software sequence which involves
a read to the status register USR followed by an access to the RXR data register.
Bit 6
NF: Noise flag
0: No noise is detected
1: Noise is detected
The NF flag is the noise flag. When this read only flag is "0", it indicates no noise
condition. When the flag is "1", it indicates that the UART has detected noise on the
receiver input. The NF flag is set during the same cycle as the RXIF flag but will not
be set in the case of as overrun. The NF flag can be cleared by a software sequence
which will involve a read to the status register USR followed by an access to the RXR
data register.
Bit 5
FERR: Framing error flag
0: No framing error is detected
1: Framing error is detected
The FERR flag is the framing error flag. When this read only flag is "0", it indicates
that there is no framing error. When the flag is "1", it indicates that a framing error
has been detected for the current character. The flag can also be cleared by a software
sequence which will involve a read to the status register USR followed by an access to
the RXR data register.
Bit 4
OERR: Overrun error flag
0: No overrun error is detected
1: Overrun error is detected
The OERR flag is the overrun error flag which indicates when the receiver buffer has
overflowed. When this read only flag is "0", it indicates that there is no overrun error.
When the flag is "1", it indicates that an overrun error occurs which will inhibit further
transfers to the RXR receive data register. The flag is cleared by a software sequence,
which is a read to the status register USR followed by an access to the RXR data
register.
Bit 3
RIDLE: Receiver status
0: data reception is in progress (data being received)
1: no data reception is in progress (receiver is idle)
The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates
that the receiver is between the initial detection of the start bit and the completion of
the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the
completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1"
indicating that the UART receiver is idle and the RX pin stays in logic high condition.
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Enhanced Touch Voice A/D Flash MCU
Bit 2
Bit 1
Bit 0
RXIF: Receive RXR data register status
0: RXR data register is empty
1: RXR data register has available data
The RXIF flag is the receive data register status flag. When this read only flag is "0",
it indicates that the RXR read data register is empty. When the flag is "1", it indicates
that the RXR read data register contains new data. When the contents of the shift
register are transferred to the RXR register, an interrupt is generated if RIE=1 in the
UCR2 register. If one or more errors are detected in the received word, the appropriate
receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The
RXIF flag is cleared when the USR register is read with RXIF set, followed by a read
from the RXR register, and if the RXR register has no data available.
TIDLE: Transmission status
0: data transmission is in progress (data being transmitted)
1: no data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only
flag is "0", it indicates that a transmission is in progress. This flag will be set to "1"
when the TXIF flag is "1" and when there is no transmit data or break character being
transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state
in logic high condition. The TIDLE flag is cleared by reading the USR register with
TIDLE set and then writing to the TXR register. The flag is not generated when a data
character or a break is queued and ready to be sent.
TXIF: Transmit TXR data register status
0: character is not transferred to the transmit shift register
1: character has transferred to the transmit shift register (TXR data register is empty)
The TXIF flag is the transmit data register empty flag. When this read only flag is "0",
it indicates that the character is not transferred to the transmitter shift register. When
the flag is "1", it indicates that the transmitter shift register has received a character
from the TXR data register. The TXIF flag is cleared by reading the UART status
register (USR) with TXIF set and then writing to the TXR data register. Note that
when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data
register is not yet full.
UCR1 Register
The UCR1 register together with the UCR2 register are the UART control registers that are used
to set the various options for the UART function such as overall on/off control, parity control, data
transfer bit length, etc. Further explanation on each of the bits is given below.
Bit
7
6
5
4
3
2
1
0
Name
UARTEN
BNO
PREN
PRT
STOPS
TXBRK
RX8
TX8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
POR
0
0
0
0
0
0
x
Bit 7
Rev. 1.10
0
"x": unknown
UARTEN: UART function enable control
0: Disable UART; TX and RX pins are in a floating state.
1: Enable UART; TX and RX pins function as UART pins
The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART
will be disabled and the RX pin as well as the TX pin will be set in a floating state.
When the bit is equal to "1", the UART will be enabled and the TX and RX pins will
function as defined by the TXEN and RXEN enable control bits. When the UART
is disabled, it will empty the buffer so any character remaining in the buffer will be
discarded. In addition, the value of the baud rate counter will be reset. If the UART
is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK,
RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and
RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will
remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending
transmissions and receptions will be terminated and the module will be reset as defined
above. When the UART is re-enabled, it will restart in the same configuration.
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Enhanced Touch Voice A/D Flash MCU
Rev. 1.10
Bit 6
BNO: Number of data transfer bits selection
0: 8-bit data transfer
1: 9-bit data transfer
This bit is used to select the data length format, which can have a choice of either
8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be
selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If
9-bit data length format is selected, then bits RX8 and TX8 will be used to store the
9th bit of the received and transmitted data respectively.
Bit 5
PREN: Parity function enable control
0: Parity function is disabled
1: Parity function is enabled
This bit is the parity function enable bit. When this bit is equal to 1, the parity function
will be enabled. If the bit is equal to 0, then the parity function will be disabled.
Bit 4
PRT: Parity type selection bit
0: Even parity for parity generator
1: Odd parity for parity generator
This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will
be selected. If the bit is equal to 0, then even parity type will be selected.
Bit 3
STOPS: Number of stop bits selection
0: One stop bit format is used
1: Two stop bits format is used
This bit determines if one or two stop bits are to be used. When this bit is equal to "1",
two stop bits format are used. If the bit is equal to "0", then only one stop bit format is
used.
Bit 2
TXBRK: Transmit break character
0: No break character is transmitted
1: Break characters transmit
The TXBRK bit is the Transmit Break Character bit. When this bit is equal to "0",
there are no break characters and the TX pin operates normally. When the bit is
equal to "1", there are transmit break characters and the transmitter will send logic
zeros. When this bit is equal to "1", after the buffered data has been transmitted, the
transmitter output is held low for a minimum of a 13-bit length and until the TXBRK
bit is reset.
Bit 1
RX8: Receive data bit 8 for 9-bit data transfer format (read only)
This bit is only used if 9-bit data transfers are used, in which case this bit location will
store the 9th bit of the received data known as RX8. The BNO bit is used to determine
whether data transfers are in 8-bit or 9-bit format.
Bit 0
TX8: Transmit data bit 8 for 9-bit data transfer format (write only)
This bit is only used if 9-bit data transfers are used, in which case this bit location
will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to
determine whether data transfers are in 8-bit or 9-bit format.
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Enhanced Touch Voice A/D Flash MCU
UCR2 Register
The UCR2 register is the second of the UART control registers and serves several purposes. One
of its main functions is to control the basic enable/disable operation if the UART Transmitter and
Receiver as well as enabling the various UART interrupt sources. The register also serves to control
the baud rate speed, receiver wake-up function enable and the address detect function enable.
Further explanation on each of the bits is given below.
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
TXEN
RXEN
BRGH
ADDEN
WAKE
RIE
TIIE
TEIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
TXEN: UART Transmitter enable control
0: UART Transmitter is disabled
1: UART Transmitter is enabled
The TXEN bit is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter
will be disabled with any pending data transmissions being aborted. In addition the
buffers will be reset. In this situation the TX pin will be set in a floating state. If the
TXEN bit is equal to "1" and the UARTEN bit is also equal to 1, the transmitter will be
enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a
transmission will cause the data transmission to be aborted and will reset the transmitter.
If this situation occurs, the TX pin will be set in a floating state.
Bit 6
RXEN: UART Receiver enable control
0: UART Receiver is disabled
1: UART Receiver is enabled
The RXEN bit is the Receiver Enable Bit. When this bit is equal to "0", the receiver
will be disabled with any pending data receptions being aborted. In addition the
receiver buffers will be reset. In this situation the RX pin will be set in a floating state.
If the RXEN bit is equal to "1" and the UARTEN bit is also equal to 1, the receiver
will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN
bit during a reception will cause the data reception to be aborted and will reset the
receiver. If this situation occurs, the RX pin will be set in a floating state.
Bit 5
BRGH: Baud Rate speed selection
0: Low speed baud rate
1: High speed baud rate
The bit named BRGH selects the high or low speed mode of the Baud Rate Generator.
This bit, together with the value placed in the baud rate register, BRG, controls the
baud rate of the UART. If the bit is equal to 0, the low speed mode is selected.
Bit 4
ADDEN: Address detect function enable control
0: Address detection function is disabled
1: Address detection function is enabled
The bit named ADDEN is the address detection function enable control bit. When this
bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th
bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if
BNO=1, has a value of "1", then the received word will be identified as an address,
rather than data. If the corresponding interrupt is enabled, an interrupt request will be
generated each time the received word has the address bit set, which is the 8th or 9th
bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th
bit of the received word is "0" with the address detection function being enabled, an
interrupt will not be generated and the received data will be discarded.
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Enhanced Touch Voice A/D Flash MCU
Bit 3
WAKE: RX pin falling edge wake-up function enable control
0: RX pin wake-up function is disabled
1: RX pin wake-up function is enabled
The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and
the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the
device. If this bit is equal to 0 and the device is in IDLE or SLEEP mode, any edge
transitions on the RX pin will not wake up the device.
Bit 2
RIE: Receiver interrupt enable control
0: Receiver related interrupt is disabled
1: Receiver related interrupt is enabled
The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the
receiver overrun flag OERR or received data available flag RXIF is set, the UART
interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request
flag will not be influenced by the condition of the OERR or RXIF flags.
Bit 1
TIIE: Transmitter Idle interrupt enable control
0: Transmitter idle interrupt is disabled
1: Transmitter idle interrupt is enabled
The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and
when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the
UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt
request flag will not be influenced by the condition of the TIDLE flag.
Bit 0
TEIE: Transmitter Empty interrupt enable control
0: Transmitter empty interrupt is disabled
1: Transmitter empty interrupt is enabled
The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and
when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the
UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt
request flag will not be influenced by the condition of the TXIF flag.
Baud Rate Generator
To setup the speed of the serial data communication, the UART function contains its own dedicated
baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the
period of which is determined by two factors. The first of these is the value placed in the BRG
register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH
bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which
in turn determines the formula that is used to calculate the baud rate. The value in the BRG register,
N, which is used in the following baud rate calculation formula determines the division factor. Note
that N is the decimal value placed in the BRG register and has a range of between 0 and 255.
UCR2 BRGH Bit
0
1
Baud Rate (BR)
fSYS / [64 (N+1)]
fSYS / [16 (N+1)]
By programming the BRGH bit which allows selection of the related formula and programming the
required value in the BRG register, the required baud rate can be setup. Note that because the actual
baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error
associated between the actual and requested value. The following example shows how the BRG
register value N and the error value can be calculated.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
BRG Register
Bit
7
6
5
4
3
2
1
0
Name
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
Bit 7~0
BRG7~BRG0: Baud Rate values
By programming the BRGH bit in the UCR2 register which allows selection of the
related formula described above and programming the required value in the BRG
register, the required baud rate can be setup.
Calculating the Baud Rate and Error Values
For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the
actual baud rate and the error value for a desired baud rate of 4800.
From the above table the desired baud rate BR = fSYS / [64 (N+1)]
Re-arranging this equation gives N = [fSYS / (BR×64)] - 1
Giving a value for N = [4000000 / (4800×64)] - 1 = 12.0208
To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives
an actual or calculated baud rate value of BR = 4000000 / [64 × (12+1)] = 4808
Therefore the error is equal to (4808 - 4800) / 4800 = 0.16%
UART Setup and Control
For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ,
format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity
is supported by the UART hardware and can be setup to be even, odd or no parity. For the most
common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used
as the default setting, which is the setting at power-on. The number of data bits and stop bits, along
with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in
the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit
baud rate generator, while the data is transmitted and received LSB first. Although the transmitter
and receiver of the UART are functionally independent, they both use the same data format and baud
rate. In all cases stop bits will be used for data transmission.
Enabling/Disabling the UART Interface
The basic on/off function of the internal UART function is controlled using the UARTEN bit in the
UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act
as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX
pin, then it will default to a logic high value.
Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be used as an
I/O or other pin-shared functional pin. When the UART function is disabled, the buffer will be
reset to an empty condition, at the same time discarding any remaining residual data. Disabling the
UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK,
RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be
set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected.
If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending
transmissions and receptions will be immediately suspended and the UART will be reset to a
condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the
same configuration.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Data, Parity and Stop Bit Selection
The format of the data to be transferred is composed of various factors such as data bit length,
parity on/off, parity type, address bits and the number of stop bits. These factors are determined by
the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits
which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN
bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to
be used. The following table shows various formats for data transmission. The address detect mode
control bit identifies the frame as an address character. The number of stop bits, which can be either
one or two, is independent of the data length.
Start Bit
Data Bits
Address Bits
Parity Bit
Stop Bit
Example of 8-bit Data Formats
1
8
0
0
1
1
7
0
1
1
1
7
1
0
1
Example of 9-bit Data Formats
1
9
0
0
1
1
8
0
1
1
1
8
1
0
1
Transmitter Receiver Data Format
The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.
8-Bit Data Format
9-Bit Data Format
UART Transmitter
Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1
register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which
is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the
Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the
transmit data register, which is known as the TXR register. The data to be transmitted is loaded
into this TXR register by the application program. The TSR register is not written to with new data
until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been
transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It
should be noted that the TSR register, unlike many other registers, is not directly mapped into the
Data Memory area and as such is not available to the application program for direct read/write
operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but
the data will not be transmitted until the TXR register has been loaded with data and the baud rate
generator has defined a shift clock source. However, the transmission can also be initiated by first
loading data into the TXR register, after which the TXEN bit can be set. When a transmission of
data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in
an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission
will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/O
or other pin-shared function.
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Transmitting Data
When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with
the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the
internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been
selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a
data transfer can be summarized as follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a
UART transmitter pin.
• Access the USR register and write the data that is to be transmitted into the TXR register. Note
that this step will clear the TXIF bit.
This sequence of events can now be repeated to send additional data. It should be noted that when
TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is
always achieved using the following software sequence:
1. A USR register access
2. A TXR register write execution
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is
empty and that other data can now be written into the TXR register without overwriting the previous
data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission,
a write instruction to the TXR register will place the data into the TXR register, which will be
copied to the shift register at the end of the present transmission. When there is no data transmission
in progress, a write instruction to the TXR register will place the data directly into the shift register,
resulting in the commencement of data transmission, and the TXIF bit being immediately set. When
a frame transmission is complete, which happens after stop bits are sent or after the break frame, the
TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used:
1. A USR register access
2. A TXR register write execution
Note that both the TXIF and TIDLE bits are cleared by the same software sequence.
Transmitting Break
If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break
character transmission consists of a start bit, followed by 13xN "0" bits, where N=1, 2, etc. If a
break character is to be transmitted, then the TXBRK bit must be first set by the application program
and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually
kept at a logic high level, then the transmitter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the
last break character and subsequently send out one or two stop bits. The automatic logic high at the
end of the last break character will ensure that the start bit of the next frame is recognized.
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UART Receiver
The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming
the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In
this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the
receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which
is received on the RX external input pin is sent to the data recovery block. The data recovery block
operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the
baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the
receive data register, if the register is empty. The data which is received on the external RX input pin
is sampled three times by a majority detect circuit to determine the logic level that has been placed
onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly
mapped into the Data Memory area and as such is not available to the application program for direct
read/write operations.
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep
FIFO data buffer, where two bytes can be held in the FIFO while the 3rd byte can continue to be
received. Note that the application program must ensure that the data is read from RXR before the
3rd byte has been completely shifted in, otherwise the 3rd byte will be discarded and an overrun error
OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as
follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART
receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received, the following sequence of events will occur:
• The RXIF bit in the USR register will be set then RXR register has data available, at least one
more character can be read.
• When the contents of the shift register have been transferred to the RXR register and if the RIE
bit is set, then an interrupt will be generated.
• If during reception, a frame error, noise error, parity error or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
1. A USR register access
2. A RXR register read execution
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Receiving Break
Any break character received by the UART will be managed as a framing error. The receiver will
count and expect a certain number of bit times as specified by the values programmed into the BNO
and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as
complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR
is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the
RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit,
the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid
stop bit before looking for the next start bit. The receiver will not make the assumption that the
break condition on the line is the next start bit. A break is regarded as a character that contains only
zeros with the FERR flag set. The break character will be loaded into the buffer and no further data
will be received until stop bits are received. It should be noted that the RIDLE read only flag will go
high when the stop bits have not yet been received. The reception of a break character on the UART
registers will result in the following:
• The framing error flag, FERR, will be set.
• The receive data register, RXR, will be cleared.
• The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit and
the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE
flag, will have a zero value. In between the reception of a stop bit and the detection of the next start
bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
Receiver Interrupt
The read only receive interrupt flag, RXIF, in the USR register is set by an edge generated by the
receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift
Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if
RIE=1.
Managing Receiver Errors
Several types of reception errors can occur within the UART module, the following section describes
the various types and how they are managed by the UART.
Overrun Error – OERR
The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in
the FIFO register, while a 3th byte can continue to be received. Before the 3th byte has been entirely
shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag
OERR will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
• The OERR flag in the USR register will be set.
• The RXR contents will not be lost.
• The shift register will be overwritten.
• An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the USR register followed by a read to the RXR
register.
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Noise Error – NF
Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is
detected within a frame, the following will occur:
• The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit.
• Data will be transferred from the shift register to the RXR register.
• No interrupt will be generated. However this bit rises at the same time as the RXIF bit which
itself generates an interrupt.
Note that the NF flag is reset by a USR register read operation followed by an RXR register read
operation.
Framing Error – FERR
The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of
stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERR flag will be
set. The FERR flag is buffered along with the received data and is cleared in any reset.
Parity Error – PERR
The read only parity error flag, PERR, in the USR register, is set if the parity of the received word
is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the
parity type, odd or even, is selected. The read only PERR flag is buffered along with the received
data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buffered
along with the corresponding word and should be read before reading the data word.
UART Interrupt Structure
Several individual UART conditions can generate a UART interrupt. When these conditions exist,
a low pulse will be generated to get the attention of the microcontroller. These conditions are a
transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address
detect and an RX pin wake-up. When any of these conditions are created, if its corresponding
interrupt control is enabled and the stack is not full, the program will jump to its corresponding
interrupt vector where it can be serviced before returning to the main program. Four of these
conditions have the corresponding USR register flags which will generate a UART interrupt if its
associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable control bits, while the two receiver interrupt
conditions have a shared enable control bit. These enable bits can be used to mask out individual
UART interrupt sources.
The address detect condition, which is also a UART interrupt source, does not have an associated
flag, but will generate a UART interrupt when an address detect condition occurs if its function
is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a
UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the
microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin, if the
WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt
occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for
the oscillator to restart and stabilize before the system resumes normal operation.
Note that the USR register flags are read only and cannot be cleared or set by the application
program, neither will they be cleared when the program jumps to the corresponding interrupt
servicing routine, as is the case for some of the other interrupts. The flags will be cleared
automatically when certain actions are taken by the UART, the details of which are given in the
UART register section. The overall UART interrupt can be disabled or enabled by the related
interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether
the interrupt requested by the UART module is masked out or allowed.
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USR Registe�
UCR� Registe�
T�ans�itte� E�pty Flag
TXIF
TEIE
T�ans�itte� Idle Flag
TIDLE
TIIE
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RIE
OR
Re�eive� Data Availa�le
RXIF
WAKE
0
1
Re�eive� Ove��un Flag
OERR
RX Pin
Wake-up
0
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1
EMI
0
1
Inte��upt signal
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1
0
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0
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UART Interrupt Structure
Address Detect Mode
Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this
special function. If this bit is set to 1, then an additional qualifier will be placed on the generation
of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit
is equal to 1, then when the data is available, an interrupt will only be generated, if the highest
received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the
microcontroller must also be enabled for correct interrupt generation. The highest address bit is the
9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received
word will be defined as an address rather than data. A Data Available interrupt will be generated
every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive
Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last
but status. The address detection and parity functions are mutually exclusive functions. Therefore, if
the address detect function is enabled, then to ensure correct operation, the parity function should be
disabled by resetting the parity function enable bit PREN to zero.
ADDEN
Bit 9 if BNO=1
Bit 8 if BNO=0
UART Interrupt Generated
0
√
1
√
0
X
1
√
0
1
ADDEN Bit Function
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UART Power Down and Wake-up
When the MCU system clock is switched off, the UART will cease to function. If the MCU executes
the "HALT" instruction and switches off the system clock while a transmission is still in progress,
then the transmission will be paused until the UART clock source derived from the microcontroller
is activated. In a similar way, if the MCU executes the "HALT" instruction and switches off the
system clock while receiving data, then the reception of data will likewise be paused. When the
MCU enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2, transmit and receive
registers, as well as the BRG register will not be affected. It is recommended to make sure first that
the UART data transmission or reception has been finished before the microcontroller enters the
IDLE or SLEEP mode.
The UART function contains a receiver RX pin wake-up function, which is enabled or disabled
by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the
receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the
IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the MCU from the IDLE0
or SLEEP Mode. Note that as it takes certain system clock cycles after a wake-up, before normal
microcontroller operation resumes, any data received during this time on the RX pin will be ignored.
For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global
interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must be set. If the EMI and URE
bits are not set then only a wake up event will occur and no interrupt will be generated. Note also
that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes,
the UART interrupt will not be generated until after this time has elapsed.
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Serial Interface – SPIA
These devices contain an independent SPI function. It is important not to confuse this independent
SPI function with the additional one contained within the combined SIM function, which is
described in another section of this datasheet. This independent SPI function will carry the name
SPIA to distinguish it from the other one in the SIM.
This SPIA interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the device can be
either master or slave. Although the SPIA interface specification can control multiple slave devices
from a single master, this device is provided only one SCSA pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pins to select the slave devices.
SPIA Interface Operation
The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial
Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA
interface pins are pin-shared with other functions, the SPIA interface pins must first be selected
by configuring the corresponding selection bits in the pin-shared function selection registers.
The SPIA interface function is disabled or enabled using the SPIAEN bit in the SPIAC0 register.
Communication between devices connected to the SPIA interface is carried out in a slave/master
mode with all data transfer initiations being implemented by the master. The master also controls the
clock/signal. As the device only contains a single SCSA pin only one slave device can be utilised.
The SCSA pin is controlled by the application program, set the SACSEN bit to "1" to enable the
SCSA pin function and clear the SACSEN bit to "0" to place the SCSA pin into an I/O function.
SPIA Master/Slave Connection
The SPIA Serial Interface function includes the following features:
• Full-duplex synchronous data transfer
• Both Master and Slave mode
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
The status of the SPIA interface pins is determined by a number of factors such as whether the
device is in the master or slave mode and upon the condition of certain control bits such as SACSEN
and SPIAEN.
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SPIA Registers
There are three internal registers which control the overall operation of the SPIA interface. These are
the SPIAD data register and two registers SPIAC0 and SPIAC1.
Register
Name
SPIAC0
Bit
7
6
SASPI2 SASPI1
SPIAC1
—
—
SPIAD
D7
D6
5
4
SASPI0
—
SACKPOLB SACKEG
D5
D4
3
—
SAMLS
D3
2
1
0
—
SPIAEN
SPIAICF
SACSEN SAWCOL
D2
D1
SATRF
D0
SPIA Registers List
SPIAD Register
The SPIAD register is used to store the data being transmitted and received. Before the device
writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register.
After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any
transmission or reception of data from the SPIA bus must be made via the SPIAD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
"x": unknown
There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0
is used to control the enable/disable function and to set the data transmission clock frequency.
Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision
flag, etc.
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SPIAC0 Register
Bit
7
6
5
4
3
2
1
0
Name
SASPI2
SASPI1
SASPI0
—
—
—
SPIAEN
SPIAICF
R/W
R/W
R/W
R/W
—
—
—
R/W
R/W
POR
1
1
1
—
—
—
0
0
Bit 7~5
Rev. 1.10
SASPI2~SASPI0: SPIA Master/Slave clock select
000: SPIA master mode with clock fSYS /4
001: SPIA master mode with clock fSYS /16
010: SPIA master mode with clock fSYS /64
011: SPIA master mode with clock fSUB
100: SPIA master mode with clock CTM0 CCRP match frequency/2
101: SPIA slave mode
11x: SPIA disable
Bit 4~2
Unimplemented, read as "0"
Bit 1
SPIAEN: SPIIA Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit
is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA
lines will lose the SPI function and the SPIA operating current will be reduced to a
minimum value. When the bit is high the SPIA interface is enabled.
Bit 0
SPIAICF: SPIA Incomplete Flag
0: SPIA incomplete condition not occurred
1: SPIA incomplete condition occurred
This bit is only available when the SPIA is configured to operate in an SPIA slave
mode. If the SPIA operates in the slave mode with the SPIAEN and SACSEN bits
both being set to 1 but the SCSA line is pulled high by the external master device
before the SPIA data transfer is completely finished, the SPIAICF bit will be set to 1
together with the SATRF bit. When this condition occurs, the corresponding interrupt
will occur if the interrupt function is enabled. However, the SATRF bit will not be set
to 1 if the SPIAICF bit is set to 1 by software application program.
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SPIAC1 Register
Rev. 1.10
Bit
7
6
Name
—
—
5
4
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
SACKPOLB SACKEG
3
SAMLS
2
1
0
SACSEN SAWCOL SATRF
Bit 7~6
Unimplemented, read as "0"
Bit 5
SACKPOLB: SPIA clock line base condition selection
0: The SCKA line will be high when the clock is inactive.
1: The SCKA line will be low when the clock is inactive.
The SACKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit
is low, then the SCKA line will be high when the clock is inactive.
Bit 4
SACKEG: SPIA SCKA clock active edge type selection
SACKPOLB=0
0: SCKA is high base level and data capture at SCKA rising edge
1: SCKA is high base level and data capture at SCKA falling edge
SACKPOLB=1
0: SCKA is low base level and data capture at SCKA falling edge
1: SCKA is low base level and data capture at SCKA rising edge
The SACKEG and SACKPOLB bits are used to setup the way that the clock signal
outputs and inputs data on the SPIA bus. These two bits must be configured before
data transfer is executed otherwise an erroneous clock edge may be generated. The
SACKPOLB bit determines the base condition of the clock line, if the bit is high, then
the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is
low, then the SCKA line will be high when the clock is inactive. The SACKEG bit
determines active clock edge type which depends upon the condition of SACKPOLB
bit.
Bit 3
SAMLS: SPIA data shift order
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Bit 2
SACSEN: SPIA SCSA pin control
0: Disable
1: Enable
The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then
the SCSA pin function will be disabled and can be placed into I/O pin or other pinshared functions. If the bit is high, the SCSA pin will be enabled and used as a select
pin.
Bit 1
SAWCOL: SPIA write collision flag
0: No collision
1: Collision
The SAWCOL flag is used to detect whether a data collision has occurred or not.
If this bit is high, it means that data has been attempted to be written to the SPIAD
register during a data transfer operation. This writing operation will be ignored if data
is being transferred. This bit can be cleared by the application program.
Bit 0
SATRF: SPIA Transmit/Receive complete flag
0: SPIA data is being transferred
1: SPIA data transfer is completed
The SATRF bit is the Transmit/Receive Complete flag and is set to 1 automatically
when an SPIA data transfer is completed, but must cleared to 0 by the application
program. It can be used to generate an interrupt.
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SPIA Communication
After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when
data is written to the SPIAD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into
the SPIAD registers.
The master should output a SCSA signal to enable the slave device before a clock signal is provided.
The slave data to be transferred should be well prepared at the appropriate moment relative to the
SCSA signal depending upon the configurations of the SACKPOLB bit and SACKEG bit. The
accompanying timing diagram shows the relationship between the slave data and SCSA signal for
various configurations of the SACKPOLB and SACKEG bits. The SPIA will continue to function if
the SPIA clock source is active.
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SPIA Master/Slave Mode Timing Diagram
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   SPIA Transfer Control Flow Chart
Rev. 1.10
199
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
SPIA Bus Enable/Disable
To enable the SPIA bus, set SACSEN=1 and SCSA =0, then wait for data to be written into the
SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD
(TXRX buffer) register, then transmission or reception will start automatically. When all the data has
been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received
on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in.
When the SPIA bus is disabled, the SCKA, SDIA, SDOA and SCSA pins can become I/O pins or
other pin-shared functions using the corresponding pin-shared function control bits.
SPIA Operation
All communication is carried out using the 4-line interface for either Master or Slave Mode.
The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting
this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then
be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled
and the SCSA line will be an I/O pin or other pin-shared functions and can therefore not be used for
control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are
set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master
Mode the SCKA line will be either high or low depending upon the clock polarity selection bit
SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition.
If SPIAEN is low, then the bus will be disabled and SCSA, SDIA, SDOA and SCKA pins will all
become I/O pins or other pin-shared functions using the corresponding pin-shared function control
bits. In the Master Mode the Master will always generate the clock signal. The clock and data
transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode,
the clock signal will be received from an external master device for both data transmission and
reception. The following sequences show the order to be followed for data transfer in both Master
and Slave Mode.
Master Mode:
• Step 1
Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control
register.
• Step 2
Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted
first, this must be same as the Slave device.
• Step 3
Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface.
• Step 4
For write operations: write the data to the SPIAD register, which will actually place the data into
the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5.
For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer
until all the data has been received at which point it will be latched into the SPIAD register.
• Step 5
Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal
to zero then go to the following step.
• Step 6
Check the SATRF bit or wait for a SPIA serial bus interrupt.
Rev. 1.10
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December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• Step 7
Read data from the SPIAD register.
• Step 8
Clear SATRF.
• Step 9
Go to step 4.
Slave Mode:
• Step 1
Select the SPI Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register
• Step 2
Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted
first, this setting must be the same with the Master device.
• Step 3
Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface.
• Step 4
For write operations: write the data to the SPIAD register, which will actually place the data into
the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5.
For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer
until all the data has been received at which point it will be latched into the SPIAD register.
• Step 5
Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal
to zero then go to the following step.
• Step 6
Check the SATRF bit or wait for a SPIA serial bus interrupt.
• Step 7
Read data from the SPIAD register.
• Step 8
Clear SATRF.
• Step 9
Go to step 4.
Error Detection
The SAWCOL bit in the SPIAC1 register is provided to indicate errors during data transfer. The bit
is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates
a data collision has occurred which happens if a write to the SPIAD register takes place during a
data transfer operation and will prevent the write operation from continuing.
Rev. 1.10
201
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Touch Key Function
Each device provides multiple touch key functions. The touch key function is fully integrated and
requires no external components, allowing touch key functions to be implemented by the simple
manipulation of internal registers.
Touch Key Structure
The touch keys are pin shared with the I/O pins, with the desired function chosen via the pin-shared
selection register bit. Keys are organised into several groups, with each group known as a module
and having a module number, M0 to Mn. Each module is a fully independent set of four Touch Keys
and each Touch Key has its own oscillator. Each module contains its own control logic circuits and
register set. Examination of the register names will reveal the module number it is referring to.
Device
BS66FV360
BS66FV350
BS66FV340
Total Key Number
Touch Key Module
Touch Key
M0
KEY1~KEY4
28
24
20
M1
KEY5~KEY8
M2
KEY9~KEY12
M3
KEY13~KEY16
M4
KEY17~KEY20
M5
KEY21~KEY24
M6
KEY25~KEY28
M0
KEY1~KEY4
M1
KEY5~KEY8
M2
KEY9~KEY12
M3
KEY13~KEY16
M4
KEY17~KEY20
M5
KEY21~KEY24
M0
KEY1~KEY4
M1
KEY5~KEY8
M2
KEY9~KEY12
M3
KEY13~KEY16
M4
KEY17~KEY20
Touch Key Structure
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Key
KEY 1
OSC
TKMn16DH / TKMn16DL
( to Data Memory Sector 5)
Key
KEY 2
OSC
Mux .
Multifrequency
Filter
16-bit C/F Counter
TKCFOV
Key
KEY 3
OSC
MnDFEN
Key
KEY 4
OSC
TKMnROH / TKMnROL
( from Data Memory Sector 6)
TKMnC2
MnTSS
fSYS/4
Reference Oscillator
Filter
TKTMR
M
U
X
8-bit Time Slot Counter
5-bit unit period counter
TKRCOV
Module 0
Module n
16-bit C/F Counter
Value
(Sector 5)
TKTMR
8-bit Time Slot Counter
Preload Register
fSYS
fSYS/2
fSYS/4
fSYS/8
Reference Osc.
Capacitor Value
(Sector 6)
Data
Bus
Overflow
M
U
X
16-bit Counter
TK16OV
TK16DL / TK16DH
TK16S1~TK16S0
Touch Key
Data Memory
Note: The structure contained in the dash line is identical for each touch key module which contains four touch keys.
Touch Key Function Block Diagram
Touch Key Register Definition
Each touch key module, which contains four touch key functions, has its own suite registers. The
following table shows the register set for each touch key module. The Mn within the register name
refers to the Touch Key module number. The series of devices has up to seven Touch Key Modules
dependent upon the selected device.
Name
Description
TKTMR
Touch key time slot 8-bit counter preload register
TKC0
Touch key function Control register 0
TKC1
Touch key function Control register 1
TK16DL
Touch key function 16-bit counter low byte
TK16DH
Touch key function 16-bit counter high byte
TKMn16DL
Touch key module n 16-bit C/F counter low byte
TKMn16DH
Touch key module n 16-bit C/F counter high byte
TKMnROL
Touch key module n reference oscillator capacitor select low byte
TKMnROH
Touch key module n reference oscillator capacitor select high byte
TKMnC0
Touch key module n Control register 0
TKMnC1
Touch key module n Control register 1
TKMnC2
Touch key module n Control register 2
Touch Key Module Registers List
Rev. 1.10
203
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Bit
Register
Name
7
6
5
4
3
2
1
0
TKTMR
D7
D6
D5
D4
D3
D2
D1
D0
—
TKMOD
TKBUSY
TKC1
D7
D6
D5
TSCS
TK16S1
TK16S0
TKFS1
TKFS0
TK16DL
D7
D6
D5
D4
D3
D2
D1
D0
TK16DH
D15
D14
D13
D12
D11
D10
D9
D8
TKC0
TKRAMC TKRCOV
TKCFOV TK16OV
TKST
TKMn16DL
D7
D6
D5
D4
D3
D2
D1
D0
TKMn16DH
D15
D14
D13
D12
D11
D10
D9
D8
TKMnROL
D7
D6
D5
D4
D3
D2
D1
D0
TKMnROH
—
—
—
—
—
—
D9
D8
TKMnC0
—
—
MnDFEN
D4
TKMnC1
MnTSS
—
MnROEN MnKOEN MnK4EN MnK3EN MnK2EN MnK1EN
TKMnC2
MnSK31
MnSK30
MnSK21
MnSK20
MnSOFC MnSOF2 MnSOF1 MnSOF0
MnSK11
MnSK10
MnSK01
MnSK00
1
0
Touch Key Function Registers List
TKTMR Register
Bit
7
6
5
4
3
2
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
D7~D0: Touch key time slot 8-bit counter preload register
The touch key time slot counter preload register is used to determine the touch key
time slot overflow time. The time slot unit period is obtained by a 5-bit counter and
equal to 32 time slot clock cycles. Therefore, the time slot counter overflow time is
equal to the following equation shown.
Time slot counter overflow time = (256—TKTMR[7:0]) × 32 tTSC, where tTSC is the
time slot counter clock.
Bit 7~0
TKC0 Register
Bit
Name
6
5
4
3
2
1
0
TKST
TKCFOV
TK16OV
—
TKMOD
TKBUSY
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R
POR
0
0
0
0
0
—
0
0
Bit 7
Rev. 1.10
7
TKRAMC TKRCOV
TKRAMC: Touch key Data RAM access control
0: Accessed by MCU
1: Accessed by Touch key module
This bit determines that the touch key RAM is used by the MCU or touch key
module. However, the touch key module will have the priority to access the touch
key RAM when the touch key module operates in the auto scan mode, i.e., the TKST
bit state is changed from 0 to 1 when the TKMOD bit is set low. After the touch key
auto scan operation is completed, i.e., the TKBUSY bit state is changed from 1 to 0,
the touch key RAM access will be controlled by the TKRAMC bit. Therefore, it is
recommended to set the TKRAMC bit to 1 when the touch key module operates in the
auto scan mode. Otherwise, the contents of the touch key RAM may be modified as
this RAM space is configured by the touch key module followed by the MCU access.
204
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Enhanced Touch Voice A/D Flash MCU
Rev. 1.10
Bit 6
TKRCOV: Touch key time slot counter overflow flag
0: No overflow occurs
1: Overflow occurs
This bit can be accessed by application programs. When this bit is set by touch key
time slot counter overflow, the corresponding touch key interrupt request flag will be
set. However, if this bit is set by application programs, the touch key interrupt request
flag will not be affected.
In auto scan mode, if the time slot counter overflows but the touch key auto scan
operation is not completed, the TKRCOV bit will not be set. At this time, the touch
key module n 16-bit C/F counter, touch key function 16-bit counter and 5-bit time
slot unit period counter will be automatically cleared but the 8-bit time slot counter
will be reloaded from the 8-bit time slot counter preload register. When the touch
key auto scan operation is completed, the TKRCOV bit and the Touch Key Interrupt
request flag, TKMF, will be set and all modules key and reference oscillators will
automatically stop. The touch key modules 16-bit C/F counter, touch key function
16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter will be
automatically switched off.
In manual scan mode, if the time slot counter overflows, the TKRCOV bit and the
Touch Key Interrupt request flag, TKMF, will be set and all modules key and reference
oscillators will automatically stop. The touch key module 16-bit C/F counter, touch
key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot
counter will be automatically switched off.
Bit 5
TKST: Touch key detection Start control
0: Stopped or no operation
0→1: Start detection
In all modules the touch key module 16-bit C/F counter, touch key function 16-bit
counter and 5-bit time slot unit period counter will automatically be cleared when this
bit is cleared to zero. However, the 8-bit programmable time slot counter will not be
cleared. When this bit is changed from low to high, the touch key module 16-bit C/F
counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit
time slot counter will be switched on together with the key and reference oscillators to
drive the corresponding counters.
Bit 4
TKCFOV: Touch key module 16-bit C/F counter overflow flag
0: No overflow occurs
1: Overflow occurs
This bit is set by touch key module 16-bit C/F counter overflow and must be cleared to
0 by application programs.
Bit 3
TK16OV: Touch key function 16-bit counter overflow flag
0: No overflow occurs
1: Overflow occurs
This bit is set by touch key function 16-bit counter overflow and must be cleared to 0
by application programs.
Bit 2
Unimplemented, read as "0"
Bit 1
TKMOD: Touch key scan mode select
0: Auto scan mode
1: Manual scan mode
In manual scan mode the reference oscillator capacitor value should be properly
configured before the scan operation begins and the touch key module 16-bit C/F counter
value should be read after the scan operation finishes by application program.
In auto scan mode the data movement which is described above is implemented by
hardware. The individual reference oscillator capacitor value and 16-bit C/F counter
content for all scanned keys will be read from and written into a dedicated Touch Key
Data Memory area. In auto scan mode the keys to be scanned can be arranged in a specific
sequence which is determined by the MnSK3[1:0] ~ MnSK0[1:0] bits in the TKMnC2
register. The scan operation will not be stopped until all arranged keys are scanned.
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Enhanced Touch Voice A/D Flash MCU
Bit 0TKBUSY: Touch key scan operation busy flag
0: Not busy – no scan operation is executed or scan operation is complete
1: Busy – scan operation is executing
This bit indicates whether the touch key scan operation is executing or not. It is set to
1 when the TKST bit is set high to start the scan operation and cleared to 0 when the
touch key time slot counter overflows in the manual scan mode or the selected touch
keys scan operation is completed in the auto scan mode.
TKC1 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
TSCS
TK16S1
TK16S0
TKFS1
TKFS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
1
1
Bit 7~5
D7~D5: Data bits for test only
These bits are used for test purpose only and must be kept as "000" for normal
operations.
Bit 4TSCS: Touch key time slot counter select
0: Each touch key module uses its own time slot counter
1: All touch key modules use Module 0 time slot counter
Bit 3~2
TK16S1~TK16S0: Touch key function 16-bit counter clock source select
00: fSYS
01: fSYS/2
10: fSYS/4
11: fSYS/8
Bit 1~0
TKFS1~TKFS0: Touch Key oscillator and Reference oscillator frequency select
00: 500 kHz
01: 1000 kHz
10: 1500 kHz
11: 2000 kHz
TK16DH/TK16DL – Touch Key Function 16-bit Counter Register Pair
Register
Bit
Name
TK16DH
7
6
5
4
3
TK16DL
2
1
D15 D14 D13 D12 D11 D10 D9
0
7
6
5
4
3
2
1
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register pair is used to store the touch key function 16-bit counter value. This 16-bit counter can
be used to calibrate the reference or key oscillator frequency. When the touch key time slot counter
overflows in the manual scan mode, this 16-bit counter will be stopped and the counter content will
be unchanged. However, this 16-bit counter content will be cleared to zero at the end of the time slot 0,
slot 1 and slot 2 but kept unchanged at the end of the time slot 3 in the auto scan mode. This register
pair will be cleared to zero when the TKST bit is set low.
Rev. 1.10
206
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
TKMn16DH/TKMn16DL – Touch Key Module n 16-bit C/F Counter Register Pair
Register
Bit
Name
TKMn16DH
7
6
5
4
TKMn16DL
3
2
1
D15 D14 D13 D12 D11 D10 D9
0
7
6
5
4
3
2
1
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register pair is used to store the touch key module n 16-bit C/F counter value. This 16-bit C/F
counter will be stopped and the counter content will be kept unchanged when the touch key time
slot counter overflows in the manual scan mode. However, this 16-bit C/F counter content will be
cleared to zero at the end of the time slot 0, slot 1 and slot 2 but kept unchanged at the end of the
time slot 3 when the auto scan mode is selected. This register pair will be cleared to zero when the
TKST bit is set low.
TKMnROH/TKMnROL – Touch Key Module n Reference Oscillator Capacitor Select Register Pair
Register
TKMnROH
TKMnROL
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
This register pair is used to store the touch key module n reference oscillator capacitor value. This
register pair will be loaded with the corresponding next time slot capacitor value from the dedicated
touch key data memory at the end of the current time slot when the auto scan mode is selected.
The reference oscillator internal capacitor value =
TKMnRO[9 : 0]x 50pF
1024
.
TKMnC0 Register
Rev. 1.10
Bit
7
6
5
4
Name
—
—
MnDFEN
D4
3
R/W
—
—
R/W
R/W
R/W
POR
—
—
0
0
0
2
1
0
MnSOF1
MnSOF0
R/W
R/W
R/W
0
0
0
MnSOFC MnSOF2
Bit 7~6
Unimplemented, read as "0"
Bit 5
MnDFEN: Touch key module n multi-frequency control
0: Disable
1: Enable
This bit is used to control the touch key oscillator frequency doubling function. When
this bit is set to 1, the key oscillator frequency will be doubled.
Bit 4
D4: Data bit for test only
The bit is used for test purpose only and must be kept as "0" for normal operations.
Bit 3
MnSOFC: Touch key module n C-to-F oscillator frequency hopping function control
select
0: Controlled by the MnSOF2~MnSOF0
1: Controlled by hardware circuit
This bit is used to select the touch key oscillator frequency hopping function control
method. When this bit is set to 1, the key oscillator frequency hopping function is
controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value.
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Enhanced Touch Voice A/D Flash MCU
Bit 2~0
MnSOF2~MnSOF0: Touch key module n Reference and Key oscillators hopping
frequency select
000: fHOP0 – Min. hopping frequency
001: fHOP1
010: fHOP2
011: fHOP3
100: fHOP4 – Selected touch key oscillator frequency
101: fHOP5
110: fHOP6
111: fHOP7 – Max. hopping frequency
These bits are used to select the touch key oscillator frequency for the hopping
function. Note that these bits are only available when the MnSOFC bit is cleared to 0.
TKMnC1 Register
Rev. 1.10
Bit
7
6
Name
MnTSS
—
5
4
R/W
R/W
—
R/W
R/W
POR
0
—
0
0
3
2
1
0
MnK3EN
MnK2EN
MnK1EN
R/W
R/W
R/W
R/W
0
0
0
0
MnROEN MnKOEN MnK4EN
Bit 7
MnTSS: Touch key module n time slot counter clock source select
0: Touch key module n reference oscillator
1: fSYS/4
Bit 6
Unimplemented, read as "0"
Bit 5
MnROEN: Touch key module n Reference oscillator enable control
0: Disable
1: Enable
This bit is used to enable the touch key module n reference oscillator. In auto scan
mode the reference oscillator will automatically be enabled by setting the MnROEN
bit high when the TKST bit is set from low to high if the reference oscillator is
selected as the time slot clock source. The combination of the MnTSS, TSCS and
MnK4EN~MnK1EN bits determines whether the reference oscillator is used or
not. When the TKBUSY bit is changed from high to low, the MnROEN bit will
automatically be set low to disable the reference oscillator. Note that for touch
key module 0 the M0ROEN bit will automatically be set high in auto scan mode
when the TKST bit is set from low to high regardless of the M0TSS, TSCS and
M0K4EN~M0K1EN bits setting.
In manual scan mode the reference oscillator should first be enabled before setting the
TKST bit from low to high if the reference oscillator is selected to be used and will be
disabled when the TKBUSY bit is changed from high to low.
Bit 4
MnKOEN: Touch key module n Key oscillator enable control
0: Disable
1: Enable
This bit is used to enable the touch key module n key oscillator. In auto scan mode the
key oscillator will automatically be enabled by setting the MnKOEN bit high when the
TKST bit is set form low to high. When the TKBUSY bit is changed from high to low,
the MnKOEN bit will automatically be set low to disable the key oscillator.
In manual scan mode the key oscillator shoule first be enabled before setting the TKST
bit from low to high if the relevant key is enabled to be scanned and will be disabled
when the TKBUSY bit is changed from high to low.
Bit 3
MnK4EN: Touch key module n Key 4 enable control
0: Disable
1: Enable
Bit 2
MnK3EN: Touch key module n Key 3 enable control
0: Disable
1: Enable
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Enhanced Touch Voice A/D Flash MCU
Bit 1
MnK2EN: Touch key module n Key 2 enable control
0: Disable
1: Enable
Bit 0
MnK1EN: Touch key module n Key 1 enable control
0: Disable
1: Enable
TKMnC2 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
MnSK31
MnSK30
MnSK21
MnSK20
MnSK11
MnSK10
MnSK01
MnSK00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
0
0
1
0
0
Bit 7~6
MnSK31~MnSK30: Touch key module n time slot 3 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 3 and only available in
the auto scan mode.
Bit 5~4
MnSK21~MnSK20: Touch key module n time slot 2 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 2 and only available in
the auto scan mode.
Bit 3~2
MnSK11~MnSK10: Touch key module n time slot 1 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 1 and only available in
the auto scan mode.
Bit 1~0
MnSK01~MnSK00: Touch key module n time slot 0 key scan select
00: KEY 1
01: KEY 2
10: KEY 3
11: KEY 4
These bits are used to select the desired scan key in time slot 0 in the auto scan mode
or used as the multiplexer for scan key select in the manual mode.
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Enhanced Touch Voice A/D Flash MCU
Touch Key Operation
When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase.
By using this capacitance variation to change slightly the frequency of the internal sense oscillator,
touch actions can be sensed by measuring these frequency changes. Using an internal programmable
divider the reference clock is used to generate a fixed time period. By counting a number of
generated clock cycles from the sense oscillator during this fixed time period touch key actions can
be determined.
TKST
MnKOEN
MnROEN
Ha�dwa�e set to “0”
KEY OSC CLK
Refe�en�e OSC CLK
fCFTMCK Ena�le
fCFTMCK (MnDFEN=0)
fCFTMCK (MnDFEN=0)
TKBUSY
TKRCOV
Set Tou�h Key inte��upt �equest flag
Touch Key Manual Scan Mode Timing Diagram
Each touch key module contains four touch key inputs which are shared logical I/O pins, and the
desired function is selected using register Bits. Each touch key has its own independent sense
oscillator. There are therefore four sense oscillators within each touch key module.
During this reference clock fixed interval, the number of clock cycles generated by the sense
oscillator is measured, and it is this value that is used to determine if a touch action has been made
or not. At the end of the fixed reference clock time interval a Touch Key interrupt signal will be
generated in the manual scan mode.
Using the TSCS bit in the TKC1 register can select the module 0 time slot counter as the time
slot counter for all modules. All modules use the same started signal, TKST, in the TKC0 register.
The touch key module 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter in
all modules will be automatically cleared when the TKST bit is cleared to zero, but the 8-Bit
programmable time slot counter will not be cleared. The overflow time is setup by user. When the
TKST bit changes from low to high, the 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period
counter and 8-bit time slot timer counter will be automatically switched on.
The key oscillator and reference oscillator in all modules will be automatically stopped and the 16bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter
will be automatically switched off when the time slot counter overflows. The clock source for the
time slot counter is sourced from the reference oscillator or fSYS/4 which is selected using the
MnTSS bit in the TKMnC1 register. The reference oscillator and key oscillator will be enabled by
setting the MnROEN bit and MnKOEN bits in the TKMnC1 register.
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Enhanced Touch Voice A/D Flash MCU
When the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual
touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled.
Each touch key module consists of four touch keys, KEY1 ~ KEY4 are contained in module 0,
KEY5 ~ KEY8 are contained in module 1, KEY9 ~ KEY12 are contained in module 2, etc. Each
touch key module has an identical structure.
Auto Scan Mode
There are two scan modes contained for the touch key function. The auto scan mode can minimize
the load of the application programs and improve the touch key scan operation performance. The
auto scan mode and manual scan mode are selected using the TKMOD bit in the TKC0 register.
When the TKMOD bit is set low, the auto scan mode is selected to scan the keys in each module in a
specific sequence determined by the MnSK3[1:0]~MnSK0[1:0] in the TKMnC2 register.
In the auto scan mode the key oscillator and reference oscillator will automatically be enabled when
the TKST bit is set from low to high and disabled automatically when the TKBUSY bit changes
from high to low. The whole auto scan operation will sequentially be carried out in the above
specific way from time slot 0 to time slot 3. When the TKST bit is set from low to high in the auto
scan mode, the internal capacitor value of the corresponding reference oscillator for the selected key
to be scanned in the time slot 0 will first be read from a specific location of the dedicated touch key
data memory and loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit
C/F counter value will be written into the corresponding location of the time slot 3 scanned key in
the touch key module data memory. After this, the selected key will start to be scanned in time slot
0. At the end of the time slot 0 key scan operation, the reference oscillator internal capacitor value
for the next selected key will be read from the touch key data memory and loaded into the next
TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value of the current scanned key
will be written into the corresponding touch key data memory. At the end of the time slot 3 key scan
operation, the reference oscillator internal capacitor value for the time slot 0 selected key will again
be read from the touch key data memory and loaded into the corresponding TKMnROH/TKMnROL
registers. Then the 16-bit C/F counter value will be written into the relevant location of the time
slot 3 scanned key in the touch key module data memory. At the end of the auto scan mode, the first
reference oscillator internal capacitor value will again be read from the touch key data memory and
loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value
will again be written into the relevant touch key data memory. After four selected keys are scanned,
the TKRCOV bit will be set high and the TKBUSY bit will be set low as well as an auto scan mode
operation is completed.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Key Auto S�an Cy�le
TKST
Ti�e slot 0
Module 0
Ti�e slot 1
Ti�e slot 1
Ti�e slot �
Ti�e slot �
Ti�e slot 3
Ti�e slot 3
Ti�e slot 0
Module 1
Ti�e slot 1
Ti�e slot 1
Ti�e slot �
Ti�e slot �
Ti�e slot 3
Ti�e slot 3
Ti�e slot 0
Module n
Ti�e slot 1
Ti�e slot 1
Ti�e slot �
Ti�e slot �
Ti�e slot 3
Ti�e slot 3
TKBUSY
Clea�ed �y softwa�e
TKRCOV
Tou�h Key Data
Me�o�y A��ess
: Set Tou�h Key inte��upt �equest flag
: Read �N �ytes f�o� Tou�h Key Data Me�o�y to TKMnROH/TKMnTROL �egiste�s
: W�ite �N �ytes f�o� TKMn1�DH/TKMn1�DL �egiste�s to Tou�h Key Data Me�o�y
N = Tou�h Key Module Nu��e�; n = Module Se�ial Nu��e�
Touch Key Auto Scan Mode Timing Diagram
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Touch Key Data Memory
The device provides two dedicated Data Memory area for the touch key auto scan mode. One area
is used to store the 16-bit C/F counter values of the touch key module 0~n and located in Data
Memory Sector 5. The other area is used to store the reference oscillator internal capacitor values of
the touch key module 0~n and located in Data Memory Sector 6.
16-bit C/F
counter value
(Sector 5)
00H
01H
02H
Ref. OSC
Capacitor value
(Sector 6)
TKM016DL_K1
TKM0ROL_K1
TKM016DH_K1
TKM0ROH_K1
TKM016DL_K2
TKM0ROL_K2
TKM016DH_K2
TKM0ROH_K2
Module 0
TKM016DL_K3
TKM016DH_K3
Touch Key Circuit
16-bit C/F counter
TKM016DL_K4
TKM0ROL_K4
TKM016DH_K4
TKM0ROH_K4
TKM116DL_K1
TKM1ROL_K1
TKM116DH_K1
TKM1ROH_K1
TKM116DL_K2
TKM1ROL_K2
TKM116DH_K2
TKMnROL / TKMnROH
Step 1
10-bit Ref. OSC
capacitor
Module 1
TKM116DL_K3
TKM116DH_K3
Step 2
TKM1ROL_K3
TKM116DL_K4
TKM1ROL_K4
TKM116DH_K4
TKM1ROH_K4
TKM216DL_K1
TKM2ROL_K1
TKM216DH_K1
TKM2ROH_K1
TKM216DL_K2
TKM2ROL_K2
Module 2
TKM216DL_K3
TKM216DH_K3
TKM2ROH_K2
TKM2ROL_K3
TKM2ROH_K3
TKM216DL_K4
TKM2ROL_K4
TKM216DH_K4
TKM2ROH_K4
TKM316DL_K1
TKM3ROL_K1
TKM316DH_K1
TKM3ROH_K1
TKM316DL_K2
TKM3ROL_K2
TKM316DH_K2
Module n
TKM316DL_K3
TKM316DH_K3
xxH
TKM1ROH_K2
TKM1ROH_K3
TKM216DH_K2
TKMn16DL / TKMn16DH
TKM0ROL_K3
TKM0ROH_K3
TKM3ROH_K2
TKM3ROL_K3
TKM3ROH_K3
TKM316DL_K4
TKM3ROL_K4
TKM316DH_K4
TKM3ROH_K4
Touch Key Data Memory Map
Touch Key Data Memory
Device
Sector : Address
BS66FV340
5: 00H~27H
6: 00H~27H
BS66FV350
5: 00H~2FH
6: 00H~2FH
BS66FV360
5: 00H~37H
6: 00H~37H
Touch Key Data Memory Summary
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Enhanced Touch Voice A/D Flash MCU
Touch Key Scan Operation Flow Chart
Sta�t
W�ite Ref. OSC Capa�ito�
to TKMnROH/TKMnROL
Tou�h Key Manual S�an Ope�ation Sta�t
1
Set Sta�t �it TKST 0
Busy flag TKBUSY=1
Initiate Ti�e Slot &
1�-�it C/F Counte�
All Ti�e Slot &
1�-�it C/F Counte�
Sta�t to �ount
Ti�e Slot &
1�-�it C/F Counte�
Keep �ounting
TKRCOV=0
All Ti�e Slot
Counte� ove�flow ?
TKRCOV=1
Tou�h key �usy flag
TKBUSY=0
Gene�ate Inte��upt
�equest flag
Read C/F �ounte� f�o�
TKMn1�DH/TKMn1�DL
Tou�h key s�an end
0
Set TKST �it 1
End
Touch Key Manual Scan Mode Flow Chart – TKMOD=1, TSCS=0
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Sta�t
W�ite Ref. OSC inte�nal
Capa�ito� value
to Data Me�o�y (Se�to� � )
Tou�h Key Auto S�an Ope�ation Sta�t
1
Set Sta�t �it TKST 0
Busy flag TKBUSY=1
Load Ref. OSC inte�nal
Capa�ito� value f�o�
Data Me�o�y (Se�to� � )
Load Ref. OSC inte�nal
Capa�ito� value f�o�
Data Me�o�y (Se�to� � )
Sto�e C/F �ounte� value to
Data Me�o�y (Se�to� � )
Sto�e C/F �ounte� value to
Data Me�o�y (Se�to� � )
Tou�h key �usy flag
TKBUSY=0
Initiate Ti�e Slot &
1�-�it C/F Counte�
TKRCOV = 1
Ti�e Slot �ounte� &
1�-�it C/F �ounte�
Sta�t to �ount
Ti�e Slot &
1�-�it C/F Counte�
Keep �ounting
No
Gene�ate Inte��upt
�equest flag
Tou�h key s�an end
0
Set TKST �it 1
Ti�e Slot
Counte� ove�flow ?
Yes
All key s�an finish ?
Read C/F �ounte� value f�o�
Data Me�o�y (Se�to� �)
No
S�an sele�ted key
in next ti�e slot
End
Yes
Touch Key Auto Scan Mode Flow Chart – TKMOD=0, TSCS=0
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Touch Key Interrupt
The touch key only has single interrupt, when the time slot counter in all the touch key modules or
in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys
mentioned here are the keys which are enabled. The 16-bit C/F counter, 16-bit counter, 5-bit time
slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared.
The TKCFOV flag which is the 16-bit C/F counter overflow flag will go high when any of the Touch
Key Module 16-bit C/F counter overflows. As this flag will not be automatically cleared, it has to be
cleared by the application program.
The TK16OV flag which is the 16-bit counter overflow flag will go high when the 16-bit counter
overflows. As this flag will not be automatically cleared, it has to be cleared by the application
program. More details regarding the touch key interrupt is located in the interrupt section of the
datasheet.
Programming Considerations
After the relevant registers are setup, the touch key detection process is initiated by changing the
TKST Bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV
flag which is the time slot counter flag will go high when the counter overflows. When this happens
an interrupt signal will be generated.
When the external touch key size and layout are defined, their related capacitances will then
determine the sensor oscillator frequency.
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Enhanced Touch Voice A/D Flash MCU
Low Voltage Detector – LVD
Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
The Low Voltage Detector also has the capability of generating an interrupt signal.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which
a low voltage condition will be determined. A low voltage condition is indicated when the LVDO
bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage
value. The LVDEN bit is used to control the overall on/off function of the low voltage detector.
Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the
internal low voltage detector circuits. As the low voltage detector will consume a certain amount of
power, it may be desirable to switch off the circuit when not in use, an important consideration in
power sensitive battery powered applications.
LVDC Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
LVDO
LVDEN
VBGEN
VLVD2
VLVD1
VLVD0
R/W
—
—
R
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5
LVDO: LVD output flag
0: No Low Voltage Detected
1: Low Voltage Detected
Bit 4
LVDEN: Low Voltage Detector Enable control
0: Disable
1: Enable
Bit 3
VBGEN: Bandgap Voltage Output Enable control
0: Disable
1: Enable
Bit 2~0
VLVD2~VLVD0: LVD Voltage selection
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V
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Enhanced Touch Voice A/D Flash MCU
LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be
set high indicating a low power supply voltage condition. The Low Voltage Detector function is
supplied by a reference voltage which will be automatically enabled. When the device is powered
down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low
Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the
LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that
of VLVD, there may be multiple bit LVDO transitions.
LVD Operation
The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling
the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been
set high by a low voltage condition. When the device is powered down the Low Voltage Detector
will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set,
causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the
device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up
function is not required then the LVF flag should be first set high before the device enters the SLEEP
or IDLE Mode.
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Software LCD Driver
The devices have the capability of driving external LCD panels. The common pins for LCD driving,
SCOM0~SCOM5, and segment pins, SSEG0~SSEG38, are pin shared with certain pin on the I/O
ports. The LCD signals (COM and SEG) are generated using the application program.
LCD Control Registers
The LCD COM and SEG driver enables a range of selections to be provided to suit the requirement
of the LCD panel which is being used. The bias current choice is implemented using the ISEL1
and ISEL0 bits in the SLCDC0 register. All COM and SEG pins are pin-shared with I/O pins and
selected as COM and SEG pins using the corresponding pin function selection bits together with the
COM/SEG selection bits in the SLCDC1 register.
Register
Name
Bit
7
SLCDC0 FRAME
SLCDC1
6
5
4
3
2
1
0
ISEL1
ISEL0
LCDEN
—
—
—
—
—
COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS2 COMSEGS1 COMSEGS0
—
LCD Driver Control Registers List
SLCDC0 Register
Bit
7
6
5
4
3
2
1
0
Name
FRAME
ISEL1
ISEL0
LCDEN
—
—
—
—
R/W
R/W
R/W
R/W
R/W
—
—
—
—
POR
0
0
0
0
—
—
—
—
Bit 7
FRAME: SCOM/SSEG Output Frame selection
0: Frame 0
1: Frame 1
Bit 6~5
ISEL1~ISEL0: Select SCOM/SSEG typical bias current (VDD=5V)
00: 8.3μA
01: 16.7μA
10: 50μA
11: 100μA
Bit 4
LCDEN: SCOM/SSEG Module enable control
0: Disable
1: Enable
The SCOMn and SSEGm lines can be enabled using the corresponding pin-shared
selection bits if the LCDEN bit is set to 1. When the LCDEN bit is cleared to 0, then
the SCOMn and SSEGm outputs will be fixed at a VSS level.
Bit 3~0
Unimplemented, read as "0".
SLCDC1 Register
Bit
7
6
Name
—
— COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS2 COMSEGS1 COMSEGS0
4
3
2
1
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Bit 5
Bit 4
Rev. 1.10
5
Unimplemented, read as "0".
COMSEGS5: SCOM5 or SSEG5 pin function select
0: SCOM5
1: SSEG5
COMSEGS4: SCOM4 or SSEG4 pin function select
0: SCOM4
1: SSEG4
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Enhanced Touch Voice A/D Flash MCU
Bit 3
COMSEGS3: SCOM3 or SSEG3 pin function select
0: SCOM3
1: SSEG3
Bit 2
COMSEGS2: SCOM2 or SSEG2 pin function select
0: SCOM2
1: SSEG2
Bit 1
COMSEGS1: SCOM1 or SSEG1 pin function select
0: SCOM1
1: SSEG1
Bit 0
COMSEGS0: SCOM0 or SSEG0 pin function select
0: SCOM0
1: SSEG0
Note that the LCDEN and corresponding pin-shared selection bits should be properly configured
before the SCOMn/SSEGn function is determined.
LCD Operation
An external LCD panel can be driven using the devices by configuring the I/O pins as common pins
and segment pins. The LCD driver function is controlled using the LCD control registers which in
addition to controlling the overall on/off function also controls the R-type bias current on the SCOM
and SSEG pins. This enables the LCD COM and SEG driver to generate the necessary VSS, (1/3)
VDD, (2/3)VDD and VDD voltage levels for LCD 1/3 bias operation.
The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver. This bit is
used in conjunction with the corresponding pin-shared function selection bits for the SCOMn and
SSEGm pins to select which I/O pins are used for LCD driving. Note that the corresponding Port
Control register does not need to first setup the pins as outputs to enable the LCD driver operation.
VDD
SSEG� & SCOMn
Pin-sha�ed sele�tion
VDD
SCOM0/SSEG0
(�/3) VDD
(1/3) VDD
LCD
Voltage
Sele�t
Ci��uit
LCD
COM/SEG
Analog
Swit�h
SCOM�/SSEG�
SSEG�
SSEG38
ISEL[1:0]
LCDEN
FRAME
Software Controlled LCD Driver Structure
Rev. 1.10
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
LCD Frames
A cyclic LCD waveform includes two frames known as Frame 0 and Frame 1 for which the
following offers a functional explanation.
• Frame 0
To select Frame 0, clear the FRAME bit in the SLCDC 0 register to 0.
In frame 0, the COM signal output can have a value of VDD or a VBIAS value of (1/3)×VDD. The
SEG signal output can have a value of VSS or a VBIAS value of (2/3)×VDD.
• Frame 1
To select Frame 1, set the FRAME bit in the SLCDC0 register to 1.
In frame 1, the COM signal output can have a value of VSS or a VBIAS value of (2/3)×VDD. The
SEG signal output can have a value of VDD or a VBIAS value of (1/3)×VDD.
The COMn waveform is controlled by the application program using the FRAME bit in the
SLCDC0 register and the corresponding pin-shared I/O data bit for the respective COM pin to
determine whether the COMn output has a value of VDD, VSS or VBIAS. The SEGm waveform is
controlled in a similar way using the FRAME bit and the corresponding pin-shared I/O data bit for
the respective SEG pin to determine whether the SEGm output has a value of VDD, VSS or VBIAS.
The accompanying waveform diagram shows a typical 1/3 bias LCD waveform generated using the
application program together with the LCD voltage select circuit. Note that the depiction of a "1" in
the diagram illustrates an illuminated LCD pixel. The COM and SEG signals polarity generated on
pins SCOMn and SSEGm, whether "0" or "1", are generated using the corresponding pin-shared I/O
data register bit.
Frame 0
Frame 1
1
COM0
0
0
0
0
Frame 0
0
Frame 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
VDD
(2/3) VDD
(1/3) VDD
VSS
VDD
(2/3) VDD
(1/3) VDD
VSS
VDD
(2/3) VDD
(1/3) VDD
VSS
VDD
(2/3) VDD
(1/3) VDD
VSS
1
VDD
(2/3) VDD
(1/3) VDD
VSS
1
VDD
(2/3) VDD
(1/3) VDD
VSS
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
SEG1
0
1
0
0
1
0
0
1
0
1
SEG0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
0
1
1
COM3
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
COM2
1
1
0
0
Frame 0
1
1
0
0
0
1
COM1
0
Frame 0
Note: The logical values shown in the above diagram are the corresponding pin-shared I/O data bit value.
1/3 Bias LCD Waveform – 4-COM & 2-SEG Application
Rev. 1.10
221
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Voice Playing Controller
These devices contain a fully integrated 16-bit D/A converter complete with volume control together
with a power amplifier. The voice data located in the PLADH and PLADL register pair can be output
to the external speaker using the 16-bit D/A converter. The power amplifier offers the possibility of
directly driving external speakers. The volume control can be adjusted using the USVC [6:0] bits.
PLADH
8
PLADL
8
1�-�it D/A +
Powe� A�plifie�
DAEN
PAEN
Speake�
USVC[�:0]
Voice Playing Controller Block Diagram
Voice Controller Registers
The overall voice play function is controlled using a series of registers. Two control registers exist
to control the 16-bit D/A converter and power amplifier functions together with the speaker mute
control. Two data register pairs exist to store the data which is to be played.
Bit
Register
Name
7
6
5
4
3
2
1
0
USVC
MUTEB
USVC6
USVC5
USVC4
USVC3
USVC2
USVC1
USVC0
DAEN
PLAC
—
—
—
—
—
—
PAEN
PLADL
P_D7
P_D6
P_D5
P_D4
P_D3
P_D2
P_D1
P_D0
PLADH
P_D15
P_D14
P_D13
P_D12
P_D11
P_D10
P_D9
P_D8
Voice Playing Controller Registers List
USVC Register
Bit
7
6
5
4
3
2
1
0
Name
MUTEB
USVC6
USVC5
USVC4
USVC3
USVC2
USVC1
USVC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Rev. 1.10
MUTEB: Speaker Mute control
0: Mute speaker output
1: Enable speaker output
This bit is used to enable the speaker output function. When this bit is cleared to 0, the
speaker output will be muted.
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Enhanced Touch Voice A/D Flash MCU
Bit 6~0
USVC6~USVC0: Speaker volume control
000_1100:
Gain ≈ 6.0 dB
110_1110:
Gain ≈ -9.0 dB
000_1011:
Gain ≈ 5.5 dB
110_1101:
Gain ≈ -9.5 dB
000_1010:
Gain ≈ 5.0 dB
110_1100:
Gain ≈ -10.0 dB
000_1001:
Gain ≈ 4.5 dB
110_1011:
Gain ≈ -10.5 dB
000_1000:
Gain ≈ 4.0 dB
110_1010:
Gain ≈ -11.0 dB
000_0111:
Gain ≈ 3.5 dB
110_1001:
Gain ≈ -11.5 dB
000_0110:
Gain ≈ 3.0 dB
110_1000:
Gain ≈ -12.0 dB
000_0101:
Gain ≈ 2.5 dB
110_0111:
Gain ≈ -13.0 dB
000_0100:
Gain ≈ 2.0 dB
110_0110:
Gain ≈ -14.0 dB
000_0011:
Gain ≈ 1.5 dB
110_0101:
Gain ≈ -15.0 dB
000_0010:
Gain ≈ 1.0 dB
110_0100:
Gain ≈ -16.0 dB
000_0001:
Gain ≈ 0.5 dB
110_0011:
Gain ≈ -17.0 dB
000_0000:
Gain ≈ 0.0 dB
110_0010:
Gain ≈ -18.0 dB
111_1111:
Gain ≈ -0.5 dB
110_0001:
Gain ≈ -19.0 dB
111_1110:
Gain ≈ -1.0 dB
110_0000:
Gain ≈ -20.0 dB
111_1101:
Gain ≈ -1.5 dB
101_1111:
Gain ≈ -21.0 dB
111_1100:
Gain ≈ -2.0 dB
101_1110:
Gain ≈ -22.0 dB
111_1011:
Gain ≈ -2.5 dB
101_1101:
Gain ≈ -23.0 dB
111_1010:
Gain ≈ -3.0 dB
101_1100:
Gain ≈ -24.0 dB
111_1001:
Gain ≈ -3.5 dB
101_1011:
Gain ≈ -25.0 dB
111_1000:
Gain ≈ -4.0 dB
101_1010:
Gain ≈ -26.0 dB
111_0111:
Gain ≈ -4.5 dB
101_1001:
Gain ≈ -27.0 dB
111_0110:
Gain ≈ -5.0 dB
101_1000:
Gain ≈ -28.0 dB
111_0101:
Gain ≈ -5.5 dB
101_0111:
Gain ≈ -29.0 dB
111_0100:
Gain ≈ -6.0 dB
101_0110:
Gain ≈ -30.0 dB
111_0011:
Gain ≈ -6.5 dB
101_0101:
Gain ≈ -31.0 dB
111_0010:
Gain ≈ -7.0 dB
101_0100:
Gain ≈ -32.0 dB
Others:
Reserved
111_0001:
Gain ≈ -7.5 dB
111_0000:
Gain ≈ -8.0 dB
110_1111:
Gain ≈ -8.5 dB
These bits are used to control the output volume which ranges from -32dB~6dB. When
the USVC5~USVC0 bits value is changed, the new value will be loaded into the D/A
converter.
PLAC Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
PAEN
DAEN
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1
PAEN: Power Amplifier Enable control
0: Disable
1: Enable
Bit 0
DAEN: 16-bit D/A converter Enable control
0: Disable
1: Enable
Note that the 16-bit D/A converter and power amplifier will all be disabled when the
MCU enters the Power down Mode.
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Enhanced Touch Voice A/D Flash MCU
PLADL Register
Bit
7
6
5
4
3
2
1
0
Name
P_D7
P_D6
P_D5
P_D4
P_D3
P_D2
P_D1
P_D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
P_D7~P_D0: Play data low byte register bit 7~bit 0
This register is used to store the 16-bit play data low byte. Note that the low byte play
data register should first be modified followed by the high byte play data register being
written if the 16-bit play data is necessary to be updated.
PLADH Register
Bit
7
6
5
4
3
2
1
0
Name
P_D15
P_D14
P_D13
P_D12
P_D11
P_D10
P_D9
P_D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.10
P_D15~P_D8: Played data high byte register bit 7~bit 0
This register is used to store the 16-bit play data high byte data. Note that the low byte
play data register should first be modified followed by the high byte play data register
being written if the 16-bit play data is necessary to be updated.
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Enhanced Touch Voice A/D Flash MCU
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. These devices contain several external
interrupt and internal interrupts functions. The external interrupts are generated by the action of
the external INT0 and INT1 pins, while the internal interrupts are generated by various internal
functions such as the TMs, Time Base, LVD, EEPROM, SIM, UART and the A/D converter, etc.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the
accompanying table. The number of registers depends upon the device chosen but fall into three
categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second
is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG
register to setup the external interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual interrupts as well
as interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an "E" for enable/disable bit or "F" for request flag.
Function
Global
Enable Bit
Request Flag
EMI
—
INTn Pins
INTnE
INTnF
Touch Key
TKME
TKMF
UART
URE
URF
Multi-function
MFnE
MFnF
A/D Converter
ADE
ADF
Time Base
TBnE
TBnF
Notes
—
n=0~1
—
—
n=0~3
—
n=0~1
LVD
LVE
LVF
—
EEPROM write operation
DEE
DEF
—
—
SIM
SIME
SIMF
SPIA
SPIAE
SPIAF
—
CTMnPE
CTMnPF
CTMnAE
CTMnAF
n = 0 for BS66FV340
n = 0 ~ 1 for BS66FV350/BS66FV360
PTMnPE
PTMnPF
PTMnAE
PTMnAF
CTM
PTM
STM
STMPE
STMPF
STMAE
STMAF
n=0~1
—
Interrupt Register Bit Naming Conventions
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Bit
Register
Name
7
6
5
4
3
2
1
0
INTEG
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
—
INT1F
INT0F
MF0F
INT1E
INT0E
MF0E
EMI
INTC1
ADF
MF1F
URF
TKMF
ADE
MF1E
URE
TKME
INTC2
MF3F
TB1F
TB0F
MF2F
MF3E
TB1E
TB0E
MF2E
MFI0
—
—
CTM0AF
CTM0PF
—
—
CTM0AE CTM0PE
MFI1
STMAF
STMPF
—
—
STMAE
STMPE
—
—
MFI2
PTM1AF
PTM1PF
PTM0AF
PTM0PF
PTM1AE
PTM1PE
PTM0AE
PTM0PE
MFI3
SPIAF
SIMF
DEF
LVF
SPIAE
SIME
DEE
LVE
Interrupt Registers List – BS66FV340
Bit
Register
Name
7
6
5
4
3
2
1
0
INTEG
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
—
INT1F
INT0F
MF0F
INT1E
INT0E
MF0E
EMI
INTC1
ADF
MF1F
URF
TKMF
ADE
MF1E
URE
TKME
INTC2
MF3F
TB1F
TB0F
MF2F
MF3E
TB1E
TB0E
MF2E
MFI0
—
—
CTM0AF
CTM0PF
—
—
CTM0AE CTM0PE
MFI1
STMAF
STMPF
CTM1AF
CTM1PF
STMAE
STMPE
CTM1AE CTM1PE
MFI2
PTM1AF
PTM1PF
PTM0AF
PTM0PF
PTM1AE
PTM1PE
PTM0AE
PTM0PE
MFI3
SPIAF
SIMF
DEF
LVF
SPIAE
SIME
DEE
LVE
Interrupt Registers List – BS66FV350/BS66FV360
INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as "0"
Bit 3~2
INT1S1~INT1S0: Interrupt edge control for INT1 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 1~0
INT0S1~INT0S0: Interrupt edge control for INT0 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
INTC0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
INT1F
INT0F
MF0F
INT1E
INT0E
MF0E
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6
INT1F: INT1 interrupt request flag
0: No request
1: Interrupt request
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Enhanced Touch Voice A/D Flash MCU
Bit 5
INT0F: INT0 interrupt request flag
0: No request
1: Interrupt request
Bit 4
MF0F: Multi-function 0 interrupt request flag
0: No request
1: Interrupt request
Bit 3
INT1E: INT1 interrupt control
0: Disable
1: Enable
Bit 2
INT0E: INT0 interrupt control
0: Disable
1: Enable
Bit 1
MF0E: Multi-function 0 interrupt control
0: Disable
1: Enable
Bit 0
EMI: Global interrupt control
0: Disable
1: Enable
INTC1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
ADF
MF1F
URF
TKMF
ADE
MF1E
URE
TKME
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
ADF: A/D Converter interrupt request flag
0: No request
1: Interrupt request
Bit 6
MF1F: Multi-function 1 interrupt request flag
0: No request
1: Interrupt request
Bit 5
URF: UART transfer interrupt request flag
0: No request
1: Interrupt request
Bit 4
TKMF: Touch key interrupt request flag
0: No request
1: Interrupt request
Bit 3
ADE: A/D Converter interrupt control
0: Disable
1: Enable
Bit 2
MF1E: Multi-function 1 interrupt control
0: Disable
1: Enable
Bit 1
URE: UART transfer interrupt control
0: Disable
1: Enable
Bit 3
TKME: Touch key interrupt control
0: Disable
1: Enable
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Enhanced Touch Voice A/D Flash MCU
INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
MF3F
TB1F
TB0F
MF2F
MF3E
TB1E
TB0E
MF2E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
1
0
Bit 7
MF3F: Multi-function 3 interrupt request flag
0: No request
1: Interrupt request
Bit 6
TB1F: Time Base 1 interrupt request flag
0: No request
1: Interrupt request
Bit 5
TB0F: Time Base 0 interrupt request flag
0: No request
1: Interrupt request
Bit 4
MF2F: Multi-function 2 interrupt request flag
0: No request
1: Interrupt request
Bit 3
MF3E: Multi-function 3 interrupt control
0: Disable
1: Enable
Bit 2
TB1E: Time Base 1 interrupt control
0: Disable
1: Enable
Bit 1
TB0E: Time Base 0 interrupt control
0: Disable
1: Enable
Bit 0
MF2E: Multi-function 2 interrupt control
0: Disable
1: Enable
MFI0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
Name
—
—
CTM0AF
CTM0PF
—
—
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5
CTM0AF: CTM0 Comparator A match Interrupt request flag
0: No request
1: Interrupt request
Bit 4
CTM0PF: CTM0 Comparator P match Interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as "0"
Bit 1
CTM0AE: CTM0 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 0
CTM0PE: CTM0 Comparator P match Interrupt control
0: Disable
1: Enable
228
CTM0AE CTM0PE
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
MFI1 Register – BS66FV340
Bit
7
6
5
4
3
2
1
0
Name
STMAF
STMPF
—
—
STMAE
STMPE
—
—
R/W
R/W
R/W
—
—
R/W
R/W
—
—
POR
0
0
—
—
0
0
—
—
1
0
Bit 7
STMAF: STM Comparator A match Interrupt request flag
0: No request
1: Interrupt request
Bit 6
STMPF: STM Comparator P match Interrupt request flag
0: No request
1: Interrupt request
Bit 5~4
Unimplemented, read as "0"
Bit 3
STMAE: STM Comparator A match Interrupt control
0: Disable
1: Enable
Bit 2
STMPE: STM Comparator P match Interrupt control
0: Disable
1: Enable
Bit 1~0
Unimplemented, read as "0"
MFI1 Register – BS66FV350/BS66FV360
Rev. 1.10
Bit
7
6
5
4
3
2
Name
STMAF
STMPF
CTM1AF
CTM1PF
STMAE
STMPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
STMAF: STM Comparator A match Interrupt request flag
0: No request
1: Interrupt request
Bit 6
STMPF: STM Comparator P match Interrupt request flag
0: No request
1: Interrupt request
Bit 5
CTM1AF: CTM1 Comparator A match Interrupt request flag
0: No request
1: Interrupt request
Bit 4
CTM1PF: CTM1 Comparator P match Interrupt request flag
0: No request
1: Interrupt request
Bit 3
STMAE: STM Comparator A match Interrupt control
0: Disable
1: Enable
Bit 2
STMPE: STM Comparator P match Interrupt control
0: Disable
1: Enable
Bit 1
CTM1AE: CTM1 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 0
CTM1PE: CTM1 Comparator P match Interrupt control
0: Disable
1: Enable
229
CTM1AE CTM1PE
December 15, 2016
BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
MFI2 Register
Bit
7
6
5
4
3
2
1
0
Name
PTM1AF
PTM1PF
PTM0AF
PTM0PF
PTM1AE
PTM1PE
PTM0AE
PTM0PE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
PTM1AF: PTM1 Comparator A match Interrupt request flag
0: No request
1: Interrupt request
Bit 6
PTM1PF: PTM1 Comparator P match Interrupt request flag
0: No request
1: Interrupt request
Bit 5
PTM0AF: PTM0 Comparator A match Interrupt request flag
0: No request
1: Interrupt request
Bit 4
PTM0PF: PTM0 Comparator P match Interrupt request flag
0: No request
1: Interrupt request
Bit 3
PTM1AE: PTM1 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 2
PTM1PE: PTM1 Comparator P match Interrupt control
0: Disable
1: Enable
Bit 1
PTM0AE: PTM0 Comparator A match Interrupt control
0: Disable
1: Enable
Bit 0
PTM0PE: PTM0 Comparator P match Interrupt control
0: Disable
1: Enable
MFI3 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
SPIAF
SIMF
DEF
LVF
SPIAE
SIME
DEE
LVE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
SPIAF: SPIA Interrupt request flag
0: No request
1: Interrupt request
Bit 6
SIMF: SIM Interrupt request flag
0: No request
1: Interrupt request
Bit 5
DEF: Data EEPROM Interrupt request flag
0: No request
1: Interrupt request
Bit 4
LVF: LVD Interrupt request flag
0: No request
1: Interrupt request
Bit 3
SPIAE: SPIA Interrupt control
0: Disable
1: Enable
230
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Enhanced Touch Voice A/D Flash MCU
Bit 2
SIME: SIM Interrupt control
0: Disable
1: Enable
Bit 1
DEE: Data EEPROM Interrupt control
0: Disable
1: Enable
Bit 0
LVE: LVD Interrupt control
0: Disable
1: Enable
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/D
conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag
actually generates a program jump to the relevant interrupt vector is determined by the condition of
the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector;
if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be
generated and the program will not jump to the relevant interrupt vector. The global interrupt enable
bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a JMP which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a RETI, which retrieves the original Program Counter address from the
stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI
bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
Rev. 1.10
231
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Enhanced Touch Voice A/D Flash MCU
Legend
xxF
Request Flag� no auto �eset in ISR
xxF
Request Flag� auto �eset in ISR
xxE
Ena�le Bits
Inte��upts �ontained within
Multi-Fun�tion Inte��upts
CTM0 P
CTM0PF
CTM0PE
CTM0 A
CTM0AF
CTM0AE
Fo� BS��FV3�0/BS��FV3�0 only
CTM1 P
CTM1PF
CTM1PE
CTM1 A
CTM1AF
CTM1AE
STM P
STMPF
STMPE
STM A
STMAF
STMAE
PTM0 P
PTM0PF
PTM0PE
PTM0 A
PTM0AF
PTM0AE
PTM1 P
PTM1PF
PTM1PE
PTM1 A
PTM1AF
PTM1AE
LVD
LVF
LVE
EEPROM
DEF
DEE
SIM
SIMF
SIME
SPIA
SPIAF
SPIAE
EMI auto disa�led in ISR
Inte��upt
Na�e
Request
Flags
Ena�le
Bits
Maste�
Ena�le
M. Fun�t. 0
MF0F
MF0E
EMI
INT0 Pin
INT0F
INT0E
EMI
08H
INT1 Pin
INT1F
INT1E
EMI
0CH
Tou�h Key
TKMF
TKME
EMI
10H
UART
URF
URE
EMI
14H
M. Fun�t. 1
MF1F
MF1E
EMI
18H
A/D
ADF
ADE
EMI
1CH
M. Fun�t. �
MF�F
MF�E
EMI
�0H
Ti�e Base 0
TB0F
TB0E
EMI
�4H
Ti�e Base 1
TB1F
TB1E
EMI
�8H
M. Fun�t. 3
MF3F
MF3E
EMI
�CH
Vector P�io�ity
High
04H
Low
Interrupt Scheme
External Interrupt
The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external
interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set,
which will occur when a transition, whose type is chosen by the edge select bits, appears on the
external interrupt pins. To allow the program to branch to its respective interrupt vector address,
the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E,
must first be set. Additionally the correct interrupt edge type must be selected using the INTEG
register to enable the external interrupt function and to choose the trigger edge type. As the external
interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if
their external interrupt enable bit in the corresponding interrupt register has been set and the external
interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also
be setup as an input by setting the corresponding bit in the port control register. When the interrupt
is enabled, the stack is not full and the correct transition type appears on the external interrupt pin,
a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the
external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the
external interrupt pins will remain valid even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
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Enhanced Touch Voice A/D Flash MCU
Touch Key Interrupt
For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the Touch Key interrupt
enable TKME must be first set. An actual Touch Key interrupt will take place when the Touch Key
request flag, TKMF, is set, a situation that will occur when the time slot counter overflows. When
the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs, a
subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced,
the Touch Key interrupt request flag, TKMF, will be automatically reset and the EMI Bit will be
automatically cleared to disable other interrupts.
UART Transfer Interrupt
The UART Transfer Interrupt is controlled by several UART transfer conditions. When one of these
conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller.
These conditions are a transmitter data register empty, transmitter idle, receiver data available,
receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and UART Interrupt
enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of the
conditions described above occurs, a subroutine call to the UART Interrupt vector, will take place.
When the interrupt is serviced, the UART Interrupt flag, URF, will be automatically cleared. The
EMI bit will also be automatically cleared to disable other interrupts.
A/D Converter Interrupt
The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/
D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF,
is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit,
ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion
process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the
interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI
bit will also be automatically cleared to disable other interrupts.
Time Base Interrupt
The function of the Time Base Interrupt is to provide regular time signal in the form of an internal
interrupt. It is controlled by the overflow signal from its internal timer. When this happens its
interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt
vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be
set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine
call to its respective vector location will take place. When the interrupt is serviced, the interrupt
request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other
interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its
clock source, fPSC0 or fPSC1, originates from the internal clock source fSYS, fSYS/4 or fSUB and then
passes through a divider, the division ratio of which is selected by programming the appropriate bits
in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock
source which in turn controls the Time Base interrupt period is selected using the CLKSEL0[1:0]
and CLKSEL1[1:0] bits in the PSCR0 and PSCR1 register respectively.
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fSYS
fSYS/4
fSUB
M
U
X
fPSC0
P�es�ale� 0
TB0ON
fPSC0/�8 ~ fPSC0/�1�
M
U
X
TB0[�:0]
CLKSEL0[1:0]
fSYS
fSYS/4
fSUB
M
U
X
fPSC1
Ti�e Base 0 Inte��upt
P�es�ale� 1
fPSC1/�8 ~ fPSC1/�1�
M
U
X
TB1ON
CLKSEL1[1:0]
Ti�e Base 1 Inte��upt
TB1[�:0]
Time Base Interrupts
PSCR0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
CLKSEL01
CLKSEL00
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
unimplemented, read as "0"
Bit 1~0
CLKSEL01~CLKSEL00: Prescaler 0 clock source fPSC0 selection
00: fSYS
01: fSYS/4
1x: fSUB
PSCR1 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
CLKSEL11
CLKSEL10
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
unimplemented, read as "0"
Bit 1~0
CLKSEL11~CLKSEL10: Prescaler 1 clock source fPSC1 selection
00: fSYS
01: fSYS/4
1x: fSUB
TB0C Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
TB0ON
—
—
—
—
TB02
TB01
TB00
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7
TB0ON: Time Base 0 Enable Control
0: Disable
1: Enable
Bit 6~3
unimplemented, read as "0"
Bit 2~0
TB02~TB00: Time Base 0 time-out period selection
000: 28/fPSC0
001: 29/fPSC0
010: 210/fPSC0
011: 211/fPSC0
100: 212/fPSC0
101: 213/fPSC0
110: 214/fPSC0
111: 215/fPSC0
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Enhanced Touch Voice A/D Flash MCU
TB1C Register
Bit
7
6
5
4
3
2
1
0
Name
TB1ON
—
—
—
—
TB12
TB11
TB10
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7
Bit 6~3
Bit 2~0
TB1ON: Time Base 1 Enable Control
0: Disable
1: Enable
unimplemented, read as "0"
TB12~TB10: Time Base 1 time-out period selection
000: 28/fPSC1
001: 29/fPSC1
010: 210/fPSC1
011: 211/fPSC1
100: 212/fPSC1
101: 213/fPSC1
110: 214/fPSC1
111: 215/fPSC1
Multi-function Interrupt
Within the device there are up to four Multi-function interrupts. Unlike the other independent
interrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM interrupts, LVD interrupt, EEPROM write operation interrupt,
SIM and SPIA interface interrupts.
A Multi-function interrupt request will take place when any of the Multi-function interrupt request
flags MFnF are set. The Multi-function interrupt flags will be set when any of their included
functions generate an interrupt request flag. To allow the program to branch to its respective interrupt
vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one
of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of
the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts.
However, it must be noted that, although the Multi-function Interrupt request flags will be
automatically reset when the interrupt is serviced, the request flags from the original source of
the Multi-function interrupts will not be automatically reset and must be manually reset by the
application program.
TM Interrupt
The Compact, Standard and Periodic TMs have two interrupts, one comes from the comparator A
match situation and the other comes from the comparator P match situation. All of the TM interrupts
are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt
request flags and two enable control bits. A TM interrupt request will take place when any of the TM
request flags are set, a situation which occurs when a TM comparator P or A match situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE,
must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match
situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take
place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other
interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.
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Enhanced Touch Voice A/D Flash MCU
LVD Interrupt
The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD
Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs
when the Low Voltage Detector function detects a low power supply voltage. To allow the program
to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage
Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When
the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to
the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function
interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically
cleared, it has to be cleared by the application program.
EEPROM Interrupt
The EEPROM Write Interrupt is contained within the Multi-function Interrupt. An EEPROM
Write Interrupt request will take place when the EEPROM Write Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, EEPROM Write Interrupt enable bit,
DEE, and associated Multi-function interrupt enable bit must first be set. When the interrupt is
enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective
Multi-function Interrupt vector will take place. When the EEPROM Write Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function
interrupt request flag will be automatically cleared. As the DEF flag will not be automatically
cleared, it has to be cleared by the application program.
Serial Interface Module Interrupt
The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the
Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request
flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM
interface, an I2C slave address match or I2C bus time-out occurrence. To allow the program to
branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial
Interface Interrupt enable bit, SIME, and Multi-function interrupt enable bit must first be set. When
the interrupt is enabled, the stack is not full and any of the above described situations occurs, a
subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial
Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts,
however only the Multi-function interrupt request flag will be also automatically cleared. As the
SIMF flag will not be automatically cleared, it has to be cleared by the application program.
SPIA Interface Interrupt
The SPIA Interface Module Interrupt is contained within the Multi-function Interrupt. A SPIA Interrupt
request will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte
of data has been received or transmitted by the SPIA interface. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, the Serial Interface Interrupt
enable bit, SPIAE, and Multi-function interrupt enable bit must first be set. When the interrupt is
enabled, the stack is not full and a byte of data has been transmitted or received by the SPIA interface,
a subroutine call to the respective Multi-function Interrupt vector, will take place. When the SPIA
Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts.
However, only the Multi-function interrupt request flag will be also automatically cleared. As the
SPIAF flag will not be automatically cleared, it has to be cleared by the application program.
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Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low
to high and is independent of whether the interrupt is enabled or not. Therefore, even though these
devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as
external edge transitions on the external interrupt pins, a low power supply voltage or comparator
input change may cause their respective interrupt flag to be set high and consequently generate
an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an
interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be
set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect
on the interrupt wake-up function.
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be
automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the "CALL" instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
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Application Circuits
5V Application
VCC(5V)
HT7133-1
VDD
V33
LDO
VCC(5V)
22µF
0.1µF
10µF
VDD
VDD
1Ω
47µF
BIAS
Key1
10µF
VDD: Digital Power
AVDD_PA: Power Amplifier Power
AVDD_PA
AUD
Note:
Digital Volume Control
Without VR
1nF
XT1
PB2/VDDIO
XT2
4
PC4/SDOA
PC5/SCKA
PC6/SDIA
PC7/SCSAB
OSC1
OSC2
RX
I/O
I/O
Speaker
8Ω
1µF
1kΩ
10kΩ
SP+
SP-
F/W enable VDDIO function
by PBS0 register
SPI Flash
ROM
2.7kΩ
A/D
V33
SPI Flash ROM maximum
operating voltage is 3.6V
1µF
AUD_IN
Keyx
Analog signal
10μF
1nF
RTC
32768Hz
Note:
VR (Variable Resistor)
for Volume Control
System
Crystal
RS_DIR
TX
RS488
Transceiver
SCOMx
SSEGx
VSS
AVSS_PA
TM
PWM / Capture
VSS: Digital Ground
AVSS_PA: Power Amplifier Ground
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Enhanced Touch Voice A/D Flash MCU
3V Application
47µF
VDD
VDD
VCC(3.3V)
1Ω
10µF
VCC(3.3V)
22µF
0.1µF
VDD
VDD: Digital Power
AVDD_PA: Power Amplifier Power
AVDD_PA
BIAS
Key1
AUD
1µF
2.7kΩ
AUD_IN
Keyx
Analog signal
10μF
1nF
A/D
F/W disable VDDIO
function by PBS0 register
XT1
PB2/VDDIO
XT2
SPI Flash ROM maximum
operating voltage is 3.6V
SPI FLASH
ROM
4
PC4/SDOA
PC5/SCKA
PC6/SDIA
PC7/SCSAB
OSC1
OSC2
RX
I/O
I/O
Speaker
8Ω
1µF
1kΩ
1nF
RTC
32768Hz
10kΩ
SP+
SP-
VDD
Note:
Digital Volume Control
Without VR
Note:
VR (Variable Resistor)
for Volume Control
System
Crystal
RS_DIR
TX
RS488
Transceiver
SCOMx
SSEGx
VSS
AVSS_PA
TM
PWM / Capture
VSS: Digital Ground
AVSS_PA: Power Amplifier Ground
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].
i" instructions respectively. The feature removes the need for programmers to first read the 8-bit
output port, manipulate the input data to ensure that other bits are not changed and then output the
port with the correct new data. This read-modify-write process is taken care of automatically when
these bit operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The instructions related to the data memory access in the following table can be used when the
desired data memory is located in Data Memory sector 0.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract immediate data from ACC with Carry
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1
1Note
1Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,x
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
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Enhanced Touch Voice A/D Flash MCU
Mnemonic
Description
Cycles Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2Note
2Note
2Note
None
None
None
2Note
None
1
1Note
1Note
1
1Note
1
1
None
None
None
TO, PDF
None
None
TO, PDF
Bit Operation
CLR [m].i
SET [m].i
Branch Operation
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m]
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if Data Memory is not zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
Table Read Operation
TABRD [m] Read table (specific page) to TBLH and Data Memory
TABRDL [m] Read table (last page) to TBLH and Data Memory
ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
ITABRDL [m]
Data Memory
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
SWAP [m]
SWAPA [m]
HALT
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if
no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT” instruction the TO and PDF flags may be affected by the execution status. The TO
and PDF flags are cleared after the “CLR WDT” instructions is executed. Otherwise the TO and PDF
flags remain unchanged.
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Enhanced Touch Voice A/D Flash MCU
Extended Instruction Set
The extended instructions are used to support the full range address access for the data memory.
When the accessed data memory is located in any data memory sections except sector 0, the
extended instruction can be used to access the data memory instead of using the indirect addressing
access to improve the CPU firmware performance.
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
2
2Note
2
2Note
2
2Note
2
2Note
2Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
2
2
2
2Note
2Note
2Note
2Note
2
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
2
2Note
2
2Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
2
2Note
2
2Note
2
2Note
2
2Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
2
2Note
None
None
Clear bit of Data Memory
Set bit of Data Memory
2Note
2Note
None
None
Arithmetic
LADD A,[m]
LADDM A,[m]
LADC A,[m]
LADCM A,[m]
LSUB A,[m]
LSUBM A,[m]
LSBC A,[m]
LSBCM A,[m]
LDAA [m]
Logic Operation
LAND A,[m]
LOR A,[m]
LXOR A,[m]
LANDM A,[m]
LORM A,[m]
LXORM A,[m]
LCPL [m]
LCPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
LINCA [m]
LINC [m]
LDECA [m]
LDEC [m]
Rotate
LRRA [m]
LRR [m]
LRRCA [m]
LRRC [m]
LRLA [m]
LRL [m]
LRLCA [m]
LRLC [m]
Data Move
LMOV A,[m]
LMOV [m],A
Bit Operation
LCLR [m].i
LSET [m].i
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
Mnemonic
Description
Cycles Flag Affected
Branch
LSZ [m]
LSZA [m]
LSNZ [m]
LSZ [m].i
LSNZ [m].i
LSIZ [m]
LSDZ [m]
LSIZA [m]
LSDZA [m]
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if Data Memory is not zero
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
None
None
None
None
None
None
None
None
None
3Note
3Note
3Note
None
None
None
3Note
None
2Note
2Note
2Note
2
None
None
None
None
Table Read
LTABRD [m] Read table to TBLH and Data Memory
LTABRDL [m] Read table (last page) to TBLH and Data Memory
LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
LITABRDL [m]
Data Memory
Miscellaneous
LCLR [m]
LSET [m]
LSWAP [m]
LSWAPA [m]
Clear Data Memory
Set Data Memory
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles
are required, if no skip takes place two cycles is required.
2. Any extended instruction which changes the contents of the PCL register will also require three cycles for
execution.
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Enhanced Touch Voice A/D Flash MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
ADCM A,[m]
Description
Operation
Affected flag(s)
ADD A,[m]
Description
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
Add Data Memory to ACC
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
ADD A,x
Description
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added.
The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C, SC
Operation
Affected flag(s)
ADDM A,[m]
Description
Operation
Affected flag(s)
AND A,[m]
Description
Operation
Affected flag(s)
AND A,x
Description
Operation
Affected flag(s)
ANDM A,[m]
Description
Operation
Affected flag(s)
Rev. 1.10
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND
operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
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Enhanced Touch Voice A/D Flash MCU
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CALL addr
Description
Operation
Affected flag(s)
CPL [m]
Description
Operation
Affected flag(s)
CPLA [m]
Description
Operation
Affected flag(s)
DAA [m]
Description
Operation
Affected flag(s)
Rev. 1.10
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or
[m] ← ACC + 60H or
[m] ← ACC + 66H
C
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Enhanced Touch Voice A/D Flash MCU
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
Operation
Affected flag(s)
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of
the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
HALT
Description
Operation
Operation
Affected flag(s)
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
JMP addr
Description
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
Operation
Affected flag(s)
OR A,x
Description
Operation
Affected flag(s)
ORM A,[m]
Description
Operation
Affected flag(s)
RET
Description
Operation
Affected flag(s)
RET A,x
Description
Operation
Affected flag(s)
RETI
Description
Operation
Affected flag(s)
RL [m]
Description
Operation
Affected flag(s)
Rev. 1.10
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR
operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified
immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the
RETI instruction is executed, the pending Interrupt routine will be processed before returning
to the main program.
Program Counter ← Stack
EMI ← 1
None
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
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Enhanced Touch Voice A/D Flash MCU
RLA [m]
Description
Operation
Affected flag(s)
RLC [m]
Description
Operation
Affected flag(s)
RLCA [m]
Description
Operation
Affected flag(s)
RR [m]
Description
Operation
Affected flag(s)
RRA [m]
Description
Operation
Affected flag(s)
RRC [m]
Description
Operation
Affected flag(s)
Rev. 1.10
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
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Enhanced Touch Voice A/D Flash MCU
RRCA [m]
Description
Operation
Affected flag(s)
SBC A,[m]
Description
Operation
Affected flag(s)
SBC A, x
Description
Operation
Affected flag(s)
SBCM A,[m]
Description
Operation
Affected flag(s)
SDZ [m]
Description
Operation
Affected flag(s)
SDZA [m]
Description
Operation
Affected flag(s)
Rev. 1.10
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces
the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
Subtract immediate data from ACC with Carry
The immediate data and the complement of the carry flag are subtracted from the
Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is
negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag
will be set to 1.
ACC ← ACC - [m] - C
OV, Z, AC, C, SC, CZ
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
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Enhanced Touch Voice A/D Flash MCU
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
Operation
Affected flag(s)
SIZA [m]
Description
Operation
Affected flag(s)
SNZ [m].i
Description
Operation
Affected flag(s)
SNZ [m]
Description
Operation
Affected flag(s)
SUB A,[m]
Description
Operation
Affected flag(s)
Rev. 1.10
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m]≠ 0
None
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
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Enhanced Touch Voice A/D Flash MCU
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator.
The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C, SC, CZ
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SUB A,x
Description
Operation
Affected flag(s)
SZ [m]
Description
Operation
Affected flag(s)
SZA [m]
Description
Operation
Affected flag(s)
SZ [m].i
Description
Operation
Affected flag(s)
Rev. 1.10
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero,
the following instruction is skipped. As this requires the insertion of a dummy instruction
while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
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Enhanced Touch Voice A/D Flash MCU
TABRD [m]
Description
Operation
Affected flag(s)
TABRDL [m]
Description
Operation
Affected flag(s)
ITABRD [m]
Description
Operation
Affected flag(s)
ITABRDL [m]
Description
Operation
Affected flag(s)
XOR A,[m]
Description
Operation
Affected flag(s)
XORM A,[m]
Description
Operation
Affected flag(s)
XOR A,x
Description
Operation
Affected flag(s)
Rev. 1.10
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair
(TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved
to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the
table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte
moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code
(last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and
the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
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Extended Instruction Definition
The extended instructions are used to directly access the data stored in any data memory sections.
LADC A,[m]
Description
Operation
Affected flag(s)
LADCM A,[m]
Description
Operation
Affected flag(s)
LADD A,[m]
Description
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
Add Data Memory to ACC
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
LADDM A,[m]
Description
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
Operation
Affected flag(s)
LAND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
LCLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
LCLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
LANDM A,[m]
Description
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
LCPL [m]
Description
Operation
Affected flag(s)
LCPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or
[m] ← ACC + 60H or
[m] ← ACC + 66H
C
LDEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
LDECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
LINC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
LINCA [m]
Description
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
LDAA [m]
Description
Operation
Operation
Affected flag(s)
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
LMOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
LMOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
LOR A,[m]
Description
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
Operation
Affected flag(s)
LORM A,[m]
Description
Operation
Affected flag(s)
LRL [m]
Description
Operation
Affected flag(s)
LRLA [m]
Description
Operation
Affected flag(s)
LRLC [m]
Description
Operation
Affected flag(s)
LRLCA [m]
Description
Operation
Affected flag(s)
Rev. 1.10
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
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Enhanced Touch Voice A/D Flash MCU
LRR [m]
Description
Operation
Affected flag(s)
LRRA [m]
Description
Operation
Affected flag(s)
LRRC [m]
Description
Operation
Affected flag(s)
LRRCA [m]
Description
Operation
Affected flag(s)
LSBC A,[m]
Description
Operation
Affected flag(s)
LSBCM A,[m]
Description
Operation
Affected flag(s)
Rev. 1.10
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces
the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
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LSDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
LSET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
LSET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
LSIZ [m]
Description
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
LSDZA [m]
Description
Operation
Operation
Affected flag(s)
LSIZA [m]
Description
Operation
Affected flag(s)
LSNZ [m].i
Description
Operation
Affected flag(s)
Rev. 1.10
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
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LSNZ [m]
Description
Operation
Affected flag(s)
LSUB A,[m]
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the content of the specified Data Memory is not 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m] ≠ 0
None
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
LSWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
LSWAPA [m]
Description
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
LSUBM A,[m]
Description
Operation
Affected flag(s)
LSZ [m]
Description
Operation
Affected flag(s)
LSZA [m]
Description
Operation
Affected flag(s)
Rev. 1.10
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero,
the following instruction is skipped. As this requires the insertion of a dummy instruction
while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
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LSZ [m].i
Description
Operation
Affected flag(s)
LTABRD [m]
Description
Operation
Affected flag(s)
LTABRDL [m]
Description
Operation
Affected flag(s)
LITABRD [m]
Description
Operation
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved
to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the
table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte
moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
Affected flag(s)
None
LITABRDL [m]
Description
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code
(last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and
the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
Operation
Affected flag(s)
LXOR A,[m]
Description
Operation
Affected flag(s)
LXORM A,[m]
Description
Operation
Affected flag(s)
Rev. 1.10
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
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Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the Package/Carton Information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.10
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Enhanced Touch Voice A/D Flash MCU
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.472 BSC
—
B
—
0.394 BSC
—
C
—
0.472 BSC
—
D
—
0.394 BSC
—
E
—
0.032 BSC
—
F
0.012
0.015
0.018
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
A
—
12.00 BSC
—
B
—
10.00 BSC
—
C
—
12.00 BSC
—
D
—
10.00 BSC
—
E
—
0.80 BSC
—
F
0.30
0.37
0.45
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
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Enhanced Touch Voice A/D Flash MCU
48-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.020 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
―
0.008
α
0°
―
7°
Symbol
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.50 BSC
—
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
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BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
Copyright© 2016 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.10
265
December 15, 2016