EtronTech Em614163A-30/35/40/45 256K x 16 High Speed EDO DRAM Preliminary Features Pin Assignment (Top View) • Fast Access Time: 30/35/40/45ns 40-Pin SOJ 40/44-Pin TSOP-II • Fast EDO Page Cycle Time: 13.3/15/16/18ns • EDO Page Mode Operation • Single +5V ¡Ó 10% Power Supply • Low Power Dissipation • Individual Byte Control via Dual CAS Inputs • Three Refresh Modes • 512-Cycle Refresh in 8ms(9 rows and 9 columns) • TTL Compatible • 40-Pin, 400-mil Plastic SOJ Package, or 40/44-Pin, 400-mil Plastic TSOP-II Package. Ordering Information Part Number Em614163A-30 EM614163TS-30 Em614163A-35 EM614163TS-35 Em614163A-40 EM614163TS-40 Em614163A-45 EM614163TS-45 Speed 30ns 30ns 35ns 35ns 40ns 40ns 45ns 45ns Package SOJ TSOP-II SOJ TSOP-II SOJ TSOP-II SOJ TSOP-II Key Specifications Speed -30 -35 -40 -45 tRAC 30ns 35ns 40ns 45ns tCAC 9ns 10ns 11ns 12ns tAA 16ns 18ns 20ns 22ns tOEA 9ns 9ns 10ns 10ns tRC tPC 53ns 13.3ns 60ns 15ns 66ns 16ns 75ns 18ns Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vss I/O15 I/O14 I/O13 I/O12 Vss I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 Vss I/O15 I/O14 I/O13 I/O12 Vss I/O11 I/O10 I/O9 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LC AS UCAS OE A8 A7 A6 A5 A4 Vss Pin Names A0 - A8 Address Inputs RAS Row Address Strobe UCAS Column Address Strobe (Upper Byte Control) LCAS Column Address Strobe (Lower Byte Control) WE Write Enable OE Output Enable I/O0 - I/O15 Data Input/Output VCC +5V Power Supply VSS Ground NC No Connection Overview The Em614163A-30/35/40/45 is a high speed EDO(Extended Data Output) DRAM organized in 262,144 words by 16 bits. It supports EDO Page Mode and 16-bit data width for high data bandwidth applications. The EDO Page Mode is an accelerated access that provides a shorter page cycle and a faster data access time than the traditional Fast Page Mode. precharge time to occur without the output data going invalid. Therefore, the EDO CAS timing can be condensed to carry more data out in a given period. Compared with Fast Page Mode DRAM, the EDO DRAM data output will be held valid after CAS goes HIGH, as long as RAS and OE are held LOW and WE is held HIGH. This feature allows CAS The Em614163A-30/35/40/45 is ideally suitable for high performance graphics frame buffers, CDROMs, disk drivers, set top boxes, and DSP applications. The Em614163A-30/35/40/45 fully utilizes the EDO Page Mode advantages. It allows 512 random access within a page with a fast cycle time as short as 13.3/15/16/18 ns. Etron Technology, Inc. 1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5779001 Etro n Techn olo gy, Inc. reserves th e right to make chan ges to its pro ducts and specificat ion s without notice. April 1997 EtronTech Em614163A-30/35/40/45 Block Diagram RAS LCAS Clock Ge nerator Circuit Vcc (5 V) x 3 Vss (0 V) x 3 Lower UCAS Lower Data-In Buffer DO0 DO1 .......... WE Lower Data-Out Buffer Row Decoder Row & Column Address Buffer Upper Data-Out Buffer Memo ry Cell DO8 DO9 .......... .......... .......... Preliminary Sense Amplifier & I/O Control A8 DO7 Upper Data-In Buffer .......... A0 Lower Data In pu ts/Ou tpu ts Column Decoder A0 - A8 A0 A1 A2 A3 A4 A5 A6 A7 A8 .......... Upper DO15 OE 2 Upper Data In pu ts/Ou tpu ts Ou tp ut Enable In pu t April 1997 EtronTech Em614163A-30/35/40/45 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VT - 0.5 to +7.0 V Supply voltage relative to VSS VCC - 0.5 to +7.0 V Short circuit output current IOUT 50 mA PT 1.0 W Operating temperature TOPT 0 to +70 °C Storage temperature TSTG - 55 to +125 °C Power dissipation Capacitance (Ta = 25°C; VCC = 5V ¡Ó 10%; f = 1MHz) Parameter Symbol Typ. Max. Unit Input capacitance (A0 - A8) Input capacitance ( RAS , UCAS , LCAS , WE , OE ) Output capacitance(I/O0 - I/O15) Notes: 1. Capacitance is sampled and not 100% tested. Note CI 1 ¡Ð 5 pF 1 CI 2 ¡Ð 5 pF 1 CI/O ¡Ð 7 pF 1 Truth Table Function RAS LCAS UCAS WE OE Addresses tR tC DQs Standby H H →X H →X X X X X Read: Word L L L H L ROW COL Read: Lower Byte L L H H L ROW COL Read: Upper Byte L H L H L ROW COL L L L L X ROW COL L L H L X ROW COL L H L L X ROW COL L L L H →L L →H ROW COL Data-out, Data-in H →L Write: Word (Early Write) Write: Lower Byte (Early) Write: Upper Byte (Early) Read Write Notes High-Z Data-out Lower byte, data-out Upper byte, high-Z Lower byte, high-Z Upper byte, data-out Data-in Lower byte, data-in Upper byte, high-Z Lower byte, high-Z Upper byte, data-in 1, 2 EDO-Page- 1st Cycle L H →L H L ROW COL Data-out 2 Mode Read 2nd Cycle L H →L H →L H L n/a COL Data-out 2 EDO-Page- 1st Cycle L H →L H →L L X ROW COL Data-in 1 Mode Write 2nd Cycle L H →L H →L L X n/a COL Data-in 1 H →L H →L L →H ROW COL Data-out, Data-in 1, 2 1, 2 EDOPage-Mode Read-Write 1st Cycle L H →L 2nd Cycle L H →L H →L H →L L →H n/a COL Data-out, Data-in Hidden Read L →H →L L L H L ROW COL Data-out Refresh Write L →H →L L L L X ROW COL Data-in L H H X X ROW n/a High-Z H →L L L X X X X High-Z RAS# only refresh CBR Refresh 2 1, 3 4 Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. Preliminary 3 April 1997 EtronTech Em614163A-30/35/40/45 4. At least one of the two CAS signals must be active ( LCAS or UCAS ). Preliminary 4 April 1997 EtronTech Em614163A-30/35/40/45 Recommended Operating Conditions Parameter Symbol Supply voltage Min Typ Max Unit Notes VSS 0 0 0 V 2 VCC 4.5 5.0 5.5 V 1, 2 Input high voltage VIH 2.4 ¡Ð VCC + 0.3 V 1 Input low voltage VIL - 0.5 ¡Ð 0.8 V 1, 3 Notes: 1. All voltage referenced to VSS. 2. The supply voltage with all VCC pins must be the same level. The supply voltage with all VSS pins must be the same level. 3. VIL(min.) = - 1.2V for pulse width ¡Ø 30ns. DC Characteristics TA = 0 to +70°C; Vcc = +5V ± 10%, Vss = 0V Em614163A Parameter Operating current Standby current RAS -only refresh Symbol ICC 1 ICC 2 ICC 3 current Test Conditions -30/35/40/45 RAS cycling LCAS , UCAS cycling tRC = min. RAS , LCAS , UCAS = VIH Dout = High-Z RAS , LCAS , UCAS , OE = VCC - 0.2V Dout = High-Z RAS cycling, CAS = VIH tRC = min. RAS = VIH LCAS , UCAS = VIL Dout = enable Unit Notes 1, 2 Min Max ¡Ð 280/250/225/200 mA ¡Ð 2 mA ¡Ð 1 mA ¡Ð 280/250/225/200 mA 2 ¡Ð 5 mA 1 Standby current ICC 5 CAS -before- RAS refresh current ICC 6 tRC = min. RAS , CAS cycling ¡Ð 280/250/225/200 mA Fast page mode current ICC 7 tPC = min. ¡Ð 280/250/225/200 mA Input leakage current ILI 0V¡ÕVin¡ÕVCC -10 10 µA Output leakage current ILO 0V¡ÕVout¡ÕVCC Dout = Disable -10 10 µA 2.4 Output high voltage VOH IOH = - 2.5 mA Output low voltage VOL IOL = + 2.1 mA 1, 3 V 0.4 V Notes: 1. ICC depends on output load condition when the device is selected. ICC -max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while LCAS and UCAS = VIL. 4. All the VCC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage. Preliminary 5 April 1997 EtronTech Em614163A-30/35/40/45 AC Characteristics (2, 3, 4, 5) (Ta = 0 to +70°C; VCC = 5V ¡Ó 10%, VSS = 0V) Test Conditions • Input rise and fall times: 2ns • AC test condition, input pulse levels 0V to 3V • Output load: 1 TTL loads and 50pF • Output timing reference levels: VOH = 2.0V VOL = 0.8V Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Em614163A Parameter Symbol -30/35/40/45 Min Max Unit Notes 1 Random read or write cycle time RAS precharge time tRC 53/60/66/75 ¡Ð ns tRP 19/21/22/26 ¡Ð ns RAS pulse width tRAS 30/35/40/45 100,000 ns 6 U/LCAS pulse width tCAS 5/6/7/8 100,000 ns 7 Row address setup time tASR 0 ¡Ð ns Row address hold time tRAH 6/6/6/7 ¡Ð ns Column address setup time tASC 0 ¡Ð ns 8 Column address hold time RAS to U/LCAS delay time tCAH 5/6/6/7 ¡Ð ns 8 tRCD 10/11/12/13 21/25/29/33 ns 9 RAS to column address delay time tRAD 8/9/10/11 15/17/18/20 ns 10 Column address to RAS lead time tRAL 16/18/20/22 ¡Ð ns RAS hold time tRSH 6/7/7/8 ¡Ð ns U/LCAS hold time tCSH 30/35/40/45 ¡Ð ns Column address hold time from RAS tAR 22/25/30/35 ¡Ð ns Write command time from RAS tWCR 22/25/30/35 ¡Ð ns Data-in hold time from RAS tDHR 22/25/30/35 ¡Ð ns U/LCAS to RAS precharge time tCRP 5/5/5/5 ¡Ð ns OE to data-in delay time tOED 7/7/8/8 ¡Ð ns tT 1 50 ns tREF ¡Ð 8 ms tCLZ 0 Transition time (rise and fall) Refresh period CAS to output in Low-Z Preliminary 6 11 12 ns April 1997 EtronTech Em614163A-30/35/40/45 Read Cycle Em614163A Parameter Symbol -30/35/40/45 Unit Notes Min Max tRAC ¡Ð 30/35/40/45 ns 13 tCAC ¡Ð 9/10/11/12 ns 14, 15, 16 Access time from column address tAA ¡Ð 16/18/20/22 ns 15, 17 Access time from OE tOEA ¡Ð 9/9/10/10 ns Read command setup time tRCS 0 ¡Ð ns 8 Read command hold time to U/LCAS tRCH 0 ¡Ð ns 11, 18 Read command hold time to RAS tRRH 0 ¡Ð ns 18 Output buffer turn-off time Output buffer turn-off OE tOFF 0 6/7/8/8 ns 19 tOEZ 0 6/7/8/8 ns 19 Access time from RAS Access time from U/LCAS Write Cycle Write command setup time tWCS 0 ¡Ð ns 8, 20 Write command hold time tWCH 5/6/6/6 ¡Ð ns 8 Write command pulse width Write command to RAS lead time tWP 5/6/6/6 ¡Ð ns tRWL 10 ¡Ð ns Write command to U/LCAS lead time tCWL 5/5/6/6 ¡Ð ns 21 Data-in setup time tDS 0 ¡Ð ns 22 Data-in hold time OE hold time from WE tDH 5/6/6/7 ¡Ð ns 22 tOEH 5/6/6/6 ¡Ð ns Read-Modify-Write Cycle Em614163A Parameter Symbol -30/35/40/45 Min Max Unit Notes Read-modify-write cycle time RAS to WE delay time tRWC 73/83/90/100 ¡Ð ns 1 tRWD 41/49/54/60 ¡Ð ns 20 U/LCAS to WE delay time tCWD 20/24/25/27 ¡Ð ns 20 Column address to WE delay time tAWD 33/40/44/49 ¡Ð ns 20 tCSR 6/7/8/9 ¡Ð ns 8 tCHR 7/8/9/10 ¡Ð ns 11 tRPC 5 ¡Ð ns 8 tCPN 5/5/5/6 ¡Ð ns 23 Refresh Cycle U/LCAS setup time ( CAS -before- RAS refresh cycle) U/LCAS hold time ( CAS -before- RAS refresh cycle) RAS precharge to U/LCAS hold time U/LCAS precharge time in normal mode Preliminary 7 April 1997 EtronTech Em614163A-30/35/40/45 EDO Page Mode Cycle Em614163A Parameter Symbol -30/35/40/45 Unit Notes Min Max tPC 13.3/15/16/18 ¡Ð ns 25 23 EDO page mode cycle time EDO page mode U/LCAS precharge time EDO page mode RAS pulse width tCP 5/5/5/6 ¡Ð ns tRASP 30/35/40/45 100,000 ns 24 Access time from U/LCAS precharge tCPA ¡Ð 18/21/23/25 ns 11, 15 tCPRH 13/14/15/16 ¡Ð ns tCPW 27/31/36/41 ¡Ð ns tPRWC 35/40/45/50 ¡Ð ns tOES 5 ¡Ð ns tOEHC 6 ¡Ð ns tOEP 6 ¡Ð ns tORD 0 ¡Ð ns RAS hold time from U/LCAS precharge EDO page mode read-modify-write cycle U/LCAS precharge to WE delay time EDO page mode read-modify-write cycle time OE low to CAS high setup time OE high hold time from CAS high OE high pulse width OE setup prior to RAS during hidden refresh cycle Data output hold after CAS low tCOH 3/3/3/5 ¡Ð ns Output disable delay from WE tWHZ 0 13 ns WE pulse width for output disable when CAS high tWPZ 6 ¡Ð ns tCPT 30 ¡Ð ns 11 Counter Test Cycle U/LCAS precharge time in counter test cycle Preliminary 8 23 April 1997 EtronTech Em614163A-30/35/40/45 Notes: 1. Assume tT = 2ns. 2. An initial pause of 100 us is required after power up followed by a minimum of eight initialization cycles ( RAS -only refresh cycle or CAS -beofre- RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS -before- RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the device. LCAS and UCAS cannot be straggered within the same write/read cycles. 5. All the VCC and all the VSS pins shall be supplied with the same voltages. 6. tRAS(min) = tRWD (min) + tRWL(min) + tT in read-modify-write cycle. 7. tCAS(min) = tCWD (min) + tCWL(min) + tT in read-modify-write cycle. 8. tASC , tCAH , tRCS, tCSR , tWCS, tWCH , and tRPC are determined by the earlier falling edge of UCAS or LCAS . 9. Operation with the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only: If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 10. Operation with the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only: If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 11. tCRP, tCHR , tRCH , tCPA and tCPW are determined by the later rising edge of UCAS or LCAS . 12. VIH (min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 13. Assumes that tRCD ¡Ø tRCD (max) and tRAD ¡Ø tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 14. Assumes that tRCD ¡Ø tRCD (max) and tRAD ¡Ø tRAD (max). 15. Access time is determined by the longer of tAA or tCAC or tCPA. 16. tCAC is guaranteed for one TTL and 50pF load. 17. Assumes that tRCD ¡Ø tRCD (max) and tRAD ¡Ø tRAD (max). 18. Either tRCH or tRRH must be satisfied for a read cycle. 19. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. The tOFF is determined by the later rising edge of RAS or CAS . 20. tWCS, tRWD , tCWD , and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS¡Ù tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ¡Ù tRWD (min), tCWD ¡Ù tCWD (min), tAWD ¡Ù tAWD (min) and tCPW ¡Ù tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 21. tCWL shall be satisfied by both UCAS , LCAS . 22. These parameters are referenced to UCAS or LCAS leading edge in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 23. tCPN , tCP, and tCPT are determined by the time that both UCAS and LCAS are high. 24. tRASP defines RAS pulse width in fast page mode cycles. 25. Assume tT = 2ns. Preliminary 9 April 1997 EtronTech Em614163A-30/35/40/45 Timing Waveforms • Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH tT t CAS UCAS LCAS t RAD t ASR Address t RAH t RAL t ASC Row t CAH Column t RRH t RCH t RCS WE t DZC t CDD OPEN DIN t ODD t DZO OE t OEA t OEZ t CAC t AA t OFF t RAC DOUT Preliminary D OUT 10 April 1997 EtronTech Em614163A-30/35/40/45 • Early Write Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH tT t CAS UCAS LCAS t RAH t ASR Address Row t ASC t CAH Column t WCS t WCH WE t DS DIN DOUT Preliminary t DH D in OPEN 11 April 1997 EtronTech Em614163A-30/35/40/45 • Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t CAS t RCD t CRP UCAS LCAS t RAD t ASR Address t RAH t ASC Row t CAH Column t CWD t RCS t CWL t AWD t RWL t RWD t WP WE t DH t DZC t DS OPEN DIN D in t OEH t ODD t DZO OE t OEA t CAC t AA t OEZ t RAC DOUT Preliminary Dout OUT 12 April 1997 EtronTech Em614163A-30/35/40/45 • Delayed Write Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH tT t CAS UCAS LCAS t ASR Address t RAH t ASC Row t CAH Column t CWL t RCS t RWL t WP WE t DS t DZC OPEN Din DIN t DZO t DH t ODD t OEH OE t OEZ DOUT Preliminary Invalid Dout 13 April 1997 EtronTech Em614163A-30/35/40/45 • EDO Page Mode Read Cycle t RASP t RP t CPRH RAS tT t PC t CSH t RCD t CAS t RSH t CAS t CP t CP t CRP t CAS UCAS LCAS t t RAD t Address ASR t RAH t ASC Row t t CAH t ASC CAH Column 2 Column 1 t CAH tASC Column N t RCS t RRH t RCS t RCH t RCH t RCH t RCS RAL WE OPEN OPEN OPEN DIN t OED t OED t OEHC t OEP OE t OEA t t CAC OES t OEA t OEA t CAC t CAC t AA t AA t AA t CPA t RAC DOUT t OFF t OFF t OFF t OEZ t OEZ Dout 2 Dout 1 t OEZ Valid Dout N DOU N T t COH Preliminary 14 April 1997 EtronTech Em614163A-30/35/40/45 •EDO Page Mode Early Write Cycle t RASP t RP RAS tT t RSH t PC t CSH t CAS t RCD t CAS t CP t CP t CRP t CAS UCAS LCAS t ASR Address t RAH Row t ASC t CAH t ASC Column 1 t WCS t WCH t DS t DH t CAH Column 2 t WCS t WCH tASC t CAH Column N t WCS t WCH WE DIN t DS Din 1 Din 2 t DS t DH Din N OPEN Dout Preliminary t DH 15 April 1997 EtronTech Em614163A-30/35/40/45 • EDOage P Mode Read -Modify-Write Cycle t RASP t t RP CPRH RAS t T t CRP t PRWC t CP t t CP t CAS RCD t CAS t CAS UCAS LCAS t RAD t ASR t RAH Address t t ASC Row t ASC ASC t CAH t CAH t CAH Column 1 Column 2 Column N t CWL t RWD t CWL CPW t RCS CWD t CWL t CPW t AWD t AWD t t t AWD t RCS t CWD t RWL t CWD WE t RCS t WP t WP t WP t DS t DS t DS t t DH OPEN t DH OPEN Din 1 D IN OPEN Din 2 t DH Din N t OED OED t OED t OEH t OEH t OEH OE t OEA t t CAC t CAC t CAC t AA t AA t AA t RAC D t OEA OEA t OEZ t CPA t OEZ t t CPA OEZ OU T Dout 1 Preliminary Dout N Dout 2 16 April 1997 EtronTech Em614163A-30/35/40/45 Read Cycle with WE Controlled Disable RAS t CSH t RCD tT t CAS UCAS LCAS t RAD t ASR Address t RAH t ASC Row t CAH Column t t RCS RCH t RRH WE t WHZ t DZC OPEN DIN t ODD t DZO OE t OEA t OEZ t CAC t AA t RAC DOUT D OUT t Preliminary CLZ 17 April 1997 EtronTech Em614163A-30/35/40/45 • EDO-Page-Mode Read-Early-Write Cycle RAS t CSH t RCD tT t CAS t CAS UCAS LCAS t CP t RAD t AS t ASR Address t RAH tASC t t C CAH Column Row CAH Column t t RCS RCH t t WCH WCS WE t DS t DH OPEN DIN DIN OE t OEA t CAC t WHZ t AA t RAC DOUT D OUT t Preliminary CLZ 18 April 1997 EtronTech Em614163A-30/35/40/45 •RAS-Only Refresh Cycle t RC t RP t RAS RAS tT t RPC t CRP t CRP UCAS LCAS t ASR t RAH Address Row t OFF OPEN DOUT •CAS-Before-RAS Refresh Cycle t RC t RP RAS t RC t RAS t RP t RAS t RP tT t RPC t RPC t CPN t CSR t CHR t CPN t CRP t CSR t CHR UCAS LCAS Address t OFF DOUT Preliminary OPEN 19 April 1997 EtronTech Em614163A-30/35/40/45 • Hi dden Refresh Cycle t RC t RC t RC t RP t RAS (READ) t RAS (REFRE SH ) t RP t RAS t RP (REF RE SH) RAS tT t CHR t RSH t CRP t CAS t RCD UCAS LCAS t RAL t RAD t ASR Address t RAH t ASC Row t CAH Co lu mn t RRH t RCS t RCH WE t CDD t DZC OP EN DIN t DZO t ODD OE t OEZ t OEA t RAC t AA t CAC t OFF DOUT Preliminary Valid Do DOUT ut 20 April 1997 EtronTech Em614163A-30/35/40/45 • CAS Before RAS Refresh Counter Check Cycle (WRITE) t RP t RAS t RP tT RAS t RPC t CSR t CHR t CPT t RSH t CPN t CRP t CAS UCAS LCAS t ASC t CAH Column Address t WCS t WCH WE t CDD t DS t DH t DZC Din Din OE t OFF OPEN Dout Preliminary 21 April 1997 EtronTech Em614163A-30/35/40/45 Outline Drawing 40-Pin SOJ 40 21 E HE 20 1 D c A2 A L A1 S Seating Plane Symbol A A1 A2 b1 b c D E e e1 HE L S Y θ b e D θ y e1 b1 Dimension in inch Min Num Max ¡Ð ¡Ð 0.144 ¡Ð ¡Ð 0.025 0.105 0.110 0.115 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 ¡Ð 1.025 1.035 0.395 0.400 0.405 0.044 0.050 0.056 Dimension in mm Min Num Max ¡Ð ¡Ð 3.66 ¡Ð ¡Ð 0.64 2.67 2.79 2.92 0.66 0.71 0.81 0.41 0.46 0.56 0.20 0.25 0.36 ¡Ð 26.04 26.29 10.03 10.16 10.29 1.12 1.2 1.42 0.348 0.430 0.088 ¡Ð ¡Ð 0¢X 8.84 10.92 2.24 ¡Ð ¡Ð 0¢X 0.368 0.440 0.098 ¡Ð ¡Ð ¡Ð 0.388 0.450 0.108 0.050 0.004 10¢X 9.35 11.18 2.49 ¡Ð ¡Ð ¡Ð 9.86 11.43 2.74 1.27 0.10 10¢X Notes: 1. Dimension D Max & S include mold flash or tie bar burrs. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch and are determined at the mold parting line. 4. Controlling dimension : inch 5. General appearance spec. should be based on final visual inspection spec. Preliminary 22 April 1997 EtronTech Em614163A-30/35/40/45 40/44-Pin TSOP-II 44 HE E 0.254 + θ° L L1 + 1 S e B Symbol A A1 A2 B c D E e HE L L1 S y θ y Dimension in inch Min Num Max ¡Ð ¡Ð 0.047 ¡Ð ¡Ð 0.002 0.037 0.039 0.041 0.010 0.014 0.018 ¡Ð ¡Ð 0.006 0.721 0.725 0.729 0.396 0.400 0.404 ¡Ð ¡Ð 0.031 Min ¡Ð 0.05 0.95 0.25 ¡Ð 18.31 10.06 ¡Ð 0.455 0.016 ¡Ð ¡Ð ¡Ð 0¢X 11.56 0.40 ¡Ð ¡Ð ¡Ð 0¢X 0.463 0.020 0.031 ¡Ð ¡Ð ¡Ð 0.471 0.024 ¡Ð 0.036 0.004 5¢X C A A1 A2 D L L1 Dimension in mm Num Max ¡Ð 1.20 ¡Ð ¡Ð 1.00 1.05 0.35 0.45 ¡Ð 0.15 18.41 18.51 10.16 10.26 ¡Ð 0.80 11.76 0.50 0.80 ¡Ð ¡Ð ¡Ð 11.96 0.60 ¡Ð 0.93 0.10 5¢X Notes : 1. Dimension D&E do not include interiead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension : MM Preliminary 23 April 1997