A64S0616 1M X 16 Bit Low Voltage Super RAMTM Preliminary Document Title 1M X 16 Bit Low Voltage Super RAMTM Revision History Rev. No. History Issue Date Remark Preliminary 0.0 Initial issue November 30, 2001 0.1 Add tASC, tAHC, tCEH, tWEH July 31, 2002 PRELIMINARY (July, 2002, Version 0.1) AMIC Technology, Inc. A64S0616 1M X 16 Bit Low Voltage Super RAMTM Preliminary Features n Operating voltage: 2.7V to 3.1V n Access times: 70 ns (max.) n Current: A64S0616 series: Operating: 35mA (max.) Power Down Standby: 10µA (max.) n Fully SRAM compatible operation n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Industrial operating temperature range: -25°C to +85°C for -I n Available in 48-ball Mini BGA (6X8) package. General Description The A64S0616 is a low operating current 16,777,216-bit Super RAM organized as 1,048,576 words by 16 bits and operates on low power supply voltage from 2.7V to 3.1V. It is built using AMIC’s high performance CMOS DRAM process. Using hidden refresh technique, the A64S0616 provides a 100% compatible asynchronous interface. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. This A64S0616 is suited for low power application such as mobile phone and PDA or other battery-operated handheld device. Pin Configuration n Mini BGA (6X8) Top View 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B I/O8 HB A3 A4 CE1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 GND A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC A64S0616G PRELIMINARY (July, 2002, Version 0.1) 1 AMIC Technology, Inc. A64S0616 Block Diagram VCC A0 VSS GND 16,777,216 DECODER MEMORY ARRAY A18 A19 I/O0 I/O8 INPUT COLUMN I/O INPUT DATA CIRCUIT DATA CIRCUIT I/O15 I/O7 CE1 CE2 LB HB OE WE CONTROL CIRCUIT Pin Description Symbol A0 - A19 Description Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input I/O0 - I/O15 Data Input/Outputs WE Write Enable Input LB Byte Enable Input (I/O0 to I/O7) HB Byte Enable Input (I/O8 to I/O15) OE Output Enable Input VCC Power VSS Ground GND Ground NC PRELIMINARY No Connection (July, 2002, Version 0.1) 2 AMIC Technology, Inc. A64S0616 Recommended DC Operating Conditions (TA = 0°C to + 70°C or -25°C to 85°C) Symbol Parameter Min. Max. Unit 2.7 3.1 V VCC Supply Voltage VSS Ground 0 0 V GND Ground 0 0 V VIH Input High Voltage 2.4 VCC + 0.3 V VIL Input Low Voltage -0.3 +0.6 V CL Output Load - 30 pF TTL Output Load - 1 - Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.1V, GND = 0V) -70 Parameter -85 Unit Min. Max. Min. Max. Conditions ILI Input Leakage Current - 1 - 1 µA VIN = GND to VCC ILO Output Leakage Current - 1 - 1 µA CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC - 35 - 30 mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA - 5 - 5 mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0mA ICC1 Dynamic Operating Current ICC2 PRELIMINARY (July, 2002, Version 0.1) 3 AMIC Technology, Inc. A64S0616 DC Electrical Characteristics (continued) Symbol Parameter -70 -85 Unit Min. Max. Min. Max. Conditions ISB1 Standby Power Supply Current - 100 - 100 µA CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V VIN ≥ 0V ISB2 Power Down Mode Standby Current - 10 - 10 µA CE2 ≤ 0.2V VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1mA VOH Output High Voltage 2.4 - 2.4 - V IOH = -1.0mA Truth Table I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current CE1 CE2 OE WE LB HB H H X X X X Not selected Not selected ISB1, ISB X H X X H H Not selected Not selected ISB1, ISB X L X X X X Not selected Not selected ISB2 L L Read Read ICC1, ICC2 L H Read High - Z ICC1, ICC2 H L High - Z Read ICC1, ICC2 L L Write Write ICC1, ICC2 L H Write Not Write/Hi - Z ICC1, ICC2 H L Not Write/Hi - Z Write ICC1, ICC2 X X High - Z High - Z ICC1, ICC2 L L L H H H L X H H L H High - Z High - Z ICC1, ICC2 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 10 pF VIN = 0V CI/O* Input/Output Capacitance - 10 pF VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (July, 2002, Version 0.1) 4 AMIC Technology, Inc. A64S0616 Initialization The A64S0616 is initialized in the power-on sequence according to the following. 1. To stabilize internal circuits, after turning on the power, a 350µs or longer wait time must precede any signal toggling. 2. After the wait time, it can be normal operation. Power on Chart VCC(min) VCC CE1 50ns (min) 350us CE2 Normal Operation Wait Time Notes: 1. Following power application, make CE2 and CE1 high level during the wait time interval. 2. After power on sequence, the normal operating CE2 must keep at high. Power on / Depower down State Machine Power on CE1=V IH, CE2=V IH Wait 350us Initial State CE1=V IL, CE2=V IH CE1=V IH, CE2=V IH CE1=V IH CE2=V IH, Active CE1=V IH CE2=V IL, CE1=V IH, CE2=V IH CE1=V IL, CE2=V IH Standby Mode Power Down Mode CE1=V IH CE2=V IL, Standby Mode Characteristics Standby Mode Memory Cell Data Hold Standby Supply Current (µA) Standby Valid 100 (ISB1) Power down Invalid 10 (ISB2) PRELIMINARY (July, 2002, Version 0.1) 5 AMIC Technology, Inc. A64S0616 Avoid Timing Following figures are show you an abnormal timing which is not supported on Super RAM and their solution. At normal operation, if your system have a timing which sustain invalid states over 10µs at normal mode like Figure 1. There are some guide line for proper operation of Super RAM. When your system have multiple invalid address signal shorter than tRC on the timing which showed in Figure 1, Super RAM need toggle the CE1 to “high” about “tRC” (Figure 2). Over 10us CE1 Less than t RC Address Figure 1 toggle CE1 to high every 10us 70ns 10us CE1 Address Figure 2 PRELIMINARY (July, 2002, Version 0.1) 6 AMIC Technology, Inc. A64S0616 AC Characteristics (TA = 0°C to +70°C or -25°C to 85°C, VCC = 2.7V to 3.1V) Symbol Parameter -70 -85 Unit Min. Max. Min. Max. 70 - 85 - ns Address Skew - 10 - 10 ns tAA Address Access Time - 70 - 85 ns tACE Chip Enable Access Time - 70 - 85 ns tBE Byte Enable Access Time - 70 - 85 ns tOE Output Enable to Output Valid - 35 - 45 ns tCLZ Chip Enable to Output in Low Z 10 - 10 - ns Read Cycle tRC tSKEW Read Cycle Time tBLZ Byte Enable to Output in Low Z 5 - 5 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z 0 25 0 35 ns tBHZ Byte Disable to Output in High Z 0 25 0 35 ns tOHZ Output Disable to Output in High Z 0 25 0 35 ns tOH Output Hold from Address Change 10 - 10 - ns tASC Address Setup to CE1 Low 0 - 0 - ns tAHC Address Hold Time from CE1 High 0 - 0 - ns tCEH CE1 High Pulse With 10 - 10 - ns Write Cycle Time 70 - 85 - ns - 10 - 10 ns Write Cycle tWC tSKEW Address Skew tCW Chip Enable to End of Write 60 - 70 - ns tBW Byte Enable to End of Write 60 - 70 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 60 - 70 - ns tWP Write Pulse Width 50 - 55 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 20 - 20 ns tDW Data to Write Time Overlap 30 - 35 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns tASC Address Setup to CE1 Low 0 - 0 - ns tAHC Address Hold Time from CE1 High 0 - 0 - ns tCEH CE1 High Pulse With 10 - 10 - ns tWEH WE High Pulse With 10 - 10 - ns Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (July, 2002, Version 0.1) 7 AMIC Technology, Inc. A64S0616 Timing Waveforms (1, 2, 4, 6) Read Cycle 1 tSKEW tRC tSKEW tRC Address tAA tOH tAA tOH DOUT tASC CE1 PRELIMINARY (July, 2002, Version 0.1) 8 AMIC Technology, Inc. A64S0616 Read Cycle 2-1 (1, 3, 6) tSKEW tRC tSKEW tRC Address tASC tAHC tASC tAHC tAA tAA tCEH tBE CE1 tACE tCLZ 5 tACE tCLZ 5 tCHZ 5 tBE HB , LB tCHZ 5 tBE tBLZ 5 tBHZ 5 tBLZ 5 tBHZ 5 OE tOE tOLZ 5 tOE tOLZ 5 tOHZ 5 tOHZ 5 DOUT Read Cycle 2-2 (1, 3, 6) tSKEW tSKEW tRC tSKEW tRC Address tASC tAHC tAA tAA CE1 tACE tCLZ 5 HB , LB tCHZ 5 tBE tBLZ 5 tBE tBHZ 5 tBLZ 5 tBHZ 5 OE tOE tOLZ 5 tOE tOLZ 5 tOHZ 5 tOHZ 5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE1 = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE1 and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high for Read Cycle. PRELIMINARY (July, 2002, Version 0.1) 9 AMIC Technology, Inc. A64S0616 Timing Waveforms (continued) (6) Write Cycle 1-1 (Write Enable Controlled) tSKEW tWC tSKEW tWC Address tASC tAHC tASC tAHC tAW tAW tCW tCEH tCW CE1 tBW tBW HB , LB tWR 3 tAS 1 tWR 3 tAS 1 tWP2 tWP2 WE tDW tDH tDW tDH Data In tWHZ 4 tWHZ 4 tOW tOW Data Out (6) Write Cycle 1-2 (Write Enable Controlled) tSKEW tSKEW tWC tSKEW tWC Address tASC tAHC CE1 tBW tBW HB , LB tWR3 tAS 1 tWR 3 tAS 1 tWP2 tWP2 WE tWEH tDW tDH tDW tDH Data In tWHZ 4 tWHZ 4 tOW tOW Data Out PRELIMINARY (July, 2002, Version 0.1) 10 AMIC Technology, Inc. A64S0616 Timing Waveforms (continued) (6) Write Cycle 2-1 (Chip Enable Controlled) tSKEW tWC tSKEW tWC Address tAHC tAW tAHC tAW tASC tASC tCW 2 tCEH tCW 2 CE1 tWR 3 tBW tWR 3 tBW HB , LB tWP tWP WE tDW tDH tDW tDH Data In tWHZ 4 tWHZ 4 tOW tOW Data Out (6) Write Cycle 2-2 (Chip Enable Controlled) tSKEW tSKEW tWC tSKEW tWC Address tAHC tAW tASC CE1 tWR 3 tBW tWR 3 tBW HB , LB tWP tWP WE tDW tDH tDW tDH Data In tWHZ 4 tWHZ 4 tOW tOW Data Out PRELIMINARY (July, 2002, Version 0.1) 11 AMIC Technology, Inc. A64S0616 Timing Waveforms (continued) (6) Write Cycle 3-1 (Byte Enable Controlled) tSKEW tWC tSKEW tWC Address tAHC tAW tAHC tAW tASC tASC tCW tAS 1 tBW 2 tCEH tCW CE1 tWR 3 tAS 1 tWR 3 tBW 2 HB , LB tWP tWP WE tDW tDH tDW tDH Data In tWHZ 4 tWHZ 4 tOW tOW Data Out (6) Write Cycle 3-2 (Byte Enable Controlled) tSKEW tSKEW tWC tSKEW tWC Address tAHC tAW tASC CE1 tAS 1 tWR 3 tBW 2 tAS 1 tWR 3 tBW 2 HB , LB tWP tWP WE tDW tDH tDW tDH Data In tWHZ 4 tWHZ 4 tOW tOW Data Out Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CE1, WE and ( HB and, or LB ). 3. tWR is measured from the earliest of CE1 or WE or ( HB and, or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high for Write Cycle. PRELIMINARY (July, 2002, Version 0.1) 12 AMIC Technology, Inc. A64S0616 AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise And Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 3 and 4 TTL TTL CL CL 30pF 5pF * Including scope and jig. * Including scope and jig. Figure 3. Output Load Figure 4. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Ordering Information Access Time (ns) Operating Current Max. (mA) Power Down Mode Standby Current Max. (µ µA) Package A64S0616G-70 70 35 10 48B Mini BGA A64S0616G-85 85 30 10 48B Mini BGA A64S0616G-70I 70 35 10 48B Mini BGA A64S0616G-85I 85 30 10 48B Mini BGA Part No. Note: -I is for industrial operating temperature range PRELIMINARY (July, 2002, Version 0.1) 13 AMIC Technology, Inc. A64S0616 Package Information Mini BGA 6X8 (48 BALLS) Outline Dimensions unit : millimeter(mm) Bottom View Top View Pin A1 Index Pin A1 Index 6 5 4 3 2 1 C C1 A B C D A E F G H A B Diameter D Solder Ball B1 D E2 0.10 E1 E PRELIMINARY Symbol Min Typ Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E 1.00 1.10 1.20 E1 - 0.36 - E2 0.2 0.25 0.3 (July, 2002, Version 0.1) 14 AMIC Technology, Inc.