Features • LDO1: 2.75V (Default) and 1.8V (Programmable by TWI), 70 mA Linear Very Low Drop Out Regulator with High PSRR and Low Noise. • LDO2: 1.8V (Default) and 1.5V (Programmable by TWI), 70 mA Linear Low Drop Out Regulator with High PSRR and Low Noise. • LDO3: 1.8V (Default) and 1.5V or 1.2V (Programmable by TWI), 70 mA Linear Low Drop Out Regulator with high PSRR and Low noise. • LDO4: 1.8V, 2mA Linear Low Drop Out Regulator with Very Low Quiescent Current, +/100 mV Adjustable. Main Supply Rail from 2.8V to 5.5V Independent Auxiliary Supply for LDO4 Backup Section, 2.8V to 5.5V Internal State Machine for Startup and Delayed Reset Generation Additional External Reset Input Two Wire Interface for Independent Power Up/Power Down and Output Voltage Programming for Each LDO. • LDOs Voltage Customization Possible on Request • Available in 3 x 3 x 0.9 mm 16-pin QFN Package • Applications: GPS Modules, WLAN Devices, Wireless Modules. • • • • • 1. Description The AT73C237 is a four-channel Power Supply Power Management Unit (PMU) available in a small outline QFN 3 x 3mm package. It is a fully integrated, attractively priced, combined Power Management device for wireless modules, GPS and WLAN devices. It integrates 4X Linear Low Drop Out Regulators, three of which (LDO1, 2, 3) provide high-accuracy RF performance and 1X (LDO4) with very low quiescent current, that can be supplied by an external backup battery (VDD4) on a separate rail. An internal Low Power Bandgap (LPBG) requiring no external capacitor for decoupling, is used as reference voltage for LDO4 and starts when VDD4 is present. LDO4 regulates its output voltage with extremely low quiescent current, maximizing the lifetime of the backup battery. Power Management and Analog Companions (PMAAC) AT73C237 4-channel Power Management for Wireless Modules An Internal State Machine manages the startup of the other LDOs. An economic High Precision Bandgap (HPBG) provides highly accurate, low noise voltage reference to LDOs 1, 2, 3 while operating in switching mode to optimize the quiescent current. The AT73C237 features a Two-wire Interface (TWI) to increase the efficiency of the system by disabling individually each LDO when not needed. 6362A–PMAAC–01-Jul-08 2. Block Diagram Figure 2-1. AT73C237 Functional Block Diagram VDD1 (13) LDO1 2.75V/70mA VO1 (14) VDD2 (9) LDO2 1.80V/70mA VO2 (10) VDD3 (3) LDO3 1.80V/70mA VO3 (2) 2.70V Supply Monitor VDD4 (7) VO4 (5) LDO4 1.80V/2mA VZAP (8) TRIM Low Power Bandgap Reference LPBG RCOSC POR LDO Main Bandgap Reference HVBG VBG (16) GNDA (15) XRESIN (1) XRESO (4) TWCK (11) Level Shifters TWI Interface and Digital State Machine TWD (12) GNDD (6) 2 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 3. Pin Description Table 3-1. Pin Name Pin Description I/O Pin Number Type Function Input 1 Digital Reset in pin Output 2 Analog LDO3 output voltage Input 3 Power LDO3 input voltage XRESO Output 4 Digital Reset out pin VO4 Output 5 Analog LDO4 output voltage GNDD GND 6 Power Digital ground VDD4 Input 7 Power LDO4 input voltage VZAP Input 8 Digital Reserved for manufacturing purposes. VDD2 Input 9 Power LDO2 input voltage Output 10 Analog LDO2 output voltage TWCK(2) Input 11 Digital TWI input clock or LDO1,2,3 enable at logic “1“, disable at “0“ TWD(3) Input 12 Digital TWI input/output or tied to Vdd Input 13 Power LDO1 input voltage Output 14 Analog LDO1 output voltage GND/Input 15 Analog Analog ground and ESD ground Output 16 Analog Voltage reference for analog cells XRESIN VO3 VDD3 (1) VO2 VDD1 (4) VO1 GNDA/AVSS VBG Note: 1. Connect to ground (via an internal pull-down) 2. Connected to VDD1, 2 or 3 on AT73C237. 3. Connected to VDD1, 2 or 3 on AT73C237. 4. VDD1, 2, 3 should have the same input voltage. 3 6362A–PMAAC–01-Jul-08 4. Application Block Diagram Figure 4-1. AT73C237 Application Block Diagram With GPS Module J1 : "ON" for 237 J2 : "OFF" for 237 C1 C5 TX C9 TWI VBG (16) GNDA (15) VO1 (14) VDD1 (13) GPS Baseband XRESIN (1) TWD (12) Core and IOs VO3 (2) C3 TWCK (11) AT73C237 VDD3 (3) VO2 (10) C7 C2 XRESO (4) VO4 (5) RX VDD2 (9) GNDD (6) VDD4 (7) VZAP (8) C6 C8 C4 3V Back up Coin-Cell D1 D2 Eg: Panasonic CR1025 Li-Ion Battery 3.0V to 4.2V Typical Application Components Design Schematic Reference Pin C1 VO1 C2 VO2 C3 VO3 C4 VO4 C5 VDD1 C6 VDD2 C7 VDD3 C8 VDD4 C9 VBG D1, D2 4 Description 2.2 µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA®: GRM155R60J225ME15 TDK: C1005X5R0J225MT 1 µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J105KE19 TDK: C1005X5R0J105KT 100 nF ± 15% Ceramic Capacitor, X5R, 0402, 10V MURATA: GRM155R61A104KA01 TDK: C1005X5R1C104KT ON-Semiconductor®: BAS70-04LT1 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 5. Electrical Characteristics 5.1 Absolute Maximum Ratings Table 5-1. Absolute Maximum Ratings Operating Temperature (Industrial)..................-40°C to + 85°C Storage Temperature........................................-55°C to + 150°C Power Supply Input on VDD.................................-0.3V to + 5.5V Digital I/O Input Voltage...................................... -0.3V to + 5.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Other Pins.......................................................-0.3V to + 5.5V ESD (all pins).......................................................................2 KV 5.2 Recommended Operating Conditions Table 5-2. Recommended Operating Conditions Parameter Condition Operating Temperature Power Supply Input VDD1, VDD2, VDD3, VDD4 Min Max Units -40 85 °C 2.8 5.5 V 5 6362A–PMAAC–01-Jul-08 5.3 Quiescent Current In Different Operating Modes Table 5-3. Quiescent Current In Different Operating Modes Quiescent [µA] Modes Conditions MODE0 VDD4 not present, chip disabled, all VDDs quiescent current Typ Max 0 0.1 12 18 800 1000 VDD4 present, VDD3 not present (typical mode with back-up battery on VDD4) • LDO4 MODE1 • LPBG • POR • HPBG in switching mode VDD4 present, VDD3 present • LDO4 • LPBG • POR • Supply Monitor • Registers MODE2 • Oscillator • State Machine • HPBG • LDO1 • LDO2 • LDO3 6 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 6. Startup Procedure 6.1 At VDD4 Rising • LPBG, LDO4, RCOSC start up • POR connected to LDO4 output VO4 resets the state machine and enables: – The reading of the internal fuses (TRIM cell in the application diagram) in order to set up the programmed output voltage of LDO1, LDO2, LDO3, and the correct reference voltage and oscillation frequency – The Two Wire Interface – Then under control of the state machine: a. HPBG is turned on b. After 4 ms, the Supply Monitor on VDD3 is turned on. c. If VDD3 is present and greater than 2.7V, LDO1, 2, 3 are turned on. During LDO regulator startup VDD3 voltage is checked. d. Then XRESO is kept grounded for 180 ms, and set to “1” for 1ms before following XRESIN. During that state VDD3 voltage is monitored and if lower than 2.6V, LDO regulators 1, 2 and 3 are stopped and XRESO grounded. Both XRESIN and the Supply Monitor on VDD3 are debounced at rising and falling edges for two 10 kHz clock cycles. The debounce time is typically between 100 µs and 200 µs. Timings are defined ± 40%. 6.2 At VDD3 Falling • The Supply monitor generates a shut down control signal when VDD3 reaches 2.6V • The State machine sets XRESO to logic “0”. • The State machine switches off LDO1, LDO2, LDO3. HPBG is kept enabled in order to assure a fast new startup of the LDOs. 7 6362A–PMAAC–01-Jul-08 Figure 6-1. Startup Procedure VDD4 is present RCOSC Running POR reset signal goes to low Load fuse regs HPBG en=0 VDD3 Monitor en=0 LDO3 en=0 LDO2 en=0 LDO1 en=0 XRESO=0 Start Wait xms HPBG en=1 VDD3 Monitor en=0 LDO3 en=0 LDO2 en=0 LDO1 en=0 XRESO=0 HPBG Wait 4ms HPBG en=1 VDD3 Monitor en=1 LDO3 en=0 LDO2 en=0 LDO1 en=0 XRESO=0 32 clock pulses Test VDD3 VDD3 > 2.7V HPBG en=1 VDD3 Monitor en=1 LDO3 en=1 LDO2 en=1 LDO1 en=1 XRESO=1 100µs (1 clock pulse) Wait 1ms VDD3 < 2.6V Start LDOs Wait 180ms Wait 1ms HPBG en=1 VDD3 Monitor en=1 LDO3 en=1 LDO2 en=1 LDO1 en=1 XRESO=1 Reset Gen. VDD3 < 2.6V Wait 1ms Wait 1ms VDD3 < 2.6V HPBG en=1 VDD3 Monitor en=1 LDO3 en=1 LDO2 en=1 LDO1 en=1 XRESO=XRESIN 8 Ext. Reset AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 7. Timing Diagram Figure 7-1. AT73C237 Timings VIN 2.7V VBAT LDO4 POR 1.5V RCOSC tbg HPBG tini tensm Supply Monitor tini enabled tstart2 LDO1,2,3 tstart1 XRESIN tdelay XRESO Table 7-1. Parameter tresgen Timing Parameters Signal Constraint Min Guard time tini Max Units 100 µsec tbg HPBG HPBG startup time 2 msec tensm Supply monitor Supply monitor enable 4 msec tstart1 VO1, VO2, VO3 3 5 µsec tstart2 VO1, VO2, VO3 10 100 µsec tresgen XRESO 100 500 msec 1 msec tdelay LDO1,2,3 Startup time 9 6362A–PMAAC–01-Jul-08 8. Electrical Specification 8.1 LDO1 Table 8-1. LDO1 Parametric Table Symbol Parameter Comments Min Typ Max Units VDD1 Operating supply voltage Switching Regulated 2.8 3.3 5.5 V Default 2.70 2.75 2.8 VO1 Output voltage Programmed 1.75 1.80 1.85 I1 Load current IQC Quiescent current ISC Shutdown current ISH Short circuit current tR Startup time ∆VDC Line regulation static ∆VDC Load regulation static PSSR Power Supply Rejection Ratio ∆VOUT Startup Overshoot VNT Total Output Noise Table 8-2. V With at least 300mV drop out 100 With at least 200mV drop out 70 mA 250 300 µA 1 µA HiZ output 350 1 10 mA 100 µsec From VDD=3.0V to 3.6V 5 mV From 10% to 100% I1 30 From 0 to 100% I1 40 mV Sine Wave, 100 kHz frequency, 3.3V mean +/- 100 m vPP 65 dB Sine Wave, 10 kHz frequency, 3.3V mean +/- 100 m vPP 60 dB Sine Wave, 1 kHz frequency, 3.3V mean +/- 100 m vPP 45 dB 10 Hz - 100 kHz 35 100 mV 100 µVRMS LDO1 External Components Schematic Reference Description C1 (Input Capacitor) 2.2µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J225ME15 TDK: C1005X5R0J225MT C5 (Output Capacitor) 1µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J105KE19 TDK: C1005X5R0J105KT 10 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 Figure 8-1. LDO Load Regulation Load Regulation: Vout1 = 2.75V 2.8 Vin=2.8V 2.79 2.78 Vout1 (V) 2.77 2.76 2.75 2.74 2.73 Vin=3.3V 2.72 Vin=5.5V 2.71 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 I Load (mA) Load Regulation: Vout1 = 1.8V 1.791 1.79 1.789 Vout1 (V) Vin=2.8V 1.788 1.787 Vin=3.3V Vin=5.5V 1.786 1.785 1.784 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 I Load (mA) Figure 8-2. A: CH1 Pwr Spec 100 uVrms LogMag decades LDO1 Output Noise X:1.001 kHz Y:775.467 nVrms LogMag 3 100 nVrms A: CH1 Pwr Spec 100 uVrms decades 5Hz Band:15.4997 uVrms AVG: 30 1.605kHz X:1 kHz Y:10.4272 uVrms 2 1 uVrms 1kHz Band:30.8786 uVrms AVG: 30 103.4kHz 11 6362A–PMAAC–01-Jul-08 8.2 LDO2 Table 8-3. LDO2 Parametric Table Symbol Parameter Comments Min Typ Max Units VDD2 Operating supply voltage Switching Regulated 2.8 3.3 5.5 V Default 1.75 1.80 1.85 VO2 Output voltage Programmed 1.45 1.50 1.55 I2 Load current IQC Quiescent current ISC Shutdown current ISH Short circuit current tR Startup time ∆VDC Line regulation static ∆VDC Load regulation static PSSR Power Supply Rejection Ratio ∆VOUT Startup Overshoot VNT Total Output Noise Table 8-4. V With at least 300mV drop out 100 With at least 200mV drop out 70 mA 250 300 µA 1 µA HiZ output 350 1 10 mA 100 µsec From VDD=3.0V to 3.6V 5 mV From 10% to 100% I2 30 From 0 to 100% I2 40 mV Sine Wave, 100 kHz frequency, 3.3V mean +/- 100 m vPP 70 dB Sine Wave, 10 kHz frequency, 3.3V mean +/- 100 m vPP 65 dB Sine Wave, 1 kHz frequency, 3.3V mean +/- 100 m vPP 45 dB 10 Hz - 100 kHz 25 100 mV 50 µVRMS LDO2 External Components Schematic Reference Description C2 (Input Capacitor) 2.2µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J225ME15 TDK: C1005X5R0J225MT C6 (Output Capacitor) 1µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J105KE19 TDK: C1005X5R0J105KT 12 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 Figure 8-3. LDO2 Load Regulation Load Regulation: Vout2 = 1.8V Vout2 (V) 1.7875 1.786 Vin=2.8V 1.7845 Vin=3.3V Vin=5.5V 1.783 1.7815 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 I Load (mA) Load Regulation: Vout2 = 1.5V 1.499 Vout2 (V) 1.498 1.497 Vin=2.8V 1.496 Vin=5.5V 1.495 Vin=3.3V 1.494 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 I Load (mA) Figure 8-4. A: CH1 Pwr Spec 100 uVrms LogMag decades LDO2 Output Noise X:1.001 kHz Y:564.828 nVrms LogMag 3 100 nVrms A: CH1 Pwr Spec 10 uVrms decades 5Hz Band:10.1724 uVrms AVG: 30 1.605kHz X:1 kHz Y:5.0418 uVrms 1 1 uVrms 1kHz Band:19.7939 uVrms AVG: 30 103.4kHz 13 6362A–PMAAC–01-Jul-08 8.3 LDO3 Table 8-5. LDO3 Parametric Table Symbol Parameter Comments Min Typ Max Units VDD3 Operating supply voltage Switching Regulated 2.8 3.3 5.5 V Default 1.75 1.80 1.85 Programmed 1.45 1.50 1.55 Programmed 1.18 1.23 1.28 VO3 Output voltage I3 Load current IQC Quiescent current ISC Shutdown current ISH Short circuit current tR Startup time ∆VDC Line regulation static ∆VDC Load regulation static PSSR Power Supply Rejection Ratio ∆VOUT Startup Overshoot VNT Total Output Noise Table 8-6. With at least 300mV drop out 100 With at least 200mV drop out 70 mA 250 300 µA 1 µA HiZ output 350 1 10 mA 100 µsec From VDD=3.0V to 3.6V 5 mV From 10% to 100% I3 30 From 0 to 100% I3 40 mV Sine Wave, 100 kHz frequency, 3.3V mean +/- 100 m vPP 70 dB Sine Wave, 10 kHz frequency, 3.3V mean +/- 100 m vPP 65 dB Sine Wave, 1 kHz frequency, 3.3V mean +/- 100 m vPP 45 dB 10 Hz - 100 kHz 20 100 mV 50 µVRMS LDO3 External Components Schematic Reference Description C3 (Input Capacitor) 2.2µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J225ME15 TDK: C1005X5R0J225MT C7 (Output Capacitor) 1µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J105KE19 TDK: C1005X5R0J105KT 14 V AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 Figure 8-5. LDO3 Load Regulation Load Regulation: Vout3 = 1.5V Load Regulation: Vout3 = 1.8V 1.793 1.502 1.5005 1.791 Vin=2.8V Vin=3.3V Vout3 (V) Vout3 (V) 1.499 1.789 1.787 1.4975 1.496 Vin=5.5V 1.785 Vin=2.8V 1.4945 1.783 Vin=5.5V 1.493 Vin=3.3V 1.781 1.4915 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 I Load (mA) I Load (mA) Load Regulation: Vout3 = 1.23V 1.2395 1.238 Vout3 (V) 1.2365 Vin=3.3V 1.235 1.2335 1.232 Vin=2.8V 1.2305 Vin=5.5V 1.229 1.2275 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 I Load (mA) Figure 8-6. A: CH1 Pwr Spec 100 uVrms LDO3 Output Noise X:1.001 kHz Y:604.928 nVrms LogMag decades LogMag 3 100 nVrms A: CH1 Pwr Spec 10 uVrms decades 5Hz Band:8.7275 uVrms AVG: 30 1.605kHz X:1 kHz Y:4.27822 uVrms 1 1 uVrms 1kHz Band:19.8695 uVrms AVG: 30 103.4kHz 15 6362A–PMAAC–01-Jul-08 8.4 LDO4 Table 8-7. LDO4 Parametric Table Symbol Parameter Comments Min Typ Max Units VDD4 Operating supply voltage Switching Regulated 2.8 3.3 5.5 V VO4 Output voltage Default 1.7 1.8 1.9 V I4 Load current 2 mA TVO4 Trimming range 0 80 mV IQC Quiescent current 1 3 µA ISC Shutdown current 0.5 µA tR Startup time 100 µsec ∆VDC Line regulation static 2.8V< VDD4 <5.5V 100 mV ∆VDC Load regulation static 0< I4 <1.8mA 100 mV Table 8-8. -80 HiZ output 1 10 LDO4 External Components Schematic Reference Description C4 (Input Capacitor) 2.2µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J225ME15 TDK: C1005X5R0J225MT C8 (Output Capacitor) 1µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J105KE19 TDK: C1005X5R0J105KT 16 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 8.5 High Performance Bandgap (HPBG) Table 8-9. HPBG Parametric Table Symbol Parameter Conditions Min VI Operating supply voltage Backup Battery or Supercap 2.4 VBG Output voltage Factory trimmed ISC Shutdown current encore = en = 0, dcrun = 0 (1) IQC Quiescent current tS Startup time C9= 100 nF 1 VN Output noise BW 10 Hz to 100 kHz 7 Table 8-10. Typ Max Units 3.6 V 1.231 1 V 6 Not pulsed 300 Pulsed 30 2 ms External Components Description C9 (Output Capacitor) 100 nF ± 15% Ceramic Capacitor, X5R, 0402, 10V MURATA P/N: GRM155R61A104KA01 TDK: C1005X5R1C104KT Low Power Bandgap (LPBG) Table 8-11. LPBG Parametric Table Symbol Parameter Conditions Min 2.8 VI Operating supply voltage Backup Battery or Supercap IQC Quiescent current At VBAT 3. =V tS Startup time VLPBG Bandgap Voltage 8.7 µA µVRMS Schematic Reference 8.6 µA 1.15 Typ Max Unit 5.5 V 4 7.5 µA 50 100 µs 1.2 1.25 V Voltage Monitor Table 8-12. Voltage Monitor Parametric Table Symbol Parameter IQC Quiescent current VPON SM on threshold VPOFF SM on threshold Conditions Min Typ Max Unit 5 20 µA 2.7 2.72 V 2.6 2.62 V 17 6362A–PMAAC–01-Jul-08 8.8 XRESIN Table 8-13. XRESIN Parametric Table Limits Symbol Parameter Conditions Min Driven by CPU GPIO Typ Max Unit VDD4 V Driven by CPU open drain output Hiz V Connected to VDD4 when not used VDD4 VI Input supply voltage range IIH High input current 5 µA IIL Low input current 50 µA Max Unit 8.9 V XRESO Table 8-14. XRESO Parametric Table Symbol Parameter Conditions Min Typ VI Input supply voltage range VOH High output voltage 200 mV VOL Low output voltage 150 mV Max Unit 8.10 VDD4 V TWCK Table 8-15. TWCK Parametric Table Symbol Parameter VI Input supply voltage range IIH High input current 15 µA IIL Low input current 13 µA Max Unit 8.11 Conditions Min Typ VDD4 V TWD Table 8-16. TWD Parametric Table Symbol Parameter Conditions Min Typ VI Input supply voltage range VDD4 V IIH High input current 20 µA IIL Low input current 20 µA VOH High output voltage 200 mV VOL Low output voltage 150 mV 18 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 9. Functional Description The AT73C237 is a fully integrated, attractively priced, combined Power Management. It integrates the following power supplies channels. 9.1 LDO1 LDO1 is a 2.75V/70mA LDO, compatible with RF performances. LDO1 can work with supply from 3.0V up to 5.5V and needs at least 300 mV of minimum drop-out. This LDO is designed to supply the RF section of wireless devices, showing high PSRR up to 100 kHz with very low noise on wide frequency bandwidth. LDO1 requires a 2.2 µF output capacitor. • Additionally, 1.80V output voltages programming is possible via the TWI serial interface. Figure 9-1. LDO1 Functional Diagram VDD1 VIN current reference VBG VO1 vouts sel1 overcurrent detection C1 GNDA on1 AVSS VDDESD GNDA 19 6362A–PMAAC–01-Jul-08 9.2 LDO2 LDO2 is a 1.80V/70mA LDO, compatible with RF performances. LDO2 can work with supply from 3.0V up to 5.5V and needs at least 300 mV of minimum drop-out. This LDO is designed to supply RF section of wireless devices, showing high PSRR up to 100kHz, very low noise on wide frequency bandwidth. LDO2 requires a 2.2 µF output capacitor. • Additionally, 1.50V output voltages programming is possible via the TWI serial interface. Figure 9-2. LDO2 Functional Diagram VDD2 VIN current reference VBG VO2 vouts sel2 overcurrent detection C2 GNDA on2 AVSS VDDESD 20 GNDA AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 9.3 LDO3 LDO3 is a 1.80V/70mA LDO, compatible with RF performances (see electrical specifications for details). LDO3 can work with supply from 3.0V up to 5.5V and needs at least 300mV of minimum drop-out. This LDO is designed to supply RF section of wireless devices, showing high PSRR up to 100 kHz, low noise on wide frequency bandwidth. LDO3 requires a 2.2 µF output capacitor. • Additionally, 1.50V or 1.20V output voltages programming is possible via the TWI serial interface on AT73C237. Figure 9-3. LDO3 Functional Diagram VDD3 VINC VIN current reference VBG VO3 vouts sel3<1:0> overcurrent detection C3 GNDA on3 AVSS VDDESD GNDA 21 6362A–PMAAC–01-Jul-08 9.4 LDO4 LDO4 is a 1.80V/2mA LDO with very low quiescent current. LDO4 can work with supply from 2.8V up to 5.5V. LDO4 requires a 1 µF output capacitor. It needs at least 300 mV of minimum drop-out. LDO4 is always active once the pin VDD4 is supplied since it is used as internal reference supply. The VDD4 rail is independent from the other input rails (VDD1, 2, 3), allowing LDO4 to be used to supply a Real Time Clock from a separate backup battery, for example. Figure 9-4. LDO4 Functional Diagram VDD4 VBATC VIN IBIAS VBG vcore vouts sel4 <1:0> trcore <1:0> VO4 C4 GNDA en3 AVSS VDDESD VZAP 9.5 VZAPC GNDDC GNDA High Performance Bandgap (HPBG) HPBG is a low power, low noise Band Gap circuit providing very accurate voltage reference to LDOs that then can supply RF sections. HPBG operates in switching mode decreasing its current consumption. Economic high performance Bandgap is particularly interesting when RF LDOs are in idle mode (output voltage provided with very low output current e.g. <1mA). HPBG is biased from an internal regulator supplied by VDD4, thus it is not active when only VDD3 is present. HPBG requires at least external 100nF capacitor to achieve very low noise/high accuracy voltage reference. HPBG is trimmed to 1.231V during product test. 9.6 Low Power Bandgap (LPBG) LPBG is a low power Bandgap circuit used as reference voltage for LDO4. LPBG starts up as soon as VDD4 is present and doesn't require any external capacitor for decoupling. 9.7 Reset Generator A Reset Generator produces an output reset (rising from “0” to “1”), called XRESO, at least 100 ms after the input reset state is activated. The input reset state can be produced by: • VDD3 rising up, XRESIN not used or at “1”. • External signal rising up on XRESIN and VDD3 present. 22 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 9.8 State Machine An Internal State Machine supervises the start up of the regulators connected to VDD1, VDD2 and VDD3. The startup configuration is in the following order LDO3 then LDO1 then LDO2. A voltage must be present on VDD4 to supply LDO4. 9.9 Oscillator An Internal Oscillator (RCOSC) is used to generate the internal master clock which synchronizes the state machine controlling the start up of the LDOs and HPBG. 9.10 Power-On-Reset A Power-On-Reset (POR) monitors the output of LDO4 (VO4) and generates an internal signal to enable the trimming registers to be loaded for LDO1, LDO2, LDO3 output voltage programming, as well as for the reference voltages and internal oscillator trimming. This internal signal is released when VO4 is higher then 1.5V ± 300 mV. 9.11 Supply Monitor A Supply Monitor is set on VDD3 and generates an internal signal to enable state machine to startup the LDOs and to generate the XRESO signal. The threshold has been set to 2.7V when rising up and 2.6V when falling down. 9.12 Digital Control On AT73C237, the pins TWCK, TWD are respectively the clock and data lines of a true two-wire interface, allowing to activate and disable the output voltage delivered by the regulators LDO1, LDO2, LDO3 and also to change their output voltage value. 23 6362A–PMAAC–01-Jul-08 9.13 Two-wire Interface (TWI) Protocol The two-wire interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds up to 400 Kbits per second, based one a byte oriented transfer format. The TWI is slave only and single byte access. The interface adds flexibility to the power supply solution, enabling LDO regulators to be controlled depending on the instantaneous application requirements. The AT73C237 has the following 7-bit address:1001000. Attempting to read data from register addresses not listed in this section results in 0xFF being read out. • TWCK is an input pin for the clock • TWD is an open-drain pin that drives or receives the serial data The data put on the TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be followed by an acknowledgement. Each transfer begins with a START condition and terminates with a STOP condition. • A high-to-low transition on TWD while TWCK is high defines a START condition. • A low-to-high transition on TWD while TWCK is high defines a STOP condition. Figure 9-5. TWI Start/Stop Cycle TWD TWCK Start Figure 9-6. Stop TWI Data Cycle TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop After the host initiates a Start condition, it sends the 7-bit slave address defined above to notify the slave device. A Read/Write bit follows (Read = 1, Write = 0). The device acknowledges each received byte. The first byte sent after device address and R/W bit is the address of the device register the host wants to read or write. For a write operation the data follows the internal address For a read operation a repeated Start condition needs to be generated followed by a read on the device. 24 AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 Figure 9-7. S TWD Figure 9-8. TWD S ADDR W TWD Write Operation A ADDR W A IADDR DATA A A P TWD Read Operation IADDR A S ADDR R A DATA N P • S = Start • P = Stop • W = Write • R = Read • A = Acknowledge • N = Not Acknowledge • ADDR = Device address • IADDR = Internal address 25 6362A–PMAAC–01-Jul-08 10. Registers Table 10-1. 10.1 Registers Address Register Description Access Reset value 0×00 LDO_CTRL LDO control Read / Write 0x0F 0×08 LDO_TRIM1 LDO 1,2,3 trim Read / Write 0x00 0×0A LDO_TRIM4 LDO4 trim Read / Write 0x00 LDO Control: LDO_CTRL (0x00) 7 6 5 4 3 2 1 0 - - - - Onldo4 Onldo3 Onldo2 Onldo1 Table 10-2. 10.2 Bit Name Description Reset value 7:4 - Not used - 3 Onldo4 LDO4 enable (active high, HiZ when off) 1 2 Onldo3 LDO3 enable (active high, HiZ when off) 1 1 Onldo2 LDO2 enable (active high, HiZ when off) 1 0 Onldo1 LDO1 enable (active high, HiZ when off) 1 LDO 1,2,3 trim: LDO_TRIM1 (0x08) 7 6 5 4 3 2 - - - Sel1 Sel2 Sel3 Table 10-3. 26 LDO_CTRL (0x00) Structure 1 0 - LDO_TRIM1 (0x08) Structure Bit Name Description Reset value 7:5 - Not used - 4 Sel1 LDO1 output voltage select 0 3 Sel2 LDO2 output voltage select 0 2:1 Sel3 LDO3 output voltage select 00 0 - Not used - AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 Table 10-4. 10.3 LDO_TRIM1 (0x08) - Output Voltages Selection Sel1 VO1 Sel2 VO2 Sel3 VO3 0 2.75V 0 1.8V 00 1.8V 1 1.8V 1 1.5V 01 1.5V - - - - 10 1.23V - - - - 11 1.8 LDO 4 trim: LDO_TRIM4 (0x0A) 7 6 5 4 3 - - - - Sel4 Table 10-5. 2 1 0 trcore1 trcore0 LDO_TRIM1 (0x08) Structure Bit Name Description Reset value 7:4 - Not used - 3:2 Sel4 LDO4 output voltage select 00 1:0 trcore LDO4 output voltage trimming 00 Table 10-6. LDO_TRIM1 (0x08) - Sel4 Sel4 VO4 00 1.8V 01 - 10 - 11 - Table 10-7. LDO_TRIM1 (0x08) - trcore trcore VO4 00 Typ value (1.8V) 01 +80mV 10 -80mV 11 Typ value (1.8V) 27 6362A–PMAAC–01-Jul-08 AT73C237 11. Package Information Figure 11-1. Mechanical Package Drawing for 16-lead Quad Flat No Lead Package 29 6362A–PMAAC–01-Jul-08 12. Ordering Information Table 12-1. 30 Ordering Information Ordering Code Package Package Type Temperature Operating Range AT73C237 QFN 3x3 mm Green 0°C to +70°C AT73C237 6362A–PMAAC–01-Jul-08 AT73C237 13. Revision History Doc. Rev Comments 6362A First issue Change Request Ref. 31 6362A–PMAAC–01-Jul-08 AT73C237 Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 1 2 Block Diagram .......................................................................................... 2 3 Pin Description ......................................................................................... 3 4 Application Block Diagram ..................................................................... 4 5 Electrical Characteristics ........................................................................ 5 6 5.1 Absolute Maximum Ratings ...............................................................................5 5.2 Recommended Operating Conditions ...............................................................5 5.3 Quiescent Current In Different Operating Modes ..............................................6 Startup Procedure .................................................................................... 7 6.1 At VDD4 Rising ..................................................................................................7 6.2 At VDD3 Falling .................................................................................................7 7 Timing Diagram ........................................................................................ 9 8 Electrical Specification .......................................................................... 10 9 8.1 LDO1 ...............................................................................................................10 8.2 LDO2 ...............................................................................................................12 8.3 LDO3 ...............................................................................................................14 8.4 LDO4 ...............................................................................................................16 8.5 High Performance Bandgap (HPBG) ...............................................................17 8.6 Low Power Bandgap (LPBG) ..........................................................................17 8.7 Voltage Monitor ...............................................................................................17 8.8 XRESIN ...........................................................................................................18 8.9 XRESO ............................................................................................................18 8.10 TWCK ..............................................................................................................18 8.11 TWD ................................................................................................................18 Functional Description .......................................................................... 19 9.1 LDO1 ...............................................................................................................19 9.2 LDO2 ...............................................................................................................20 9.3 LDO3 ...............................................................................................................21 9.4 LDO4 ...............................................................................................................22 9.5 High Performance Bandgap (HPBG) ...............................................................22 i 6362A–PMAAC–01-Jul-08 9.6 Low Power Bandgap (LPBG) ..........................................................................22 9.7 Reset Generator ..............................................................................................22 9.8 State Machine ..................................................................................................23 9.9 Oscillator ..........................................................................................................23 9.10 Power-On-Reset ..............................................................................................23 9.11 Supply Monitor .................................................................................................23 9.12 Digital Control ..................................................................................................23 9.13 Two-wire Interface (TWI) Protocol ...................................................................24 10 Registers ................................................................................................. 26 10.1 LDO Control: LDO_CTRL (0x00) .....................................................................26 10.2 LDO 1,2,3 trim: LDO_TRIM1 (0x08) ................................................................26 10.3 LDO 4 trim: LDO_TRIM4 (0x0A) .....................................................................27 11 Package Information .............................................................................. 29 12 Ordering Information ............................................................................. 30 13 Revision History ..................................................................................... 31 Table of Contents....................................................................................... i ii AT73C237 6362A–PMAAC–01-Jul-08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/PowerManage Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 6362A–PMAAC–01-Jul-08