Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM Document Title 2M x 16 bit Pseudo SRAM ( EMP216MEAF Series ) Specification Revision History Revision No. History Draft Date Remark 0.0 Initial Draft Oct. 24 , 2005 Preliminary Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-717 The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM 2Mb x16 Pseudo Static RAM Specification GENERAL DESCRIPTION The EMP216MEAF series is 33,554,432 bits of Pseudo SRAM which uses DRAM type memory cells, but this device has refresh-free operation and extreme low power consumption technology. Furthermore the interface is compatible to a low power Asynchronous type SRAM. The EMP216MEAF is organized as 2,097,152 Words x 16 bit. FEATURES - Organization :2M x16 - Power Supply Voltage : 2.7 ~ 3.3V - Separated I/O power(VccQ) & Core power(Vcc) - Three state outputs - Byte read/write control by UB# / LB# - Support Page Read/Write operation with 16 words - Support PASR, RMS, DPD and Auto-TCSR for power saving - Package type : 48-FPBGA 6.0x8.0 PRODUCT FAMILY Part Number Operating Temp. EMP216MEAF-70E Power Supply -25oC to 85oC 2.7V to 3.3V Speed (tRC) 70ns Power Dissipation Standby Operating (ISB1, Max.) (ICC2, Max.) 100uA 25mA FUNCTION BLOCK DIAGRAM ZZ# CS# UB# LB# WE# OE# CONTROL LOGIC A0~A20 ADDRESS DECODER DQ0~ DQ15 Self-Refresh CONTROL ROW SELECT COLUMN SELECT Memory Array 2M X 16 Din/Dout BUFFER I/O CIRCUIT Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PIN DESCRIPTION ( 48-FBGA-6.00x8.00 ) 2 1 3 4 5 6 A LB# OE# A0 A1 A2 ZZ# B DQ8 UB# A3 A4 CS# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 DNU A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 TOP VIEW (Ball Down) Name Function Name Function CS# Chip select inputs LB# Lower byte (DQ0~7) OE# Output enable input UB# Upper byte (DQ8~15) WE# Write enable input VCC Power supply ZZ# Low Power Control VCCQ I/O Power supply DQ0-15 Data In-out VSS(Q) Ground A0-20 Address inputs NC DNU Do Not Use No connection Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM ABSOLUTE MAXIMUM RATINGS 1) Parameter Symbol Ratings Unit Voltage on Any Pin Relative to Vss VIN, VOUT -0.2 to VCCQ+0.3V V Voltage on Vcc supply relative to Vss VCC, VCCQ -0.22) to 3.6V V Power Dissipation Storage Temperature Operating Temperature PD 1.0 TSTG -65 to 150 o C TA -25 to 85 o C W 1. Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Undershoot at power-off : -1.0V in case of pulse width < 20ns FUNCTIONAL DESCRIPTION CS# ZZ# OE# WE# LB# UB# DQ0~7 DQ8~15 Mode Power H H X X X X High-Z High-Z Deselected Stand by H L X X X X High-Z High-Z Deselected Low Power Mode X H X X H H High-Z High-Z Deselected Stand by L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active L H L H L H Data Out High-Z Lower Byte Read Active L H L H H L High-Z Data Out Upper Byte Read Active L H L H L L Data Out Data Out Word Read Active L H X L L H Data In High-Z Lower Byte Write Active L H X L H L High-Z Data In Upper Byte Write Active L H X L L L Data In Data In Word Write Active Note: X means don’t care. (Must be low or high state) Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Symbol Min Typ Max Unit VCC 2.7 3.0 3.3 V VCCQ 2.7 3.0 3.3 V VSS, VSSQ 0 0 0 V Input high voltage VIH 0.8 * VCCQ - VCCQ + 0.22) V Input low voltage VIL - 0.2 * VCCQ V Supply voltage Ground 1. 2. 3. 4. -0.23) TA= -25 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Ouput capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=VSS to VCCQ , VCC=VCCmax -1 - 1 uA Output leakage current ILO CS#=VIH , ZZ#=VIH , OE#=VIH or WE#=VIL , VIO=VSS to VCCQ , VCC=VCCmax -1 - 1 uA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS#<0.2V, ZZ#=VIH , VIN<0.2V or VIN>VCCQ-0.2V - - 3 mA ICC2 Cycle time = Min, IIO=0mA, 100% duty, CS#=VIL, ZZ#=VIH, VIN=VIL or VIH - - 25 mA Output low voltage VOL IOL = 0.5mA, VCC=VCCmin - - 0.2*VCCQ V Output high voltage VOH IOH = -0.5mA, VCC=VCCmin 0.8*VCCQ - - V Standby Current (CMOS) ISB - - 100 uA Average operating current CS#,ZZ#>VCCQ-0.2V, Other inputs = 0 ~ VCCQ (Typ. condition : VCC=3.0V @ 25oC) (Max. condition : VCC=3.3V @ 85oC) 1. Maximum Icc specifications are tested with VCC = VCCmax. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Dout Input Pulse Level : 0.2V to VCCQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VCCQ/2 CL1) 1) Output Load (See right) : CL = 30pF 1. Including scope and Jig capacitance AC CHARACTERISTICS (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = -25C to +85oC) Symbol Parameter List Read Write Page Speed Min Max Unit Read Cycle Time tRC 70 20k ns Address access time tAA - 70 ns Chip enable to data output tCO - 70 ns Output enable to valid output tOE - 25 ns UB#, LB# enable to data output tBA - 70 ns Chip enable to low-Z output tLZ 10 - ns UB#, LB# enable to low-Z output tBLZ 10 - ns Output enable to low-Z output tOLZ 5 - ns Chip disable to high-Z output tHZ 0 15 ns UB#, LB# disable to high-Z output tBHZ 0 15 ns Output disable to high-Z output tOHZ 0 15 ns Output hold from Address change tOH 5 - ns Write Cycle Time tWC 70 20k ns Chip enable to end of write tCW 60 - ns Address setup time tAS 0 - ns Address valid to end of write tAW 60 - ns UB#, LB# valid to end of write tBW 60 - ns Write pulse width tWP 50 - ns Write recovery time tWR 0 - ns Write to output high-Z tWHZ 0 15 ns Data to write time overlap tDW 20 - ns Data hold from write time tDH 0 - ns End write to output low-Z tOW 5 - ns Maximum cycle time tMRC - 20k ns Page mode cycle time tPC 25 - ns Page mode address access time tPAA - 25 ns Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM TIMING DIAGRAMS READ CYCLE (1) (Address controlled, CS#=OE#=VIL, ZZ#=WE#=VIH, UB# or/and LB#=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid READ CYCLE (2) (ZZ#=WE#=VIH) tRC Address tAA CS# tOH tCO tHZ tBA LB#, UB# tBHZ tOE OE# Data Out tOLZ High-Z tBLZ tOHZ Data Vaild tLZ NOTES (READ CYCLE) 1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than tRC for continuous periods > 20us. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PAGE READ CYCLE (ZZ#=WE#=VIH, 16 Words access) tMRC Address (A20~A4) tRC Address (A3~A0) tPC tPC tPC tPC tAA tCO tOH CS# tHZ tBA LB#,UB# tBHZ tOE OE# Data Out tPAA tOLZ High-Z tBLZ Data Valid tPAA Data Valid tPAA tPAA Data Valid Data Valid tOHZ Data Valid tLZ NOTES (READ CYCLE) 1. tHZ , tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. Do not Access device with cycle timing shorter than tRC for continuous periods > 20us. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM WRITE CYCLE (1) (WE# controlled, ZZ#=VIH) tWC Address tAW tCW CS# tBW LB#,UB# WE# tAS Data In tWR tWP tDH tDW High-Z Data Valid tWHZ tOW Data Undefined Data Out WRITE CYCLE (2) (CS# controlled, ZZ#=VIH) tWC Address tAS CS# tWR tCW tAW LB#,UB# tBW WE# tWP tDH tDW Data In Data Out Data Valid High-Z WRITE CYCLE (3) (UB#/LB# controlled, ZZ#=VIH) tWC Address tWR tCW CS# tAW LB#,UB# tAS tBW tWP WE# tDW Data Valid Data In Data Out tDH High-Z Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PAGE WRITE CYCLE (ZZ#=VIH, 16 Words access) tMRC Address (A20~A4) tWC tPC tPC tPC tPC Address (A3~A0) CS# LB#,UB# tAS WE# tDW Data In High-Z tWHZ tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid tDW tDH Data Valid tOW Data Out NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS#, low WE# and low UB# or LB#. A write begins at the last transition among low CS# and low WE# with asserting UB# or LB# low for single byte operation or simultaneously asserting UB# and LB# low for word operation. A write ends at the earliest transition among high CS# and high WE#. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from CS# going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS# or WE# going high. 5. Do not Access device with cycle timing shorter than tWC for continuous periods > 20us. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM LOW POWER MODES Mode Register Set A20 ~ A5 A4 A3 A2 All 0 (Reserved for future) DPD Enable/Disable Array Mode Selection Array Half Selection DPD Enable / Disable A1 A0 Array Refresh Area Selection Array Mode Selection A4 Type A3 Type 0 Deep Power Down Enable 0 Partial Array Refresh Mode (Default) 1 DPD Disable (Default) 1 Reduced Memory Size Mode Array Half Selection (Top/Down) Array Refresh Area Selection A2 Type A1 A0 Type 0 Bottom (Default) 0 0 Full Array (Default) 1 Top 0 1 RFU (Reserved for future) 1 0 1/2 Array 1 1 1/4 Array NOTES 1. The Partial Array Refresh and Deep Power Down mode is issued only during ZZ# low state. 2. The RMS (Reduced Memory Size) mode is enabled after ZZ# goes high and remains enabled after ZZ# goes high. To change to a different mode, the mode register will have to be re-written. 3. If register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that ZZ# is driven low and there is no MRS update. When ZZ# is driven high, all of the register settings will return to dafault state for the part (i.e. full array refresh, Deep Power Down disabled.) Mode Register Set UpdateTiming Diagram tWC Address tCW CS# tWR tAS tAW LB#,UB# tBW tWP WE# tZZWE ZZ# NOTES Register write start Register write complete Register update complete The register update takes place after over the tZZWE maximum time of 1us. Once the register is updated the next time ZZ# goes low, without any updates to the register starting within the tZZWE maximum time of 1us, the part will refresh the array selected. The data bus is a don’t care when ZZ# is low during the register updates. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM LOW POWER MODES Deep Power Down Mode Entry & Exit ~ ~~ ~ tWC A4 tWR ~ ~ tCW tAS tAW tBW ~ ~~ ~ CS# UB#,LB# ~ ~~ ~ tWP WE# tZZWE tZZmin ~ ~ ZZ# tR Normal operation Register Write Start Deep Power Down Exit Parameter Description Min Max Unit tZZWE ZZ# low to Write Enable Low 0 1 us tR(Deep Power Down mode only) Operation Recovery Time 200 - us tZZmin Low Power Mode Time 10 - us Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM Address Information for PASR mode and RMS mode Partial Array Self Refresh Mode (A3=0, A4=1) A2 A1 A0 Refresh Section Address Size Density 0 1 1 1/4 000000h~07FFFFh 512Kb x 16 8Mb 0 1 0 1/2 000000h~0FFFFFh 1Mb x 16 16Mb X 0 0 Full 000000h~1FFFFFh 2Mb x 16 32Mb 1 1 1 1/4 180000h~1FFFFFh 512Kb x 16 8Mb 1 1 0 1/2 100000h~1FFFFFh 1Mb x 16 16Mb Reduced Memory Size Mode (A3=1, A4=1) A2 A1 A0 Refresh Section Address Size Density 0 1 1 1/4 000000h~07FFFFh 512Kb x 16 8Mb 0 1 0 1/2 000000h~0FFFFFh 1Mb x 16 16Mb 1 1 1 1/4 180000h~1FFFFFh 512Kb x 16 8Mb 1 1 0 1/2 100000h~1FFFFFh 1Mb x 16 16Mb Low Power Mode Characteristics Parameter Symbol Deep Power Down Current IZZ Partial Array Refresh Mode Standby Current Reduced Memory Size Mode Standby Current IZZa IZZb Test Conditions ZZ# < 0.2V, Other inputs = 0 ~ VCCQ (Max. condition : VCC=3.3V @ 85oC) Array Min Typ Max Unit No Refresh - - 10 uA 1/4 Array - - 65 uA 1/2 Array - - 75 uA ISB1a RMS mode. Other inputs = 0 ~ VCCQ 1/4 Array - - 65 uA ISB1b (Max. condition : VCC=3.3V @ 85oC) 1/2 Array - - 75 uA Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM TIMING WAVEFORM OF POWER UP 200us VCC(Min.) VCC CS# Power Up Mode Normal Operation NOTE ( POWER UP ) 1. After Vcc reaches Vcc(Min.) , wait 200us with CS# high. Then you get into the normal operation. Rev 0.0 Preliminary EMP216MEAF Series 2Mx16 Pseudo Static RAM PACKAGE DIMENSION 48 Ball Fine Pitch BGA (0.75mm ball pitch) Bottom View Top View A1 corner index area A1 index Mark B B1 B 6 5 4 3 2 1 A B C C1 C C D E C/2 F G H B/2 Side View 4 E2(Seating plane) A 3 D(Diameter) Detail A 0.25 Typ. E1 E C 5 Min. Typ. Max. A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E - 1.00 1.10 E1 - 0.75 - E2 0.20 0.25 0.30 R - - 0.08 R 0.75 Typ. C A NOTES 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. All dimensions are millimeters. 3. Dimension “D” is measured at the maximum solder ball diameter in a plane parallel to datum C. 4. Primary datum C (Seating plane) is defined by the crown of the solder balls. 5. This is a controlling dimension. Rev 0.0