RT8055B 3A, 2MHz, Synchronous Step-Down Converter General Description Features The RT8055B is a high efficiency synchronous, step-down DC/DC converter. Its input voltage range is from 2.6V to 5.5V and provides an adjustable regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. z The RT8055B is operated in forced continuous PWM Mode which minimizes ripple voltage and reduces the noise and RF interference. The RT8055B is available in the WDFN-10L 3x3 package. z z z z z z z z Applications z z z z z Ordering Information z RT8055B z Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Low RDS(ON) Internal Switches : 100mΩ Ω Programmable Frequency : 300kHz to 2MHz No Schottky Diode Required 0.8V Reference Voltage Allows for Low Output Voltage Forced Continuous Mode Operation 100% Duty Cycle Operation Input Over Voltage Protection Power Good Output Voltage Indicutor RoHS Compliant and Halogen Free Portable Instruments Battery-Powered Equipment Notebook Computers Distributed Power Systems IP Phones Digital Cameras 3G/3.5G Data Card Pin Configurations (TOP VIEW) SHDN/RT GND LX LX PGND 1 2 3 4 5 GND The internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external Schottky diode. The switching frequency is set by an external resistor. The 100% duty cycle provides low dropout operation extending battery life in portable systems. Current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. z High Efficiency : Up to 95% 11 10 9 8 7 6 COMP FB PGOOD VDD PVDD WDFN-10L 3x3 Marking Information K3= : Product Code K3=YM DNN YMDNN : Date Code DS8055B-03 April 2011 www.richtek.com 1 RT8055B Typical Application Circuit 6 VIN 5V CIN 22µF RT8055B 3, 4 PVDD LX R3 R4 100k 7 8 ROSC 180k 1 2,11 (Exposed Pad) 5 VOUT1 3.3V/3A CF 22pF VDD FB 9 C1 PGOOD L1 2µH PGOOD COMP R1 75k COUT 22µF x 2 R2 24k 10 SHDN/RT RCOMP 30k GND CCOMP 470pF PGND Note : Using X5R/X7R Ceramic Capacitors Table 1. Recommended Component Selsction VOUT 3.3 2.5 1.8 1.5 1.2 1.0 R1 (kΩ) 75 51 30 21 12 6 R2 (kΩ) 24 24 24 24 24 24 RCOMP (kΩ) 30 27 22 18 15 13 CCOMP (nF) 0.47 0.47 0.47 0.47 0.47 0.47 L1 (μH) 2.2 2.2 2.2 2.2 1.0 1.0 C OUT (μF) 22 x 2 22 x 2 22 x 2 22 x 2 22 x 2 22 x 2 Functional Pin Description Pin No. 1 Pin Name Pin Function Shutdown Control or Frequency Setting Input. Connect a resistor to ground from SHDN/RT this pin sets the switching frequency. Force this pin to VDD or GND causes the device to be shut down. Signal Ground. All small-signal components and compensation components should 2, 11 (Exposed Pad) GND be connected to this ground, which in turn connects to PGND at one point. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 3, 4 LX Internal Power MOSFET Switches Output. Connect this pin to the inductor. 5 PGND Power Ground. Connect this pin close to the negative terminal of CIN and COUT. 6 PVDD Power Supply Input. Decouple this pin to PGND with a capacitor. 7 VDD 8 PGOOD Power Good Indicator. The pin is an open drain logic output that is pulled to Ground. 9 FB Feedback Pin. This pin receives the feedback voltage from a resistive divider connected across the output. Signal Supply Input. Decouple this pin to GND with a capacitor. Generally, VDD is equal to PVDD. Error Amplifier Compensation Point. The current comparator threshold increases 10 www.richtek.com 2 COMP with this control voltage. Connect external compensation elements to this pin to stabilize the control loop. DS8055B-03 April 2011 RT8055B Function Block Diagram SHDN/RT PVDD ISEN SD OSC Slope Comp. COMP 0.8V EA FB OC Limit Output Clamp Internal Soft-Star Driver 0.9V LX Control Logic 0.7V NISEN OTP 0.4V VREF POR PGND N-MOSFET ILIM PGOOD GND VDD DS8055B-03 April 2011 www.richtek.com 3 RT8055B Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VDD, PVDD ---------------------------------------------------------------------------- −0.3V to 6.5V LX Pin Switch Voltage -------------------------------------------------------------------------------------------- −0.3V to (PVDD + 0.3V) <30ns ---------------------------------------------------------------------------------------------------------------- −5V to 7.5V Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to 6.5V LX Pin Switch Current -------------------------------------------------------------------------------------------- 4A Power Dissipation, PD @ TA = 25°C WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------- 1.667W Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA ----------------------------------------------------------------------------------------------- 60°C/W WDFN-10L 3x3, θJC ----------------------------------------------------------------------------------------------- 7.8°C/W Junction Temperature --------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z (Note 4) Supply Input Voltage ---------------------------------------------------------------------------------------------- 2.6V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C Electrical Characteristics (VDD = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range VDD 2.6 -- 5.5 V Feedback Reference Voltage VREF 0.784 0.8 0.816 V Feedback Leakage Current IFB VFB = 3.3V -- -- 0.1 μA Active, VFB = 0.7V, Not Switching -- 500 -- μA Shutdown -- -- 1 μA DC Bias Current Output Voltage Line Regulation ΔVLINE VIN = 2.6V to 5.5V -- 0.1 -- %/V Output Voltage Load Regulation ΔVLOAD VIN = 5V, VOUT = 3.3V, I OUT = 0A to 3A -- 0.4 -- % Error Amplifier Transconductance gm -- 400 -- μA/V Current Sense Transresistance -- 0.4 -- Ω -- -- 1 μA ROSC = 180kΩ 1.44 1.8 2.16 MHz Adjustable Switching Frequency Range 0.3 -- 2 MHz RT Leakage Current Switching Frequency RS SHDN/RT = VIN = 5.5V Switch On Resistance, High RDS(ON)_P I SW = 0.3A -- 100 160 mΩ Switch On Resistance, Low RDS(ON)_N I SW = 0.3A -- 100 170 mΩ To be continued www.richtek.com 4 DS8055B-03 April 2011 RT8055B Parameter Peak Current Limit Symbol Min Typ Max Unit 3.5 -- -- A V DD Rising -- 2.4 -- V V DD Falling -- 2.2 -- V V SHDN Rising -- V OUT Falling (Fault) -- 87 -- %V OUT V OUT Rising (Good) -- 90 -- %V OUT V OUT Rising (Fault) -- 114 -- %V OUT V OUT Falling (Good) -- 111 -- %V OUT ILIM Under Voltage Lockout Threshold Shutdown Threshold Test Conditions V SHDN VIN − 0.85 V IN − 0.4 V Power Good (PGOOD) Power Good Threshold Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity four layers test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8055B-03 April 2011 www.richtek.com 5 RT8055B Typical Operating Characteristics Output Voltage vs. Input Voltage Efficiency vs. Output Current 3.36 100 90 3.35 Output Voltage (V) Efficiency (%) 80 70 60 50 40 30 20 3.34 3.33 3.32 3.31 10 VIN = 5V, VOUT = 3.3V IOUT = 0A, VOUT = 3.3V 3.30 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.5 3.0 3.7 3.9 4.1 Output Current (A) 4.5 4.7 4.9 5.1 5.3 5.5 Input Voltage (V) Output Voltage vs. Output Current VIN UVLO vs. Temperature 3.40 2.50 3.38 2.45 2.40 3.36 VIN UVLO (V) Output Voltage (V) 4.3 3.34 3.32 3.30 2.35 Rising 2.30 2.25 2.20 Falling 2.15 2.10 3.28 2.05 VIN = 5V, VOUT = 3.3V 3.26 VOUT = 3.3V 2.00 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 -50 -25 0 Output Current (A) 50 75 100 125 Switching Frequency vs. Temperature Switching Frequency vs. Input Voltage 2.1 2.1 2.0 1.9 1.8 1.7 1.6 VIN = 5V, VOUT = 3.3V IOUT = 0.3A, fSW = 1.8MHz 1.5 Switching Frequency (MHz)1 Switching Frequency (MHz)1 25 Temperature (°C) 2.0 1.9 1.8 1.7 1.6 VIN = 5V, VOUT = 3.3V IOUT = 0.3A, fSW = 1.8MHz 1.5 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 Input Voltage (V) www.richtek.com 6 5.1 5.3 5.5 -50 -25 0 25 50 75 100 125 Temperature (°C) DS8055B-03 April 2011 RT8055B Output Current Limit vs. Temperature 6.0 5.5 5.5 Output Current Limit (A) Output Current Limit (A) Output Current Limit vs. Input Voltage 6.0 5.0 4.5 4.0 3.5 3.0 2.5 5.0 4.5 4.0 3.5 3.0 2.5 VIN = 5V, VOUT = 3.3V VOUT = 3.3V 2.0 2.0 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 -50 -25 0 50 75 100 125 Reference Voltage vs. Temperature 0.840 3.38 0.832 3.36 0.824 Reference Voltage (V) Output Voltage (V) Output Voltage vs. Temperature 3.40 3.34 3.32 3.30 3.28 3.26 3.24 VIN = 5V, VOUT = 3.3V IOUT = 0A 3.22 25 Temperature (°C) Input Voltage (V) 0.816 0.808 0.800 0.792 0.784 0.776 0.768 0.760 3.20 -50 -25 0 25 50 75 100 125 -50 0 25 50 75 Temperature (°C) Output Ripple Output Ripple VLX (5V/Div) VLX (5V/Div) VOUT (5mV/Div) VOUT (5mV/Div) VIN = 5V, VOUT = 3.3V IOUT = 3A Time (500ns/Div) DS8055B-03 April 2011 -25 Temperature (°C) 100 125 VIN = 5V, VOUT = 3.3V IOUT = 0A Time (500ns/Div) www.richtek.com 7 RT8055B Load Transient Response Load Transient Response VOUT (200mV/Div) VOUT (200mV/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 5V, VOUT = 3.3V IOUT = 0A to 3A Time (100μs/Div) VIN = 5V, VOUT = 3.3V IOUT = 0A to 2A Time (100μs/Div) Power On from VIN VIN (2V/Div) VOUT (2V/Div) PGOOD (2V/Div) VIN = 5V, VOUT = 3.3V Time (1ms/Div) www.richtek.com 8 DS8055B-03 April 2011 RT8055B The basic RT8055B application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Output Voltage Setting The output voltage is set by an external resistive divider according to the following equation : VOUT = VREF × ⎛⎜1 + R1 ⎞⎟ ⎝ R2 ⎠ where VREF equals to 0.8V typical. The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 1. VOUT R1 FB RT8055B R2 GND Figure 1. Setting the Output Voltage Soft-Start The RT8055B contains an internal soft-start clamp that gradually raises the clamp on the COMP pin. The operating frequency of the RT8055B is determined by an external resistor that is connected between the SHDN/RT pin and GND. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. The RT resistor value can be determined by examining the frequency vs. RRT curve. Although frequencies as high as 2MHz are possible, the minimum on-time of the RT8055B imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns. Therefore, the minimum duty cycle is equal to 100 x 110ns x f (Hz). 3.0 Switching Frequency (MHz)1 Application Information 2.5 RRT = 180k for 1.8MHz 2.0 1.5 1.0 0.5 0.0 0 200 400 600 800 1000 ROSC (K (kΩ)) Figure 2 Power Good Output 100% Duty Cycle Operation The power good output is an open drain output and requires a pull up resister. When the output voltage is 14% above or 13% below its set voltage, PGOOD will be pulled low. It is held low until the output voltage returns to within the allowed tolerances once more. In Soft-Start, PGOOD is actively held low and is allowed to transition high until the Soft-Start is finished and the output voltage reaches 90% of its set voltage. When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. Operating Frequency Low Supply Operation Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. The RT8055B is designed to operate down to an input supply voltage of 2.6V. One important consideration at low input supply voltages is that the RDS(ON) of the PChannel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8055B is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. DS8055B-03 April 2011 The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-MOSFET and the inductor. www.richtek.com 9 RT8055B Slope Compensation and Inductor Peak Current CIN and COUT Selection Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8055B, however, separated inductor current signals are used to monitor over current condition. This keeps the maximum output current relatively constant regardless of duty cycle. The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. V V ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥ VIN ⎦ ⎣ f ×L ⎦ ⎣ Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of ΔIL = 0.4(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : ⎡ VOUT ⎤ ⎡ VOUT ⎤ L =⎢ × ⎢1 − ⎥ ⎥ ⎣ f × ΔIL(MAX) ⎦ ⎣ VIN(MAX) ⎦ The inductor's current rating (caused a 40°C temperature rising from 25°C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. www.richtek.com 10 V IRMS = IOUT(MAX) OUT VIN VIN −1 V OUT This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the Effective Series Resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by : ⎡ 1 ⎤ ΔVOUT ≤ ΔIL ⎢ESR + 8fCOUT ⎥⎦ ⎣ The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. DS8055B-03 April 2011 RT8055B Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VDD. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. 2.00 Maximum Power Dissipation (W) Using Ceramic Input and Output Capacitors Four Layers PCB 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curves for RT8055B Package Thermal Considerations Layout Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : Follow the PCB layout guidelines for optimal performance of RT8055B. ` A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the GND pin at one point that is then connected to the PGND pin close to the IC. The exposed pad should be connected to GND. ` Connect the terminal of the input capacitor(s), CIN, as close as possible to the PVDD pin. This capacitor provides the AC current into the internal power MOSFETs. ` LX node is with high frequency voltage swing and should be kept within small area. Keep all sensitive small-signal nodes away from the LX node to prevent stray capacitive noise pick-up. ` Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of powercomponents. PD(MAX) = (TJ(MAX) − TA ) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8055B, the maximum junction temperature is 125°C and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For WDFN-10L 3x3 packages, the thermal resistance θJA is 60°C/W on the standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for WDFN-10L 3x3 package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT8055B package, the Figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. DS8055B-03 April 2011 You can connect the copper areas to any DC net (PVDD, VDD, VOUT, PGND, GND, or any other DC rail in your system). ` Connect the FB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and GND. www.richtek.com 11 RT8055B GND VOUT COUT Place the feedback and compensation components as close to the IC as possible CCOMP ROSC SHDN/RT GND L1 LX LX PGND 1 2 3 4 5 RCOMP 10 9 GND LX should be connected to Inductor by wide and short trace, keep sensitive components away from this trace. 8 11 7 6 R2 COMP FB PGOOD VDD PVDD CF VOUT C1 R1 GND R3 CIN GND VIN Place the input and output capacitors as close to the IC as possible Figure 4. PCB Layout Guide Recommended component selection for Typical Application Component Supplier Series TAIYO YUDEN NR 8040 Table 2. Inductors Inductance (μH) DCR (mΩ) Current Rating (mA) Dimensions (mm) 2 9 7800 8x8x4 Table 3. Capacitors for CIN and COUT Component Supplier TDK TDK Panasonic Panasonic TAIYO YUDEN TAIYO YUDEN TAIYO YUDEN www.richtek.com 12 Part No. C3225X5R0J226M C2012X5R0J106M ECJ4YB0J226M ECJ4YB1A106M LMK325BJ226ML JMK316BJ226ML JMK212BJ106ML Capacitance (μF) 22 10 22 10 22 22 10 Case Size 1210 0805 1210 1210 1210 1206 0805 DS8055B-03 April 2011 RT8055B Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8055B-03 April 2011 www.richtek.com 13