Cirrus CS61584A-IL3 Dual t1/e1 line interface Datasheet

CS61584A
CS61584A
Dual
Dual T1/E1
T1/E1 Line
Line Interface
Interface
Features
– AT&T Publication 62411
– ETSI ETS 300 011, 300 233, CTR 12, TBR 13
l Dual
T1/E1 Line Interface
Volt and 5 Volt Versions
l Crystal-less Jitter Attenuator Meets
European CTR 12 and ETSI ETS 300 011
Specifications
l Matched Impedance Transmit Drivers
l Transmitter Tri-state Capability
l Common Transmit and
ReceiveTransformers for all Modes
l Serial and Parallel Host Mode Operation
l User-customizable Pulse Shapes
l Supports JTAG Boundary Scan
l Compliant with:
l TR-NET-00499
l 3.3
Description
The CS61584A is a dual line interface for T1/E1 applications, designed for high-volume cards where low
power and high density are required. The device is optimized for flexible microprocessor control through a
serial or parallel Host mode interface. Hardware mode
operation is also available.
Matched impedance drivers reduce power consumption
and provide substantial transmitter return loss. The
transmitter pulse shapes are customizable to allow nonstandard line loads. Crystalless jitter attenuation complies with most stringent standards. Support of JTAG
boundary scan enhances system testability and
reliability.
– ITU-T Recommendations: G.703, G.704,
G.706, G.732, G.775 and I.431
– American National Standards (ANSI): T1.102,
T1.105, T1.403, T1.408, and T1.231
– FCC Rules and Regulations: Part 68 and Part
15
Serial Port
Parallel Port
Hardware Mode
IPOL
IPOL (DTACK)
CLKE
ORDERING INFORMATION
See page 53.
CS61584A-IQ3:3.3V, 64-pin TQFP, -40 to +85° C
CS61584A-IL5:5.0V, 68-pin PLCC, -40 to +85° C
CS61584A-IQ5:5.0V, 64-pin TQFP, -40 to +85° C
CS
INT
SCLK
SDO
SDI
SPOL
P/S
AD3
AD4
AD5
AD6
AD7 ALE(AS) WR(R/W) BTS
CS
INT
RD(DS)
AD0
AD1
AD2
P/S
ATTEN0 ATTEN1 RLOOP1 RLOOP2 LLOOP TAOS1 TAOS2 CON01 CON02 CON11 CON12 CON21 CON22 CON31 CON32
CONTROL
TCLK1
(TDATA1) TPOS1
(AIS1) TNEG1
RCLK1
(RDATA1) RPOS1
(BPV1) RNEG1
TCLK2
(TDATA2) TPOS2
(AIS2) TNEG2
RCLK2
(RDATA2) RPOS2
(BPV2) RNEG2
E
N
C
O
D
E
R
D
E
C
O
D
E
R
E
N
C
O
D
E
R
D
E
C
O
D
E
R
R
E
M
O
T
E
L
O
C
A
L
L
O
O
P
B
A
C
K
1
JITTER
ATTENUATOR
L
O
O
P
B
A
C
K
R
E
M
O
T
E
L
O
C
A
L
L
O
O
P
B
A
C
K
1
JITTER
ATTENUATOR
L
O
O
P
B
A
C
K
PULSE
SHAPING
CIRCUITRY
TAOS
LOS &
AIS
DETECT
CLOCK &
DATA
RECOVERY
TAOS
PULSE
SHAPING
CIRCUITRY
LOS &
AIS
DETECT
CLOCK &
DATA
RECOVERY
2
REFCLK
XTALOUT
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
http://www.cirrus.com
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
L
O
O
P
B
A
C
K
2
RECEIVER
L
O
C
A
L
DRIVER
L
O
O
P
B
A
C
K
2
RECEIVER
CONTROL
CLOCK GENERATOR
JTAG
4
L
O
C
A
L
DRIVER
1XCLK
2
2
2
TTIP1
TRING1
RTIP1
RRING1
TTIP2
TRING2
RTIP2
RRING2
RESET
MODE
3
TV+ TGND RV+ RGND DV+ DGND AV+ AGND BGREF PD1 PD2 LOS1 LOS2
SAD4 SAD5 SAD6 SAD7
ZTX1 ZTX2 LOS1 LOS2
Hardware Mode
Parallel Port
Serial Port
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
 Cirrus
Copyright  Cirrus
Logic, Inc.
2005 Logic, Inc. 2000
(All Rights Reserved)
(All Rights Reserved)
JAN ‘01
SEP ‘05
DS261PP5
DS261F1
1
DS261PP5
CS61584A
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
RECOMMENDED OPERATING CONDITIONS ....................................................................... 5
ANALOG CHARACTERISTICS ................................................................................................ 6
ANALOG CHARACTERISTICS ................................................................................................ 7
DIGITAL CHARACTERISTICS ................................................................................................. 8
SWITCHING CHARACTERISTICS .......................................................................................... 8
SWITCHING CHARACTERISTICS - SERIAL PORT ............................................................. 10
SWITCHING CHARACTERISTICS - PARALLEL PORT ........................................................ 11
SWITCHING CHARACTERISTICS - JTAG ............................................................................ 14
2. OVERVIEW ............................................................................................................................. 15
2.1 AT&T 62411 Customer Premises Application .................................................................. 16
2.2 Asynchronous Multiplexer Application ............................................................................. 16
2.3 Synchronous Application ................................................................................................. 16
3. TRANSMITTER ....................................................................................................................... 16
4. RECEIVER .............................................................................................................................. 18
5. JITTER ATTENUATOR .......................................................................................................... 19
6. REFERENCE CLOCK ............................................................................................................ 20
7. POWER-UP RESET ................................................................................................................ 20
8. LINE CONTROL AND MONITORING .................................................................................... 20
8.1 Line Code Encoder/Decoder ............................................................................................ 20
8.2 Alarm Indication Signal .................................................................................................... 20
8.3 Bipolar Violation Detection ............................................................................................... 21
8.4 Excessive Zeros Detection .............................................................................................. 21
8.5 Loss of Signal .................................................................................................................. 21
8.6 Transmit All Ones ............................................................................................................ 21
8.7 Receive All Ones ............................................................................................................. 21
8.8 Local Loopback ................................................................................................................ 22
8.9 Remote Loopback ............................................................................................................ 22
8.10 Driver Tristate ................................................................................................................ 22
8.11 Power Down ................................................................................................................... 22
8.12 Reset Pin ....................................................................................................................... 23
9. HOST MODE ........................................................................................................................... 23
9.1 Register Set ..................................................................................................................... 23
9.1.1 Status Registers .................................................................................................. 23
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including
use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the
property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other
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Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS261PP5
DS261F1
DS261PP5
10.
11.
12.
13.
CS61584A
9.1.2 Mask Registers ................................................................................................... 25
9.1.3 Control A Registers ............................................................................................. 26
9.1.4 Control B Registers ............................................................................................. 27
9.1.5 Arbitrary Waveform Registers ............................................................................. 27
9.2 Serial Port Operation ....................................................................................................... 30
9.3 Parallel Port Operation .................................................................................................... 31
JTAG BOUNDARY SCAN .................................................................................................... 31
10.1 JTAG Data Registers (DR) ............................................................................................ 32
10.2 JTAG Instructions and Instruction Register (IR) ............................................................ 33
10.3 JTAG TAP Controller ..................................................................................................... 33
10.4 Test-Logic-Reset State .................................................................................................. 33
10.5 Run-Test/Idle State ........................................................................................................ 34
10.6 Select-DR-Scan State ................................................................................................... 34
10.7 Capture-DR State .......................................................................................................... 34
10.8 Shift-DR State ................................................................................................................ 34
10.9 Exit1-DR State ............................................................................................................... 34
10.10 Pause-DR State ........................................................................................................... 35
10.11 Exit2-DR State ............................................................................................................. 35
10.12 Update-DR State ......................................................................................................... 35
10.13 Select-IR-Scan State ................................................................................................... 35
10.14 Capture-IR State .......................................................................................................... 35
10.15 Shift-IR State ............................................................................................................... 35
10.16 Exit1-IR State .............................................................................................................. 36
10.17 Pause-IR State ............................................................................................................ 36
10.18 Exit2-IR State .............................................................................................................. 36
10.19 Update-IR State ........................................................................................................... 36
10.20 JTAG Application Examples ........................................................................................ 36
PIN DESCRIPTIONS ............................................................................................................ 39
PACKAGE DIMENSIONS .................................................................................................... 46
APPLICATIONS ................................................................................................................... 48
13.1 Line Interface ................................................................................................................. 48
13.2 Power Supply ................................................................................................................ 50
13.3 Quartz Crystal Specifications ........................................................................................ 50
13.4 Crystal Oscillator Specifications .................................................................................... 50
13.5 Transformers ................................................................................................................. 51
13.6 Designing for AT&T 62411 ............................................................................................ 51
13.7 Line Protection ............................................................................................................... 51
13.8 Loop Selection Equations .............................................................................................. 51
LIST OF TABLES
Table 1. Line Configuration Selections............................................................................................. 17
Table 3. Jitter Attenuation Control.................................................................................................... 19
Table 4. CS61584A Register Set ..................................................................................................... 23
Table 5. Status Registers ................................................................................................................. 24
Table 6. Mask Registers................................................................................................................... 25
Table 7. Control A Registers ............................................................................................................ 26
Table 8. Control B Registers ............................................................................................................ 27
Table 9. Arbitrary Waveform Registers ............................................................................................ 28
Table 10. Boundary Scan Register .................................................................................................. 32
Table 11. Device Identifcation Register............................................................................................ 33
Table 12. ......................................................................................................................................... 33
DS261PP5
DS261F1
3
DS261PP5
CS61584A
Table 13. CS61584A External Components..................................................................................... 48
Table 14. Quartz Crystal Specifications ........................................................................................... 50
Table 15. Suggested Quartz Crystals............................................................................................... 50
Table 16. Suggested Crystal Oscillators .......................................................................................... 50
Table 17. Transformer Specifications ............................................................................................... 51
Table 18. Recommended Transformers........................................................................................... 52
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
4
Signal Rise And Fall Characteristics .............................................................................. 9
Recovered Clock and Data Switching Characteristics ................................................... 9
Transmit Clock and Data Switching Characteristics ...................................................... 9
Serial Port Write Timing Diagram ................................................................................. 10
Serial Port Read Timing Diagram ................................................................................ 10
Parallel Port Timing - Motorola Mode ........................................................................... 12
Parallel Port Timing - Intel Read Mode ........................................................................ 12
Parallel Port Timing - Intel Write Mode ........................................................................ 12
Parallel Port Timing - Motorola Mode to RAM .............................................................. 13
Parallel Port Timing - Intel Read Mode from RAM or ROM ......................................... 13
Parallel Port Timing - Intel Write Mode to RAM ........................................................... 13
JTAG Switching Characteristics ................................................................................... 14
Examples of CS61584A Applications ........................................................................... 15
Typical Pulse Shape at DSX-1 Cross Connect ............................................................ 17
Mask of the Pulse at the 2048 kbps Interface .............................................................. 17
Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and
jitter Attenuator) ............................................................................................................ 18
Typical Jitter Transfer Function .................................................................................... 19
Alarm Indication Event Relationships ........................................................................... 24
Phase Definition of Arbitrary Waveforms ..................................................................... 29
Example of Summing of Waveforms ............................................................................ 29
Serial Read/Write Format (SPOL = 0) .......................................................................... 30
Address Command byte ............................................................................................... 30
JTAG Circuitry Block Diagram ..................................................................................... 31
TAP Controller State Diagram ...................................................................................... 34
JTAG Instruction Register update ................................................................................ 37
JTAG Data Register update ......................................................................................... 38
Hardware Mode Configuration ..................................................................................... 48
Host Mode Serial Port Configuration ............................................................................ 49
Host Mode Parallel Port Configuration ......................................................................... 49
DS261PP5
DS261F1
DS261PP5
CS61584A
1. CHARACTERISTICS AND SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Unit
-
6.0
V
Vin
RGND - 0.3
(RV+) + 0.3
V
DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 1)
Input Voltage (Any Pin)
Iin
-10
10
mA
Ambient Operating Temperature
Input Current (Any Pin)
(Note 2)
TA
-40
85
°C
Storage Temperature
Tstg
-65
150
°C
Notes: 1. Referenced to RGND1, RGND2, TGND1, TGND2, AGND, DGND at 0 V.
2. Transient currents of up to 100 mA will not cause SCR latch-up.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
DC Supply (TV+1, TV+2, RV+1, RV+2, AV+, DV+) (Note 3)
3.3 V
5.0 V
Ambient Operating Temperature
TA
(Note 4)
(Note 5)
(Note 6)
(Note 5)
(Note 5)
PC
Power Consumption Per Channel (5.0 V)
T1
T1
E1, 75 Ω
E1, 120 Ω
(Note 4)
(Note 5)
(Note 6)
(Note 5)
(Note 5)
PC
REFCLK Frequency
T1
1XCLK = 1
T1
1XCLK = 0
E1
1XCLK = 1
E1
1XCLK = 0
Typ
Max
3.135
4.75
3.3
5.0
3.465
5.25
-40
25
85
Unit
V
Power Consumption Per Channel (3.3 V)
T1
T1
E1, 75 Ω
E1, 120 Ω
REFCLK Frequency
Min
°C
mW
-
310
190
250
230
-
-
350
250
320
310
-
(1.544 100 ppm)
(12.352 100 ppm)
1.544
mW
(2.048 100 ppm)
(16.384 100 ppm)
12.352
2.048
16.384
(1.544 + MHz
100 ppm)
(12.352 + MHz
100 ppm)
(2.048 + MHz
100 ppm)
(16.384 + MHz
100 ppm)
Notes: 3. TV+1, TV+2, AV+, DV+, RV+1, RV+2 should be connected together. TGND1, TGND2, RGND1, GND2,
DGND1, DGND2, DGND3 should be connected together.
4. Per channel power consumption while driving line load over operating temperature range. Includes
device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a
50 pF capacitive load.
5. Assumes 100% ones density and maximum line length at maximum supply voltage (3.465 V or 5.25 V).
6. Assumes 50% ones density and 300 ft. line length at typical supply voltage (3.3 V or 5.0 V).
Specifications are subject to change without notice
DS261PP5
DS261F1
5
DS261PP5
CS61584A
ANALOG CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal.)
Parameter
Receiver
RTIP/RRING Differential Input Impedance
Sensitivity Below DSX-1 (0 dB = 2.4 V)
Loss of Signal Threshold
Data Decision Threshold
T1, DSX-1
(Note 7)
(Note 8)
T1, FCC Part 68 and E1 (Note
9)
(Note 10)
Allowable Consecutive Zeros before LOS
Receiver Input Jitter Tolerance (DSX-1, E1)
10 Hz and below
(Note 11)
2 kHz
10 kHz - 100 kHz
Receiver Return Loss
(Notes 12, 13, and 14)
51 kHz - 102 kHz
102 kHz - 2.048 MHz
2.048 MHz - 3.072 MHz
Jitter Attenuator
Jitter Attenuator Corner Frequency
T1
(Notes 12 and 15)
E1
Attenuation at 10 kHz Jitter Frequency
(Notes 12 and 15)
Attenuator Input Jitter Tolerance
(Note 12)
(Before Onset of FIFO Overflow or Underflow Protection)
Transmitter
Arbitrary Pulse Amplitude at Transformer Secondary
T1, DSX-1
T1, DS1
E1, 75 Ω
E1, 120 Ω
Symbol
Min
Typ
Max
Unit
60
55
45
40
20
-13.6
0.3
65
50
-
70
75
55
60
kΩ
dB
V
% of
Peak
160
175
190
bits
UI
300
6.0
0.4
-
-
12
18
14
22
24
22
-
1.25
28
4.0
1.25
60
43
-
-
73
52
43
52
-
dB
Hz
dB
UIpk-pk
mV/LS
B
Notes: 7. For input amplitude of 1.2 Vpk to 4.14 Vpk.
8. For input amplitude of 0.5 Vpk to 1.2 Vpk, and 4.14 Vpk to 5.0 Vpk.
9. For input amplitude of 1.07 Vpk to 4.14 Vpk.
10. For input amplitude of 4.14 Vpk to 5.0 Vpk.
11. Jitter tolerance increases at lower frequencies. Refer to the Receiver section.
12. Not production tested. Parameters guaranteed by design and characterization.
13. Typical performance using the line interface circuitry recommended in the Applications section.
14. Return loss = 20 log10 ABS((z1 + z0) / (z1 - z0)) where z1 = impedance of the transmitter or receiver, and
z0 = cable impedance.
15. Attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. Circuit
attenuates jitter at 20 dB/decade above the corner frequency. Output jitter can increase significantly
when more than 28 UI's are input to the attenuator. The jitter attenuator -3 dB knee in T1 mode is
selectable for 4.0 Hz or 1.25 Hz. Refer to the Jitter Attenuator section.
6
DS261PP5
DS261F1
DS261PP5
CS61584A
ANALOG CHARACTERISTICS (Continued)
Parameter
Transmitter (Continued)
AMI Output Pulse Amplitudes
(Note 16)
E1, 75 Ω
(Note 17)
E1, 120 Ω
(Note 18)
T1, DSX-1
(Note 19)
Recommended Transmitter Output Load (3.3 V) (Note 16)
T1
E1, 75 Ω
E1, 120 Ω
Recommended Transmitter Output Load (5.0 V) (Note 16)
T1
E1, 75 Ω
E1, 120 Ω
Jitter Added During Remote Loopback
10 Hz - 8 kHz
8 kHz - 40 kHz
10 Hz - 40 kHz
Broad Band
(Note 20)
Power in 2 kHz band about 772 kHz
(Notes 12 and 13)
(DSX-1 only)
Power in 2 kHz band about 1.544 MHz
(Note 12 and 13)
(referenced to power in 2 kHz band at 772 kHz, DSX-1 only)
Positive to Negative Pulse Imbalance
(Notes 12 and 13)
T1, DSX-1
E1, amplitude at center fo pulse interval
E1, width at 50% of nominal amplitude
Transmitter Return Loss
(Notes 12, 13, and 14)
51 kHz - 102 kHz
102 kHz - 2.048 MHz
2.048 MHz - 3.072 MHz
(Note 21)
E1 Short Circuit Current
5.0 V
3.3 V
E1 and DSX-1 Output Pulse Rise/Fall Times
(Note 22)
E1 Pulse Width (at 50% of peak amplitude)
E1 Pulse Amplitude for a space
E1, 75 Ω
E1, 120 Ω
Symbol
Min
Typ
Max
Unit
2.14
2.7
2.4
2.37
3.0
3.0
2.6
3.3
3.6
-
24.8
18.6
30.0
-
-
76.6
57.4
90.6
-
-
0.020
0.015
0.015
0.045
-
12.6
15
17.9
dBm
-29
-38
-
dB
-5
-5
0.2
-
0.5
5
5
dB
%
%
8
14
10
-
25
18
12
70
50
-
mArms
mArms
-
50
-
ns
-
244
-
ns
-0.237
-0.3
-
0.237
0.3
V
V
V
Ω
Ω
UI
dB
Notes: 16. Using a transformer that meets the specifications in the Applications section.
17. Measured across 75 Ω at the output of the transmit transformer for CON3/2/1/0 = 0/0/0/0.
18. Measured across 120 Ω at the output of the transmit transformer for CON3/2/1/0 = 0/0/0/1.
19. Measured at the DSX-1 Cross-Connect for line length settings CON3/2/1/0 = 0/0/1/0, 0/0/1/1, 0/1/0/0,
0/1/0/1, and 0/1/1/0 after the length of #22 ABAM cable specified in Table 1.
20. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
21. Transformer secondary shorted with 0.5 Ω resistor during the transmission of 100% ones.
22. At transformer secondary and measured from 10% to 90% of amplitude.
DS261PP5
DS261F1
7
DS261PP5
CS61584A
DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal.)
Parameter
Symbol
Min
Max
Unit
High-Level Input Voltage
(Note 23)
VIH
(DV+) - 0.5
-
V
Low-Level Input Voltage
(Note 23)
VIL
-
0.5
V
High-Level Output Voltage (Iout = -40 µA)
(Note 24)
VOH
(DV+) - 0.3
-
V
Low-Level Output Voltage (Iout = 1.6 mA)
(Note 24)
VOL
-
0.3
V
-
±10
µA
Input Leakage Current (Digital pins except J-TMS and J-TDI)
Notes: 23. Digital inputs are designed for CMOS logic levels.
24. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.
SWITCHING CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal;
Inputs: Logic 0 = 0 V, Logic 1 = DV+.)
Parameter
T1 Clock/Data
TCLK Frequency
(Note 25)
TCLK Duty Cycle
RCLK Duty Cycle
(Note 26)
Rise Time (All Digital Outputs)
(Note 27)
Fall Time (All Digital Outputs)
(Note 27)
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
E1 Clock/Data
TCLK Frequency
(Note 25)
TCLK Duty Cycle
RCLK Duty Cycle
(Note 26)
Rise Time (All Digital Outputs)
(Note 27)
Fall Time (All Digital Outputs)
(Note 27)
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
Symbol
Min
Typ
Max
Unit
ftclk
-
1.544
-
MHz
tpwh2/tpw2
20
50
80
%
tpwh1/tpw1
45
50
55
%
tr
-
-
65
ns
tf
-
-
65
ns
tsu1
-
274
-
ns
th1
-
274
-
ns
tsu2
25
-
-
ns
th2
25
-
-
ns
ftclk
-
2.048
-
MHz
tpwh2/tpw2
20
50
80
%
tpwh1/tpw1
45
50
55
%
tr
-
-
65
ns
tf
-
-
65
ns
tsu1
-
194
-
ns
th1
-
194
-
ns
tsu2
25
-
-
ns
th2
25
-
-
ns
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be
tolerated by the CS61584A, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.
26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the transmit path
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
27. At max load of 50 pF.
8
DS261PP5
DS261F1
DS261PP5
t
CS61584A
t
r
90%
f
90%
Any Digital Output
10%
10%
Figure 1. Signal Rise And Fall Characteristics
tpw1
RCLK
(for CLKE = high)
t pwl1
t pwh1
t su1
RPOS
RNEG
RDATA
BPV
t h1
RCLK
(for CLKE = low)
Figure 2. Recovered Clock and Data Switching Characteristics
t pw2
t pwh2
TCLK
TPOS
TNEG
TDATA
t su2
t h2
Figure 3. Transmit Clock and Data Switching Characteristics
DS261PP5
DS261F1
9
DS261PP5
CS61584A
SWITCHING CHARACTERISTICS - SERIAL PORT (TA = -40 to 85 °C; DV+, TV+, RV+ =
nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+)
Parameter
Symbol
Min
Typ
Max
Unit
SDI to SCLK Setup Time
tdc
25
-
-
ns
SCLK to SDI Hold Time
tcdh
25
-
-
ns
SCLK Low Time
tcl
50
-
-
ns
SCLK High Time
tch
50
-
-
ns
SCLK Rise and Fall Time
tr, tf
-
-
15
ns
CS to SCLK Setup Time
tcc
20
-
-
ns
tcch
20
-
-
ns
tcwh
100
-
-
ns
tcdv
-
-
50
ns
tcdz
-
50
-
ns
SCLK to CS Hold Time
(Note 28)
CS Inactive Time
SDO Valid to SCLK
(Note 29)
CS to SDO High Z
Notes: 28. If SPOL = 0, then CS should return high no sooner than 20 ns after the 16th rising edge of SCLK during
a serial port read.
29. Output load capacitance = 50 pF.
t cwh
CS
t cc
t cch
t ch
t cl
SCLK
t cdh
t dc
SDI
LSB
t cdh
LSB
CONTROL BYTE
MSB
DATA BYTE
Figure 4. Serial Port Write Timing Diagram
CS
t cdz
SCLK
t cdv
HIGH
SDO
SPOL = 0
Figure 5. Serial Port Read Timing Diagram
10
DS261PP5
DS261F1
DS261PP5
CS61584A
SWITCHING CHARACTERISTICS - PARALLEL PORT (TA = -40 to 85 °C;
TV+, RV+ = nominal ± 0.3 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+)
Parameter
Symbol
Min
Max
Unit
tcyc
250
-
ns
Pulse Width, DS Low or RD High
PWel
150
-
ns
Pulse Width, DS High or RD Low
PWeh
150
-
ns
Input Rise/Fall Times
tr, tf
-
30
ns
Cycle Time
R/W Hold Time
trwh
10
-
ns
R/W Setup Time Before DS High
trws
50
-
ns
CS Setup Time Before DS, WR, or RD Active
tcs
50
-
ns
CS Setup Time Before DS, WR, or RD Active for RAM/ROM
tcsr
130
-
ns
CS Hold Time
tch
20
-
ns
Read Data Hold Time
tdhr
10
80
ns
Write Data Hold Time
tdhw
5
-
ns
Muxed Address Valid to AS or ALE Fall
tasl
15
-
ns
Muxed Address Hold Time
tahl
10
-
ns
Delay Time DS, WR, or RD to AS or ALE Rise
tasd
25
-
ns
40
-
ns
tased
40
-
ns
Output Data Delay Time from DS or RD
tddr
20
120
ns
Data Setup Time
tdsw
80
-
ns
DTACK Delay
tdkd
5
-
ns
DTACK Hold Time
tdkh
5
-
ns
taamir
50
-
ns
Pulse Width AS or ALE High
Delay Time AS or ALE to DS, WR, or RD
AS/ALE Min Low Interval for RAM/ROM
DS261PP5
DS261F1
11
DS261PP5
CS61584A
PW ash
AS
PWeh
t asd
t ased
DS
t cyc
t rws
t rwh
R/W
t ddr
t asl
t dhr
AD0-AD7
(READ)
t ahl
t ch
t cs
CS
t dsw
t asl
AD0-AD7
(WRITE)
t ahl
t dhw
t dkd
t dkh
DTACK
(READ and WRITE)
Figure 6. Parallel Port Timing - Motorola Mode
t cyc
ALE
t asd
PW ash
WR
t ased
t asd
PWel
RD
t cs
t ch
CS
t asl
t dhr
t ddr
AD0-AD7
t ahl
Figure 7. Parallel Port Timing - Intel Read Mode
t cyc
ALE
t asd
PW ash
RD
t ased
t asd
PWel
WR
t cs
t ch
CS
t asl
t dhw
AD0-AD7
t ahl
t dsw
Figure 8. Parallel Port Timing - Intel Write Mode
12
DS261PP5
DS261F1
DS261PP5
PW ash
CS61584A
PW ash
AS
PWeh
t aamir
t asd
t ased
DS
t cyc
t rws
t rwh
R/W
t asl
t ddr
t asl
t dhr
AD0-AD7
(READ)
t ahl
t ahl
t csr
t ch
CS
t dsw
t asl
t asl
AD0-AD7
(WRITE)
t ahl
t dhw
t ahl
t dkd
t dkh
DTACK
(READ and WRITE)
Figure 9. Parallel Port Timing - Motorola Mode to RAM
t cyc
ALE
t asd
PWash
PWash
WR
t aamir
t ased
t asd
PWel
RD
t csr
t ch
CS
t asl
t ddr
t asl
t dhr
AD0-AD7
t ahl
t ahl
Figure 10. Parallel Port Timing - Intel Read Mode from RAM or ROM
t cyc
ALE
t asd
PWash
PWash
WR
t aamir
t ased
t asd
PWel
RD
t csr
t ch
CS
t asl
t asl
t dhr
AD0-AD7
t ahl
t ahl
t dsw
Figure 11. Parallel Port Timing - Intel Write Mode to RAM
DS261PP5
DS261F1
13
DS261PP5
CS61584A
SWITCHING CHARACTERISTICS - JTAG (TA = -40 to 85 °C; TV+, RV+ = nominal ± 0.3 V;
Inputs: Logic 0 = 0 V, Logic 1 = RV+)
Parameter
Symbol
Min
Max
Unit
Cycle Time
tcyc
200
-
ns
J-TMS/J-TDI to J-TCK Rising Setup Time
tsu
50
-
ns
J-TCK Rising to J-TMS/J-TDI Hold Time
th
50
-
ns
J-TCK Falling to J-TDO Valid
tdv
-
60
ns
t cyc
J-TCK
t su
th
J-TMS
J-TDI
t dv
J-TDO
Figure 12. JTAG Switching Characteristics
14
DS261PP5
DS261F1
DS261PP5
2. OVERVIEW
CS61584A
The line driver generates waveforms compatible
with E1 (CCITT G.703), T1 short haul (DSX-1)
and T1 FCC Part 68 Option A (DS1). A single
transformer turns ratio is used for all waveform
types. The driver internally matches the impedance
of the load, providing excellent return loss to insure
superior T1/E1 pulse quality. An additional benefit
of the internal impedance matching is a 50 percent
reduction in power consumption compared to implementing return loss using external resistors that
causes the transmitter to drive the equivalent of two
line loads.
The CS61584A is a dual line interface for T1/E1
applications, designed for high-volume cards
where low power and high density are required.
The device can be operated in either Hardware
mode using control pins or in Host mode using an
internal register set. One board design can support
all T1/E1 short-haul modes by only changing component values in the receive and transmit paths (if
REFCLK and TCLK are connected externally).
Figure 13 illustrates applications of the CS61584A
in various environments.
LOOP TIMED APPLICATION
REFCLK
CS61584A
TPOS
TTIP
TNEG
LINE DRIVER
TCLK
TRING
TRANSMIT
CIRCUITRY
CS62180B
FRAMER
RCLK
RPOS
JITTER
ATTENUATOR
RTIP
LINE RECEIVER
RRING
RECEIVE
CIRCUITRY
RNEG
ASYNCHRONOUS MUX APPLICATION
(i.e., VT1.5 card for SONET or SDH mux)
REFCLK
CS61584A
TDATA
TTIP
JITTER
ATTENUATOR
MUX
TCLK
(gapped)
RCLK
LINE DRIVER
AMI
B8ZS,
HDB3,
CODER
AIS
DETECT
RDATA
TRING
RTIP
LINE RECEIVER
RRING
TRANSMIT
CIRCUITRY
RECEIVE
CIRCUITRY
SYNCHRONOUS APPLICATION
(Including 62411 systems with multiple T1 lines)
REFCLK
CS61584A
TCLK
TTIP
TPOS
LINE DRIVER
TRING
TNEG
CS62180B
FRAMER
TRANSMIT
CIRCUITRY
RCLK
RPOS
RNEG
JITTER
ATTENUATOR
RTIP
LINE RECEIVER
RRING
RECEIVE
CIRCUITRY
Figure 13. Examples of CS61584A Applications
DS261PP5
DS261F1
15
DS261PP5
The line receiver contains all the necessary clock
and data recovery circuits.
The jitter attenuator meets AT&T 62411 requirements when using either a 1X or 8X reference
clock supplied by either a quartz crystal, crystal oscillator, or external reference at the REFCLK input
pin.
2.1
AT&T 62411 Customer Premises
Application
The AT&T 62411 specification applies to the T1
interface between the customer premises and the
carrier, and must be implemented by the customer
premises equipment in order to connect to the
AT&T network.
In 62411 applications, the management of jitter is a
very important design consideration. Typically, the
jitter attenuator is placed in the receive path of the
CS61584A to reduce the jitter input to the system
synchronizer. The jitter attenuated recovered clock
is used as the input to the transmit clock to implement a loop-timed system. A Stratum 4 (±32 ppm)
quality clock or better should be input to REFCLK.
Note that any jitter present on the reference clock
will not be filtered by the jitter attenuator.
2.2
Asynchronous Multiplexer
Application
Asynchronous multiplexers accept multiple T1/E1
lines (which are asynchronous to each other), and
combine them into a higher speed transmission rate
(e.g. M13 muxes and SONET muxes). In these systems, the jitter attenuator is placed in the transmit
path of the CS61584A to remove the gapped clock
jitter input by the multiplexer to TCLK. Because
the transmit clock is jittered, the reference clock to
the CS61584A is provided by an external source
operating at 1X or 8X the data rate. Because T1/E1
framers are not usually required in asynchronous
multiplexers, the B8ZS/AMI/HDB3 coders in the
CS61584A are activated to provide data interfaces
on TDATA and RDATA.
16
2.3
CS61584A
Synchronous Application
A typical example of a synchronous application is
a T1 card in a central office switch or a 0/1 digital
cross-connect system. These systems place the jitter attenuator in the receive path to reduce the jitter
presented to the system. A Stratum 3 or better system clock is input to the CS61584A transmit and
reference clocks.
3. TRANSMITTER
The transmitter accepts data from a T1 or E1 system and outputs pulses of appropriate shape to the
line. The transmit clock (TCLK) and transmit data
(TPOS and TNEG, or TDATA) are supplied synchronously. Data is sampled on the falling edge of
the TCLK input.
During Hardware mode operation, the configuration pins (CON[3:0]) control transmitted pulse
shapes, transmitter source impedance, receiver
slicing level, and driver tristate as shown in
Table 1. During Host mode operation, the configuration is established by the CON[3:0] bits in the
Control B registers. Typical output pulses are
shown in Figures 14 and 15. These pulse shapes are
fully pre-defined by circuitry in the CS61584A,
and are fully compliant with appropriate standards
when used with our application guidelines in standard installations. Both channels must be operated
at the same line rate (both T1 or both E1).
Host mode operation permits arbitrary transmit
pulse shapes to be created and downloaded to the
CS61584A. These custom pulse shapes can be used
to compensate for waveform degradation caused by
non-standard cables, transformers, or protection
circuitry (refer to the Arbitrary Waveform Registers section).
Note that the pulse width for Part 68 Option A
(324 ns) is narrower than the optimal pulse width
for DSX-1 (350 ns). The CS61584A automatically
adjusts the pulse width based on the configuration
selection.
DS261PP5
DS261F1
DS261PP5
Percent of
nominal
peak
voltage
CS61584A
269 ns
120
110
NORMALIZED
AMPLITUDE
100
244 ns
194 ns
90
1.0
ANSI T1.102
SPECIFICATION
G.703
Specification
80
0.5
50
0
10
CS61584A
OUTPUT
PULSE SHAPE
Nominal Pulse
0
-10
-0.5
-20
0
250
500
750
219 ns
488 ns
1000
TIME (nanoseconds)
Figure 14. Typical Pulse Shape at DSX-1 Cross Connect
C
O
N
3
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
C
O
N
2
0
0
0
0
0
0
1
1
1
0
1
1
0
1
1
1
C
O
N
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
C
O
N
0
0
0
1
1
0
1
0
1
0
0
1
0
1
1
0
1
Transmit Pulse
Width at 50%
Amplitude
244 ns (50%)
244 ns (50%)
244 ns (50%)
244 ns (50%)
350 ns (54%)
350 ns (54%)
350 ns (54%)
350 ns (54%)
350 ns (54%)
350 ns (54%)
324 ns (50%)
324 ns (50%)
324 ns (50%)
Reserved
Transmit Hi Z
Transmit Hi Z
Figure 15. Mask of the Pulse at the 2048 kbps Interface
Transmit Pulse Shape
Receiver
Slicing
Level
Line Code
Encoder /
Decoder
E1: square, 2.37 V into 75 Ω
Arbitrary E1 Wave into 75 Ω
E1: square, 2.37 V into 75 Ω
Arbitrary E1 Wave into 120 Ω
DSX-1: 0-133 ft.
DSX-1: 133-266 ft.
DSX-1: 266-399 ft.
DSX-1: 399-533 ft.
DSX-1: 533-655 ft.
Arbitrary DSX-1 Waveform
DS1: FCC Part 68 Option A with undershoot
DS1: FCC Part 68 Option A (0 dB)
Arbitrary DS1 Waveform
50%
50%
50%
50%
65%
65%
65%
65%
65%
65%
65%
65%
65%
AMI/HDB3
AMI/HDB3
AMI/HDB3
AMI/HDB3
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
AMI/B8ZS
Tristate TTIP/TRING Driver Outputs
Tristate TTIP/TRING Driver Outputs
50%
65%
AMI/HDB3
AMI/B8ZS
Table 1. Line Configuration Selections
DS261PP5
DS261F1
17
DS261PP5
The transmitter impedance changes with the line
length options in order to match the load impedance (75 Ω for E1 coax, 100 Ω for T1, 120 Ω for
E1 shielded twisted pair), providing a minimum of
14 dB return loss for T1 and E1 frequencies during
the transmission of both marks and spaces. This
improves signal quality by minimizing reflections
from the transmitter. Impedance matching also reduces load power consumption by a factor of two
when compared to the return loss achieved by using
external resistors.
The CS61584A driver will automatically detect an
inactive TLCK (i.e., no data clocked to the driver)
or REFCLK input. When either of these conditions
are detected the driver is forced to the tristate (highimpedance) condition. If the jitter attenuator is in
the transmit path, the driver will tristate after 170 to
182 TCLK clock cycles. If the attenuator is not in
the transmit path, the driver will tristate after 4 to
12 TCLK clock cycles. During Host mode operation, the CLKLOST bit in the Status register goes
high to indicate when the driver is tristated due to
the absence of TCLK or REFCLK. The driver exits
the tristate condition when four clock cycles are input to TCLK. On power-up or reset, the driver is
tristated until REFCLK is present and four clock
cycles are input to TCLK. In Host mode the driver
will have to be taken out of the tristate condition by
writing the CON[3:0]. The driver is not forced to
the tristate condition during remote loopback if
TCLK is absent.
When the transmit configuration established by
CON[3:0], TAOS, or LLOOP changes state, the
transmitter stabilizes within 22 TCLK bit periods.
The transmitter takes longer to stabilize when
RLOOP1 or RLOOP2 is selected because the timing circuitry must adjust to the new frequency from
RCLK.
CS61584A
by the European specification BS6450. This spec is
met for 5.0 V operation only.
4. RECEIVER
The input signal is connected to the receiver
through a step down transformer (1.15:1 for 5 V
and 2:1 for 3.3 V). Data and clock are extracted
from the T1/E1 signal input to the line interface and
to the system. The signal is detected differentially
across the receive transformer and can be recovered over the entire range of short haul cable
lengths. The transmit and receive transformer specifications are identical and are presented in the Applications section. As shown in Table 1, the
receiver slicing level is set at 65% for DS1/DSX-1
short-haul and at 50% for all other applications.
The clock recovery circuit is a second-order phase
locked loop that can tolerate up to 0.4 UI of jitter
from 10 kHz to 100 kHz without generating errors
(Figure 13). The clock and data recovery circuit is
tolerant of long strings of consecutive zeros and
will successfully recover a 1-in-175 jitter-free line
input signal.
Recovered data at RPOS and RNEG (or RDATA)
is stable and may be sampled using the recovered
clock RCLK. During Hardware mode operation,
CS61584A
Performance
300
138
100
AT&T 62411
(1990 Version)
28
PEAK-TO-PEAK
JITTER
10
(unit intervals)
1
.4
.1
When the transmitter transformer secondaries are
shorted through a 0.5 Ω resistor, the transmitter
will output a maximum of 50 mA-rms, as required
18
1
10
100 300 700 1k
10k
100k
JITTER FREQUENCY (Hz)
Figure 16. Minimum Input Jitter Tolerance of Receiver
(Clock Recovery Circuit and jitter Attenuator)
DS261PP5
DS261F1
DS261PP5
the CLKE pin determines the clock polarity where
the output data is stable and valid as shown in
Table 2. During Host mode operation, the polarity
is established by the CLKE bit in the Control A register. When CLKE is low, RPOS and RNEG (or
RDATA) are valid on the rising edge of RCLK.
When CLKE is high, RPOS and RNEG (or RDATA) are valid on the falling edge of RCLK
During Host mode operation, the data at RPOS and
RNEG (or RDATA) may be forced to output an unframed all-ones pattern by setting both the
LLOOP1 and LLOOP2 bits in the Control B register to "1".
CLKE
DATA
LOW
RPOS, RNEG
or RDATA
RPOS, RNEG
or RDATA
HIGH
CLOCK Clock edge for
valid data
RCLK
Rising
RCLK
Rising
RCLK
Falling
RCLK
Falling
Table 2. Recovered Data/Clock Options
0
Minimum Attenuation Limit
Attenuation in dB
10
62411 Requirements
20
30
T1 Mode
40
Maximum
Attenuation
Limit
50
E1 Mode
60
1
10
Measured Performance
100
1k
10 k
Frequency in Hz
Figure 17. Typical Jitter Transfer Function
5. JITTER ATTENUATOR
The jitter attenuator can be switched into either the
receive or transmit paths. Alternatively, it can also
be removed from both paths to reduce the propagation delay. Figure 14 illustrates the typical jitter attenuation curves.
DS261PP5
DS261F1
CS61584A
During Hardware mode operation, the location of
the jitter attenuators for both channels is controlled
by the ATTEN0 and ATTEN1 pins. During Host
mode operation, the location of the jitter attenuators are independent and are controlled by the ATTEN[1:0] bits in the Control A registers. Table 3
shows how these pins are decoded.
The attenuator consists of a 64-bit FIFO, a narrowband monolithic PLL, and control logic. Signal jitter is absorbed in the FIFO which is designed to
neither overflow nor underflow. If overflow or underflow is imminent, the jitter transfer function is
altered to ensure that no bit-errors occur. Under this
condition, jitter gain may occur and external provisions may be required. The jitter attenuator will
typically tolerate 43 UIs before the overflow/underflow mechanism occurs. If the jitter attenuator
has not had time to "lock" to the average incoming
frequency (e.g. following a device reset) the attenuator will tolerate a minimum of 22 UIs before the
overflow/underflow mechanism occurs.
The jitter attenuator -3 dB knee frequency is 4.0 Hz
for T1 mode and 1.25 Hz for E1 mode as selected
by the CON[3:0] pins or register bits. A 1.25 Hz
knee for the E1 mode guarantees jitter attenuation
compliance to European specifications CTR 12 and
ETSI ETS 300 011. Setting ATTEN[1:0] = 11 will
place the jitter attenuator in the receive path with a
1.25 Hz knee for both T1 and E1 modes of operation.
For T1/E1 line cards used in high-speed mutiplexers (e.g., SONET and SDH), the jitter attenuator is
typically used in the transmit path. The attenuator
can accept a transmit clock with gaps ≤ 28 UIs and
a transmit clock burst rate of ≤ 8 MHz.
ATTEN1 ATTEN0
0
0
0
1
1
0
1
1
Location of Jitter Attenuator
Receiver
Disabled
Transmitter
Receiver w/ 1.25 Hz knee
Table 3. Jitter Attenuation Control
19
DS261PP5
6. REFERENCE CLOCK
The CS61584A requires a reference clock with a
minimum accuracy of ±100 ppm for T1 and E1 applications. This clock can be either a 1X clock (i.e.,
1.544 MHz or 2.048 MHz), or can be a 8X clock
(i.e., 12.352 MHz or 16.384 MHz) as selected by
the 1XCLK pin. This clock may be supplied from
internal system timing or a CMOS crystal oscillator
and input to the REFCLK pin. An 8X quartz crystal
may be connected across the REFCLK and XTALOUT pins and the 1XCLK pin set low. The quartz
crystal and CMOS crystal oscillator specifications
and are presented in the Applications section.
In systems with a jittered transmit clock, the reference clock should not be tied to the transmit clock
and a separate external quartz crystal or crystal oscillator should drive the reference clock input. Any
jitter present on the reference clock will not be filtered by the jitter attenuator.
7. POWER-UP RESET
On power-up, the device is held in a static state until the power supply achieves approximately 60%
of the power supply voltage. When this threshold is
crossed, the device waits another 10 ms to allow the
power supply to reach operating voltage and then
calibrates the transmit and receive circuitry. This
initial calibration takes less than 20 ms but can occur only if REFCLK and TCLK are present.
Power-up reset initializes the control logic and register set and performs the same functions as the RESET pin. During Host mode operation, a reset event
is indicated by the Latched-Reset bit in the Status
register.
8. LINE CONTROL AND MONITORING
Line control and monitoring of the CS61584A may
be implemented in either Hardware or Host mode.
Hardware mode is selected when the MODE pin is
set low and allows the device to be configured and
monitored using control pins. Host mode is selected when the MODE pin is set high and allows the
20
CS61584A
device to be configured and monitored using an internal register set.
The following controls and indications are available in Hardware mode: line length selection, receive clock edge, jitter attenuator location, loss of
signal, transmit all ones, local loopback, remote
loopback, and power down. Host mode operation
offers several additional control options (refer to
the Host Mode section).
Note:
Please refer to the Loop Selection Equations in
the Applications section.
8.1
Line Code Encoder/Decoder
Hardware mode supports only transparent operation to permit the line code to be encoded and decoded by an external T1/E1 framing device.
Recovered data is output on the RNEG and RPOS
pins in NRZ format and transmitted data is input on
the TNEG and TPOS pins.
Host mode supports transparent, AMI, B8ZS, or
HDB3 line encoding and decoding for applications
not using an external T1/E1 framer (i.e. multiplexers). The CODER, AMI-T, and AMI-R bits in the
Control A registers select the coder mode for a given channel. The selection of the transmit encoder is
independent from the selection of the receive decoder. When CODER = 1, the transmit data is input
to the encoder on TDATA and the receive data is
output from the decoder on RDATA in NRZ format.
8.2
Alarm Indication Signal
During Host mode operation, the alarm indication
signal (AIS) is detected by the receiver and reported using the AIS and Latched-AIS bits in the Status
registers. The receiver detects the AIS condition on
observation of 99.9% ones density in a 5.3 ms period (< 9 zeros in 8192 bits). If CODER = 1 in the
Control A registers, the TNEG pin becomes the
AIS output pin that is set high on detection of AIS.
The AIS condition is exited when ≥ 9 zeros are detected in 8192 bits.
DS261PP5
DS261F1
DS261PP5
8.3
Bipolar Violation Detection
During Host mode operation, a bipolar violation
(BPV) is detected by the receiver and reported using the Latched-BPV bit in the Status registers. If
CODER = 1 in the Control A registers, the RNEG
pin becomes the BPV output strobe pin that is set
high for one bit period on detection of a BPV. Note
that B8ZS (or HDB3) zero substitutions are not
flagged as bipolar violations if the B8ZS (or
HDB3) decoder has been enabled (CODER = 1 and
AMI-R = 0 in the Control A registers).
8.4
Excessive Zeros Detection
During Host mode operation if CODER = 1 and
EXZ = 1 in the Control A register, the BPV output
pin is OR’ed with receive excessive zero events. In
AMI mode when AMI-Rx = 1, the BPV pin is set
high for one bit period when 16 or more consecutive zeros are received. In B8ZS mode when AMIRx = 0, the BPV pin is set high for one bit period
when 8 or more consecutive zeros are received.
This is in accordance with the ANSI T1.231 specification. For E1 operation with HDB3 disabled, the
excessive zeros detection is also disabled. For E1
with HDB3 enabled the BPV pin goes high for every set of 4 consecutively received zeros.
8.5
Loss of Signal
During Hardware mode and Host mode operation,
the loss of signal (LOS) condition is detected by the
receiver and reported when the LOS pin is set high.
Loss of signal is indicated when 175 ±15 consecutive zeros are received, or when the receive
(RTIP/RRING) signal level drops below the receiver sensitivity of the device. The LOS condition is
exited according to the ANSI T1.231-1993 criteria
that requires a minimum 12.5% ones density signal
over 175 ±75 bit periods with no more than 100
consecutive zeros. During LOS, recovered data is
squelched and zeroes are output on RPOS/RNEG
(RDATA).
DS261PP5
DS261F1
CS61584A
During Host mode operation, LOS is reported using the LOS and Latched-LOS bits in the Status
registers. Note that both the LOS pin and register
indications are available in Host mode operation.
The LOS pin and/or bit is set high when the device
is reset, in power-up, or a channel is powered-down
and returns low when data is recovered by the receiver.
During LOS condition the RPOS (RDATA),
RNEG pins are forced low, except when LLOOP1
(digital loopback) is enabled, or when the AAO
(Automatic All Ones) bit is set in the channel 1
mask register. Setting the AAO bit high forces unframed all ones pattern out on the RPOS (RDATA), RNEG pins when LOS condition occurs.
When the jitter attenuator is in the receive path and
LOS occurs, the frequency of the last valid recovered signal is held at RCLK. When the jitter attenuator is not in the receive path, the output
frequency becomes the frequency of the reference
clock.
8.6
Transmit All Ones
During Hardware mode operation, transmit all ones
(TAOS) is selected by setting the TAOS pin high.
During Host mode, TAOS is controlled using the
TAOS bit in the Control B registers.
Selecting TAOS causes continuous ones to be
transmitted to the line on TTIP and TRING at the
frequency of REFCLK. In this mode, the transmit
data inputs TPOS and TNEG (or TDATA) are ignored. A TAOS request overrides the data transmitted to the line interface during local and remote
loopbacks. Note that the CLKLOST interrupt is
not available for TCLK in the TAOS mode.
8.7
Receive All Ones
During Host mode operation, the data at RPOS and
RNEG (or RDATA) may be forced to output an unframed all-ones pattern by setting both the
LLOOP1 and LLOOP2 bits in the Control B register to "1". An automatic Receive All Ones (AAO)
21
DS261PP5
response to a Loss of Signal condition for either
channel is activated by setting bit 1 of the channel
1 Mask register to 1.
8.8
Local Loopback
Selecting LLOOP causes the TCLK, TPOS, and
TNEG (or TDATA) inputs to be looped back
through the jitter attenuator (if enabled) to the
RCLK, RPOS, and RNEG (or RDATA) outputs.
The receive line interface is ignored, but data at
TPOS and TNEG (or TDATA) continues to be
transmitted to the line interface at TTIP and
TRING. During Hardware mode operation, simultaneous local loopback 2 of both channels is selected by setting the LLOOP pin high. During Host
mode operation, local loopback 1 on a per channel
basis is controlled using the LLOOP1 bit in the
Control B registers.
During Hardware mode operation, a per channel local loopback 1 is performed when both the RLOOP
and TAOS pins are high. The data at TPOS and
TNEG is overridden with an all-ones pattern (TAOS)
and the receive input at RTIP and RRING is ignored.
During Host mode operation, local loopback 2 can
also be selected using the LLOOP2 bit in the Control
B registers. Selecting LLOOP2 causes the TCLK,
TPOS, and TNEG (or TDATA) inputs to be looped
back to the RCLK, RPOS, and RNEG (or RDATA)
outputs. The line driver, line receiver, and jitter attenuator (if enabled) are also included. The receive
line interface is ignored, but data at TPOS and
TNEG (or TDATA) continues to be transmitted to
the line interface at TTIP and TRING.
A TAOS request overrides the data transmitted to
the line interface during both local loopbacks. A
TAOS request also overrides the data received at
RPOS and RNEG (or RDATA) during local loopback 2. Note that simultaneous selection of local
and remote loopback modes is not valid.
22
8.9
CS61584A
Remote Loopback
During Hardware mode operation, remote loopbacks of either channel is selected by setting the
RLOOP pin high. During Host mode operation, remote loopback of each channel is controlled using
the RLOOP bit in the Control B registers.
Selecting RLOOP causes the data received from
the line interface at RTIP and RRING to be looped
back through the jitter attenuator (if enabled) and
retransmitted on TTIP and TRING. Data input to
TPOS and TNEG (or TDATA) is ignored, but data
recovered from RTIP and RRING continues to be
output on RPOS and RNEG (or RDATA).
Remote loopback is functional if TCLK is absent.
A TAOS request overrides the data transmitted to
the line interface during a remote loopback. Note
that simultaneous selection of local and remote
loopback modes is not valid.
8.10
Driver Tristate
The drivers may be independently tristated in all
modes of operation. During Hardware mode operation, setting the CON[3:0] pins of a channel to
"111X" will tristate the driver. During Host mode serial port operation, the ZTX1 and ZTX2 pins perform
the driver tristate function and setting the CON[3:0]
bits in the Control B registers to "111X" will also
tristate the driver. During Host mode parallel port operation, setting the CON[3:0] bits in the Control B
register to "111X" tristates the driver. In host mode,
the CS61584A powers up with CON[3:0] set to
1110, which tristates the transmitter.
8.11
Power Down
During Hardware mode operation, channel power
down is selected by setting the PD1 or PD2 pin
high. During Host mode operation, channel power
down is controlled using the PD bit in the Control
A registers. Power down places the transmitter, receiver, and jitter attenuator in reset. The RCLK,
RPOS, RNEG, RDATA, AIS, BPV, TTIP, and
TRING output pins are placed in a high-impedance
DS261PP5
DS261F1
DS261PP5
CS61584A
state. LOS will go high, and the status register will
be reset, but the Control, Mask, and Arbitrary
Waveform registers remain unchanged. The channel not in power down and the processor port will
still to operate normally.
lished by the SAD[7:4] pins. The four least
significant bits of the address specify the register
address in the range of 0x00 to 0x09 for the selected
device. Parallel port option is compatible with Motorola and Intel 8-bit, multiplexed address/data bus.
Simultaneously selecting PD1 and PD2 will place
all the above-mentioned pins in high impedance
state and power down additional analog circuitry
that is shared by both channels. The status registers
are reset. In the hardware mode all output pins are
tri-stated and internally pulled up to the positive
supply rail. After exiting the power down state, the
channel will be fully operational in less than 20 ms.
9.1
8.12
Reset Pin
The CS61584A is continuously calibrated during
operation to insure the performance of the device
over power supply and temperature. This continuous calibration function eliminates the need to reset
the line interface during operation.
During Hardware and Host modes of operation, a
device reset is selected by setting the RESET pin
high for a minimum of 200 ns. The reset function
initiates on the falling edge of RESET and requires
less than 20 ms to complete. The control logic and
register set are initialized and the transmit and receive circuitry is calibrated if REFCLK and TCLK
are present. During Host mode operation, a reset
event is indicated by the Latched-Reset bit in the
Status register.
9. HOST MODE
Host mode allows the CS61584A to be configured
and monitored using an internal register set. This
option is selected when the MODE pin is set high.
Using the P/S pin, serial or 8-bit parallel interface
ports are available in Host mode. During serial port
operation, the registers are specified by a 6-bit address in the range of 0x10 to 0x19. During parallel
port operation, the registers are specified by an 8bit address. The four most significant bits of the address selects one of 16 devices on the board, estabDS261PP5
DS261F1
Register Set
The register set available during Host mode operation is presented in Table 4.
Serial Port Parallel Port
Address
Address*
0x10
0xY0
0x11
0xY1
0x12
0xY2
0x13
0xY3
0x14
0xY4
0x15
0xY5
0x16
0xY6
0x17
0xY7
0x18
0xY8
0x19
0xY9
Description
Ch 1 Status
Ch 2 Status
Ch 1 Mask
Ch 2 Mask
Ch 1 Control A
Ch 2 Control A
Ch 1 Control B
Ch 2 Control B
Ch 1 Arbitrary Pulse Shape
Ch 2 Arbitrary Pulse Shape
*Y denotes the SAD[7:4] address of the CS61584A device.
Table 4. CS61584A Register Set
9.1.1
Status Registers
The Status registers are read-only registers and are
shown in Table 5. The CS61584A generates an interrupt on the INT pin any time an unmasked Status
register bit changes. When BTS is low (Intel
mode), the IPOL pin determines the polarity of the
INT pin. When BTS is high (Motorola mode), INT
polarity is active low (IPOL becomes DTACK).
Reading both Status register clears the interrupt
and deactivates the INT pin.
LOS: Set high while the loss of signal condition is
detected. Reading the Status register does not clear
the LOS bit. A LOS interrupt is generated only on
the falling edge of the LOS alarm condition. The
Latched-LOS bit generates an interrupt on the rising edge of LOS. Refer to the timing diagram in
Figure 18.
23
DS261PP5
Latched-LOS: Set high on the rising edge of the
loss of signal condition. Reading the Status register
clears the Latched-LOS bit and deactivates the INT
pin. Refer to the timing diagram in Figure 18.
AIS: Set high while the alarm indication signal is
detected. Reading the Status register does not clear
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
CS61584A
the AIS bit. An AIS interrupt is generated only on
the falling edge of the AIS alarm condition. The
Latched-AIS bit generates an interrupt on the rising
edge of AIS. Refer to the timing diagram in
Figure 18.
Status Register (Channel 1)
Serial Port Address: 0x10; Parallel Port Address: 0xY0
Description
Definition
1
0
LOS1
LOS currently detected
no LOS
Latched-LOS1
LOS event since last read
no LOS
AIS1
AIS currently detected
no AIS
Latched-AIS1
AIS event since last read
no AIS
Latched-BPV1
BPV event since last read
no BPV
Latched-Overflow1 Pulse overflow since last read
no overflow
Latched-Reset
Reset event since last read
no reset
Interrupt1
Interrupt event since last read
no interrupt
Status Register (Channel 2)
Serial Port Address: 0x11; Parallel Port Address: 0xY1
Description
Definition
1
0
LOS2
LOS currently detected
no LOS
Latched-LOS2
LOS event since last read
no LOS
AIS2
AIS currently detected
no AIS
Latched-AIS2
AIS event since last read
no AIS
Latched-BPV2
BPV event since last read
no BPV
Latched-Overflow2 Pulse overflow since last read
no overflow
Latched-CLKLOST TCLK or REFCLK absent
TCLK and REFCLK present
Interrupt2
Interrupt event since last read
no interrupt
Reset
Value
1
1
0
0
0
0
1
1
Reset
Value
1
1
0
0
0
0
0
1
Table 5. Status Registers
AIS/LOS Currently Active
(AIS/LOS bit & AIS/LOS pin)
Latched LOS
(Latch AIS/LOS bit)
"Short" AIS/LOS event
Cleared by read
Set by start
of AIS/LOS
Interrupt
(INT)
Read AIS/LOS bits
"Long" AIS/LOS event
Cleared by read
Set by Change
of AIS/LOS
Figure 18. Alarm Indication Event Relationships
24
DS261PP5
DS261F1
DS261PP5
Latched-AIS: Set high on the rising edge of the
alarm indication signal condition. Reading the Status register clears the Latched-AIS bit and deactivates the INT pin. Refer to the timing diagram in
Figure 18.
Latched-BPV: Indicates a bipolar violation has
been received since the last read of the Status register. Reading the Status register clears the
Latched-BPV bit and deactivates the INT pin. This
bit is set only when the line code decoder is enabled
in the Control A register.
Latched-Overflow: Indicates a waveform generated using the Arbitrary Waveform register has exceeded full scale since the last read of the Status
register. Reading the Status register clears the
Latched-Overflow bit and deactivates the INT pin.
Latched-Reset: Indicates a reset event (power-up or
RESET pin) has occurred since the last read of the
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
CS61584A
Status register. Reading the Status register clears
the Latched-Reset bit and deactivates the INT pin.
This bit is not maskable.
Latched-CLKLOST: Set high when TCLK or REFCLK are absent. Reading the Status register clears
the Latched-CLKLOST bit and deactivates the INT
pin.
Interrupt: Indicates a change in the Status register
since the last read. Reading the Status register
clears the Interrupt bit and deactivates the INT pin.
9.1.2
Mask Registers
The Mask registers are read-write registers and are
shown in Table 6. The Mask registers disables the
interrupts in the corresponding Status register on a
per-bit basis. Masking a Status register bit forces it
to remain at zero and prevents the INT pin from activating on the condition.
Mask Register (Channel 1)
Serial Port Address: 0x12; Parallel Port Address: 0xY2
Description
Definition
1
0
Mask LOS1
Mask Interrupt
Enable Interrupt
Mask Latched-LOS1
Mask Interrupt
Enable Interrupt
Mask AIS1
Mask Interrupt
Enable Interrupt
Mask Latched-AIS1
Mask Interrupt
Enable Interrupt
Mask Latched-BPV1
Mask Interrupt
Enable Interrupt
Mask Latched-Overflow1 Mask Interrupt
Enable Interrupt
Automatic All Ones, AAO Ones at RPOS/NEG on LOS Zeros at RPOS/NEG on LOS
Mask Interrupt1
Mask Interrupt
Enable Interrupt
Mask Register (Channel 2)
Serial Port Address: 0x13; Parallel Port Address: 0xY3
Description
Definition
1
0
Mask LOS2
Mask Interrupt
Enable Interrupt
Mask Latched-LOS2
Mask Interrupt
Enable Interrupt
Mask AIS2
Mask Interrupt
Enable Interrupt
Mask Latched-AIS2
Mask Interrupt
Enable Interrupt
Mask Latched-BPV2
Mask Interrupt
Enable Interrupt
Mask Latched-Overflow2 Mask Interrupt
Enable Interrupt
Mask Latched-CLKLOST Mask Interrupt
Enable Interrupt
Mask Interrupt2
Mask Interrupt
Enable Interrupt
Reset
Value
0
0
0
0
0
0
0
0
Reset
Value
0
0
0
0
0
0
0
0
Table 6. Mask Registers
DS261PP5
DS261F1
25
DS261PP5
CS61584A
AAO: The Automatic All-Ones (AAO) bit in the
Mask Register (Channel 1, bit 1) causes an unframed all-ones pattern to be output at the RPOS
and RNEG (or RDATA) pins when the receiver is
in a loss of signal (LOS) condition.
CODER: Controls the coder mode function. The
TPOS, TNEG, RPOS, and RNEG pins are active
when the transparent mode is enabled. The TDATA, RDATA, AIS, and BPV pins are active when
the coder mode is enabled.
9.1.3
AMI-T: Controls the line encoder in the transmit
direction. The selection of B8ZS or HDB3 is determined by the CON[3:0] bits (See the Transmitter
section).
Control A Registers
The Control A registers are read-write registers and
are shown in Table 7. The Control A registers select device configuration and power down control.
PD: Controls per channel power down.
AMI-R: Controls the line decoder in the receive direction. The selection of B8ZS or HDB3 is determined by the CON[3:0] bits (See the Transmitter
section).
ATTEN0 and ATTEN1: Controls the jitter attenuator location and -3 dB knee frequency (See Jitter
Attenuator section).
EXZ: Controls the automatic detection of excessive
zeros on the BPV pin according to ANSI T1.231
when coder mode is enabled (CODERx = 1).
CLKE: Establishes the edge of the of RCLK that
RPOS and RNEG (or RDATA) are valid.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Control A Register (Channel 1)
Serial Port Address: 0x14; Parallel Port Address: 0xY4
Description
Definition
1
0
CLKE
RPOS/RNEG (or RDATA) valid on RPOS/RNEG (or RDATA) valid on
falling edge of RCLK
rising edge of RCLK
PD1
Power down channel
Power up channel
ATTEN01
Jitter attenuator location
(See Jitter Attenuator section)
ATTEN11
CODER1
Coder mode enabled
Transparent mode enabled
AMI-T1
AMI encoder enabled
B8ZS/HDB3 encoder enabled
AMI-R1
AMI decoder enabled
B8ZS/HDB3 decoder enabled
Factory Test
Test
Normal operation
Control A Register (Channel 2)
Serial Port Address: 0x15; Parallel Port Address: 0xY5
Description
Definition
1
0
EXZ
Excessive zeros detection for both Excessive zeros detection for both
channels enabled
channels disabled
PD2
Power down channel
Power up channel
ATTEN02
Jitter attenuator location
(See Jitter Attenuator section)
ATTEN12
CODER2
Coder mode enabled
Transparent mode enabled
AMI-T2
AMI encoder enabled
B8ZS/HDB3 encoder enabled
AMI-R2
AMI decoder enabled
B8ZS/HDB3 decoder enabled
Factory Test
Test
Normal operation
Reset
Value
0
0
0
0
0
0
0
0
Reset
Value
0
0
0
0
0
0
0
0
Table 7. Control A Registers
26
DS261PP5
DS261F1
DS261PP5
CS61584A
Factory Test: Must be cleared for normal device
operation.
LLOOP2 simultaneously causes all ones to be output from RPOS/RNEG (RDATA).
9.1.4
LLOOP2: Controls the local loopback #2 function
for the channel. Includes the line driver, line receiver, and jitter attenuator, if enabled. See LLOOP1,
above, for receive all ones function.
Control B Registers
The Control B registers are read-write registers and
are shown in Table 8. The Control B registers select
device configuration and loopback control.
TAOS: Controls the transmission of all ones to the
line interface. A TAOS request overrides the data
transmitted to the line interface during local and remote loopbacks.
CON[3:0]: Controls the configuration of the line
driver, line receiver, coder, and driver tristate as
shown in the Transmitter section. Both channels
must be configured to operate at the same rate (both
T1 or both E1).
RLOOP: Controls the remote loopback function for
the channel.
9.1.5
LLOOP1: Controls the local loopback #1 function
for the channel. Includes the jitter attenuator, if enabled. In host mode, selecting LLOOP1 and
In addition to the predefined T1 and E1 pulse
shapes, arbitrary pulse shapes may be created during Host mode operation using the registers shown
in Table 9. This flexibility can be used to compen-
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Arbitrary Waveform Registers
Control B Register (Channel 1)
Serial Port Address: 0x16; Parallel Port Address: 0xY6
Description
Definition
1
0
TAOS1
Enable transmit all ones
Disable transmit all ones
RLOOP1
Enable remote loopback
Disable remote loopback
LLOOP11
Enable local loopback #1
Disable local loopback #1
LLOOP21
Enable local loopback #2
Disable local loopback #2
CON31
Line configuration selections
(See Transmitter section)
CON21
CON11
CON01
Control B Register (Channel 2)
Serial Port Address: 0x17; Parallel Port Address: 0xY7
Description
Definition
1
0
TAOS2
Enable transmit all ones
Disable transmit all ones
RLOOP2
Enable remote loopback
Disable remote loopback
LLOOP12
Enable local loopback #1
Disable local loopback #1
LLOOP22
Enable local loopback #2
Disable local loopback #2
CON32
Line configuration selections
(See Transmitter section)
CON22
CON12
CON02
Reset
Value
0
0
0
0
1
1
1
0
Reset
Value
0
0
0
0
1
1
1
0
Table 8. Control B Registers
DS261PP5
DS261F1
27
DS261PP5
sate for waveform degradation that may result from
non-standard cables, transformers, or protection
circuitry.
Arbitrary waveform generation is enabled when the
CON[3:0] line configuration selection in the Control B register is set to one of four arbitrary waveform modes (See the Transmitter section). The
arbitrary pulse shape of mark (a transmitted "1") is
specified by describing the pulse shape across three
Unit Intervals (UIs). One UI in DS1 applications is
648 ns (1.544 MHz period) and one UI in E1 applications is 488 ns (2.048 MHz period). For example,
arbitrary waveform generation allows the DSX-1
return-to-zero "tail" to extend further into the next
UI or allows T1 long-haul waveforms to be defined
across all three UIs. The amplitude of a space (a
transmitted "0") is fixed at zero volts.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
CS61584A
All three UIs are divided into 14 equal phases for a
total of 42 phase segments. The shape of the pulse
is then defined by writing the amplitude of each
phase segment to the Arbitrary Waveform register
42 times in sequence from UI1/phase1 to
UI3/phase14. The custom pulse shape must be defined using the Arbitrary Waveform register before
setting the CON[3:0] configuration selection to one
of the arbitrary generation settings (i.e., 1001,
1010, or 1011).
For DS1 applications, the CS61584A divides the
648 ns UI into 14 equal phases of 46.3 ns. For
DSX-1 applications, the 648 ns UI is divided into
13 equal phases of 49.8 ns. The phase amplitude information written for phase 14 of each UI is ignored. For E1 applications, the 488 ns UI is divided
into 12 equal phases of 40.7 ns. The phase ampli-
Arbitrary Waveform Register (Channel 1)
Serial Port Address: 0x18; Parallel Port Address: 0xY8
Description
Definition
1
0
0
MSB
Arbitrary pulse shape definitions
Reset
Value
undefined
LSB
Arbitrary Waveform Register (Channel 2)
Serial Port Address: 0x19; Parallel Port Address: 0xY9
Description
Definition
1
0
0
MSB
Arbitrary pulse shape definitions
Reset
Value
undefined
LSB
Table 9. Arbitrary Waveform Registers
28
DS261PP5
DS261F1
DS261PP5
tude information written for phases 13 and 14 of
each UI is ignored. Examples of arbitrary waveforms are illustrated in Figure 19.
The amplitude of each phase segment is described
by a 7-bit, 2’s complement number (bit 8 is ignored). A positive value describes pulse amplitude
and a negative value describes pulse undershoot.
For DSX-1 applications with CON[3:0] = 1010, the
typical output voltage step is 73 mV/LSB across
the secondary (line side) of the transformer. For
DS1 applications with CON[3:0] = 1011, the typical output voltage step is 52 mV/LSB across the
transformer secondary. For E1 75 Ω coaxial applications with CON[3:0] = 1000, the typical output
voltage step is 43 mV/LSB. For E1 120 Ω twistedpair applications with CON[3:0] = 1001, the typical output voltage step is 52 mV/LSB.
CS61584A
The full scale positive value is 0x3F and the full
scale negative value is 0x40. It is recommended
that the output voltage across the secondary of the
transformer (line interface side) be limited to
4.4 Vpk. At higher output voltages, the transmitter
may not be able to drive the requested voltage
based on the current operating conditions.
Because the transmitter drives either a mark or a
space to the line interface every UI, the phase amplitude information defined in UI2 and UI3 is added to the symbols transmitted at TTIP and TRING
in those intervals. Therefore, a mark defined only
for UI1 will be output exactly as programmed if another mark is transmitted in the next two UI. However, a mark defined over UI1 and UI2 with an
extended return-to-zero "tail" will cause the leading edge of a mark transmitted in the next UI to rise
or fall more quickly. This is illustrated in Figure 20.
If the hexadecimal sum of the phase amplitudes exceeds the full scale values, the sum is replaced by
the full scale value and the Latched-Overflow bit is
set in the Status register.
E1 Arbitrary Waveform Example
DSX-1 (54% duty cycle) Arbitrary Waveform Example
DS-1 (50% duty cycle) Arbitrary Waveform Example
Figure 19. Phase Definition of Arbitrary Waveforms
DS261PP5
DS261F1
Figure 20. Example of Summing of Waveforms
29
DS261PP5
9.2
Serial Port Operation
Serial port operation in Host mode is selected when
the MODE pin is set high and the P/S pin is set low.
In this mode, the CS61584A register set is accessed
by setting the chip select (CS) pin low and communicating over the SDI, SDO, and SCLK pins. Timing over the serial port is independent of the
transmit and receive system timing. Figure 21 illustrates the format of serial port data transfers.
A read or write is initiated by writing an address/command byte (ACB) to SDI. During a read
cycle, the register data addressed by the ACB is
output on SDO on the next eight SCLK clock cycles. During a write cycle, the data byte immediately follows the ACB. A second address byte is
required when reading or writing the Arbitrary
Waveform registers (see below).
Data is written to and read from the serial port in
LSB first format. When writing to the port, SDI input data is sampled by the device on the rising edge
of SCLK. The polarity of the data output on SDO is
controlled by the SPOL pin. When the SPOL pin is
low, data on SDO is valid on the rising edge of
SCLK. When the SPOL pin is high, data on SDO is
valid on the falling edge of SCLK. The SDO pin is
CS61584A
high impedance when not transmitting data. If the
host processor has a bi-directional I/O port, SDI
and SDO may be tied together.
As illustrated in Figure 22, the ACB consists of a
R/W bit, address field, and two reserved bits. The
R/W bit specifies if the current register access is a
read (R/W = 1) or a write (R/W = 0) operation. The
address field specifies the register address from
0x10 to 0x19. The reserved bit must be cleared for
normal operation of serial mode.
During register addressing, the first eight registers
are addressed as 0x10 to 0x17 in the address field
of the ACB. Because Arbitrary Waveform registers
0x18 and 0x19 access multiple bytes of RAM,
reading or writing these registers requires an Address Command Byte followed by a RAM address
byte for each data transfer. The ACB specifies either 0x18 or 0x19 in the address field to access the
channel 1 or channel 2 Arbitrary Waveform register set. The RAM address is an 8-bit, unsigned binary number in the range of 0x00 to 0x29 to
identify one of 42 RAM locations. The data byte
containing the 7-bit, 2’s complement number specifying the phase amplitude completes the 24 SCLK
write cycle.
CS
SCLK
SDI
R/W
0
0
0
0
1
0
0
D0
D1
Data Input
D2
D3
D4
Data Output
D0
D1
D2
Address/Command Byte(s)
SDO
D3
D4
D5
D6
D5
D6
D7
D7
Figure 21. Serial Read/Write Format (SPOL = 0)
B7 (MSB)
Reserved
B6
Reserved
B5
ADR4
0
0
MSB
B4
ADR3
B3
ADR2
Address Field
B2
ADR1
B1
ADR0
LSB
B0
R/W
0 = Write
1 = Read
Figure 22. Address Command byte
30
DS261PP5
DS261F1
DS261PP5
9.3
Parallel Port Operation
Parallel port operation in Host mode is selected
when the MODE and P/S pins are set high. In this
mode, the CS61584A register set is accessed using
an 8-bit, multiplexed bi-directional address/data
bus AD[7:0]. Timing over the serial port is independent of the transmit and receive system timing.
The device is compatible with both Intel and Motorola bus formats. The Intel bus format is selected
when the BTS pin is low and the Motorola bus format is selected when the BTS pin is high. A read or
write is initiated by writing an address byte to
AD[7:0]. The device latches the address on the falling edge of ALE(AS). During a read cycle, the register data is output during the later portion of the
RD or DS pulses. The read cycle is terminated and
the bus returns to a high impedance state as RD
transitions high in Intel timing or DS transitions
low in Motorola timing. During a write cycle, valid
write data must be present and held stable during
the later portion of the WR or DS pulses. A second
address byte is required when reading or writing
the Arbitrary Waveform registers (see below).
A read or write over the parallel port is initiated by
writing an address byte to AD[7:0]. The address
byte consists of two nibbles. The four most significant bits AD[7:4] select one of 16 CS61584A devices in the application. This device address value
is established by the SAD[7:4] pins. The four least
significant bits AD[3:0] are the register address for
the selected device, ranging from 0x00 to 0x09.
The first eight device registers are addressed from
0x00 to 0x07 in the four least significant bits of the
address. Because Arbitrary Waveform registers
0x08 and 0x09 access multiple bytes of RAM,
reading or writing these registers requires an additional RAM address byte for each data transfer.
The RAM address is an 8-bit, unsigned binary
number in the range of 0x00 to 0x29 to identify one
of 42 RAM locations. The data byte containing the
7-bit, 2’s complement number specifying the phase
DS261PP5
DS261F1
CS61584A
amplitude completes a write cycle. The sequence
for writing to RAM is: first ALE(AS) addresses the
device, a second ALE(AS) addresses the RAM,
then a RD or WR (R/W) accesses the RAM data.
10. JTAG BOUNDARY SCAN
Board testing is supported through JTAG boundary
scan. Using boundary scan, the integrity of the digital paths between devices on a circuit board can be
verified. This verification is supported by the ability to externally set the signals on the digital output
pins of the CS61584A, and to externally read the
signals present on the input pins of the CS61584A.
Additionally, the manufacturer ID, part number
and revision of the device can be read during board
test using JTAG boundary scan.
As shown in Figure 23, the JTAG hardware consists of data and instruction registers plus a Test
Access Port (TAP) controller. Control of the TAP
is achieved through signals applied to the Test
Mode Select (J-TMS) and Test Clock (J-TCK) input pins. Data is shifted into the registers via the
Test Data Input (J-TDI) pin, and shifted out of the
registers via the Test Data Output (J-TDO) pin.
Both J-TDI and J-TDO are clocked at a rate determined by J-TCK. The Instruction register defines
which data register is accessed in the shift operation. Note that if J-TDI is floating, an internal pullup resistor forces the pin high.
Digital output pins
Digital input pins
parallel latched
output
JTAG Block
Boundary Scan Data Register
Device ID Data Register
J-TDI
MUX
J-TDO
Bypass Data Register
J-TCK
Instruction (shift) Register
parallel latched
output
J-TMS
TAP
Controller
Figure 23. JTAG Circuitry Block Diagram
31
DS261PP5
10.1
JTAG Data Registers (DR)
The test data registers are the Boundary-Scan Register (BSR), the Device Identification Register
(DIR), and the Bypass Register (BR).
Boundary Scan Register: The BSR is connected in
parallel to all the digital I/O pins, and provides the
mechanism for applying/reading test patterns
to/from the board traces. The BSR is 62 bits long
and is initialized and read using the instruction
SAMPLE/PRELOAD. The bit ordering for the
BSR is the same as the top-view package pin out,
beginning with the LOS1 pin and moving counterclockwise to end with the PD1 pin as shown in Table 10. Note that the analog, oscillator, power,
ground, CLKE/IPOL, and MODE pins are not included as part of the boundary-scan register.
The input pins require one bit in the BSR and only
one J-TCK cycle is required to load test data for
each input pin.
The output pins have two bits in the BSR to define
output high, output low, or high impedance. The
first bit (shifted in first) selects between an outputenabled state (bit set to 1) or high-impedance state
(bit set to 0). The second bit shifted in contains the
test data that may be output on the pin. Therefore,
two J-TCK cycles are required to load test data for
each output pin.
The bi-directional pins have three bits in the BSR
to define input, output high, output low, or high impedance. The first bit shifted into the BSR configures the output driver as high-impedance (bit set to
0) or active (bit set to 1). The second bit shifted into
the BSR sets the output value when the first bit is 1.
The third bit captures the value of the pin. This pin
may have its value set externally as an input (if the
first bit is 0) or set internally as an output (if the
first bit is 1). To configure a pad as an input, the JTDI pattern is 0X0. To configure a pad as an output, the J-TDI pattern is 1X1. Therefore, three JTCK cycles are required to load test data for each
bi-directional pin.
32
CS61584A
When JTAG testing is conducted in Host mode, the
polarity of the INT pin is determined by the state of
the IPOL pin. The JTAG BSR should configure the
INT pin as an input in Hardware mode and as an
output in Host mode.
Device Identification Register: The DIR provides
the manufacturer, part number, and version of the
CS61584A. This information can be used to verify
that the proper version or revision number has been
used in the system under test. The DIR is 32 bits
long and is partitioned as shown in Table 11. Data
from the DIR is shifted out to J-TDO LSB first.
BSR Bits
Pin Name
0-2
LOS1, SAD6
3-5
TNEG1, AIS1
6
TPOS1, TDATA1
7
TCLK1
8-9
RNEG1, BPV1
10 - 11
RPOS1, RDATA1
12 - 13
RCLK1
14
ATTEN1, CS
15 - 17
RLOOP1, INT
18
RLOOP2, SCLK, RD(DS)
19 - 21
LLOOP, SDO, AD0
22 - 24
TAOS1, SDI, AD1
25 - 27
TAOS2, SPOL, AD2
28 - 30
CON01, AD3
31 - 33
CON02, AD4
34 - 36
CON11, AD5
37 - 39
CON12, AD6
40 - 42
CON21, AD7
43
CON22, ALE(AS)
44
CON31, WR(R/W)
45 - 46
RCLK2
47 - 48
RPOS2, RDATA2
49 - 50
RNEG2, BPV2
51
TCLK2
52
TPOS2, TDATA2
53 - 55
TNEG2, AIS2
56 - 58
LOS2, SAD7
59
CON32, BTS
60
PD2, SAD5
61
PD1, SAD4
Pad Type
bi-directional
bi-directional
input
input
output
output
output
input
bi-directional
input
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
input
input
output
output
output
input
input
bi-directional
bi-directional
input
input
input
Table 10. Boundary Scan Register
DS261PP5
DS261F1
DS261PP5
MSB
LSB
31 28 27
12 11
10
00000110011011100001000011001001
4 bits
16 bits
11 bits
BIT #(s)
31-28
27-14
13-12
11-1
0
Function
Version Number
Part Number
Derivative Code
Manufacturer Number
Constant Logic ‘1’
Total Bits
4
14
2
11
1
Table 11. Device Identification Register
Bypass Register: The Bypass register consists of a
single bit, and provides a serial path between J-TDI
and J-TDO, bypassing the BSR. This allows bypassing specific devices during certain board-level
tests. This also reduces test access times by reducing the total number of shifts required from J-TDI
to J-TDO.
10.2
JTAG Instructions and Instruction
Register (IR)
The instruction register (2 bits) allows the instruction to be shifted into the JTAG circuit. The instruction selects the test to be performed or the data
register to be accessed or both. The valid instructions are shifted in LSB first and are listed in
Table 12:
IR CODE
00
01
10
11
INSTRUCTION
EXTEST
SAMPLE/PRELOAD
IDCODE
BYPASS
Table 12.
EXTEST Instruction: The EXTEST instruction allows testing of off-chip circuitry and board-level
interconnect. EXTEST connects the BSR to the JTDI and J-TDO pins. The normal path between the
CS61584A logic and I/O pins is broken. The signals on the output pins are loaded from the BSR
and the signals on the input pins are loaded into the
BSR.
DS261PP5
DS261F1
CS61584A
SAMPLE/PRELOAD Instruction: The SAMPLE/PRELOAD instructions allows scanning of
the boundary-scan register without interfering with
the operation of the CS61584A. This instruction
connects the BSR to the J-TDI and J-TDO pins.
The normal path between the CS61584A logic and
its I/O pins is maintained. The signals on the I/O
pins are loaded into the BSR. Additionally, this instruction can be used to latch values into the digital
output pins.
IDCODE Instruction: The IDCODE instruction
connects the device identification register to the JTDO pin. The IDCODE instruction is forced into
the instruction register during the Test-Logic-Reset
controller state.The default instruction is IDCODE
after a device reset.
BYPASS Instruction: The BYPASS instruction
connects the minimum length bypass register between the J-TDI and J-TDO pins and allows data to
be shifted in the Shift-DR controller state.
10.3
JTAG TAP Controller
Figure 24 shows the state diagram for the TAP state
machine. A description of each state follows. Note
that the figure contains two main branches to access either the data or instruction registers. The value shown next to each state transition in this figure
is the value present at J-TMS at each rising edge of
J-TCK.
10.4
Test-Logic-Reset State
In this state, the test logic is disabled to continue
normal operation of the device. During initialization, the CS61584A initializes the instruction register with the IDCODE instruction.
Regardless of the original state of the controller,
the controller enters the Test-Logic-Reset state
when the J-TMS input is held high for at least five
rising edges of J-TCK. The controller remains in
this state while J-TMS is high. The CS61584A processor automatically enters this state at power-up.
33
DS261PP5
10.5
Run-Test/Idle State
When the TAP controller is in this state and a rising
edge is applied to J-TCK, the controller enters the
Exit1-DR state if J-TMS is high or the Shift-DR
state if J-TMS is low.
This is a controller state between scan operations.
Once in this state, the controller remains in the state
as long as J-TMS is held low. The instruction register and all test data registers retain their previous
state. When J-TMS is high and a rising edge is applied to J-TCK, the controller moves to the SelectDR state.
10.6
10.8
Select-DR-Scan State
10.9
Exit1-DR State
This is a temporary state. While in this state, if JTMS is held high, a rising edge applied to J-TCK
causes the controller to enter the Update-DR state,
which terminates the scanning process. If J-TMS is
held low and a rising edge is applied to J-TCK, the
controller enters the Pause-DR state. The test data
register selected by the current instruction retains
its previous value and the instruction does not
change during this state.
Capture-DR State
In this state, the Boundary Scan Register captures
input pin data if the current instruction is EXTEST
or SAMPLE/PRELOAD. The instruction does not
change in this state. The other test data registers,
which do not have parallel input, are not changed.
1
Shift-DR State
In this controller state, the test data register connected between J-TDI and J-TDO as a result of the
current instruction shifts data on stage toward its
serial output on each rising edge of J-TCK. The instruction does not change in this state. When the
TAP controller is in this state and a rising edge is
applied to J-TCK, the controller enters the Exit1DR state if J-TMS is high or remains in the ShiftDR state if J-TMS is low.
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its
previous state. If J-TMS is held low and a rising
edge is applied to J-TCK when in this state, the
controller moves into the Capture-DR state and a
scan sequence for the selected test data register is
initiated. If J-TMS is held high and a rising edge
applied to J-TCK, the controller moves to the Select-IR-Scan state.
10.7
CS61584A
Test-Logic-Reset
0
1
0
Select-DR-Scan
Run-Test/Idle
1
Select-IR-Scan
0
1
0
Capture-IR
1
Capture-DR
0
0
Shift-DR
0
1
Shift-IR
1
Exit1-IR
0
0
Pause-DR
0
Pause-IR
0
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-IR
Update-DR
1
0
1
1
Exit1-DR
0
1
0
1
0
Figure 24. TAP Controller State Diagram
34
DS261PP5
DS261F1
DS261PP5
10.10 Pause-DR State
The pause state allows the test controller to temporarily halt the shifting of data through the test data
register in the serial path between J-TDI and JTDO. For example, this state could be used to allow the tester to reload its pin memory from disk
during application of a long test sequence. The test
data register selected by the current instruction retains its previous value and the instruction does not
change during this state. The controller remains in
this state as long as J-TMS is low. When J-TMS
goes high and a rising edge is applied to J-TCK, the
controller moves to the Exit2-DR state.
10.11 Exit2-DR State
This is a temporary state. While in this state, if JTMS is held high, a rising edge applied to J-TCK
causes the controller to enter the Update-DR state,
which terminates the scanning process. If J-TMS is
held low and a rising edge is applied to J-TCK, the
controller enters the Shift-DR state. The test data
register selected by the current instruction retains
its previous value and the instruction does not
change during this state.
10.12 Update-DR State
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the TAP
controller is in this state and the Boundary Scan
Register is selected, data is latched into the parallel
output of this register from the shift-register path
on the falling edge of J-TCK. The data held at the
latched parallel output changes only in this state.
All shift-register stages in the test data register selected by the current instruction retain their previ-
DS261PP5
DS261F1
CS61584A
ous value and the instruction does not change
during this state.
10.13 Select-IR-Scan State
This is a temporary controller state. The test data
register selected by the current instruction retains
its previous state. If J-TMS is held low and a rising
edge is applied to J-TCK when in this state, the
controller moves into the Capture-IR state, and a
scan sequence for the instruction register is initiated. If J-TMS is held high and a rising edge is applied to J-TCK, the controller moves to the TestLogic-Reset state. The instruction does not change
during this state.
10.14 Capture-IR State
In this controller state, the shift register contained
in the instruction register loads a fixed value of
"01" on the rising edge of J-TCK. This supports
fault-isolation of the board-level serial test data
path. Data registers selected by the current instruction retain their value and the instruction does not
change during this state. When the controller is in
this state and a rising edge is applied to J-TCK, the
controller enters the Exit1-IR state if J-TMS is held
high, or the Shift-IR state if J-TMS is held low.
10.15 Shift-IR State
In this state, the shift register contained in the instruction register is connected between J-TDI and
J-TDO and shifts data one stage towards its serial
output on each rising edge of J-TCK. The test data
register selected by the current instruction retains
its previous value and the instruction does not
change during this state. When the controller is in
this state and a rising edge is applied to J-TCK, the
controller enters the Exit1-IR state if J-TMS is held
high, or remains in the Shift-IR state if J-TMS is
held low.
35
DS261PP5
10.16 Exit1-IR State
This is a temporary state. While in this state, if JTMS is held high, a rising edge applied to J-TCK
causes the controller to enter the Update-IR state,
which terminates the scanning process. If J-TMS is
held low and a rising edge is applied to J-TCK, the
controller enters the Pause-IR state. The test data
register selected by the current instruction retains
its previous value and the instruction does not
change during this state.
10.17 Pause-IR State
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the
current instruction retains its previous value and
the instruction does not change during this state.
The controller remains in this state as long as JTMS is low. When J-TMS goes high and a rising
edge is applied to J-TCK, the controller moves to
the Exit2-IR state.
CS61584A
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
10.19 Update-IR State
The instruction shifted into the instruction register
is latched into the parallel output from the shift-register path on the falling edge of J-TCK. When the
new instruction has been latched, it becomes the
current instruction. The test data registers selected
by the current instruction retain their previous value.
10.20 JTAG Application Examples
Figures 25 and 26 illustrate examples of updating
the instruction and data registers during JTAG operation.
10.18 Exit2-IR State
This is a temporary state. While in this state, if JTMS is held high, a rising edge applied to J-TCK
causes the controller to enter the Update-IR state,
which terminates the scanning process. If J-TMS is
held low and a rising edge is applied to J-TCK, the
controller enters the Shift-IR state.
36
DS261PP5
DS261F1
DS261PP5
CS61584A
TCK
Run-Test/Idle
Exit1-IR
Update-IR
Shift-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Run-Test/Idle
Select-DR-Scan
Controller state
Test-Logic-Reset
TMS
TDI
Parallel Input to IR
IR shift-register
IDCODE
Parallel output of IR
New Instruction
Parallel Input to TDR
Parallel output of TDR
Old data
TDR shift-register
Instruction register
Register selected
TDO enable
Inactive
Act
Inactive
Active
Inactive
TDO
= Don’t care or undefined
Figure 25. JTAG Instruction Register update
DS261PP5
DS261F1
37
DS261PP5
CS61584A
TCK
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Exit1-DR
Update-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Controller state
Run-Test/Idle
TMS
TDI
Parallel Input to IR
IR shift-register
Instruction
Parallel output of IR
IDCODE
Parallel Input to TDR
TDR shift-register
Parallel output of TDR
Old data
Test data register
Register Selected
TDO enable
New data
Inactive
Active
Inactive
Active
Inactive
TDO
= Don’t care or undefined
Figure 26. JTAG Data Register update
38
DS261PP5
DS261F1
DS261PP5
CS61584A
11. PIN DESCRIPTIONS
Hardware Mode
Host Mode
Serial Port
DGND1
CON01
TAOS2
Host Mode
Parallel Port
DGND1
not used
SPOL
Hardware Mode
Host Mode
Serial Port
Host Mode
Parallel Port
DGND1
AD3
AD2
DV+
DGND3
CON02
DV+
DGND3
not used
DV+
DGND3
AD4
TAOS1
SDI
AD1
CON11
not used
AD5
LLOOP
SDO
AD0
CON12
not used
AD6
RLOOP2
SCLK
RD(DS)
CON21
not used
AD7
RLOOP1
INT
INT
CON22
not used
ALE(AS)
ATTEN1
CS
CS
CON31
not used
WR(R/W)
RCLK1
RCLK1
RCLK1
RCLK2
RCLK2
RCLK2
RPOS2
RNEG2
RPOS2(RDATA2) RPOS2(RDATA2)
RNEG2(BPV2)
RNEG2(BPV2)
RPOS1
RNEG1
RPOS1(RDATA1) RPOS1(RDATA1)
RNEG1(BPV1)
RNEG1(BPV1)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
TCLK2
TCLK2
TCLK2
TPOS1(TDATA1)
4
45
TPOS2
TPOS2(TDATA2)
TPOS2(TDATA2)
TNEG1(AIS1)
TNEG1(AIS1)
5
44
TNEG2
TNEG2(AIS2)
TNEG2(AIS2)
LOS1
LOS1
SAD6
LOS2
LOS2
SAD7
J-TDO
J-TDO
J-TDO
8
41
CON32
not used
BTS
DGND2
DGND2
DGND2
9
40
J-TCK
J-TCK
J-TCK
J-TDI
J-TDI
J-TDI
J-TMS
J-TMS
J-TMS
TTIP1
TTIP1
TTIP1
TV+1
TV+1
TV+1
TCLK1
TCLK1
TCLK1
TPOS1
TPOS1(TDATA1)
TNEG1
6
7
10
43
CS61584A
64-pin TQFP
Top View
42
39
11
38
12
37
TTIP2
TTIP2
TTIP2
TV+2
TV+2
TV+2
TGND2
TGND2
TGND2
TRING2
TRING2
TRING2
PD2
ZTX2
SAD5
CLKE
RTIP2
IPOL
RTIP2
IPOL/DTACK
RTIP2
RRING2
RRING2
RRING2
RV+2
RV+2
RV+2
13
36
14
35
15
34
16
33
TGND1
TGND1
TGND1
TRING1
TRING1
TRING1
PD1
ZTX1
SAD4
ATTEN0
RTIP1
P/S
RTIP1
P/S
RTIP1
RRING1
RRING1
RRING1
RV+1
RV+1
RV+1
RGND1
RGND1
RGND1
RGND2
RGND2
RGND2
MODE
MODE
MODE
1XCLK
1XCLK
1XCLK
BGREF
BGREF
BGREF
XTALOUT
XTALOUT
XTALOUT
AGND
AGND
AGND
REFCLK
REFCLK
REFCLK
AV+
AV+
AV+
RESET
RESET
RESET
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pins labeled as “not used” should be tied to ground.
Power Supplies
AGND - Analog Ground (PLCC pin 33; TQFP pin 23)
Analog supply ground pin.
AV+ - Analog Power Supply (PLCC pin 34; TQFP pin 24)
Analog supply pin for internal bandgap reference, oscillator, and timing generation circuits.
BGREF - Bandgap Reference (PLCC pin 32; TQFP pin 22)
This pin is used by the internal bandgap reference and must be connected to ground by a 4.99 kΩ ±1%
resistor to provide an internal current reference.
DGND1, DGND2, DGND3 - Digital Ground (PLCC pins 1, 18, 67; TQFP pins 57, 9, 55)
Power supply ground pins for the digital circuitry of both channels.
DV+ - Digital Power Supply (PLCC pin 68; TQFP pin 56)
Power supply pin for the digital circuitry of both channels.
DS261PP5
DS261F1
39
DS261PP5
Hardware Mode
Host Mode
Serial Port
CS61584A
Host Mode
Parallel Port
Host Mode
Serial Port
Hardware Mode
Host Mode
Parallel Port
DGND1
DGND1
DGND1
CON01
not used
AD3
DV+
DV+
DV+
TAOS2
TAOS1
SPOL
SDI
AD2
AD1
DGND3
CON02
DGND3
not used
DGND3
AD4
LLOOP
SDO
AD0
CON11
not used
AD5
RLOOP2
RLOOP1
SCLK
INT
RD(DS)
INT
CON12
CON21
not used
not used
AD6
AD7
ALE(AS)
ATTEN1
CS
CS
CON22
not used
not used
not used
not used
CON31
not used
WR(R/W)
RCLK1
RCLK1
RCLK1
not used
not used
not used
RPOS1 RPOS1(RDATA1)
RNEG1(BPV1)
RNEG1
RPOS1(RDATA1)
RNEG1(BPV1)
RCLK2
RPOS2
RCLK2
RCLK2
RPOS2(RDATA2) RPOS2(RDATA2)
RNEG2
RNEG2(BPV2)
RNEG2(BPV2)
TCLK2
TPOS2
TCLK2
TPOS2(TDATA2)
TCLK2
TPOS2(TDATA2)
TCLK1
TCLK1
TCLK1
TPOS1
TNEG1
TPOS1(TDATA1)
TNEG1(AIS1)
TPOS1(TDATA1)
TNEG1(AIS1)
9
15
DGND2
DGND2
18
19
TRING1
ZTX1
ATTEN0
P/S
P/S
not used
not used
not used
RTIP1
RRING1
RTIP1
RRING1
RV+1
RGND1
RV+1
RGND1
60
56
DGND2
PD1
1 68 67 66 65 64 63 62 61
14
17
TRING1
2
57
SAD6
TV+1
TGND1
3
59
J-TDO
TV+1
TGND1
4
58
LOS1
TV+1
TGND1
5
12
J-TDO
J-TDI
TTIP1
6
13
LOS1
J-TDI
TTIP1
7
11
J-TDO
J-TDI
TTIP1
8
10
16
20
55
CS61584A
68-pin PLCC
Top View
TNEG2
TNEG2(AIS2)
TNEG2(AIS2)
53
LOS2
LOS2
SAD7
52
CON32
not used
BTS
51
J-TCK
J-TMS
J-TCK
J-TMS
J-TCK
J-TMS
TTIP2
TV+2
TTIP2
TV+2
TTIP2
TV+2
54
50
49
21
22
48
23
47
24
46
TRING1
25
45
TGND2
TGND2
TGND2
SAD4
26
44
TRING2
TRING2
TRING2
PD2
ZTX2
SAD5
CLKE
IPOL
IPOL/DTACK
RTIP1
RRING1
not used
RTIP2
not used
RTIP2
not used
RV+1
RGND1
RRING2
RV+2
RRING2
RV+2
RRING2
RV+2
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
RTIP2
MODE
MODE
MODE
RGND2
RGND2
RGND2
BGREF
BGREF
BGREF
1XCLK
1XCLK
1XCLK
AGND
AGND
AGND
XTALOUT
XTALOUT
XTALOUT
AV+
AV+
AV+
REFCLK
REFCLK
REFCLK
RESET
RESET
RESET
Pins labeled as “not used” should be tied to ground.
RGND1, RGND2 - Receiver Ground (PLCC pins 30, 39; TQFP pins 20, 29)
Power supply ground pins for the receiver circuitry.
RV+1, RV+2 - Receiver Power Supply (PLCC pins 29, 40; TQFP pins 19, 30)
Power supply pins for the analog receiver circuitry.
TGND1, TGND2 - Transmit Ground (PLCC pins 22, 47; TQFP pins 13, 36)
Power supply ground pins for the transmitter circuitry.
TV+1, TV+2 - Transmit Power Supply (PLCC pins 21, 48; TQFP pins 12, 37)
Power supply pins for the analog transmitter circuitry.
40
DS261PP5
DS261F1
DS261PP5
CS61584A
T1/E1 Data Inputs and Outputs
RCLK1, RCLK2 - Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48)
RPOS1, RPOS2 - Receive Positive Data (PLCC pins 11, 58; TQFP pins 2, 47)
RNEG1, RNEG2 - Receive Negative Data (PLCC pins 12, 57; TQFP pins 3, 46)
The receiver recovered clock and NRZ digital data from RTIP and RRING is output on these pins.
During Hardware mode operation, the CLKE pin determines the clock edge on which RPOS and RNEG
are stable and valid. During Host mode operation, the CLKE bit in the Control A register determines the
clock edge on which RPOS and RNEG are stable and valid. A positive pulse (with respect to ground)
received on RTIP generates a logic 1 on RPOS, and a positive pulse received on RRING generates a
logic 1 on RNEG.
RDATA1, RDATA2 - Receive Data [Host mode] (PLCC pins 11, 58; TQFP pins 2, 47)
During Host mode operation with the coders enabled, the decoded digital data stream from RTIP and
RRING is output on RDATA in NRZ format. The CLKE bit in the Control A register determines the clock
edge on which RDATA is stable and valid.
RTIP1, RTIP2 - Receive Tip (PLCC pins 27, 42; TQFP pins 17, 32)
RRING1, RRING2 - Receive Ring (PLCC pins 28, 41; TQFP pins 18, 31)
The receive AMI signal from the line interface is input on these pins. The recovered clock and data are
output on RCLK, RPOS, and RNEG (or RDATA).
TCLK1, TCLK2 - Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45)
TPOS1, TPOS2 - Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)
TNEG1, TNEG2 - Transmit Negative Data (PLCC pins 15, 54; TQFP pins 6, 43)
The transmit clock and data are input to these pins. The signal is driven to the line interface at TTIP
and TRING. Data on TPOS and TNEG are sampled on the falling edge of TCLK. An input on TPOS
causes a positive pulse to be transmitted at TTIP and TRING, while an input on TNEG causes a
negative pulse to be transmitted at TTIP and TRING.
TDATA1, TDATA2 - Transmit Data [Host mode] (PLCC pins 14, 55; TQFP pins 5, 44)
During Host mode operation with the coders enabled, the un-encoded digital data stream is input on
TDATA in NRZ format. Data at TDATA is sampled on the falling edge of TCLK.
TTIP1, TTIP2 - Transmit Tip (PLCC pins 20,49; TQFP pins 11, 38)
TRING1, TRING2 - Transmit Ring (PLCC pins 23, 46; TQFP pins 14, 35)
The transmit AMI signal to the line interface is output on these pins. The transmit clock and data are
input on TCLK, TPOS, and TNEG (or TDATA).
Oscillator
1XCLK - One-times Clock Frequency Select (PLCC pin 38; TQFP pin 28)
When 1XCLK is high, REFCLK must be a 1X clock (i.e., 1.544 MHz for T1 applications or 2.048 MHz
for E1 applications). When 1XCLK is low, REFCLK must be an 8X clock (i.e., 12.352 MHz for T1
applications or 16.384 MHz for E1 applications).
DS261PP5
DS261F1
41
DS261PP5
CS61584A
REFCLK - External Reference Clock Input (PLCC pin 36; TQFP pin 26)
Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is high, REFCLK must
be a 1X clock (i.e., 1.544 MHz ±100 ppm for T1 applications or 2.048 MHz ±100 ppm for E1
applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352 MHz ±100 ppm for T1
applications or 16.384 MHz ±100 ppm for E1 applications). The REFCLK input also determines the
transmission rate when TAOS is asserted.
XTALOUT - Crystal Oscillator Output (PLCC pin 37; TQFP pin 27)
A quartz crystal with a resonant frequency of 12.352 MHz for T1 applications or 16.384 MHz for E1
applications may be connected across the XTALOUT and REFCLK pins instead of using a CMOS
compatible clock source. The 1XCLK pin must be set low to select 8X clock operation. This pin must
remain unconnected if a quartz crystal is not used.
Control
ATTEN0, ATTEN1 - Attenuator Select [Hardware Mode] (PLCC pins 25, 8; TQFP pins 16, 64)
Selects the jitter attenuator path and -3 dB knee point for both channels (transmit/receive/neither). See
Table 3.
CLKE - Clock Edge [Hardware mode] (PLCC pin 44; TQFP pin 33)
Controls the polarity of the recovered clock RCLK. When CLKE is high, RPOS and RNEG (or RDATA)
are valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG (or RDATA) are valid on
the rising edge of RCLK.
CON01, CON11 - Configuration Selection for Channel 1 [Hardware Mode]
CON21, CON31 - (PLCC pins 2, 65, 63, 61; TQFP pins 58, 53, 51, 49)
CON02, CON12 - Configuration Selection for Channel 2 [Hardware Mode]
CON22, CON32 - (PLCC pins 66, 64, 62, 52; TQFP pins 54, 52, 50, 41)
These pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver impedance),
receiver (slicing level), coder (HDB3 vs B8ZS), and driver tristate. The CONx1 pins control channel 1
and the CONx2 pins control channel 2. Both channels must be configured to operate at the same data
rate on the line interface (both T1 or both E1). The arbitrary waveform options are not available during
Hardware mode operation. See Table 1.
LLOOP - Local Loopback [Hardware Mode] (PLCC pin 5; TQFP pin 61)
A local loopback #2 of both channels is enabled when LLOOP is high. Selecting LLOOP causes the
TCLK, TPOS/TNEG (TDATA) inputs to be looped back through the transmitter, receiver and jitter
attenuator (if enabled) to the RCLK, RPOS/RNEG (RDATA) outputs. The data at TPOS/TNEG (TDATA)
continues to be transmitted to the line interface unless overridden by a TAOS request. The input on
RTIP and RRING is ignored.
When the RLOOP and TAOS pins are both high, the TCLK, TPOS/TNEG (TDATA) inputs are looped
back (local loopback #1) through the jitter attenuator (if enabled) to the RCLK, RPOS/RNEG (RDATA)
outputs for the selected channel. The data at TPOS/TNEG (TDATA) is also overridden with an all-ones
pattern (TAOS). The receive input at RTIP and RRING is ignored.
MODE - Mode Select (PLCC pin 31; TQFP pin 21)
Hardware mode operation is selected when MODE is low, enabling the device to be configured and
monitored using control pins. Host mode operation is selected when MODE is high, enabling the device
to be configured and monitored over a microprocessor interface using the internal register set.
42
DS261PP5
DS261F1
DS261PP5
CS61584A
PD1, PD2 - Power Down [Hardware mode] (PLCC pins 24, 45; TQFP pins 15, 34)
Setting PD high places the channel in a low power, inactive state. Power down forces the transmitter,
receiver, and jitter attenuator to the reset state. All device outputs are forced to a high impedance state
to facilitate circuit board testing.
ZTX1 - Driver Tristate [Host mode - serial port]
ZTX2 - (PLCC pins 24, 45; TQFP pins 15, 34)
Setting ZTX high causes the driver at TTIP and TRING to be placed in a tristate (high-impedance)
condition.
RESET - Reset (PLCC pin 35; TQFP pin 25)
A device reset is selected by setting the RESET pin high for a minimum of 200 ns. The reset function
requires less than 20 ms to complete. The control logic and register set are initialized and LOS is set
high. The RESET pin should be set low for normal operation.
RLOOP1, RLOOP2 - Remote Loopback [Hardware Mode] (PLCC pins 7, 6; TQFP pin 63, 62)
A remote loopback of the channel is selected when RLOOP is high. The data received from the line
interface at RTIP and RRING is looped back through the jitter attenuator (if enabled) and retransmitted
on TTIP and TRING. Data recovered from RTIP and RRING continues to be output on RPOS/RNEG
(RDATA). Data input on TPOS/TNEG (TDATA) is ignored.
When the RLOOP and TAOS pins are both high, local loopback #1 is invoked along with transmit all
ones for the selected channel. The receive input at RTIP and RRING is ignored.
TAOS1 - Transmit All Ones Select [Hardware Mode]
TAOS2 - (PLCC pins 4, 3; TQFP pins 60, 59)
Setting TAOS high causes continuous ones to be transmitted on the line interface at the frequency
determined by REFCLK.
When the RLOOP and TAOS pins are both high, local loopback #1 is invoked along with transmit all
ones for the selected channel. The receive input at RTIP and RRING is ignored.
Interface
AD7, AD6, AD5, AD4 - Address/Data Bus [Host mode - parallel port]
AD3, AD2, AD1, AD0 - (PLCC pins 63-66, 2-5; TQFP pins 51-54, 58-61)
The 8-bit, multiplexed address/data bus.
ALE (AS) - Address Latch Enable (Address Strobe) [Host mode - parallel port] (PLCC pin 62;
TQFP pin 50)
The address present on the address/data bus is latched on the falling edge of this signal.
BTS - Bus Type Select [Host mode - parallel port] (PLCC pin 52; TQFP pin 41)
This pin controls the function of the RD(DS), ALE(AS), and WR(R/W) pins. Intel bus timing is selected
when BTS is low. Motorola bus timing is selected when BTS is high and the pin function is listed in
parenthesis "( )".
CS - Chip Select [Host mode] (PLCC pin 8; TQFP pin 64)
This pin must be low in order to access the serial or parallel port of the device.
DS261PP5
DS261F1
43
DS261PP5
CS61584A
INT - Receive Alarm Interrupt [Host mode] (PLCC pin 7; TQFP pin 63)
An interrupt is generated to flag the host processor when a Status register changes state. The interrupt
is cleared by reading the Status register. The logic level for an active interrupt alarm is controlled by the
IPOL pin. The INT pin is an open drain output and must be tied to the appropriate supply through a
resistor.
IPOL - Interrupt Polarity [Host mode, BTS = 0] (PLCC pin 44; TQFP pin 33)
When BTS is low (Intel bus timing), the active polarity of the INT pin is controlled by IPOL. An active
high interrupt is generated when IPOL is high. An active low interrupt is generated when IPOL is low.
When the BTS pin is high, this pin becomes DTACK and INT is active low.
DTACK - Data Acknowledge [Host mode - parallel port, BTS = 1] (PLCC pin 44; TQFP pin 33)
When the BTS pin is high (Motorola bus timing), a low pulse on DTACK indicates when the CS61584A
has latched the data during a microprocessor write cycle or when the CS61584A has output data to the
bus during a microprocessor read cycle. The polarity of the INT pin is fixed to active low when the BTS
pin is high (Motorola bus timing).
P/S - Parallel/Serial Port Selection [Host modes] (PLCC pin 25; TQFP pin 16)
Selects the method of communication to the internal register set during Host mode operation. Serial port
communication over the SDI, SDO, and SCK pins is selected when P/S is low. Parallel port
communication over an 8-bit, multiplexed address/data bus is selected when P/S is high.
RD(DS) - Read Input (Data Strobe) [Host mode - parallel port] (PLCC pin 6; TQFP pin 62)
When the BTS pin is low (Intel bus timing), a low pulse on RD selects a read operation when the CS
pin is low. When the BTS pin is high (Motorola bus timing), a high pulse on DS performs a read/write
operation when the CS pin is low.
SAD4, SAD5 - Set Chip Address [Host mode - parallel port]
SAD6, SAD7 - (PLCC pins 24, 45, 16, 53; TQFP pins 15, 34, 7, 42)
These pins are hard-wired to establish one of 16 possible device addresses to permit a shared parallel
bus system architecture. The value is compared with the upper nibble of the address byte AD[7:4] as
part of the address decode procedure.
SCLK - Serial Clock [Host mode - serial port] (PLCC pin 6; TQFP pin 62)
Serial clock used to access the register set. A high or low level can be present on SCLK when the
device is selected using the CS pin.
SDI - Serial Data Input [Host mode - serial port] (PLCC pin 4; TQFP pin 60)
Serial data input to the register set. Sampled by the device on the rising edge of SCLK.
SDO - Serial Data Output [Host mode - serial port] (PLCC pin 5; TQFP pin 61)
Serial data output from the register set. If SPOL is low, SDO is valid on the rising edge of SCLK. If
SPOL is high, SDO is valid on the falling edge of SCLK. The SDO pin goes to a high-impedance state
while the serial port is being written or after bit D7 is output on SDO during a read.
SPOL - SDO Polarity Control [Host mode - serial port] (PLCC pin 3; TQFP pin 59)
Controls the polarity of the serial data output SDO. If SPOL is low, SDO is valid on the rising edge of
SCLK. If SPOL is high, SDO is valid on the falling edge of SCLK.
WR(R/W) - Write Input (Read/Write) [Host mode - parallel port] (PLCC pin 61; TQFP pin 49)
When the BTS pin is low (Intel bus timing), a low pulse on WR selects a write operation when the CS
pin is low. When the BTS pin is high (Motorola bus timing), a high pulse on R/W selects a read
operation and a low pulse on R/W selects a write operation when the CS pin is low.
44
DS261PP5
DS261F1
DS261PP5
CS61584A
Status
AIS1, AIS2 - Alarm Indication Signal [Host mode] (PLCC pins 15, 54; TQFP pins 6, 43)
The AIS indication goes high when the receiver detects 99.9% ones density in a 5.3 ms period (< 9
zeros in 8192 bits). The AIS indication returns low when the receiver detects ≥ 9 zeros in 8192 bits.
BPV1, BPV2 - Bipolar Violation [Host mode] (PLCC pins 12, 57; TQFP pins 3, 46)
The BPV indication goes high for one RCLK bit period when a bipolar violation is detected in the
received signal. Bipolar violations caused by B8ZS (or HDB3) zero substitutions are not flagged by the
BPV pin if the coder mode is enabled.
The BPV pin also goes high for one RCLK bit period on excessive zero events if EXZ = 1 (Control A
register, channel 2). In AMI mode, the BPV pin goes high when 16 or more zeros are received. In B8ZS
mode, the BPV pin goes high when 8 or more zeros are received. This functionality is disabled when
the device is configured for E1 operation.
LOS1 - Loss of Signal [Hardware mode and Host mode - serial port]
LOS2 - (PLCC pins 16, 53; TQFP pins 7, 42)
The LOS indication goes high when 175 ±15 consecutive zeros are received on the line interface, or
when the receive (RTIP/RRING) signal level drop below the receiver sensitivity of the device. The LOS
indication returns low when a minimum 12.5% ones density signal over 175 ±75 bit periods with no
more than 100 consecutive zeros is received.
Test
J-TCK - JTAG Test Clock (PLCC pin 51; TQFP pin 40)
Data on pins J-TDI and J-TDO is valid on the rising edge of J-TCK. When J-TCK is stopped low, all
JTAG registers remain unchanged.
J-TMS - JTAG Test Mode Select (PLCC pin 50; TQFP pin 39)
An active high signal on J-TMS enables the JTAG serial port. This pin has an internal pull-up resistor
and may be unconnected to float high or tied low while the JTAG interface is not active.
J-TDI - JTAG Test Data In (PLCC pin 19; TQFP pin 10)
JTAG data is shifted into the device on this pin. This pin has an internal pull-up resistor. Data must be
stable on the rising edge of J-TCK.
J-TDO - JTAG Test Data Out (PLCC pin 17; TQFP pin 8)
JTAG data is shifted out of the device on this pin. This pin is active only when JTAG testing is in
progress. J-TDO will be updated on the falling edge of J-TCK.
DS261PP5
DS261F1
45
DS261PP5
CS61584A
12. PACKAGE DIMENSIONS
64L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.461
0.390
0.461
0.390
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
0.55
0.004
0.008
0.472 BSC
0.393 BSC
0.472 BSC
0.393 BSC
0.020 BSC
0.024
4°
MAX
0.063
0.006
0.011
0.484
0.398
0.484
0.398
0.024
0.030
7.000°
MIN
--0.05
0.17
11.70
9.90
11.70
9.90
0.40
0.45
0.00°
MILLIMETERS
NOM
1.40
0.10
0.20
12.0 BSC
10.0 BSC
12.0 BSC
10.0 BSC
0.50 BSC
0.60
4°
MAX
1.60
0.15
0.27
12.30
10.10
12.30
10.10
0.60
0.75
7.00°
Controlling dimension is mm.
JEDEC Designation: MS022
46
DS261PP5
DS261F1
DS261PP5
CS61584A
68L PLCC PACKAGE DRAWING
e
D2/E2
E1 E
B
A1
D1
D
DIM
A
A1
B
D
D1
D2
E
E1
E2
e
MIN
0.165
0.090
0.013
0.985
0.950
0.890
0.985
0.950
0.890
0.040
INCHES
NOM
0.1825
0.105
0.017
0.990
0.953
0.910
0.990
0.953
0.910
0.050
A
MAX
0.200
0.130
0.021
0.995
0.958
0.930
0.995
0.958
0.930
0.060
MIN
4.191
2.286
0.3302
25.019
24.13
22.606
25.019
24.13
22.606
1.016
MILLIMETERS
NOM
4.6355
2.667
0.4318
25.146
24.206
23.114
25.146
24.206
23.114
1.270
MAX
5.08
3.302
0.533
25.273
24.333
23.622
25.273
24.333
23.622
1.524
JEDEC #: MS-047
DS261PP5
DS261F1
47
DS261PP5
CS61584A
13. APPLICATIONS
2
2
MODE RESET PD[1:2] CLKE
REFCLK 1XCLK
2
2
3
2
3
ATTEN[0:1] RLOOP[1:2] LLOOP TAOS[1:2] CON[0:2]1 CON[0:2]2 LOS[1:2]
Hardware Control
Clock Generator
T1 1:N
TTIP1
TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
RNEG1
Framer
0.47µ F
TRING1
Channel 1
RTIP1
R1
transmit
T2 1:N
0.47µ F
receive
RRING1
TTIP2
TCLK2
TPOS2
TNEG2
RCLK2
RPOS2
RNEG2
Framer
C1
R2
0.47µ F
TRING2
RTIP2
Channel 2
T3 1:N
C2
R3
transmit
T4 1:N
0.47µ F
receive
RRING2
AV+
AGND
0.1 µ F
VCC
Power Supply
BGREF TGND2 TV+2 TV+1 TGND1 RGND2
+
R3
4.99kΩ 0.1 µ F
0.1 µ F
R4
RV+2 RV+1 RGND1 DV+ DGND1:3
3
0.1 µ F
0.1 µ F
0.01 µ F
+
22 µ F
1 µF
Figure 27. Hardware Mode Configuration
Device Suffix
Data Rate
(MHz)
-IL3 and -IQ3 (3.3 Volts)
1.544
2.048
-IL5 and -IQ5 (5.0 Volts)
1.544
2.048
REFCLK Frequency (MHz)
1XCLK = 1
1XCLK = 0
1.544
12.352
2.048
16.384
1.544
2.048
Transformer
Turns Ratio
12.352
16.384
1:2
1:1.15
Cable R1-R4 C1-C2
(Ω)
(Ω)
(pF)
100
75
120
100
75
120
12.4
9.31
15.0
38.3
28.7
45.3
560
2200
560
220
470
220
Table 13. CS61584A External Components
13.1
Line Interface
Figures 27-29 illustrate typical connection diagram
for T1 and E1 line interface circuits in Hardware,
Host serial port, and Host parallel port modes. Table 13 lists the external components that are required in T1 and E1 applications for both the 5.0
and 3.3 Volt devices.
In the transmit line interface circuitry, capacitors
C1 and C2 provide transmitter return loss. The
0.47 µF capacitor in series with the transformer pri48
mary prevents output stage imbalances from producing a DC current through the transformer that
might saturate the transformer and result in an output level offset.
In the receive line interface circuitry, resistors R1R4 provide receive impedance matching and receiver return loss. The 0.47 µF capacitor to ground
provides the necessary differential input voltage
reference for the receiver.
DS261PP5
DS261F1
DS261PP5
CS61584A
Vcc
2
REFCLK 1XCLK
2
MODE RESET ZTX[1:2] LOS[1:2]
P/S
IPOL
SPOL
CS
INT
SCLK
SDO
SDI
Host Control
Clock Generator
TTIP1
TCLK1
TPOS1 (TDATA1)
TNEG1 (AIS1)
RCLK1
RPOS1 (RDATA1)
RNEG1 (BPV1)
Framer
TRING1
Channel 1
RTIP1
C1
R1
transmit
T2 1:N
0.47µ F
receive
RRING1
TTIP2
TCLK2
TPOS2 (TDATA2)
TNEG2 (AIS2)
RCLK2
RPOS2 (RDATA2)
RNEG2 (BPV2)
Framer
T1 1:N
0.47µ F
TRING2
RTIP2
Channel 2
R2
0.47µ F
T3 1:N
C2
R3
transmit
T4 1:N
0.47µ F
receive
RRING2
R4
Power Supply
AV+
AGND BGREF TGND2 TV+2 TV+1 TGND1 RGND2 RV+2 RV+1 RGND1 DV+ DGND1:3
0.1 µ F
3
R3
0.1 µ F
4.99kΩ 0.1 µ F
0.1 µ F
0.1 µ F
0.01 µ F
+
+
1 µF
22 µ F
VCC
Figure 28. Host Mode Serial Port Configuration
Vcc
Vcc
7
REFCLK 1XCLK
Clock Generator
MODE
RESET
P/S DTACK
CS
INT
RD(DS) WR(R/W) ALE(AS)
BTS
AD[0:7]
4
SAD[4:7]
Host Control
T1 1:N
TTIP1
TCLK1
TPOS1 (TDATA1)
TNEG1 (AIS1)
RCLK1
RPOS1 (RDATA1)
RNEG1 (BPV1)
Framer
0.47µ F
TRING1
Channel 1
RTIP1
Framer
VCC
R1
transmit
T2 1:N
0.47µ F
receive
RRING1
TTIP2
TCLK2
TPOS2 (TDATA2)
TNEG2 (AIS2)
RCLK2
RPOS2 (RDATA2)
RNEG2 (BPV2)
C1
TRING2
Channel 2
RTIP2
R2
0.47µ F
T3 1:N
C2
R3
transmit
T4 1:N
0.47µ F
receive
RRING2
R4
Power Supply
AV+
AGND BGREF TGND2 TV+2 TV+1 TGND1 RGND2 RV+2 RV+1 RGND1 DV+ DGND1:3
0.1 µ F
3
R3
0.1 µ F
4.99kΩ 0.1 µ F
0.1 µ F
0.1 µ F
0.01 µ F
+
+
1 µF
22 µ F
Figure 29. Host Mode Parallel Port Configuration
DS261PP5
DS261F1
49
DS261PP5
13.2
Power Supply
As shown in Figure 27, the CS61584A operates
from a 3.3 Volt or 5.0 Volt supply. Separate power
and ground pins provide internal isolation. The best
way to configure the power supplies is to connect
all of the supply pins together at the device. The
various ground pins must not be more negative than
AGND. A 4.99 kΩ ±1% resistor must be connected
from BGREF to ground to provide an internal current reference.
De-coupling and filtering of the power supplies is
crucial for the proper operation of the analog circuits. A capacitor should be connected between
each supply and its respective ground. For capacitors smaller than 1 µF, use mylar or ceramic capacitors and place them as close as possible to their
respective power supply pins. Wire-wrap bread
boarding of the line interface is not recommended
because lead resistance and inductance defeat the
function of the de-coupling capacitors.
13.3
Quartz Crystal Specifications
When a reference clock signal is not available, a
quartz crystal operating at the 8X rate can be connected across the REFCLK and XTALOUT pins.
The crystal must be AT-cut and fundamental mode.
The minimum specifications are shown in
Table 14. Based on these specifications, quartz
crystals suggested for use with the CS61584A are
shown in Table 15.
13.4
Crystal Oscillator Specifications
When a reference clock signal is not available, a
CMOS crystal oscillator operating at either the 1X
or 8X rate can be connected at the REFCLK pin.
The oscillator must have a minimum symmetry of
40-60% and minimum stability of ±100 ppm for T1
and E1 applications. Based on these specifications,
crystal oscillators suggested for use with the
50
CS61584A
Parameter
T1 parallel resonant
frequency
E1 parallel resonant
frequency
Resonant frequency
error (CL = 20 pF)
Temperature drift
(over system limits)
Drive level
Series resistance
Shunt capacitance
Aging
Min
-
Typ
12.352
Max
-
Unit
MHz
-
16.384
-
MHz
-50
-
+50
ppm
-100
-
+100
ppm
-5
-
500
50
7
+5
µW
Ω
pF
ppm/yr
Table 14. Quartz Crystal Specifications
Manufacturer
M-tron
Part Number
397-316
522-372
SaRonix
SRX5769
SRX5772
SRX5770
SRX5773
Package Type
ATS-49
through-hole
ATSM-49
surface mount
HC-49S
through-hole
49SMLB
surface mount
NOTE: Frequency tolerances are ±32 ppm with a 40 to +85 °C operating temperature range.
Table 15. Suggested Quartz Crystals
Manufacturer
Comclok
CTS
M-tron
SaRonix
Part Number
CT31CH
CXO-65HG-5-I
MH26TAD
NTH250A
Contact Number
(800)333-9825
(815)786-8411
(800)762-8800
(800)227-8974
NOTE: Frequency tolerances are ±32 ppm with a 40 to +85 °C operating temperature range.
All are 8-pin DIP packages and can be tristated.
Table 16. Suggested Crystal Oscillators
DS261PP5
DS261F1
DS261PP5
13.5
Transformers
13.7
Recommended transformer specifications are
shown in Table 17. Based on these specifications,
the transformers recommended for use with the
CS61584A are listed in Table 18.
Turns ratio (-IL3 and IQ3)
Turns ratio (-IL5 and IQ5)
Primary inductance
Primary leakage
inductance
Secondary leakage
inductance
Interwinding capacitance
ET-constant
1:2 step-up transmit
1:2 step-down receive
1:1.15 step-up transmit
1:1.15 step-down receive
1.5 mH min at 772 kHz
0.3 µH max at 772 kHz
with secondary shorted
0.4 µH max at 772 kHz
18 pF max, primary to
secondary
16 V-µs min
Table 17. Transformer Specifications
13.6
Designing for AT&T 62411
For additional information on the requirements of
AT&T 62411 and the design of an appropriate system synchronizer, refer to the Crystal Semiconductor Application Notes "AT&T 62411 Design
Considerations - Jitter and Synchronization" and
"Jitter Testing Procedures for Compliance with
AT&T 62411."
DS261PP5
DS261F1
CS61584A
Line Protection
Secondary protection components can be added to
the line interface circuitry to provide lightning
surge and AC power-cross immunity. For additional information on the different electrical safety
standards and specific application circuit recommendations, refer to the Crystal Semiconductor
Application Note "Secondary Line Protection for
T1 and E1 Line Cards."
13.8
Loop Selection Equations
The following equations indicate the different
states that various inputs have to assume to invoke
the various loopback functions available in the device.
...... RLOOP1 =TAOS1.LLOOP.RLOOP1
...... RLOOP2 =TAOS2.LLOOP.RLOOP2
...... LLOOP11 =LLOOP2.RLOOP2.RLOOP1 +
...... ..............TAOS1.RLOOP1
...... LLOOP12 =LLOOP2.RLOOP2.RLOOP1 +
...... ..............TAOS2.RLOOP2
...... LLOOP21 =TAOS1.LLOOP2.(RLOOP1 +
RLOOP2)
...... LLOOP22 =TAOS2.LLOOP2.(RLOOP1 +
RLOOP2)
51
DS261PP5
Turns Ratio
1:2
(-IL3 and -IQ3)
Manufacturer
Halo
Pulse Engineering
Schott
Valor
1:1.15
(-IL5 and -IQ5)
Halo
Pulse Engineering
Schott
Valor
Part Number
TD08-1205A
TG26-1205N1
PE-65351
PE-65771
PE-65835
PE-65761
PE-65821
PE-65861
T1016
T1073
67129300
67115090
ST5095
ST5175T
TD38-1505A
PE-65388
PE-65770
PE-65838
PE-68674
PE-65870
T1016
T1072
67124840
ST5112
ST5171T
CS61584A
Package Type
1.5 kV through-hole, single
2 kV surface mount, dual
1.5 kV through-hole, single
1.5 kV through-hole, single extended temperature
3.0 kV through-hole, single extended temperature
1.5 kV surface mount, dual
1.5 kV surface mount, dual extended temperature
1.5 kV surface mount, dual
1.5 kV surface mount, quad
1.5 kV surface mount, octal
1.5 kV through-hole, single extended temperature
1.5 kV through-hole, dual extended temperature
1.5 kV surface mount, dual
1.5 kV surface mount, quad
1.5 kV through-hole, single
1.5 kV through-hole, single
1.5 kV through-hole, single extended temperature
3.0 kV through-hole, single extended temperature
1.5 kV surface mount, dual extended temperature
1.5 kV surface mount, dual
1.5 kV surface mount, quad
1.5 kV surface mount, octal
1.5 kV through-hole, single extended temperature
2.0 kV surface mount, dual
1.5 kV surface mount, quad
Table 18. Recommended Transformers
52
DS261PP5
DS261F1
CS61584A
ORDERING INFORMATION
Model
Operating
Voltage
CS61584A-IL3
3.3 V
CS61584A-IL5
5.0 V
Package
Temperature
68-pin PLCC
CS61584A-IQ3
-40 to +85 °C
3.3 V
CS61584A-IQ3Z (Lead Free)
64-pin LQFP
CS61584A-IQ5
5.0 V
CS61584A-IQ5Z (Lead Free)
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
3
7 Days
CS61584A-IL3
225 °C
CS61584A-IL5
CS61584A-IQ3
240 °C
CS61584A-IQ3Z (Lead Free)
250 °C
CS61584A-IQ5
240 °C
CS61584A-IQ5Z (Lead Free)
250 °C
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS261F1
53
CS61584A
REVISION HISTORY
Revision
Date
Changes
PP5
JAN 2001
Preliminary Release
F1
SEP 2005
Updated device ordering info. Updated legal notice. Added MSL data..
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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54
DS261F1