40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC AD5381 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down Package type: 100-lead LQFP (14 mm × 14 mm) User Interfaces: Parallel Serial (SPI®/QSPI™/MICROWIRE™/DSP compatible, featuring data readback) I2C® compatible Channel monitor Simultaneous output update via LDAC Clear function to user programmable code Amplifier boost mode to optimize slew rate User programmable offset and gain adjust Toggle mode enables square wave generation Thermal monitors APPLICATIONS Variable optical attenuators (VOA) Level setting (ATE) Optical micro-electro-mechanical systems (MEMs) Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×3) AVDD (×5) AGND (×5) DAC GND (×5) REFGND REFOUT/REFIN SIGNAL GND (×5) PD SER/PAR AD5381 1.25V/2.5V REFERENCE FIFO EN CS/(SYNC/AD 0) WR/(DCEN/AD 1) 12 SDO DB0 12 INTERFACE CONTROL LOGIC FIFO + STATE MACHINE + CONTROL LOGIC 12 12 DAC 12 REG 0 DAC 0 VOUT0 m REG 0 R c REG 0 R 12 INPUT 12 REG 1 12 A5 A0 12 12 DAC 12 REG 1 DAC 1 VOUT1 VOUT2 m REG 1 R c REG 1 VOUT4 12 REG 1 RESET VOUT3 R REG 0 POWER-ON RESET INPUT 12 REG 6 12 12 BUSY 12 DAC 12 REG 6 VOUT5 DAC 6 VOUT6 m REG 6 R c REG 6 R CLR VOUT 0………VOUT 38 12 INPUT 12 REG 7 12 39-TO-1 MUX 12 12 DAC 12 REG 7 DAC 7 VOUT7 VOUT8 m REG 7 R c REG 7 R VOUT38 ×5 VOUT 39/MON_OUT LDAC 03732-0-001 DB11/(DIN/SDA) DB10/(SCLK/SCL) DB9/(SPI/I2C) DB8 INPUT 12 REG 0 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD5381 TABLE OF CONTENTS General Description ......................................................................... 3 BUSY and LDAC Functions...................................................... 25 Specifications..................................................................................... 4 FIFO Operation in Parallel Mode ............................................ 25 AD5381-5 Specifications ............................................................. 4 Power-On Reset.......................................................................... 25 AD5381-3 Specifications ............................................................. 6 Power-Down ............................................................................... 25 AC Characteristics........................................................................ 7 AD5381 Interfaces.......................................................................... 26 Timing Characteristics..................................................................... 8 DSP, SPI, MICROWIRE Compatible Serial Interfaces .......... 26 Serial Interface Timing ................................................................ 8 I2C Serial Interface ..................................................................... 28 I2C Serial Interface Timing........................................................ 10 Parallel Interface......................................................................... 30 Parallel Interface Timing ........................................................... 11 Microprocessor Interfacing....................................................... 31 Absolute Maximum Ratings.......................................................... 13 Application Information................................................................ 33 Pin Configuration and Function Descriptions........................... 14 Power Supply Decoupling ......................................................... 33 Terminology .................................................................................... 17 Typical Configuration Circuit .................................................. 33 Typical Performance Characteristics ........................................... 18 AD5381 Monitor Function ....................................................... 34 Functional Description .................................................................. 21 Toggle Mode Function............................................................... 34 DAC Architecture—General..................................................... 21 Thermal Monitor Function....................................................... 34 On-Chip Special Function Registers (SFR) ............................ 22 Optical Attenuators .................................................................... 35 SFR Commands .......................................................................... 22 Utilizing the AD5381 FIFO....................................................... 35 Hardware Functions....................................................................... 25 Outline Dimensions ....................................................................... 36 Reset Function ............................................................................ 25 Ordering Guide .......................................................................... 36 Asynchronous Clear Function.................................................. 25 REVISION HISTORY 6/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Ordering Guide ...........................................................36 5/04—Revision 0: Initial Version Rev. A | Page 2 of 36 AD5381 GENERAL DESCRIPTION The AD5381 is a complete, single-supply, 40-channel, 12-bit DAC available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5381 includes a programmable internal 1.25 V/2.5 V, 10 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that allows optimization of the amplifier slew rate. The AD5381 contains a double-buffered parallel interface that features a 20 ns WR pulse width, an SPI/QSPI/MICROWIRE/DSP compatible serial interface with interface speeds in excess of 30 MHz, and an I2C compatible interface that supports a 400 kHz data transfer rate. An input register followed by a DAC register provides double buffering, allowing the DAC outputs to be updated independently or simultaneously using the LDAC input. Each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any DAC channel. Power consumption is typically 0.25 mA/channel with boost mode disabled. Table 1. Other Low Voltage Single-Supply DACs in Product Family Model AD5380BST-5 AD5380BST-3 AD5384BBC-5 AD5384BBC-3 AD5382BST-5 AD5382BST-3 AD5383BST-5 AD5383BST-3 AD5390BST-5 AD5390BCP-5 AD5390BST-3 AD5390BCP-3 AD5391BST-5 AD5391BCP-5 AD5391BST-3 AD5391BCP-3 AD5392BST-5 AD5392BCP-5 AD5392BST-3 AD5392BCP-3 Resolution 14 Bits 14 Bits 14 Bits 14 Bits 14 Bits 14 Bits 12 Bits 12 Bits 14 Bits 14 Bits 14 Bits 14 Bits 12 Bits 12 Bits 12 Bits 12 Bits 14 Bits 14 Bits 14 Bits 14 Bits AVDD Range 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V Output Channels 40 40 40 40 32 32 32 32 16 16 16 16 16 16 16 16 8 8 8 8 Linearity Error (LSB) ±4 ±4 ±4 ±4 ±4 ±4 ±1 ±1 ±3 ±3 ±3 ±3 ±1 ±1 ±1 ±1 ±3 ±3 ±3 ±3 Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead CSPBGA 100-Lead CSPBGA 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP Package Option ST-100 ST-100 BC-80 BC-80 ST-100 ST-100 ST-100 ST-100 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64 Table 2. 40-Channel, Bipolar Voltage Output DAC Model AD5379ABC Resolution 14 Bits Analog Supplies ±11.4 V to ±16.5 V Output Channels 40 Linearity Error ±3 Rev. A | Page 3 of 36 Package 108-Lead CSPBGA Package Option BC-108 AD5381 SPECIFICATIONS AD5381-5 SPECIFICATIONS Table 3. AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted Parameter ACCURACY Resolution Relative Accuracy2 (INL) Differential Nonlinearity (DNL) Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient3 DC Crosstalk3 REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output4 Output Voltage Reference TC OUTPUT CHARACTERISTICS3 Output Voltage Range2 Short-Circuit Current Load Current Capacitive Load Stability RL = ∞ RL = 5 kΩ DC Output Impedance MONITOR PIN Output Impedance Three-State Leakage Current LOGIC INPUTS (EXCEPT SDA/SCL)3 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection AD5381-51 Unit 12 ±1 ±1 ±4 ±4 ±5 ±0.024 ±0.06 2 0.5 Bits LSB max LSB max mV max mV max µV/°C typ % FSR max % FSR max ppm FSR/°C typ LSB max 2.5 1 ±10 1 to VDD/2 V MΩ min µA max V min/max Test Conditions/Comments Output unloaded 2.495/2.505 1.22/1.28 ±10 ±15 V min/max V min/max ppm/°C max ppm/°C max 0/AVDD 40 ±1 V min/max mA max mA max 200 1000 0.5 pF max pF max Ω max 500 100 Ω typ nA typ 2 0.8 ±10 10 V min V max µA max pF max 0.7 DVDD 0.3 DVDD ±1 0.05 DVDD 8 50 V min V max µA max V min pF typ ns max Guaranteed monotonic over temperature Measured at Code 32 in the linear region At 25 °C TMIN to TMAX ±1% for specified performance, AVDD = 2 × REFIN + 50 mV Typically 100 MΩ Typically ±30 nA Enabled via CR8 in the AD5381 control register. CR10 selects the reference voltage. At ambient. Optimized for 2.5 V operation. CR10 = 1. CR10 = 0 Temperature Range: +25°C to +85°C Temperature Range: –40°C to +85°C DVDD = 2.7 V to 5.5 V Total for all pins. TA = TMIN to TMAX. SMBus compatible at DVDD < 3.6 V SMBus compatible at DVDD < 3.6 V Input filtering suppresses noise spikes of less than 50 ns Rev. A | Page 4 of 36 AD5381 Parameter LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage AD5381-51 Unit Test Conditions/Comments 0.4 DVDD – 1 0.4 DVDD – 0.5 ±1 5 V max V min V max V min µA max pF typ DVDD = 5 V ± 10%, sinking 200 µA DVDD = 5 V ± 10%, sourcing 200 µA DVDD = 2.7 V to 3.6 V, sinking 200 µA DVDD = 2.7 V to 3.6 V, sourcing 200 µA SDO only SDO only V max V max µA max pF typ ISINK = 3 mA ISINK = 6 mA Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity3 ∆Midscale/∆ΑVDD AIDD 0.4 0.6 ±1 8 4.5/5.5 2.7/5.5 V min/max V min/max –85 0.375 0.475 1 2 20 80 dB typ mA/channel max mA/channel max mA max µA max µA max mW max DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation 1 Outputs unloaded, Boost off. 0.25 mA/channel typ. Outputs unloaded, Boost on. 0.325 mA /channel typ. VIH = DVDD, VIL = DGND Outputs unloaded, Boost off, AVDD = DVDD = 5 V AD5381-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5381-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5381 control register; operating the AD5381-5 with a 1.25 V reference will lead to degraded accuracy specifications. 2 Rev. A | Page 5 of 36 AD5381 AD5381-3 SPECIFICATIONS Table 4. AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted Parameter ACCURACY Resolution Relative Accuracy2 (INL) Differential Nonlinearity (DNL) Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient3 DC Crosstalk3 REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output4 Output Voltage Reference TC OUTPUT CHARACTERISTICS3 Output Voltage Range2 Short-Circuit Current Load Current Capacitive Load Stability RL = ∞ RL = 5 kΩ DC Output Impedance MONITOR PIN Output Impedance Three-State Leakage Current LOGIC INPUTS (EXCEPT SDA/SCL)3 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection AD5381-31 Unit 12 ±1 ±1 ±4 ±4 ±5 ±0.024 ±0.06 2 0.5 Bits LSB max LSB max mV max mV max µV/°C typ % FSR max % FSR max ppm FSR/°C typ LSB max 1.25 1 ±10 1 to AVDD/2 V MΩ min µA max V min/max 1.247/1.253 2.43/2.57 ±10 ±15 V min/max V min/max ppm/°C max ppm/°C max 0/AVDD 40 ±1 V min/max mA max mA max 200 1000 0.5 pF max pF max Ω max 500 100 Ω typ nA typ 2 0.8 ±10 10 V min V max µA max pF max 0.7 DVDD 0.3 DVDD ±1 0.05 DVDD 8 50 V min V max µA max V min pF typ ns max Test Conditions/Comments Output unloaded Guaranteed monotonic over temperature Measured at Code 64 in the linear region At 25 °C TMIN to TMAX ±1% for specified performance Typically 100 MΩ Typically ±30 nA Enabled via CR8 in the AD5381 control register. CR10 selects the reference voltage. At ambient. Optimized for 1.25 V operation. CR10 = 0. CR10 = 1 Temperature Range: +25°C to +85°C Temperature Range: –40°C to +85°C DVDD = 2.7 V to 3.6 V Rev. A | Page 6 of 36 Total for all pins. TA = TMIN to TMAX. SMBus compatible at DVDD< 3.6 V SMBus compatible at DVDD< 3.6 V Input filtering suppresses noise spikes of less than 50 ns AD5381 Parameter LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage AD5381-31 Unit Test Conditions/Comments 0.4 DVDD – 0.5 ±1 5 V max V min µA max pF typ Sinking 200 µA Sourcing 200 µA SDO only SDO only V max V max µA max pF typ ISINK = 3 mA ISINK = 6 mA Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity3 ∆Midscale/∆ΑVDD AIDD 0.4 0.6 ±1 8 2.7/3.6 2.7/5.5 V min/max V min/max –85 0.375 0.475 1 2 20 48 dB typ mA/channel max mA/channel max mA max µA max µA max mW max DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation Outputs unloaded, Boost off. 0.25 mA/channel typ Outputs unloaded, Boost on. 0.325 mA/channel typ VIH = DVDD, VIL = DGND Outputs unloaded, Boost off, AVDD = DVDD = 3 V 1 AD5381-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. Guaranteed by characterization, not production tested. 4 Default on the AD5381-3 is 1.25 V. Programmable to 2.5 V via cr10 in the AD5381 control register; operating the AD5381-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range. 2 3 AC CHARACTERISTICS1 Table 5. AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Slew Rate2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise 0.1 Hz to 10 Hz Output Noise Spectral Density @ 1 kHz @ 10 kHz 1 2 All Unit Test Conditions/Comments 6 8 2 3 12 15 100 1 0.8 0.1 15 40 µs typ µs max V/µs typ V/µs typ nV-s typ mV typ dB typ nV-s typ nV-s typ nV-s typ µV p-p typ µV p-p typ 150 100 nV/√Hz typ nV/√Hz typ 1/4 scale to 3/4 scale change settling to ±1 LSB. Boost mode off, CR9 = 0 Boost mode on, CR9 = 1 See Terminology section See Terminology section Effect of input bus activity on DAC output under test External reference, midscale loaded to DAC Internal reference, midscale loaded to DAC Guaranteed by design and characterization, not production tested. Slew rate can be programmed via the current boost control bit in the AD5381 control register. Rev. A | Page 7 of 36 AD5381 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING Table 6. DVDD= 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted Parameter1, 2, 3 t1 t2 t3 t4 t5 4 t6 4 t7 t7A t8 t9 t104 t11 t124 t13 t14 t15 t16 t17 t18 t19 t205 t215 t225 t23 Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.5 30 670 20 20 100 0 100 8 20 12 20 5 8 20 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns max ns min ns min µs typ ns min µs max ns max ns min ns min ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC falling edge Minimum SYNC low time Minimum SYNC high time Minimum SYNC high time in Readback mode Data setup time Data hold time 24th SCLK falling edge to BUSY falling edge BUSY pulse width low (single channel update) 24th SCLK falling edge to LDAC falling edge LDAC pulse width low BUSY rising edge to DAC output response time BUSY rising edge to LDAC falling edge LDAC falling edge to DAC output response time DAC output settling time CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SCLK falling edge to SYNC rising edge SYNC rising edge to SCLK rising edge SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V. See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. 2 3 IOL VOH (MIN) OR VOL (MAX) TO OUTPUT PIN CL 50pF 200µA IOH Figure 2. Load Circuit for Digital Output Timing Rev. A | Page 8 of 36 03731-0-003 200µA AD5381 t1 24 SCLK t3 t4 t2 24 t5 t6 SYNC t7 t8 t9 DB0 DIN DB23 t10 BUSY t11 t13 t12 t17 LDAC1 t14 VOUT1 t15 t13 LDAC2 t17 t16 VOUT2 t18 CLR 03731-0-004 VOUT t19 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t7A SYNC DB23 DIN DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB0 UNDEFINED 03731-0-005 DB23 SDO SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t1 SCLK 24 t7 t3 48 t2 t21 t22 t4 SYNC t8 t9 DIN DB23 DB0 DB23 INPUT WORD FOR DAC N DB0 INPUT WORD FOR DAC N+1 t20 UNDEFINED DB0 INPUT WORD FOR DAC N t23 LDAC Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. A | Page 9 of 36 t13 03731-0-006 DB23 SDO AD5381 I2C SERIAL INTERFACE TIMING Table 7. DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted Parameter1, 2 FSCL t1 t2 t3 t4 t5 t63 t7 t8 t9 t10 t11 Cb Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.1Cb 4 400 Unit kHz max µs min µs min µs min µs min ns min µs max µs min µs min µs min µs min ns max ns min ns max ns min ns max ns min pF max Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD,STA, start/repeated start condition hold time tSU,DAT, data setup time tHD,DAT, data hold time tHD,DAT, data hold time tSU,STA, setup time for repeated start tSU,STO, stop condition setup time tBUF, bus free time between a STOP and a START condition tR, rise time of SCL and SDA when receiving tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. See Figure 6. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3DVDD and 0.7DVDD. 2 SDA t9 t3 t10 t11 t4 SCL t6 t2 t1 t5 START CONDITION REPEATED START CONDITION Figure 6. I2C Compatible Serial Interface Timing Diagram Rev. A | Page 10 of 36 t8 t7 STOP CONDITION 03731-0-007 t4 AD5381 PARALLEL INTERFACE TIMING Table 8. DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted Parameter1,2,3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t94 t104 t114, 5 t12 t13 t14 t15 t16 t17 t18 t19 t20 Limit at TMIN, TMAX 4.5 4.5 20 20 0 0 4.5 4.5 20 700 30 670 30 20 100 20 0 100 8 20 12 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns max ns min ns min ns min µs typ ns min µsmax Description REG0, REG1, address to WR rising edge setup time REG0, REG1, address to WR rising edge hold time CS pulse width low WR pulse width low CS to WR falling edge setup time WR to CS rising edge hold time Data to WR rising edge setup time Data to WR rising edge hold time WR pulse width high Minimum WR cycle time (single-channel write) WR rising edge to BUSY falling edge BUSY pulse width low (single-channel update) WR rising edge to LDAC falling edge LDAC pulse width low BUSY rising edge to DAC output response time LDAC rising edge to WR rising edge BUSY rising edge to LDAC falling edge LDAC falling edge to DAC output response time DAC output settling time, boost mode off CLR pulse width low CLR pulse activation time 1 Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. See Figure 7. 4 See Figure 29. 5 Measured with the load circuit of Figure 2. 2 3 Rev. A | Page 11 of 36 AD5381 t0 t1 REG0, REG1, A5..A0 t4 t5 t2 CS t9 t3 WR t8 t6 t15 t7 DB11..DB0 t10 t11 BUSY t12 t13 t18 LDAC1 t14 VOUT1 t16 LDAC2 t13 t18 t17 VOUT2 CLR t19 1LDAC 2LDAC ACTIVE DURING BUSY ACTIVE AFTER BUSY Figure 7. Parallel Interface Timing Diagram Rev. A | Page 12 of 36 03731-0-008 t20 VOUT AD5381 ABSOLUTE MAXIMUM RATINGS Table 9. TA = 25°C, unless otherwise noted1 Parameter AVDD to AGND DVDD to DGND Digital Inputs to DGND SDA/SCL to DGND Digital Outputs to DGND REFIN/REFOUT to AGND AGND to DGND VOUTx to AGND Analog Inputs to AGND Operating Temperature Range Commercial (B Version) Storage Temperature Range JunctionTemperature (TJ Max) 100-lead LQFP Package θJAThermal Impedance Reflow Soldering Peak Temperature 1 Rating –0.3 V to +7 V –0.3 V to +7 V –0.3 V to DVDD + 0.3 V –0.3 V to + 7 V –0.3 V to DVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to +0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. –40°C to +85°C –65°C to +150°C 150°C 44°C/W 230°C Transient currents of up to 100 mA will not cause SCR latch-up ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 13 of 36 AD5381 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 1 75 RESET 74 DB5 PIN 1 IDENTIFIER 2 3 4 73 DB4 72 DB3 5 71 DB2 6 70 DB1 69 DB0 7 8 68 NC 67 NC 9 10 66 REG0 65 REG1 11 AD5381 12 13 64 VOUT23 63 VOUT22 TOP VIEW (Not to Scale) 14 62 VOUT21 15 61 VOUT20 60 AVDD3 16 17 59 AGND3 58 DAC_GND3 18 19 03732-0-002 50 49 48 47 46 45 44 43 42 41 40 38 39 37 36 SIGNAL_GND5 DAC_GND5 AGND5 AVDD5 VOUT5 VOUT6 VOUT7 VOUT32 VOUT33 VOUT34 VOUT35 VOUT36 VOUT37 VOUT38 VOUT39/MON_OUT VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 DAC_GND2 SIGNAL_GND2 VOUT13 VOUT14 VOUT15 35 51 AGND2 34 25 33 53 VOUT16 52 AVDD2 32 24 31 23 30 55 VOUT18 54 VOUT17 29 21 22 28 57 SIGNAL_GND3 56 VOUT19 27 20 26 FIFO EN CLR VOUT24 VOUT25 VOUT26 VOUT27 SIGNAL_GND4 DAC_GND4 AGND4 AVDD4 VOUT28 VOUT29 VOUT30 VOUT31 REF GND REFOUT/REFIN SIGNAL_GND1 DAC_GND1 AVDD1 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 AGND1 99 100 CS/(SYNC/AD0) DB11/(DIN/SDA) DB10/(SCLK/SCL) DB9/(SPI/I2C) DB8 DB7 DB6 SDO(A/B) DVDD DGND DGND A5 A4 A3 A2 A1 A0 DVDD DVDD DGND SER/PAR PD WR (DCEN/AD1) LDAC BUSY PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 8. 100-Lead LQFP Pin Configuration Table 10. Pin Function Descriptions Mnemonic VOUTx SIGNAL_GND(1–5) DAC_GND(1–5) AGND(1–5) AVDD(1–5) DGND DVDD REFGND REFOUT/REFIN Function Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5381. Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 12-bit DAC. These pins shound be connected to the AGND plane. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and should be decoupled with a 0.1 µF ceramic capacitor and 10 µF tantalum capacitor. Operating range for the AD5381-5 is 4.5 V to 5.5 V; operating range for the AD5381-3 is 2.7 V to 3.6 V. Ground for All Digital Circuitry. Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled with a 0.1 µF ceramic and a 10 µF tantalum capacitors to DGND. Ground Reference Point for the Internal Reference. The AD5381 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin and the internal reference can be disabled via the control register. The default for this pin is a reference input. Rev. A | Page 14 of 36 AD5381 Mnemonic VOUT39/MON_OUT SER/PAR CS/(SYNC/AD0) WR/(DCEN/ AD1) DB11–DB0 A5–A0 REG1, REG0 SDO/(A/B) BUSY LDAC CLR RESET PD Function This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. But when the monitor function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied high, the serial interface mode is selected and Pin 97 (SPI/I2C) is used to determine if the interface mode is SPI or I2C. Parallel interface mode is selected when SER/PAR is low. In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5381 is selected. Serial Interface Mode. This is the frame synchronization input signal for the serial clock and data. I2C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address for the device on the I2C bus. Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a daisy-chain enable in SPI mode and as a hardware address pin in I2C mode. Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low, and the address bus inputs to write to the selected device registers. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction with SER/PAR high to enable the SPI serial interface daisy-chain mode. I2C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for this device on the I2C bus. Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5381. Parallel Address Inputs. A5 to A0 are decoded to address one of the AD5381’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registers. Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the AD5381’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels contain two data registers. In normal mode, Data Register A is the default for data transfers. Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the RESET pin is low. During this time, the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However any events on LDAC during power-on reset or on RESET are ignored. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with the CLR code. Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the poweron reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where the analog current consumption is reduced to 2 µA and the digital current consumption is reduced to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. Rev. A | Page 15 of 36 AD5381 Mnemonic FIFOEN DB9 (SPI/I2C) DB10 (SCLK/SCL) DB11/(DIN/SDA) Function FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO_EN pin is sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I2C interface modes, the FIFO_EN pin should be tied low. Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB11 is the serial data (DIN) input. When serial interface mode is selected (SER/PAR = 1) and this input is high I2C Mode is selected. In this mode, DB12 is the serial clock (SCL) input and DB11 is the serial data (SDA) input. Multifunction Input Pin. In parallel interface mode, this pin acts as DB10 of the parallel input data-word. In serial interface mode, this pin acts as a serial clock input. Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 50 MHz. I2C Mode. In I2C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz operating modes. Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word. Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. I2C Mode. In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output. Rev. A | Page 16 of 36 AD5381 TERMINOLOGY Relative Accuracy DC Output Impedance Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB. This is the effective output source resistance. It is dominated by package lead resistance. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 2n – 1 VOUT(Zero-Scale) = 0 V Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal), expressed in mV. It is mainly due to offsets in the output amplifier. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change, and is measured from the BUSY rising edge. Digital-to-Analog Glitch Energy This is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 0x7FF and 0x800. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC due to both the digital change and to the subsequent analog output change at another DAC. The victim channel is loaded with midscale. DAC-to-DAC crosstalk is specified in nV-s. Digital Crosstalk Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the AD5381-5 with Code 32 loaded into the DAC register, and on the AD5381-3 with Code 64. Gain Error Gain Error is specified in the linear region of the output range between VOUT = 10 mV and VOUT = AVDD – 50 mV. It is the deviation in slope of the DAC transfer characteristic from the ideal and is expressed in %FSR with the DAC output unloaded. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other DACs. It is expressed in LSB. The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s. Digital Feedthrough When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough. Output Noise Spectral Density This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/√Hz in a 1 Hz bandwidth at 10 kHz. Rev. A | Page 17 of 36 AD5381 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 1.00 AVDD = 5V REFIN = 2.5V TA = 25°C 0.75 0.50 0.25 0 –0.25 0.25 0 –0.25 –0.50 –0.75 –0.75 –1.00 0 512 1024 1536 2048 2560 INPUT CODE 3072 3584 4096 03732-0-017 –0.50 –1.00 0 512 2.539 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 1536 2048 2560 INPUT CODE 3072 3584 4096 Figure 12. Typical AD5381-3 INL Plot 1.254 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 10nV-s AVDD = DVDD = 3V VREF = 1.25V TA = 25°C 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV-s 1.253 1.252 AMPLITUDE (V) 1.251 1.250 1.249 1.248 1.247 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 Figure 10. AD5381-5 Glitch Impulse 1.245 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 Figure 13. AD5381-3 Glitch Impulse AVDD = DVDD = 5V VREF = 2.5V TA = 25°C AVDD = DVDD = 5V VREF = 2.5V TA = 25°C VOUT VOUT Figure 11. Slew Rate with Boost Off Figure 14. Slew Rate with Boost On Rev. A | Page 18 of 36 03731-0-036 50 03732-0-004 0 03731-0-034 1.246 03732-0-003 AMPLITUDE (V) Figure 9. Typical AD5381-5 INL Plot 1024 03732-0-018 INL ERROR (LSB) 0.50 INL ERROR (LSB) AVDD = 3V REFIN = 1.25V TA = 25°C 0.75 AD5381 AVDD = 5.5V VREF = 2.5V TA = 25°C 14 PERCENTAGE OF UNITS (%) 12 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C POWER SUPPLY RAMP RATE = 10ms 10 VOUT 8 6 4 AVDD 9 10 AIDD (mA) 11 03731-0-011 8 04598-0-049 2 Figure 15. AIDD Histogram with Boost Off Figure 18. AD5381 Power-Up Transient 40 DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25°C 10 35 30 FREQUENCY 6 4 25 20 15 10 2 0 0.4 0.5 0.6 0.7 DIDD (mA) 0.8 0.9 Figure 16. DIDD Histogram 0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/°C) Figure 19. AD5381 REFOUT Temperature Coefficient WR PD BUSY AVDD = DVDD = 5V VREF = 2.5V TA = 25°C EXITS SOFT PD TO MIDSCALE VOUT VOUT 03731-0-038 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C EXITS HARDWARE PD TO MIDSCALE Figure 17. Exiting Soft Power Down Figure 20. Exiting Hardware Power Down Rev. A | Page 19 of 36 03731-0-048 04598-0-050 5 03731-0-045 NUMBER OF UNITS 8 AD5381 6 6 AVDD = DVDD = 3V VREF = 1.25V TA = 25°C FULLSCALE 5 5 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 3/4 SCALE 4 4 MIDSCALE 3 2 VOUT (V) VOUT (V) 3/4 SCALE 1/4 SCALE 1 3 FULL-SCALE MIDSCALE 2 1 ZEROSCALE 0 –20 –10 –5 –2 0 2 CURRENT (mA) 5 10 20 40 ZERO-SCALE 03731-0-039 –1 –40 –1 –40 Figure 21. AD5381-5 Output Amplifier Source and Sink Capability 0.20 5 10 20 –40 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 14ns/SAMPLE NUMBER 2.454 ERROR AT ZERO SINKING CURRENT 0.05 AMPLITUDE (V) 0 –0.05 2.453 2.452 2.451 (VDD–VOUT) AT FULL-SCALE SOURCING CURRENT 0 0.25 0.50 0.75 1.00 1.25 ISOURCE/ISINK (mA) 1.50 1.75 2.00 03731-0-047 –0.20 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 AVDD = DVDD = 5V TA = 25°C DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5µV/DIV X AXIS = 100ms/DIV AVDD = 5V TA = 25°C REFOUT DECOUPLED WITH 100nF CAPACITOR 500 0 Figure 25. Adjacent Channel DAC-to-DAC Crosstalk Figure 22. Headroom at Rails vs. Source/Sink Current 600 2.449 400 300 REFOUT = 2.5V 200 0 100 REFOUT = 1.25V 1k 10k FREQUENCY (Hz) 100k 03731-0-047 100 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C EXITS SOFT PD TO MIDSCALE Figure 23. REFOUT Noise Spectral Density Rev. A | Page 20 of 36 Figure 26. 0.1 Hz to 10 Hz Noise Plot 03731-0-041 2.450 03731-0-046 ERROR VOLTAGE (V) 1/4 SCALE –2 0 2 CURRENT (mA) 2.455 –0.15 OUTPUT NOISE (nV/ Hz) –5 2.456 0.10 –0.10 –10 Figure 24. AD5381-3 Output Amplifier Source and Sink Capability AVDD = 5V VREF = 2.5V TA = 25°C 0.15 –20 03731-0-040 0 AD5381 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5381 is a complete, single-supply, 40-channel voltage output DAC that offers 12-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the buffered reference inputs; alternatively, an external reference can be used to drive these inputs. Internal/external reference selection is via the CR8 bit in the control register; CR10 selects the reference magnitude if the internal reference is selected. All channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 kΩ in parallel with a 200 pF load. VREF AVDD ×1 INPUT REG ×2 DAC REG 12-BIT DAC c REG VOUT R VOUT = 2 × VREF × x2/2n where: x2 is the data-word loaded to the resistor string DAC. VREF is the internal reference voltage or the reference voltage externally applied to the DAC REFOUT/REFIN pin. For specified performance, an external reference voltage of 2.5 V is recommended for the AD5381-5, and 1.25 V for the AD5381-3. Data Decoding The AD5381 contains a 12-bit data bus, DB11–DB0. Depending on the value of REG1 and REG0 (see Table 11), this data is loaded into the addressed DAC input registers, offset (c) registers, or gain (m) registers. The format data, offset (c), and gain (m) register contents are shown in Table 12 to Table 14. Table 11. Register Selection R 03732-0-005 INPUT DATA m REG The complete transfer function for these devices can be represented as Figure 27. Single-Channel Architecture The architecture of a single DAC channel consists of a 12-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture guarantees DAC monotonicity. The 12-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. Each channel on these devices contains independent offset and gain control registers that allow the user to digitally trim offset and gain. These registers give the user the ability to calibrate out errors in the complete signal chain, including the DAC, using the internal m and c registers, which hold the correction factors. All channels are double buffered, allowing synchronous updating of all channels using the LDAC pin. Figure 27 shows a block diagram of a single channel on the AD5381. The digital input transfer function for each DAC can be represented as x2 = [(m + 2)/ 2n × x1] + (c – 2n – 1) where: x2 = the data-word loaded to the resistor string DAC x1 = the 12-bit data-word written to the DAC input register m = the gain coefficient (default is 0xFFE). The gain coefficient is written to the 11 most significant bits (DB11–DB1), the LSB (DB0) of the data-word is a 0. n = DAC resolution (n = 12 for AD5381) c is the12-bit offset coefficient (default is 0x800). REG1 1 1 0 0 REG0 1 0 1 0 Register Selected Input Data Register (x1) Offset Register (c) Gain Register (m) Special Function Registers (SFRs) Table 12. DAC Data Format (REG1 = 1, REG0 = 1) 1111 1111 1000 1000 0111 0000 0000 DB11 to DB0 1111 1111 1111 1110 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000 DAC Output (V) 2 VREF × (4095/4096) 2 VREF × (4094/4096) 2 VREF × (2049/4096) 2 VREF × (2048/4096) 2 VREF × (2047/4096) 2 VREF × (1/4096) 0 Table 13. Offset Data Format (REG1 = 1, REG0 = 0) 1111 1111 1000 1000 0111 0000 0000 DB11 to DB0 1111 1111 0000 0000 1111 0000 0000 1111 1110 0001 0000 1111 0001 0000 Offset (LSB) +2048 +2047 +1 0 –1 –2047 –2048 Table 14. Gain Data Format (REG1 = 0, REG0 = 1) 1111 1011 0111 0011 0000 Rev. A | Page 21 of 36 DB11 to DB0 1111 1111 1111 1111 0000 1110 1110 1110 1110 0000 Gain Factor 1 0.75 0.5 0.25 0 AD5381 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5381 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using address bits A5 to A0. REG1 = REG0 = 0, A5–A0 = 000010 DB11–DB0 = Don’t Care Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) R/W A5 A4 A3 A2 A1 A0 Function X 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Control Register Write Control Register Read Monitor Channel Soft Reset SFR COMMANDS NOP (No Operation) REG1 = REG0 = 0, A5–A0 = 000000 Performs no operation but is useful in serial readback mode to clock out data on DOUT for diagnostic purposes. BUSY pulses low during a NOP operation. Write CLR Code REG1 = REG0 = 0, A5–A0 = 000001 DB11–DB0 = Contain the CLR data Bringing the CLR line low or exercising the soft clear function will load the contents of the DAC registers with the data contained in the user configurable CLR register, and will set VOUT0 to VOUT39 accordingly. This can be very useful for setting up a specific output voltage in a clear condition. It is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all DACs, removing the need for individual writes to each DAC. Default on powerup is all zeros. Executing this instruction performs the CLR, which is functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the CLR code register. It takes 35 µs to fully execute the SOFT CLR, as indicated by the BUSY low time. Soft Power-Down REG1 = REG0 = 0, A5–A0 = 001000 DB11–DB0 = Don’t Care Executing this instruction performs a global power-down feature that puts all channels into a low power mode that reduces the analog supply current to 2 µA max and the digital current to 20 µA max. In power-down mode, the output amplifier can be configured as a high impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode. No register can be written to while in power-down. Soft Power-Up REG1 = REG0 = 0, A5–A0 = 001001 DB11–DB0 = Don’t Care This instruction is used to power up the output amplifiers and the internal reference. The time to exit power–down is 8 µs. The hardware power-down and software function are internally combined in a digital OR function. Soft RESET REG1 = REG0 = 0, A5–A0 = 001111 DB11–DB0 = Don’t Care This instruction is used to implement a software reset. All internal registers are reset to their default values, which correspond to m at full scale and c at zero. The contents of the DAC registers are cleared, setting all analog outputs to 0 V. The soft reset activation time is 135 µs. Rev. A | Page 22 of 36 AD5381 Table 16. Control Register Contents MSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 Control Register Write/Read REG1 = REG0 = 0, A5–A0 = 001100, R/W status determines if the operation is a write (R/W = 0) or a read (R/W = 1). DB11 to DB0 contains the control register data. CR7 = 0: Monitor Disabled (default on power-up). When the monitor is disabled, the MON_OUT pin assumes its normal DAC output function. CR6: Thermal Monitor Function. This function is used to monitor the AD5381’s internal die temperature when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function can be used to protect the device in cases where power dissipation may be exceeded if a number of output channels are simultaneously short-circuited. A soft power-up will re-enable the output amplifiers if the die temperature has dropped below 130°C. Control Register Contents CR11: Power-Down Status. This bit is used to configure the output amplifier state in power down. CR11 = 1. Amplifier output is high impedance (default on power-up). CR11 = 0. Amplifier output is 100 kΩ to ground. CR6 = 1: Thermal Monitor Enabled. CR10: REF Select. This bit selects the operating internal reference for the AD5381. CR10 is programmed as follows: CR6 = 0: Thermal Monitor Disabled (default on power- up). CR10 = 1: Internal reference is 2.5 V (AD5381-5 default), the recommended operating reference for AD5381-5. CR10 = 0: Internal reference is 1.25 V (AD5381-3 default), the recommended operating reference for AD5381-3. CR9: Current Boost Control. This bit is used to boost the current in the output amplifier, thereby altering its slew rate. This bit is configured as follows: CR9 = 1: Boost Mode On. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR9 = 0: Boost Mode Off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption. CR8: Internal/External Reference. This bit determines if the DAC uses its internal reference or an externally applied reference. CR5: Don’t Care. CR4 to CR0: Toggle Function Enable. This function allows the user to toggle the output between two codes loaded to the A and B register for each DAC. Control register bits CR4 to CR0 are used to enable individual groups of eight channels for operation in toggle mode. A Logic 1 written to any bit enables a group of channels; a Logic 0 disables a group. LDAC is used to toggle between the two registers. Table 17. CR Bit CR4 CR3 CR2 CR1 CR0 Group 4 3 2 1 0 Channels 32–39 24–31 16–23 8–15 0–7 Channel Monitor Function CR8 = 1: Internal Reference Enabled. The reference output depends on data loaded to CR10. CR8 = 0: External Reference Selected (default on power up). CR7: Channel Monitor Enable (see Channel Monitor Function) CR7= 1: Monitor Enabled. This enables the channel monitor function. After a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. VOUT 39 operates at the MON_OUT pin. REG1 = REG0 = 0, A5–A0 = 001010 DB11–DB6 = Contain data to address the monitored channel. A channel monitor function is provided on the AD5381. This feature, which consists of a multiplexer addressed via the interface, allows any channel output to be routed to the MON_OUT pin for monitoring using an external ADC. In channel monitor mode, VOUT 39 becomes the MON_OUT pin, to which all monitored pins are routed. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. On the AD5381, DB11 to DB6 contain the channel address for the monitored channel. Selecting channel address 63 three-states MON_OUT. Rev. A | Page 23 of 36 AD5381 Table 18. AD5381 Channel Monitor Decoding REG1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • REG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • A3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 • A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 • A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • DB11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 • DB10 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 • DB9 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 • DB8 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 • DB8 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 • DB6 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 • DB5–DB0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X • MON_OUT VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4 VOUT 5 VOUT 6 VOUT 7 VOUT 8 VOUT 9 VOUT 10 VOUT 11 VOUT 12 VOUT 13 VOUT 14 VOUT 15 VOUT 16 VOUT 17 VOUT 18 VOUT 19 VOUT 20 VOUT 21 VOUT 22 VOUT 23 VOUT 24 VOUT 25 VOUT 26 VOUT 27 VOUT 28 VOUT 29 VOUT 30 VOUT 31 VOUT 32 VOUT 33 VOUT 34 VOUT 35 VOUT 36 VOUT 37 VOUT 38 Undefined • • • • • • • • • • • • • • • • • 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 X X Undefined Three-State REG1 REG0 A5 A4 A3 A2 A1 A0 0 0 0 0 1 0 1 0 VOUT0 VOUT1 AD5381 CHANNEL MONITOR DECODING VOUT39/MON_OUT CHANNEL ADDRESS DB11–DB6 Figure 28. Channel Monitor Decoding Rev. A | Page 24 of 36 03732-0-006 VOUT37 VOUT38 AD5381 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. Reset is a negative edgesensitive input. The default corresponds to m at full-scale and to c at zero. The contents of the DAC registers are cleared, setting VOUT 0 to VOUT 39 to 0 V. This sequence takes 270 µs. The falling edge of RESET initiates the reset process; BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. The AD5381 contains a FIFO to optimize operation when operating in parallel interface mode. The FIFO Enable (level sensitive, active high) is used to enable the internal FIFO. When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO_EN pin is sampled on power-up, and after a CLR or RESET, to deter-mine if the FIFO is enabled. In either serial or I2C interface modes, FIFO_EN should be tied low. Up to 128 successive instructions can be written to the FIFO at maximum speed in parallel mode. When the FIFO is full, any further writes to the device are ignored. Figure 29 shows a comparison between FIFO mode and non-FIFO mode in terms of channel update time. Figure 29 also outlines digital loading time. ASYNCHRONOUS CLEAR FUNCTION Bringing the CLR line low clears the contents of the DAC registers to the data contained in the user configurable CLR register and sets VOUT 0 to VOUT 39 accordingly. This function can be used in system calibration to load zero-scale and full-scale to all channels. The execution time for a CLR is 35 µs. 25 WITHOUT FIFO (CHANNEL UPDATE TIME) 20 BUSY AND LDAC FUNCTIONS TIME (µs) 15 10 WITH FIFO (CHANNEL UPDATE TIME) 5 WITH FIFO (DIGITAL LOADING TIME) 0 1 4 7 10 13 16 19 22 25 28 NUMBER OF WRITES 31 34 37 40 03731-0-018 BUSY is a digital CMOS output that indicates the status of the AD5381. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1, c, or m registers. During the calculation of x2, the BUSY output goes low. While BUSY is low, the user can continue writing new data to the x1, m, or c registers, but no DAC output updates can take place. The DAC outputs are updated by taking the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. The user may hold the LDAC input permanently low, in which case the DAC outputs update immediately after BUSY goes high. BUSY also goes low during power-on reset and when a falling edge is detected on the RESET pin. During this time, all interfaces are disabled and any events on LDAC are ignored. The AD5381 contains an extra feature whereby a DAC register is not updated unless its x2 register has been written to since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the x2 registers. However, the AD5381 will only update the DAC register if the x2 data has changed, thereby removing unnecessary digital crosstalk. Figure 29. Channel Update Rate (FIFO vs. NON-FIFO) POWER-ON RESET The AD5381 contains a power-on reset generator and state machine. The power-on reset resets all registers to a predefined state and configures the analog outputs as high impedance. The BUSY pin goes low during the power-on reset sequencing, preventing data writes to the device. POWER-DOWN The AD5381 contains a global power-down feature that puts all channels into a low power mode and reduces the analog power consumption to 2 µA max and digital power consumption to 20 µA max. In power-down mode, the output amplifier can be configured as a high impedance output or can provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier will elapse before the outputs settle to their correct values. Rev. A | Page 25 of 36 AD5381 AD5381 INTERFACES The AD5381 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed to be either SPI, DSP, MICROWIRE, or I2C compatible. The SER/PAR pin selects parallel and serial interface modes. In serial mode, the SPI/I2C pin is used to select DSP, SPI, MICROWIRE, or I2C interface mode. The devices use an internal FIFO memory to allow high speed successive writes in parallel interface mode. The user can continue writing new data to the device while write instructions are being executed. The BUSY signal indicates the current status of the device, going low while instructions in the FIFO are being executed. In parallel mode, up to 128 successive instructions can be written to the FIFO at maximum speed. When the FIFO is full, any further writes to the device are ignored. To minimize both the power consumption of the device and the on-chip digital noise, the active interface only powers up fully when the device is being written to, i.e., on the falling edge of WR or the falling edge of SYNC. DSP, SPI, MICROWIRE COMPATIBLE SERIAL INTERFACES The serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy-chain mode. Daisy chaining allows many devices to be cascaded together to increase system channel count. The SER/PAR pin must be tied high and the SPI/I2C pin (Pin 97) should be tied low to enable the DSP/SPI/MICROWIRE compatible serial interface. In serial interface mode, the user does not need to drive the parallel input data pins. The serial interface’s control pins are Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5381 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 19 A/B. When toggle mode is enabled, this pin selects whether the data write is to the A or B register. With toggle disabled, this bit should be set to zero to select the A data register. R/W is the read or write control bit. A5–A0 are used to address the input channels. REG1 and REG0 select the register to which data is written, as shown in Table 11. DB11–DB0 contain the input data-word. X is a don’t care condition. Standalone Mode By connecting the DCEN (Daisy-Chain Enable) pin low, standalone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC except for a falling edge are ignored until 24 bits are clocked in. Once 24 bits have been shifted in, the SCLK is ignored. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. SYNC, DIN, SCLK—Standard 3-Wire Interface Pins. DCEN—Selects Standalone Mode or Daisy-Chain Mode. SDO—Data Out Pin for Daisy-Chain Mode. Table 19. 40-Channel, 12-bit DAC Serial Input Register Configuration MSB A/B R/W A5 A4 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 Rev. A | Page 26 of 36 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X LSB X AD5381 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A5 to A0, in association with Bits REG1 and REG0, select the register to be read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO output will contain the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. Figure 30 shows the readback sequence. For example, to read back the M register of Channel 0 on the AD5381, the following sequence should be implemented. First, write 0x404XXX to the AD5381 input register. This configures the AD5381 for read mode with the m register of Channel 0 selected. Note that data bits DB11 to DB0 are don’t cares. Follow this with a second write, a NOP condition, 0x000000. During this write, the data from the m register is clocked out on the DOUT line, i.e., data clocked out will contain the data from the m register in Bits DB11 to DB0, and the top 10 bits contain the address information as previously written. In readback mode, the SYNC signal must frame the data. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback operation, the first bit of data is clocked out on the falling edge of SYNC. By connecting the DCEN (Daisy-Chain Enable) pin high, daisychain mode is enabled. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input on the next device in the chain, a multidevice interface is constructed. Twenty-four clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD538x devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy-chain and prevents any further data from being clocked into the input shift register. If the SYNC is taken high before 24 clocks are clocked into the part, this is considered a bad frame and the data is discarded. The serial clock may be either a continuous or a gated clock. A continuous SCLK source can only be used if it can be arranged that SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. SCLK 24 48 SYNC DB23 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23 DB0 UNDEFINED DB0 NOP CONDITION DB23 SELECTED REGISTER DATA CLOCKED OUT Figure 30. Serial Readback Operation Rev. A | Page 27 of 36 DB0 03731-0-019 DIN AD5381 I2C SERIAL INTERFACE The AD5381 features an I2C compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5381 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. In selecting the I2C operating mode, first configure serial operating mode (SER/PAR = 1) and then select I2C mode by configuring the SPI/I2C pin to a Logic 1. The device is connected to the I2C bus as a slave device (i.e., no clock is generated by the AD5381). The AD5381 has a 7-bit slave address 1010 1(AD1)(AD0). The 5 MSB are hard-coded and the 2 LSB are determined by the state of the AD1 and AD0 pins. The facility to hardware configure AD1 and AD0 allows four of these devices to be configured on the bus. 2 I C Data Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals that configure START and STOP conditions. Both SDA and SCL are pulled high by the external pull-up resistors when the I2C bus is not busy. START and STOP Conditions A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high. A START condition from the master signals the beginning of a transmission to the AD5381. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. Repeated START Conditions A repeated START (Sr) condition may indicate a change of data direction on the bus. Sr may be used when the bus master is writing to several I2C devices and wants to maintain control of the bus. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data-word. ACK is always generated by the receiving device. The AD5381 devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication. AD5381 Slave Addresses A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address. When idle, the AD5381 waits for a START condition followed by its slave address. The LSB of the address word is the Read/ Write (R/W) bit. The AD5381 is a receive only device; when communicating with the AD5381, R/W = 0. After receiving the proper address 1010 1(AD1)(AD0), the AD5381 issues an ACK by pulling SDA low for one clock cycle. The AD5381 has four different user programmable addresses determined by the AD1 and AD0 bits. Write Operation There are three specific modes in which data can be written to the AD5381 DAC. 4-Byte Mode When writing to the AD5381 DACs, the user must begin with an address byte (R/W = 0) after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 31. A STOP condition follows. This allows the user to update a single channel within the AD5381 at any time and requires four bytes of data to be transferred from the master. 3-Byte Mode In 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is only required once; subsequent channel updates require the pointer byte and the data bytes. In 3-byte mode, the user begins with an address byte (R/W = 0), after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte. This addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. This is then followed by the two data bytes. REG1 and REG0 determine the register to be updated. If a STOP condition does not follow the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. This mode only requires three bytes to be sent to update any channel once the device has been initially addressed, and reduces the software overhead in updating the AD5381 channels. A STOP condition at any time exits this mode. Figure 32 shows a typical configuration. Rev. A | Page 28 of 36 AD5381 SCL 1 SDA 0 1 0 1 AD1 AD0 START COND BY MASTER R/W 0 ACK BY AD538x MSB 0 A5 A4 A3 A2 A1 A0 ACK BY AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE STOP COND BY MASTER 03731-0-020 SDA Figure 31. 4-Byte AD5381, I2C Write Operation SCL SDA 1 0 1 0 1 AD1 AD0 START COND BY MASTER R/W 0 ACK BY AD538x MSB 0 ADDRESS BYTE A5 A4 A3 A2 A1 A0 ACK BY AD538x POINTER BYTE FOR CHANNEL "N" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "N" SCL SDA 0 0 A5 A4 A3 A2 A1 A0 MSB ACK BY AD538x POINTER BYTE FOR CHANNEL "NEXT CHANNEL" SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x MOST SIGNIFICANT DATA BYTE ACK BY AD538x LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "NEXT CHANNEL" Figure 32. 3-Byte AD5381, I2C Write Operation Rev. A | Page 29 of 36 STOP COND BY MASTER 03731-0-021 SDA AD5381 2-Byte Mode PARALLEL INTERFACE Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is only required once and the pointer address pointer is configured for autoincrement or burst mode. The SER/PAR pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 7 shows the timing diagram for a parallel write. The parallel interface is controlled by the following pins: The user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of operation. The address pointer initializes to Channel 0, the data following the pointer is loaded to Channel 0, and the address pointer automatically increments to the next address. CS Pin Active Low Device Select Pin. WR Pin On the rising edge of WR, with CS low, the addresses on Pins A5 to A0 are latched; data present on the data bus is loaded into the selected input registers. REG0, REG1 Pins The REG0 and REG1 bits in the data byte determine which register will be updated. In this mode, following the initialization, only the two data bytes are required to update a channel. The channel address automatically increments from Address 0 to Channel 39 and then returns to the normal 3-byte mode of operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. A STOP condition at any time exits this mode. Toggle mode is not supported in 2-byte mode. Figure 33 shows a typical configuration. The REG0 and REG1 pins determine the destination register of the data being written to the AD5381. See Table 11. Pins A5 to A0 Each of the 40 DAC channels can be addressed individually. Pins DB11 to DB0 The AD5381 accepts a straight 12-bit parallel word on DB11 to DB0, where DB11 is the MSB and DB0 is the LSB. SCL SDA 1 0 1 0 1 AD1 START COND BY MASTER AD0 R/W A7 = 1 ACK BY CONVERTER MSB A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 ACK BY CONVERTER ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY CONVERTER ACK BY CONVERTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL REG1 REG0 MSB LSB MSB LSB ACK BY CONVERTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL N DATA FOLLOWED BY STOP Figure 33. 2-Byte, 12C Write Operation Rev. A | Page 30 of 36 ACK BY STOP CONVERTER COND BY MASTER 03731-0-022 SDA AD5381 MICROPROCESSOR INTERFACING The AD5381 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 35 shows the AD5381 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0–A5 on the AD5381. The upper address lines are decoded to provide a CS, LDAC signal for the AD5381. The fast interface timing of the AD5381 allows direct interface to a wide variety of microcontrollers and DSPs, as shown in Figure 35. being transmitted to the AD5381, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. DVDD MC68HC11 RESET AD5381 to MC68HC11 The serial peripheral interface (SPI) on the MC68HC11 is configured for Master mode (MSTR = 1), Clock Polarity bit (CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5381, the MOSI output drives the serial data line (DIN) of the AD5381, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). When data is MISO SDO MOSI DIN SCK SCLK PC7 SYNC SPI/I2C Figure 34. AD5381-to-MC68HC11 Interface µCONTROLLER/ DSP PROCESSOR* AD5381 D15 REG1 REG0 D11 DATA BUS D0 D0 ADDRESS DECODE CS LDAC A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 R/W WR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 35. AD5381-to-Parallel Interface Rev. A | Page 31 of 36 03732-0-008 UPPER BITS OF ADDRESS BUS AD5381 SER/PAR 03731-0-024 Parallel Interface AD5381 AD5381 to PIC16C6x/7x DVDD AD5381 SER/PAR SDO SDO/RC5 DIN SCK/RC3 SCLK RA1 SYNC SPI/I2C 03732-0-009 RESET SDI/RC4 Figure 36. AD5381-to-PIC16C6x/7x Interface RESET RxD SDO DIN TxD SCLK P1.1 SYNC SPI/I2C Figure 37. AD5381-to-8051 Interface AD5381 to ADSP-2101/ADSP-2103 Figure 38 shows a serial interface between the AD5381 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. ADSP-2101/ ADSP-2103 AD5381 to 8051 AD5381 SER/PAR 03732-0-010 The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the Clock Polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example I/O, port RA1 is being used to pulse SYNC and enable the serial port of the AD5381. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations may be needed depending on the mode. Figure 36 shows the connection diagram. PIC16C6X/7X DVDD 8XC51 DVDD AD5381 SER/PAR RESET Rev. A | Page 32 of 36 DR SDO DT DIN SCK TFS RFS SCLK SYNC SPI/I2C Figure 38. AD5381-to-ADSP-2101/ADSP-2103 Interface 03732-0-011 The AD5381 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data enters and exits through RxD, and a shift clock is output on TxD. Figure 37 shows how the 8051 is connected to the AD5381. Because the AD5381 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5381 requires its data to be MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. AD5381 APPLICATION INFORMATION In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5381 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5381 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible. For supplies with multiple pins (AVDD, DVDD), these pins should be tied together. The AD5381 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible and ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5381 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (this is not required on a multilayer board because there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on the VIN and REFIN lines. an ADR421 or ADR431 2.5 V reference. Suitable external references for the AD5381-3 include the ADR280 1.2 V reference. The reference should be decoupled at the REFOUT/REFIN pin of the device with a 0.1 µF capacitor. AVDD DVDD 0.1µF 10µF ADR431/ ADR421 0.1µF AVDD DVDD VOUT0 REFOUT/REFIN 0.1µF AD5381-5 REFGND VOUT39 DAC GND SIGNAL GND AGND DGND 03732-0-012 POWER SUPPLY DECOUPLING Figure 39. Typical Configuration with External Reference Figure 40 shows a typical configuration when using the internal reference. On power-up, the AD5381 defaults to an external reference; therefore, the internal reference needs to be configured and turned on via a write to the AD5381 control register. Control Register Bit CR10 allows the user choose the reference value; Bit CR8 is used to select the internal reference. It is recommended to use the 2.5 V reference when AVDD = 5 V, and the 1.25 V reference when AVDD = 3 V. AVDD DVDD 0.1µF 10µF Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. 0.1µF AVDD DVDD REFOUT/REFIN 0.1µF VOUT0 AD5381 REFGND VOUT39 SIGNAL GND AGND DGND 03732-0-013 DAC GND TYPICAL CONFIGURATION CIRCUIT Figure 39 shows a typical configuration for the AD5381-5 when configured for use with an external reference. In the circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied together to a common AGND. AGND and DGND are connected together at the AD5381 device. On power-up, the AD5381 defaults to external reference operation. All AVDD lines are connected together and driven from the same 5 V source. It is recommended to decouple close to the device with a 0.1 µF ceramic and a 10 µF tantalum capacitor. In this application, the reference for the AD5381-5 is provided externally from either Figure 40. Typical Configuration with Internal Reference Digital connections have been omitted for clarity. The AD5381 contains an internal power- on reset circuit with a 10 ms brownout time. If the power supply ramp rate exceeds 10 ms, the user should reset the AD5381 as part of the initialization process to ensure the calibration data gets loaded correctly into the device. Rev. A | Page 33 of 36 AD5381 AD5381 MONITOR FUNCTION The AD5381 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. In channel monitor mode, VOUT 39 becomes the MON_OUT pin, to which all monitored signals are routed. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. Table 18 contains the decoding information required to route any channel to MON_OUT. Selecting Channel Address 63 three-states MON_OUT. Figure 41 shows a typical monitoring circuit implemented using a 12-bit SAR ADC in a 6-lead SOT-23 package. The controller output port selects the channel to be monitored, and the input port reads the converted data from the ADC. AVDD DIN SYNC SCLK OUTPUT PORT VDD AD5381 CS SCLK VIN INPUT PORT SDATA GND DAC_GND SIGNAL_GND 03732-0-014 VOUT38 LDAC is used to switch between the A and B registers in determining the analog output. The first LDAC configures the output to reflect data in the A registers. This mode offers significant advantages if the user wants to generate a square wave at the output of all 40 channels, as might be required to drive a liquid crystal based variable optical attenuator. In this case, the user writes to the control register and enables the toggle function by setting CR4 to CR2 = 0, thus enabling the five groups of eight for toggle mode operation. The user must then load data to all 40 A and B registers. Toggling LDAC sets the output values to reflect the data in the A and B registers. The LDAC’s frequency determines the frequency of the square wave output. THERMAL MONITOR FUNCTION CONTROLLER AGND 2. 3. 4. Enable toggle mode for the required channels via the control register. Load data to A registers. Load data to B registers. Apply LDAC. Toggle mode is disabled via the control register. The first LDAC following the disabling of the toggle mode will update the outputs with the data contained in the A registers. AD7476 VOUT39/MON_OUT 1. Figure 41. Typical Channel Monitoring Circuit TOGGLE MODE FUNCTION The toggle mode function allows an output signal to be generated using the LDAC control signal that switches between two DAC data registers. This function is configured using the SFR control register as follows. A write with REG1 = REG0 = 0 and A5–A0 = 001100 specifies a control register write. The toggle mode function is enabled in groups of eight channels using Bits CR4 to CR0 in the control register. See the AD5381 control register description. Figure 42 shows a block diagram of toggle mode implementation. Each of the 40 DAC channels on the AD5381 contain an A and B data register. Note that B registers The AD5381 contains a temperature shutdown function to protect the chip in case multiple outputs are shorted. The short circuit current of each output amplifier is typically 40 mA. Operating the AD5381 at 5 V leads to a power dissipation of 200 mW per shorted amplifier. With five channels shorted, this leads to an extra watt of power dissipation. For the 100-lead LQFP, the θJA is typically 44°C/W. The thermal monitor is enabled by the user via CR6 in the control register. The output amplifiers on the AD5381 are automatically powered down if the die temperature exceeds approximately 130°C. After a thermal shutdown has occurred, the user can re-enable the part by executing a soft power-up if the temperature has dropped below 130°C or by turning off the thermal monitor function via the control register. DATA REGISTER A DAC REGISTER INPUT INPUT DATA REGISTER 12-BIT DAC VOUT DATA REGISTER B LDAC CONTROL INPUT A/B Figure 42. Toggle Mode Function Rev. A | Page 34 of 36 03732-0-015 VOUT0 can only be loaded when toggle mode is enabled. The sequence of events when configuring the AD5381 for toggle mode is AD5381 OPTICAL ATTENUATORS UTILIZING THE AD5381 FIFO Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5381 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (VOA), and optical add-drop multiplexers (OADM). In these applications, each wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimpedance amplifier and ADC in a closed-loop control system. The AD5381 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. This prevents information loss and saturation from occurring at amplification stages further along the fiber. The AD5381 FIFO mode optimizes total system update rates in applications where a large number of channels need to be updated. FIFO mode is only available when parallel interface mode is selected. The FIFO_EN pin is used to enable the FIFO. The status of FIFO_EN is sampled during the initialization sequence. Therefore, the FIFO status can only be changed by resetting the device. In a telescope that provides for the cancellation of atmospheric distortion, for example, a large number of channels need to be updated in a short period of time. In such systems, as many as 400 channels need to be updated within 40 µs. Four-hundred channels requires the use of 10 AD5381s. With FIFO mode enabled, the data write cycle time is 40 ns; therefore, each group consisting of 40 channels can be fully loaded in 1.6 µs. In FIFO mode, a complete group of 40 channels will update in 14.4 µs. The time taken to update all 400 channels is 14.4 µs + 9 × 1.6 µs = 28.8 µs. Figure 44 shows the FIFO operation scheme. ADD PORTS DROP PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 DWDM IN DWDM OUT ATTENUATOR FIBRE AWG AWG FIBRE 1n–1 ATTENUATOR 1n ATTENUATOR TIA/LOG AMP (AD8304/AD8305) N:1 MULTIPLEXER CONTROLLER 16-BIT ADC ADG731 (40:1 MUX) AD7671 (0-5V, 1MSPS) 03732-0-016 AD5381, 40-CHANNEL, 12-BIT DAC Figure 43. OADM Using the AD5381 as Part of an Optical Attenuator GROUP B CHNLS 40-79 FIFO DATA LOAD GROUP A 1.6µs 1.6µs 14.4µs GROUP C CHNLS 80-119 GROUP D CHNLS 120-159 GROUP E CHNLS 160-199 GROUP F CHNLS 200-239 GROUP G CHNLS 240-279 FIFO DATA LOAD GROUP B GROUP I CHNLS 320-359 FIFO DATA LOAD GROUP J OUTPUT UPDATE TIME FOR GROUP A 14.4µs GROUP H CHNLS 280-319 OUTPUT UPDATE TIME FOR GROUP J OUTPUT UPDATE TIME FOR GROUP B TIME TO UPDATE 400 CHANNELS = 28.8µs Figure 44. Using FIFO Mode 400 Channels Updated in Under 30 µs Rev. A | Page 35 of 36 GROUP J CHNLS 360-399 1.6µs 14.4µs 03731-0-032 GROUP A CHNLS 0-39 AD5381 OUTLINE DIMENSIONS 16.00 BSC SQ 1.60 MAX 0.75 0.60 0.45 SEATING PLANE 14.00 BSC SQ 12° TYP 100 1 76 75 PIN 1 12.00 REF TOP VIEW (PINS DOWN) 10° 6° 2° 1.45 1.40 1.35 0.15 0.05 0.20 0.09 VIEW A 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE 25 51 50 26 0.27 0.22 0.17 0.50 BSC VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BED Figure 45. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100) Dimensions shown in millimeters ORDERING GUIDE Model AD5381BST-3 AD5381BST-3-REEL AD5381BST-5 AD5381BST-5-REEL EVAL-AD5381EB Resolution 12 Bits 12 Bits 12 Bits 12 Bits Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C AVDD Range 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V Output Channels 40 40 40 40 Linearity Error (LSB) ±1 ±1 ±1 ±1 Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP Evaluation Kit Package Option ST-100 ST-100 ST-100 ST-100 Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03732–0–6/04(A) Rev. A | Page 36 of 36