Fairchild FDC6302P Digital fet, dual p-channel Datasheet

October 1997
FDC6302P
Digital FET, Dual P-Channel
General Description
Features
These Dual P-Channel logic level enhancement mode field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This device
has been designed especially for low voltage applications as a
replacement for digital transistors in load switchimg applications.
Since bias resistors are not required this one P-Channel FET
can replace several digital transistors with different bias resistors
like the IMBxA series.
-25 V, -0.12 A continuous, -0.5 A Peak.
R DS(ON) = 13 Ω @ VGS= -2.7 V
R DS(ON) = 10 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple PNP digital transistors (IMHxA series) with
one DMOS FET.
SOT-23
Absolute Maximum Ratings
Symbol
Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage
ID
Drain Current
PD
SuperSOTTM-8
SuperSOTTM-6
SO-8
SOT-223
SOIC-16
4
3
5
2
6
1
TA = 25oC unless other wise noted
FDC6302P
Units
-25
V
-8
V
- Continuous
-0.12
A
- Pulsed
-0.5
Maximum Power Dissipation
(Note 1a)
0.9
(Note 1b)
0.7
TJ,TSTG
Operating and Storage Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
W
-55 to 150
°C
6.0
kV
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
140
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
60
°C/W
© 1997 Fairchild Semiconductor Corporation
FDC6302P Rev.C
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
Min
-25
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
ID = -250 µA, Referenced to 25 o C
IDSS
Zero Gate Voltage Drain Current
VDS = -20 V, VGS = 0 V
IGSS
Gate - Body Leakage Current
VGS = -8 V, VDS= 0 V
V
TJ = 55°C
ON CHARACTERISTICS
mV /o C
-20
-1
µA
-10
µA
-100
nA
(Note 2)
∆VGS(th)/∆TJ
Gate Threshold Voltage Temp. Coefficient
ID = -250 µA, Referenced to 25 o C
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
RDS(ON)
Static Drain-Source On-Resistance
mV /o C
1.9
-0.65
-1
-1.5
V
VGS = -2.7 V, ID = -0.05A
10.6
13
Ω
VGS = -4.5 V, ID = -0.2 A
7.9
10
12
18
TJ =125°C
ID(ON)
On-State Drain Current
VGS = -2.7 V, VDS = -5 V
gFS
Forward Transconductance
VDS = -5 V, ID= -0.2 A
-0.05
A
0.135
S
11
pF
7
pF
1.4
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
(Note 2)
VDD = -6 V, ID = -0.2 A,
VGS = -4.5 V, RGEN = 50 Ω
VDS = -5 V, ID = - 0.2 A,
VGS = -4.5 V
5
12
ns
8
16
ns
9
18
ns
5
10
ns
0.22
0.31
nC
0.12
nC
0.05
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -0.7 A
(Note 2)
-1
-0.7
A
-1.3
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDC6302P Rev.C
2
0.2
V GS = -5.0V
-4.5
-4.0
-3.5
RDS(ON), NORMALIZED
-3.0
0.15
-2.7
-2.5
0.1
-2.0
0.05
0
DRAIN-SOURCE ON-RESISTANCE
-I D , DRAIN-SOURCE CURRENT (A)
Typical Electrical Characteristics
V GS = -2.0 V
1.5
-2.7
-3.0
1
1
2
3
-4.0
-3.5
-4.5
0.5
0
-2.5
4
0
0.05
,DRAIN-SOURCE ON-RESISTANCE
V GS = -2.7V
1.2
1
0.8
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
150
R DS(ON)
R DS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE (OHMS)
I D = -0.05A
ID = -0.05A
TA= 25°C
20
125 °C
15
10
5
0
0
1
2
3
4
5
6
7
8
-V GS ,GATE TO SOURCE VOLTAGE (V)
Figure 4. On Resistance Variation with
Gate-To- Source Voltage.
Figure 3. On-Resistance Variation
with Temperature.
-1
0.5
T = -55°C
J
-I , REVERSE DRAIN CURRENT (A)
V DS = -5V
25°C
-0.75
125°C
-0.5
-0.25
VGS = 0V
0.1
T J = 125°C
25°C
0.01
-55°C
S
I D , DRAIN CURRENT (A)
0.2
25
1.6
0.6
-50
0.15
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 1. On-Region Characteristics.
1.4
0.1
-I D , DRAIN CURRENT (A)
-VDS , DRAIN-SOURCE VOLTAGE (V)
0
-0.5
-1
-1.5
-2
-2.5
V GS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
-3
0.0001
0
0.2
-V
SD
0.4
0.6
0.8
1
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Body Diode Forward Voltage
Variation with Source Current and
Temperature.
FDC6302P Rev.C
Typical Electrical And Thermal Characteristics
25
I D = -0.2A
VDS = -5V
15
-10
6
-15
CAPACITANCE (pF)
-V GS , GATE-SOURCE VOLTAGE (V)
8
4
2
C iss
10
Coss
5
3
2
0
0
0.1
0.2
0.3
0.4
f = 1 MHz
V GS = 0 V
1
0.1
0.5
Q g , GATE CHARGE (nC)
1m
RD
S(
IT
10
0m
m
s
VGS = -2.7V
SINGLE PULSE
R θJA =See Note 1b
TA = 25°C
0.02
0.01
1
2
15
25
SINGLE PULSE
RθJA =See note 1b
TA = 25°C
4
s
DC
0.05
10
5
1s
0.1
5
s
POWER (W)
10
3
2
1
5
10
20
0
0.01
40
0.1
1
10
100
300
SINGLE PULSE TIME (SEC)
- VDS , DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
-ID , DRAIN CURRENT (A)
0.5
0.2
2
Figure 8. Capacitance Characteristics.
0.8
)
ON
1
-V DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
LIM
Crss
0.3
0.5
D = 0.5
0.2
0.2
0.1
0.05
0.02
0.01
0.0001
RθJA (t) = r(t) * R θJA
R θJA = See Note 1b
0.1
P(pk)
0.05
t1
0.02
0.01
Single Pulse
0.001
t2
TJ - TA = P * R JA(t)
θ
Duty Cycle, D = t 1/ t 2
0.01
0.1
1
10
100
300
t 1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.
FDC6302P Rev.C
Similar pages