AD ADG1219BRJZ-REEL7 Low capacitance, low charge injection, â±15 v/12 v icmosâ ¢ spdt in sot-23 Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
<0.5 pC charge injection over full signal range
2.5 pF off capacitance
Low leakage; 0.6 nA maximum @ 85°C
120 Ω on resistance
Fully specified at +12 V, ±15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
8-lead SOT-23 package
ADG1219
SA
D
SB
DECODER
IN
EN
SWITCHES SHOWN FOR A LOGIC “0” INPUT
06575-001
Preliminary Technical Data
Low Capacitance, Low Charge Injection,
±15 V/12 V iCMOS™ SPDT in SOT-23
ADG1219
Figure 1.
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems
GENERAL DESCRIPTION
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required. Figure 2 shows that there is
0.5
0.4
TA = 25ºC
VDD = +15V
VSS = –15V
0.3
0.2
0.1
0
VDD = 12V
VSS = 0V
–0.1
–0.2
–0.3
VDD = +5V
VSS = –5V
–0.4
–0.5
–15
–10
–5
06574-041
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced
package size.
minimum charge injection over the entire signal range of the
device. iCMOS construction also ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery-powered instruments.
CHARGE INJECTION (pC)
The ADG1219 is a monolithic iCMOS device containing an
SPDT switch. An EN input is used to enable or disable the
device. When disabled, all channels are switched off. When on,
each channel conducts equally well in both directions and has
an input signal range that extends to the supplies. Each switch
exhibits break-before-make switching action.
0
5
10
15
INPUT VOLTAGE (V)
Figure 2. Charge Injection vs. Input Voltage
Rev. PrB
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADG1219
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
Applications....................................................................................... 1
ESD Caution...................................................................................6
Functional Block Diagram .............................................................. 1
Pin Configuration and Function Descriptions..............................7
General Description ......................................................................... 1
Terminology .................................................................................... 14
Revision History ............................................................................... 2
Typical Performance Characteristics ..............................................8
Specifications..................................................................................... 3
Test Circuits..................................................................................... 12
Dual Supply ................................................................................... 3
Outline Dimensions ....................................................................... 14
Single Supply ................................................................................. 4
Ordering Guide .......................................................................... 15
REVISION HISTORY
7/07—Revision 0: Initial Version
Rev. PrB | Page 2 of 17
Preliminary Technical Data
ADG1219
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameters
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
B Version1
−40°C to +85°C
−40°C to +125°C
VDD to VSS
120
190
3.5
6
20
60
230
260
10
12
72
79
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; see Figure 23
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
Ω max
Ω typ
Ω max
nA typ
±0.6
±1
nA max
nA typ
±0.1
±0.02
±0.2
±0.6
±1
VS = VD = ±10 V; see Figure 25
±0.6
±1
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
2.0
0.8
0.005
2
Break-Before-Make Time Delay, tBBM
Charge Injection
0.1
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
77
dB typ
Channel-to-Channel Crosstalk
80
dB typ
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
0.15
520
2.5
3.3
4.3
5.1
7.5
10
% typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
tOFF (EN)
200
230
130
140
150
170
10
CD (Off)
CD, CS (On)
VS = ±10 V, VS = ±10 V; see Figure 24
±0.1
±0.01
140
170
85
105
105
125
40
tON (EN)
VS = −5 V, 0 V, +5 V; IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
±0.01
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
Unit
Rev. PrB | Page 3 of 17
VS = ±10 V, VS = ±10 V; see Figure 24
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 27
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; see Figure 31
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
ADG1219
Parameters
POWER REQUIREMENTS
IDD
Preliminary Technical Data
25°C
B Version1
−40°C to +85°C
−40°C to +125°C
0.001
1.0
IDD
140
170
ISS
0.001
1.0
±5/±16.5
VDD/VSS
1
2
Unit
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V or VDD
|VDD | = |VSS|
Temperature range for B version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameters
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
B Version1
−40°C to +85°C −40°C to +125°C
0 V to VDD
300
475
4.5
16
60
±0.01
±0.1
±0.01
±0.1
±0.02
±0.2
567
625
26
27
±0.6
±1
±0.6
±1
±0.6
±1
2.0
0.8
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
3
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tBBM
195
250
120
150
145
185
70
Charge Injection
Off Isolation
−0.8
80
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
80
dB typ
−3 dB Bandwidth
400
MHz typ
tON (EN)
tOFF (EN)
300
340
190
210
220
235
10
Rev. PrB | Page 4 of 17
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = VD = 1 V or 10 V, see Figure 25
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 27
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29;
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
Preliminary Technical Data
Parameters
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
25°C
2.9
3.7
5
5.8
8.5
11
ADG1219
B Version1
−40°C to +85°C −40°C to +125°C
0.001
1.0
IDD
140
VDD
1
2
170
5/16.5
Temperature range for B version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. PrB | Page 5 of 17
Unit
pF typ
pF max
pF typ
pF max
pF typ
pF max
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
ADG1219
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, S or D
Continuous Current per
Channel, S or D
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
8-Lead SOT-23, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb Free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
100 mA (pulsed at 1 ms,
10% duty cycle maximum)
30 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
211.5°C/W
260°C
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. PrB | Page 6 of 17
Preliminary Technical Data
ADG1219
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN 1
VDD 2
8
ADG1219
IN
SA
TOP VIEW
6 D
(Not to Scale)
VSS 4
5 SB
7
NC = NO CONNECT
06575-003
GND 3
Figure 3. SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
EN
2
3
4
5
6
7
8
VDD
GND
VSS
SB
D
SA
IN
Description
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off.
When this pin is high, the IN logic input determines which switch is turned on.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Logic Control Input.
Table 5. Truth Table
EN
0
1
1
IN
X
0
1
Switch A
Off
On
Off
Switch B
Off
Off
On
Rev. PrB | Page 7 of 17
ADG1219
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
TA = 25°C
180
VDD = 13.5V
VSS = –13.5V
200
TA = +125°C
140
ON RESISTANCE (Ω)
120
VDD = 16.5V
VSS = –16.5V
100
80
60
100
TA = –40°C
0
–18 –15 –12
–9 –6 –3
0
3
6
9
SOURCE OR DRAIN VOLTAGE (V)
12
15
0
–15
18
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
–10
–5
0
5
TEMPERATURE (°C)
600
TA = 25°C
VDD = 4.5V
VSS = –4.5V
500
10
15
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
600
TA = +125°C
VDD = 12V
VSS = 0V
500
ON RESISTANCE (Ω)
VDD = 5V
VSS = –5V
400
VDD = 5.5V
VSS = –5.5V
300
200
100
TA = +85°C
400
TA = +25°C
300
TA = –40°C
200
–4
–2
0
2
SOURCE OR DRAIN VOLTAGE (V)
4
0
6
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
06575-008
06575-005
100
0
–6
0
2
4
6
8
TEMPERATURE (°C)
10
12
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
200
450
TA = 25°C
400
VDD = 10.8V
VSS = 0V
350
VDD = 12V
VSS = 0V
0
LEAKAGE (pA)
250
VDD = 13.2V
VSS = 0V
200
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
100
300
150
–100
–200
IS(OFF)+–
ID(OFF)+–
–300
IS(OFF)–+
100
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
ID,S(ON)++
ID,S(ON)– –
–500
14
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
ID(OFF)–+
–400
06575-006
50
0
06575-007
06575-004
20
ON RESISTANCE (Ω)
TA = +25°C
50
40
ON RESISTANCE (Ω)
TA = +85°C
150
06575-030
ON RESISTANCE (Ω)
160
VDD = 15V
VSS = –15V
VDD = 15V
VSS = –15V
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 9. Leakage Currents as a Function of Temperature, 15 V Dual Supply
Rev. PrB | Page 8 of 17
Preliminary Technical Data
ADG1219
350
0.5
300
ID(OFF)+–
0.4
250
IS(OFF)–+
ID(OFF)–+
0.3
CHARGE INJECTION (pC)
ID,S(ON)++
200
ID,S(ON)– –
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
150
100
50
0
VDD = +15V
VSS = –15V
0.2
0.1
0
VDD = 12V
VSS = 0V
–0.1
–0.2
–0.3
06575-031
–50
–100
TA = 25ºC
0
20
40
60
80
100
VDD = +5V
VSS = –5V
–0.4
–0.5
–15
120
–10
–5
TEMPERATURE (°C)
0
5
10
15
INPUT VOLTAGE (V)
Figure 10.Leakage Currents as a Function of Temperature, 12 V Single Supply
Figure 13. Charge Injection vs. Input Voltage
100
300
VDD = 5V
VSS = –5V
VBIAS = +4.5V/–4.5V
50
12V SS
250
0
200
TIME (ns)
LEAKAGE (pA)
06574-041
LEAKAGE (pA)
IS(OFF)+–
–50
IS(OFF)+–
–100
150
15V DS
100
ID(OFF)+–
IS(OFF)–+
ID(OFF)–+
50
06575-032
ID,S(ON)++
ID,S(ON)– –
–200
0
20
40
60
80
100
0
–40
120
06575-027
–150
–20
0
TEMPERATURE (°C)
Figure 11. Leakage Currents as a Function of Temperature, 5 V Dual Supply
40
60
80
100
120
Figure 14. tTRANSITION Time vs. Temperature
0
200
IDD PER CHANNEL
TA = 25°C
180
–10
–20
160
VDD = 15V
VSS = –15V
TA = 25ºC
–30
ISOLATION (dB)
VDD = +15V
VSS = –15V
140
120
100
80
60
–40
–50
–60
–70
–80
40
20
–100
0
0
2
4
6
8
10
LOGIC, INX (V)
06575-022
–90
VDD = +12V
VSS = 0V
12
14
16
06575-009
IDD (µA)
20
TEMPERATURE (ºC)
–110
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 15. Off Isolation vs. Frequency
Figure 12. IDD vs. Logic Level
Rev. PrB | Page 9 of 17
1G
ADG1219
Preliminary Technical Data
0
–20
8
VDD = 15V
VSS = –15V
TA = 25ºC
7
SOURCE/DRAIN ON
6
CAPACITANCE (pF)
CROSSTALK (dB)
–30
–40
–50
–60
–70
–80
5
DRAIN OFF
4
SOURCE OFF
3
2
–90
–110
10k
100k
1M
10M
100M
VDD = 15V
VSS = –15V
TA = 25ºC
1
06575-026
–100
0
–15
1G
–10
–5
FREQUENCY (Hz)
5
10
15
Figure 19. Capacitance vs. Source Voltage for Dual Supply
0
9
VDD = 15V
VSS = –15V
TA = 25ºC
8
SOURCE/DRAIN ON
7
–4
CAPACITANCE (pF)
INSERTION LOSS (dB)
0
SOURCE VOLTAGE (V)
Figure 16. Crosstalk vs. Frequency
–2
06575-023
–10
–6
–8
–10
6
DRAIN OFF
5
4
SOURCE OFF
3
2
100k
1M
10M
100M
0
06575-024
0
1G
2
4
FREQUENCY (Hz)
Figure 17. On Response vs. Frequency
10
12
10
LOAD = 10kΩ
TA = 25°C
9
CAPACITANCE (pF)
8
1.00
THD + N (%)
8
Figure 20. Capacitance vs. Source Voltage for Single Supply
10.00
VDD = 5V, VSS = –5V, VS = 3.5Vrms
VDD = 15V, VSS = –15V, VS = 5Vrms
0.10
06575-010
100
1k
FREQUENCY (Hz)
10k
100k
SOURCE/DRAIN ON
7
6
DRAIN OFF
5
4
SOURCE OFF
3
2
0.01
10
6
SOURCE VOLTAGE (V)
1
0
–5
VDD = 5V
VSS = –5V
TA = 25ºC
–3
06575-025
–14
10k
VDD = 12V
VSS = 0V
TA = 25ºC
1
06575-021
–12
–1
1
3
SOURCE VOLTAGE (V)
Figure 21. Capacitance vs. Source Voltage for Dual Supply
Figure 18. THD + N vs. Frequency
Rev. PrB | Page 10 of 17
5
Preliminary Technical Data
ADG1219
0
–10
–20
VDD = +15V
VSS = –15V
Vp-p = 0.63V
TA = 25ºC
NO DECOUPLING CAPS ON
–40
–50
–60
DECOUPLING CAPS ON
–70
–80
06576-025
PSRR (dB)
–30
–90
–100
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 22. ACPSRR vs Frequency
Rev. PrB | Page 11 of 17
ADG1219
Preliminary Technical Data
TEST CIRCUITS
V
S
D
IDS
06575-011
VS
Figure 23. On Resistance
A
S
D
ID (OFF)
A
06575-012
IS (OFF)
VD
VS
Figure 24. Off Leakage
ID (ON)
D
NC = NO CONNECT
A
VD
06575-013
S
NC
Figure 25. On Leakage
VDD
VSS
VDD
D
SA
VOUT
RL
300Ω
IN
VIN
VIN
50%
50%
VIN
50%
50%
VSS
SB
VS
0.1µF
CL
35pF
90%
VOUT
GND
tON
90%
tOFF
06575-014
0.1µF
Figure 26. Switching Times
0.1µF
VDD
VSS
VDD
VSS
SB
VS
0.1µF
VIN
D
SA
VOUT
RL
300Ω
IN
VOUT
CL
35pF
80%
tBBM
VIN
tBBM
06575-015
GND
Figure 27. Break-Before-Make Time Delay
VSS
VDD
VSS
0.1µF
VIN (NORMALLY
CLOSED SWITCH)
SB
VS
SA
IN
VIN
GND
ON
OFF
NC
D
VOUT
CL
1nF
VIN (NORMALLY
OPEN SWITCH)
VOUT
ΔVOUT
Figure 28. Charge Injection
Rev. PrB | Page 12 of 17
QINJ = CL × ΔVOUT
06575-016
0.1µF
VDD
Preliminary Technical Data
ADG1219
VDD
VDD
0.1µF
0.1µF
0.1µF
VDD
SA
IN
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
NC
SB
VOUT
50Ω
VDD
VSS
SA
RL
50Ω
SB
50Ω
D
VS
D
GND
OFF ISOLATION = 20 log
VOUT
IN
VS
GND
06575-017
RL
50Ω
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 29. Off Isolation
VDD
R
50Ω
06575-019
VIN
VOUT
VS
Figure 31. Bandwidth
VSS
0.1µF
VDD
NC
SB
SA
VDD
NETWORK
ANALYZER
VSS
VDD
50Ω
RS
IN
VOUT
VIN
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VS
V p-p
D
06575-018
INSERTION LOSS = 20 log
RL
50Ω
AUDIO PRECISION
VSS
S
D
GND
0.1µF
50Ω
VS
VIN
VSS
0.1µF
GND
RL
10kΩ
Figure 32. THD + Noise
Figure 30. Channel-to-Channel Crosstalk
Rev. PrB | Page 13 of 17
VOUT
06575-020
0.1µF
IN
VSS
0.1µF
VSS
ADG1219
Preliminary Technical Data
TERMINOLOGY
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
IDD
The positive supply current.
ISS
The negative supply current.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
TBBM
Off time measured between the 80% point of both switches
when switching from one address state to another.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINH
The minimum input voltage for Logic 1.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
IINL (IINH)
The input current of the digital input.
On Response
The frequency response of the on switch.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
Insertion Loss
The loss due to the on resistance of the switch.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
ACPSRR (AC Power Supply Rejection Ratio)
Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
Rev. PrB | Page 14 of 17
Preliminary Technical Data
ADG1219
OUTLINE DIMENSIONS
2.90 BSC
8
7
6
5
1
2
3
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.30
1.15
0.90
1.95
BSC
1.45 MAX
0.15 MAX
0.38
0.22
0.22
0.08
SEATING
PLANE
8°
4°
0°
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 33. 8-Lead Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1219BRJZ-R21
ADG1219BRJZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Lead Small Outline Transistor Package [SOT-23]
8-Lead Lead Small Outline Transistor Package [SOT-23]
Z = RoHS Compliant Part.
Rev. PrB | Page 15 of 17
Package Option
RJ-8
RJ-8
Branding
S24
S24
ADG1219
Preliminary Technical Data
NOTES
Rev. PrB | Page 16 of 17
Preliminary Technical Data
ADG1219
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06575-0-3/08(PrB)
Rev. PrB | Page 17 of 17