TI1 DRV3210QPHPRQ1 Drv3210-q1 three-phase brushless motor driver Datasheet

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DRV3210-Q1
SLVSC08B – MAY 2013 – REVISED JULY 2016
DRV3210-Q1 Three-Phase Brushless Motor Driver
Not Recommended for New Designs
1 Features
3 Description
•
The DRV3210-Q1 device is a field-effect transistor
(FET) pre-driver designed for three-phase motor
control for applications such as an oil pump or a
water pump. The device has three high-side pre-FET
drivers and three low-side drivers which are under the
control of an external MCU. A charge pump supplies
the power for the high side, and there is no
requirement for a bootstrap capacitor. For
commutation, this integrated circuit (IC) sends a
conditional motor signal and output to the MCU.
Diagnostics provide undervoltage, overvoltage,
overcurrent, overtemperature and power-bridge
faults. One can measure the motor current using an
integrated current-sense amplifier and comparator in
a battery common-mode range, which allows the use
of the motor current in a high-side current-sense
application. External resistors set the gain. One can
configure the pre-drivers and other internal settings
through the SPI.
1
•
•
•
•
•
•
•
•
•
•
•
•
3-Phase Pre-Drivers for N-Channel MOS FieldEffect Transistors (MOSFETs)
Pulse-Width Modulation (PWM) Frequency up to
20 kHz
Fault Diagnostics
Charge Pump
Phase Comparators
Microcontroller (MCU) Reset Generator
Serial Port I/F (SPI)
Motor-Current Sense
5-V Regulator
Low-Current Sleep Mode
Operation VB Range From 5.3 to 28.5 V
AEC-Q100 Grade 1 –40°C to +125°C Ambient
Operating Temperature
48-Pin PHP
Device Information(1)
2 Applications
•
•
•
PART NUMBER
Oil pump
Fuel pump
Water pump
DRV3210-Q1
PACKAGE
BODY SIZE (NOM)
HTQFP (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Schematic
VB
VB
100nF
1uF
100uF
PGND
PGND
ALP
VCC
100uF
AREF
100nF
30KÖ
1KÖ
10nF
TEST
1mÖ
GND
ALM
GND
ALV
ALFB
30KÖ
1KÖ
4.7pF
CTLUH
CTLVH
UH
10Ö
CTLWH
UHS
CTLUL
CTLVL
UL
10Ö
CTLWL
DRV3210-Q1
Controller
PMV3
VH
10Ö
PMV2
PMV1
VHS
RES
VL
BLDC
Motor
10Ö
PRN
FAULT
CS
SCK
WH
10Ö
WHS
DIN
WL
10Ö
DOUT
VDD
1uF
GND
PGND
100nF
GND
PHTM
ENABLE
PH1M
100KÖ
30KÖ
15pF
10KÖ
100KÖ
10KÖ
15pF
10KÖ
100KÖ
10KÖ
GND
2.2uF
VB
47nF
0Ö
1uF
PDCPV
CPRD4
PH2M
15pF
10KÖ
100KÖ
10KÖ
15pF
10KÖ
CPRD3
100nF
47Ö
CPRD2
CPRD1
PH3M
NGND
GND
GND
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Not Recommended for New Designs
DRV3210-Q1
SLVSC08B – MAY 2013 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
5
5
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Supply Voltage and Current......................................
Detailed Description ............................................ 13
7.1 Functional Block Diagram ....................................... 13
7.2 Feature Description................................................. 14
7.3 Register Maps ......................................................... 24
8
Application and Implementation ........................ 31
8.1 Typical Application .................................................. 31
9
Device and Documentation Support.................. 32
9.1
9.2
9.3
9.4
9.5
Receiving Notification of Documentation Updates.. 32
Community Resources............................................ 32
Trademarks ............................................................. 32
Electrostatic Discharge Caution .............................. 32
Glossary .................................................................. 32
10 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2013) to Revision B
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Application and
Implementation section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
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Product Folder Links: DRV3210-Q1
Not Recommended for New Designs
DRV3210-Q1
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SLVSC08B – MAY 2013 – REVISED JULY 2016
5 Pin Configuration and Functions
WH
WHS
VH
VHS
UH
UHS
CPDR4
PDCPV
CPDR3
CPDR1
NGND
CPDR2
PHP Package
48-PIN HTQFP
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
VB
1
36
FAULT
TEST
2
35
PRN
CTLUH
3
34
DIN
CTLVH
4
33
SCK
CTLWH
5
32
CS
UL
6
31
VDD
DOUT
DRV3210-Q1
VL
7
30
WL
8
29
GND
CTLUL
9
28
PHTM
CTLVL
10
27
PH1M
CTLWL
11
26
PH2M
VCC
12
25
PH3M
RES
ENABLE
PMV1
PMV2
AREF
PMV3
ALFB
ALP
ALM
ALV
NC
NC
13 14 15 16 17 18 19 20 21 22 23 24
Pin Functions
PIN
TYPE
MAXIMUM
RATING
18
O
–0.3 V-40 V
Motor current-sense amplifier feedback
16
I
–0.3 V-40 V
Motor current- sense amplifier negative input
17
I
–0.3 V-40 V
Motor current- sense amplifier positive input
15
O
–0.3 V-6 V
Motor current- sense amplifier output
AREF
19
O
–0.3 V-40 V
Reference output of motor current- sense amplifier
CPDR1
47
O
–0.3 V-40 V
Charge-pump output
CPDR2
46
O
–0.3 V-40 V
Charge- pump output
CPDR3
45
O
–0.3 V-40 V
Charge- pump output
CPDR4
44
O
–0.3 V-40 V
Charge- pump output
CS
32
I
–0.3 V-6 V
SPI chip select
CTLUH
3
I
–0.3 V-6 V
Pre-driver parallel input
CTLUL
9
I
–0.3 V-6 V
Pre-driver parallel input
CTLVH
4
I
–0.3 V-6 V
Pre-driver parallel input
CTLVL
10
I
–0.3 V-6 V
Pre-driver parallel input
CTLWH
5
I
–0.3 V-6 V
Pre-driver parallel input
CTLWL
11
I
–0.3 V-6 V
Pre-driver parallel input
DIN
34
I
–0.3 V-6 V
SPI data input
DOUT
30
O
–0.3 V-6 V
SPI data output
NAME
NO.
ALFB
ALM
ALP
ALV
DESCRIPTION
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3
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SLVSC08B – MAY 2013 – REVISED JULY 2016
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Pin Functions (continued)
PIN
NAME
NO.
TYPE
MAXIMUM
RATING
DESCRIPTION
ENABLE
23
I
–0.3 V-40 V
Enable input
FAULT
36
O
–0.3 V-6 V
Diagnosis output
GND
29
I
–0.3 V-0.3 V
GND
NGND
48
I
–0.3 V-0.3 V
Power GND
PDCPV
43
O
–0.3 V-40 V
Charge pump output
PH1M
27
I
–1 V-40 V
Phase comparator input
PH2M
26
I
–1 V-40 V
Phase comparator input
PH3M
25
I
–1 V-40 V
Phase comparator input
PHTM
28
I
–1 V-40 V
Phase comparator reference input
PMV1
22
O
–0.3 V-6 V
Phase comparator output
PMV2
21
O
–0.3 V-6 V
Phase comparator output
PMV3
20
O
–0.3 V-6 V
Phase comparator output
PRN
35
I
–0.3 V-6 V
Watchdog timer-pulse input
RES
24
O
–0.3 V-6 V
MCU reset output
SCK
33
I
–0.3 V-6 V
SPI clock
TEST
2
I
–0.3 V-20 V
TEST input
UH
42
O
–5 V-40 V
Pre-driver output
UHS
41
O
–5 V-40 V
Pre-driver reference
UL
6
O
–0.3 V-20 V
Pre-driver output
VB
1
I
–0.3 V-40 V
VB input
VCC
12
I
–0.3 V-6 V
VCC supply input
NC
13
Not connected
NC
14
Not connected
VDD
31
O
–0.3 V-3.6 V
VH
40
O
–5 V-40 V
Pre-driver output
VHS
39
O
–5 V-40 V
Pre-driver reference
VL
7
O
–0.3 V-20 V
Pre-driver output
WH
38
O
–5 V-40 V
Pre-driver output
WHS
37
O
–5 V-40 V
Pre-driver reference
WL
8
O
–0.3 V-20 V
VDD supply output
Pre-driver output
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
TA
Operating temperature range
–40
125
ºC
TJ
Junction temperature
–40
150
ºC
Tstg
Storage temperature
–55
175
ºC
6.2 ESD Ratings
VALUE
V(ESD)
(1)
4
Electrostatic discharge (1)
Human body model (HBM)
±2000
Charged-device model (CDM)
±500
UNIT
V
Performance of ESD testing is according to the ACE-Q100 standard.
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Not Recommended for New Designs
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SLVSC08B – MAY 2013 – REVISED JULY 2016
6.3 Thermal Information
DRV3210-Q1
THERMAL METRIC (1)
PHP (HTQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
11.5
°C/W
RθJB
Junction-to-board thermal resistance
7.2
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Electrical Characteristics
VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WATCHDOG
VSTN (1)
(1)
tON
tOFF
(1)
Function start VCC voltage RES
-
0.8
1.3
V
Power-on time RES
2.5
3
3.5
ms
Clock-off reset time RES
64
80
96
ms
tRL
(1)
Reset-pulse low time RES
16
20
24
ms
tRH
(1)
Reset-pulse high time RES
64
80
96
ms
30
71.5
90
µs
2
-
-
µs
tRES
(1)
Reset delay time RES
Pwth
(1)
Pulse duration PRN
See Figure 1
SPI
fop
SPI clock frequency
tlead
Enable lead time
-
4
MHz
200
-
-
ns
twait
Wait time between two successive
communications
5
-
-
µs
tlag
tpw
Enable lag time
100
-
-
ns
SCLK pulse duration
100
-
-
ns
tsu
Data setup time
100
-
-
ns
th
Data hold time
100
-
-
ns
tdis
Data-output disable time
-
-
200
ns
ten
Data-output enable time
tv
Data delay time, SCK to DOUT
CL = 50 pF, see Figure 23.
-
-
100
ns
0
-
100
ns
CHARGE PUMP
Vchv1_0
Output voltage, PDCPV
VB = 5.3 V, load = 0 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+7
VB+8
-
V
Vchv1_1
Output voltage, PDCPV
VB = 5.3 V, Ioad = 5 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+5.5
VB+6.5
-
V
Vchv1_2
Output voltage, PDCPV
VB = 5.3 V, Ioad = 8 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+4.5
VB+5.5
-
V
Vchv2_0
Output voltage, PDCPV
VB = 12 V, Ioad = 0 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
Vchv2_1
Output voltage, PDCPV
VB = 12 V, Ioad = 11 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+9.5
VB+11.5
VB+13.5
V
(1)
Specified by design.
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Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Vchv2_2
Output voltage, PDCPV
Vchv3_0
UNIT
VB = 12 V, Ioad = 18 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+9
VB+11
VB+13
V
Output voltage, PDCPV
VB = 18 V, Ioad = 0 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
Vchv3_1
Output voltage, PDCPV
VB = 18 V, Ioad = 13 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
Vchv3_2
Output voltage, PDCPV
VB = 18 V, Ioad = 22 mA, C1 = C2 =
47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
VchvOV
Overvoltage detection threshold
VchvUV
Undervoltage detection threshold
tchv
Rise time
Ron
On-resistance, S1-S4
35
37.5
40
V
VB+4
VB+4.5
VB+5
V
VB = 5.3 V, C1 = C2 = 47 nF, CCP
= 2.2 µF,
R1 = R2 = 0 Ω, Vchv, UV released
1
2
See Figure 10
8
ms
Ω
HIGH-SIDE PRE-DRIVER
VOH_H
Output voltage, turnon side
Isink = 10 mA, PDCPV - xH
VOL_H
Output voltage, turnoff side
Isource = 10 mA, xH - xHS
RONH_HP On-resistance, turnon side (Pch)
U(V/W)H = PDCPV - 1 V
RONH_HN On-resistance, turnon side (Nch)
U(V/W)H = PDCPV - 2.5 V
1.35
2.7
V
25
50
mV
135
270
Ω
4
8
Ω
2.5
5
Ω
RONL_H
On-resistance turnoff side
ton_h1
Turnon time
CL = 12 nF, RL = 0 Ω from 20% to
80%
50
-
200
ns
toff_h1
Turnoff time
CL = 12 nF, RL = 0 Ω from 80% to
20%
50
-
200
ns
th-ondly1
Output delay time
CL = 12 nF, RL = 0 Ω to 20%, no
dead time
-
200
-
ns
th-offdly1
Output delay time
CL = 12 nF, RL = 0 Ω to 80%, no
dead time
-
200
-
ns
VGS_hs
Gate-source high -side voltage
difference
xH-xHS
18
V
–0.3
LOW-SIDE PRE-DRIVER
VOH_L1
Output voltage, turnon side
VB = 12 V, Isink = 10 mA, xL NGND
10
12
14
V
VOH_L2
Output voltage, turnon side
VB = 5.3 V, Isink = 10 mA, xL NGND
5.5
7.5
10
V
VOL_L
Output voltage, turnoff side
Isource = 10 mA, xL - NGND
-
25
50
mV
RONH_L
On-resistance, turnon side
-
6
12
Ω
RONL_L
On-resistance, turnoff side
2.5
5
Ω
ton_l
Turnon time
CL = 18 nF, RL = 0 Ω,
from 20% to 80% of 12 V,
from 20% to 80% of 6 V (VB = 5.3
V)
50
-
200
ns
toff_h
Turnoff time
CL = 18 nF, RL = 0 Ω,
from 80% to 20% of 12 V,
from 80% to 20% of 6 V (VB = 5.3
V)
50
-
200
ns
tl-ondly
Output delay time
CL = 18 nF, RL = 0 Ω,
to 20% of 12 V,
to 20% of VOH = 6 V (VB = 5.3 V),
no dead time
-
200
-
ns
6
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SLVSC08B – MAY 2013 – REVISED JULY 2016
Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-
200
-
ns
tl-offdly
Output delay time
CL = 18 nF, RL = 0 Ω,
to 80% of 12 V,
to 80% of VOH = 6 V (VB = 5.3 V),
no dead time
tdiff1
Differential time1
(Th-on) - (Tl-off), no dead time,
See Figure 3
–200
0
200
ns
tdiff2
Differential time2
(Tl-on) - (Tl-off), no dead time,
See Figure 3
–200
0
200
ns
Dead time
OSC1 = 10 MHz SPI register
PDCFG.DEADT
2.2
1.7
1.2
0.7
µs
tdead
2
1.5
1
0.5
PHASE COMPARTOR
Viofs
Input offset voltage
–15
-
15
mV
Vinm1
Input voltage range, PHTM
Vinm2
Input voltage range, PHTM
VB = 6 V - 28.5 V
1.3
-
4.5
V
VB = 5.3 V
1.3
-
4.2
Vinp
Input voltage range, PHxM
V
–1
-
VB
V
Vhys
Threshold hysteresis voltage
SPI register SPARE.
SEL_COMP_HYS
-
0
-
mV
12.5
25
50
25
50
100
50
100
200
VOH
Output high voltage
Isink = 2.5 mA
VOL
Output low voltage
Isource = 2.5 mA
0.9 × VCC
-
-
V
-
-
0.1 × VCC
V
tres_tr
Response time, rising
tres_tf
Response time, falling
CL = 100 pF
-
0.7
1.5
µs
CL = 100 pF
-
0.7
1.5
µs
MOTOR CURRENT SENSE
VOfs
Input offset voltage
–5
VO_0
Output voltage, ALV
Imotor = 0 A, SPI register CSCFG.
CSOFFSET
VLine
Linearity, ALV
Rshunt = 1 mΩ,
R11 = R12 = 1 kΩ,
R21 = R22 = 30 kΩ
VGain
Gain
5
mV
-
0.5
1
1.5
2
2.5
-
V
29.4
30
30.6
mV/A
10
30
-
V/V
-
1
2.5
µs
Tset_TR1
Settling time (rise), ALV ±1%
Rshunt = 1 mΩ, VGain = 30, CL =
100 pF,
Imotor = 0 A → 30 A,
(ALV: 1 V → 1.9 V, AREF = 1 V)
Tset_TR2
Settling time(rise), ALV ±1%
Rshunt = 1 mΩ, VGain = 30, CL =
100 pF,
Imotor = 0 A → 100 A,
(ALV: 1 V → 4 V, AREF = 1 V)
-
1
2.5
µs
Tset_TF1
Settling time(fall), ALV ±1%
Rshunt = 1 mΩ, VGain = 30, CL =
100 pF,
Imotor = 30 A → 0,
(ALV: 1.9 V → 1 V, AREF = 1 V)
-
1
2.5
µs
Tset_TF2
Settling time(fall), ALV ±1%
Rshunt = 1 mΩ, VGain = 30, CL =
100 pF,
Imotor = 100 A → 0,
(ALV: .4 V → 1 V, AREF = 1 V)
-
1
2.5
µs
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Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified)
PARAMETER
OVADth
Overcurrent threshold
TDEL_OV
AD
Propagation delay
(rise or fall)
tfiltMTOC
filtering time
TEST CONDITIONS
Rshunt = 1 mΩ, VGain = 30, AREF
= 1 V, ADTH = 2.5 V,
SPI register FLTCFG. MTOCTH,
OVADth = (2 × ADTH -- AREF) /
(Rshunt × VGain)
OSC1 = 9 MHz-11 MHz
MIN
TYP
MAX
UNIT
119.7
133
146.3
A
-
-
1.5
µs
0.8
1
1.2
µs
4.9
5
5.1
V
VCC
VCC1
Output Voltage
VCC2
Output Voltage
ILVCC
Load Current
VLRVCC
Load regulation
CVCC
External Capacitance
VCCUV
Under voltage detection threshold
VB = 4.5 V, ILVCC = 50 mA
50
ILVCC = 50 mA
Overvoltage detection threshold
VCCOC
Current Limit
Tvcc1
Rise Time
–50
4.5
SPI register FLTCFG. VCCUVTH
V
-
-
mA
-
50
mV
10
VCCUVHY Under voltage detection threshold
S
hysteresis
VCCOV
4.1
µF
3.7
3.9
4
4.2
4.3
4.5
V
50
100
200
mV
6
6.5
7
100
150
300
mA
0.5
ms
VCC > VCCUV, CVCC = 10 µF
V
VDD
VDD
Output Voltage
CVDD
Load Capacitance
VDDUV
Under voltage detection threshold
VDDOV
Overvoltage detection threshold
Tvdd
Rise Time
3
3.3
3.6
1
2.1
2.3
4
4.3
VDD > VDDUV, CVDD=1µF
V
µF
2.5
V
4.6
V
100
µs
VB MONITOR
VBOV
VB overvoltage detection threshold
level
26.5
27.5
28.5
V
VBUV
VB Undervoltage detection threshold
SPI register FLTCFG. VBUVTH
level
3.65
4.15
4.65
5.15
4
4.5
5
5.5
4.35
4.85
5.35
5.85
V
155
175
195
°C
5
10
15
°C
9
10
11
MHz
THERMAL SHUT DOWN
TSD
Thermal shut down threshold level
TSDhys
Thermal shut down hysteresis
OSCILLATOR
OSC1
OSC1 frequency
OSC2
OSC2 frequency
10
MHz
INPUT BUFFER1
VIH
Input threshold logic high
VIL
Input threshold logic low
Ru or Rd
Input pullup or pulldown resistance
0.7 × VCC
50
V
100
0.3 × VCC
V
150
kΩ
OUTPUT BUFFER1(2)
VOH
Output level logic high
Isink = 2.5 mA
VOL
Output level logic low
Isource = 2.5 mA
0.9 × VCC
V
0.1 × VCC
V
4
kΩ
OUTPUT BUFFER3
R_RES
8
Pull up Resistor
2
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Electrical Characteristics (continued)
VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified)
PARAMETER
VOL
TEST CONDITIONS
Output level logic low
MIN
TYP
Isource = 2 mA
MAX
UNIT
0.1 × VCC
V
6.5 Supply Voltage and Current
VB = 12 V, TA = –40°C to +125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY INPUT
VB1 (1)
VB supply voltage (motor operation) Full device functionality
5.3
12
18
V
VB2 (1)
VB supply voltage (MCU operation)
4.5
12
18
V
VB3 (2)
VB supply voltage
18
-
28.5
V
Ivb
VB operating current
ENABLE = High, no PWM
-
18
27
mA
Ivbq
VB quiescent current
ENABLE = Low
-
50
100
µA
(1)
(2)
Full device functionality
Performance of supply voltage 5.3 to 18 V is according to the ACE-Q100 (Grade 1) standard.
Specified by design.
VCC
VCCUV
VSTN
tRES
VDDUV
VDD
tRH
tRES
RES
tON
tON
tON
tRL
PRN
Pwth
tOFF
Rising edge of PRN is
detected to reset
watchdog timer.
NOTE: VCC undervoltage condition sets RES = Low.
Figure 1. Watchdog Timing Chart
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tlead
tpw
ttwaitt
tlag
tpw
CS
SCK
DIN
MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
th
tsu
MSB
DOUT
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
HiZ
HiZ
tdel
ten
tdis
Figure 2. SPI Timing Diagram
CTLUH
CTLVH
CTLWH
CTLUL
CTLVL
CTLWL
th-ondly
UH
VH
WH
th-offdly
80%
80%
20%
20%
th-on(th-ondly + ton)
UL
VL
WL
80%
xHS
th-off(th-offdly + toff)
80%
20%
NGND
20%
tl-offdly
tl-ondly
tl-off(tl-offdly + toff)
tl-on(tl-ondly + ton)
NOTE: This diagram excludes dead time to explain the timing parameters of the pre-driver.
Figure 3. Delay Time From Input to Output
10
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CTLUH
CTLVH
CTLWH
CTLUL
CTLVL
CTLWL
UH
VH
WH
tdead + th-ondly
th-offdly
UL
VL
WL
tl-offdly
tdead + tl-ondly
Figure 4. Dead Time
ALV
ALFB/2
VCC
ADTH
VLine
=´Y/´X
´Y
´X
VO_0
0A
Imotor
OVAD
0A
Imotor
Figure 5. Motor Current Sense and Overcurrent
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Motor Current
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OVADth
OVAD
tfiltMTOC
tfiltMTOC
MTOC SPI Register Flag
SPI Access
read
write 1
to clear
FAULT
Pre-Driver
Enable
Disable
Enable
(1)
MCU must set the FLTCFG.FLGLATCH_EN bit to 1 to get the latch-type operation shown in this figure.
(2)
When MTOC condition is detected, FAULT is asserted to low if FE_MTOC bit is 1.
(3)
When MTOC condition is detected, Pre Driver is disabled if SE_MTOC is 1.
Figure 6. Motor Overcurrent Event
VB
Enable
VCC
VDD
Band Gap
Charge Pump
VIH
Sleep
VIL
Device Active
Sleep
Figure 7. I/O ENABLE Timing Chart
12
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7 Detailed Description
7.1 Functional Block Diagram
1
Charge Pump
TEST
(OPEN)
2
VHS
WH
WHS
42
41
40
39
38
37
PDCPV
43
VH
44
UHS
45
UH
CPRD4
PDCPV
CPRD3
46
PDCPV
VB
47
PDCPV
48
CPRD2
NGND
CPRD1
VB
36
FAULT
35
PRN
VMS
TEST I/F
VM
VB
Battery
CTLUH
3
CTLVH
4
CTLWH
5
VCP12
VB
Monitor
TSD
34
DIN
33
SCK
32
CS
UH
VH
WH
Control Logic
UL
6
VL
7
VCP12
31
3.3V Reg
VDD
WHS
VHS
30
8
CTLUL
9
M
UHS
OVAD
NGND
WL
DOUT
OSC
VCC
WD
29
GND
UL
COMP
+
28
ADTH
CTLWL
11
12
5V Reg
AMP
18
19
AREF
ALFB
ALP
ALM
ALV
20
21
22
23
24
RES
17
27
PH1M
26
PH2M
25
PH3M
VL
WL
UHS
VHS
SLEEP
ENABLE
16
VCOM
+
PMV1
15
-
PMV2
14
+
PMV3
13
-
VB
AMP
VCC
VCC
+
COMP
-
COMP
10
COMP
VCC
CTLVL
PHTM
WHS
VM
VMS
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7.2 Feature Description
7.2.1 Watchdog
A watchdog monitors the PRN signal and VCC supply level and generates a reset to the MCU via the RES pin if
the status of PRN is not normal or if VCC is lower than the specified threshold level. Detection of a special
pattern on the PRN input during power up can disable the watchdog.
VCC
VDD
3k
VDD Under Voltage
Detection
RES
To MCU
Max 100pF
VCC
VCC Under Voltage
Detection
Reset
Logic
OSC1
Clock
Monitor
VCC
100k
PRN
Watch Dog Timer
WDT
WDT
Enable
From MCU
Digital Pattern
Detection
Figure 8. Watchdog Block Diagram
14
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Feature Description (continued)
7.2.2 Serial Port I/F
Setting device configuration and reading out diagnostic information is via SPI. SPI operates in slave mode. SPI
uses four signals according to the timing chart of Figure 2.
Status
CS
SPI Control Logic and
8-Bit Shift Register
Enable
8-Bit Shift Register
DOUT
DIN
SCK
Address
Write Data
Register Map
Read Data
System Clock
Figure 9. Block Diagram of SPI
7.2.2.1
CS - Chip Select
The MCU uses CS to select the IC. CS is normally high, and communication is possible only when it is forced
low. When CS falls, communication between the IC and the MCU starts. The transmitted data are latched and
the DOUT output pin comes out of high impedance. When CS rises, communication stops. The DOUT output pin
goes into high impedance. The next falling edge starts another communication. There is a minimum waiting time
between the two communications (twait). The pin has an internal pullup.
7.2.2.2 SCK - Synchronization Serial Clock
The MCU uses SCK to synchronize communication. SCK is normally low, and the valid clock-pulse number is 16.
At each falling edge, the MCU writes a new bit on the DIN input, and the IC writes a new bit on the DOUT output
pin. At each rising edge, the IC reads the new bit on DIN, and the MCU reads the new bit on DOUT. The
maximum clock frequency is 4 MHz. The pin has an internal pulldown.
7.2.2.3 DIN - Serial Input Data
DIN receives 16-bit data. The order of received bits is from the MSB (first) to the LSB (last). The pin has an
internal pulldown. Update of the internal register with the received bits occurs only if the number of clock pulses
is 16 while CS is low.
7.2.2.4 DOUT - Serial Output Data
DOUT transmits 16-bit data. It is a three-state output, and it is in the high-impedance state when CS is high. The
order of serial data-bit transmission is from the MSB (first) to the LSB (last).
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Feature Description (continued)
7.2.3 Charge Pump
The charge-pump block generates a supply for the high-side and low-side pre-drivers to maintain the gate
voltage on the external FETs. Use of an external storage capacitor (CCP) and bucket capacitors (C1, C2)
supports pre-driver slope and switching-frequency requirements. R1 and R2 reduce switching current if required.
The charge pump has voltage-supervisor functions such as over- and undervoltage, and selectable stop
conditions for pre-drivers.
VB
CP Supervisor
CP Logic
CP12
CPCLK
PDCPV
S2
VF
UV
MAX
CPDR2
C1
R1
CPDR1
S1
NGND
PDCPV
S4
VF
VF
CCP
CPDR4
C2
R2
CPDR3
S3
NGND
Figure 10. Charge-Pump Block Diagram
16
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Feature Description (continued)
7.2.4 Pre-Driver
The pre-driver block provides three high-side pre-drivers and three low-side pre-drivers to drive external Nchannel MOSFETs. The turnon side of the high-side pre-drivers supplies the large N-channel transistor current
for quick charge, and PMOS supports output voltages up to PDCPV. The turnoff side of the high-side pre-drivers
supplies the large N-channel transistor current for quick discharge. The low-side pre-drivers supply the large Nchannel transistor current for charge and discharge. VCP12 (created by a charge pump) controls the output
voltage of the low-side pre-driver to output less than 18 V. The pre-driver has a stop condition in some fault
conditions (Fault Detection) and SPI set (Serial Port I/F).
High Side Pre Driver
PDCPV
CTLxH
H : PU on
L : PD on
PD CTRL
UH/V
H/WH
RL
CL
UHS/
VHS/
WHS
Low Side Pre Driver
VCP12
CTLxL
H : PU on
L : PD on
PD CTRL
PDCPV
LVS
UL/VL
/WL
RL
CL
NGND
Figure 11. Pre-Driver Block Diagram
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Feature Description (continued)
7.2.5 Phase Comparator
The three-channel comparator module monitors the external FETs by detecting the drain-source voltage across
the high-side and low-side FETs. PHTM is the threshold level of the comparators usable for sensorless
communication. Figure 12 shows an example of the threshold level.
UHS,
VHS,
WHS
PH1M
PH2M
PH3M
VB
VCC
+
Clamp
PHTM
PMV1
PMV2
PMV3
-
Clamp
Figure 12. Phase Comparator Block Diagram
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Feature Description (continued)
7.2.6 Motor-Current Sense
The operational amplifier operates with an external-resistor network for higher flexibility to adjust the current
measurement to application requirements. The first-stage amplifier operates with the external resistor and the
output voltage up to VB at ALFB. External resistors can adjust amplifier gain by 10 to 30 times. The secondstage amplifier is buffered to MCU at ALV. The current sense has a comparator for motor overcurrent (OVAD).
ADTH is the overcurrent threshold level and set value by SPI. Figure 13 shows the curve of the detection level.
ALFB is divided by 2. Compare this value with ADTH. In recommended application, zero-point adjustment is
required as large-error offset in initial condition.
OVAD
VCC
+
-
ADTH
1/2ALFB
CLAMP
VCC
CLAMP
+
ALV
-
VB
-
ALFB
+
R22
C1
Battery
R11
ALP
ALM
Imotor
Rshunt
R12
R21
VCC
M
AREF
+
-
DC
C2
CLAMP
*R11, R12, R21, R22 z 0.1%
*VGain
X10: R11 = R12 = 3 k , R21 = R22 = 30 k
X20: R11 = R12 = 1.5 k , R21 = R22 = 30 k
X30: R11 = R12 = 1 k , R21 = R22 = 30 k
*C1 = 0~10 pF
*C2 = 10 nF
*AREF: 0.5/1.0/1.5/2.0/2.5 V (SPI)
*ADTH: 2.0/2.5/3.0/3.5/4.0 V (SPI)
*ALV = VGain * (Rshunt * Imotor) + AREF
*OVADth = (2 * ADTH - AREF) / (Rshunt * VGain)
Figure 13. Motor Current-Sense Block Diagram
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Feature Description (continued)
7.2.7 Regulators
The regulator block offers 5-V LDO and 3.3-V LDO. The VCC LDO regulates VB down to 5 V with an external
PNP controlled by the regulator block. The 5-V LDO is supplied to MCU and other components.
The VDD regulator regulates VB down to 3.3 V with internal FET and controller. The 5-V LDO is protected
against short to GND fault. Overvoltage and under voltage events of both supplies are detected. The under
voltage of the 5-V LDO is set by SPI.
Current
Limit
OC
VB
+
BG
AMP
-
CVCC
VCC
OV
Superviser
UV
Figure 14. VCC Block Diagram
VB
+
BG
AMP
-
CVDD
VDD
OV
Superviser
UV
Figure 15. VDD Block Diagram
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Feature Description (continued)
7.2.8 VB Monitor
The VB monitoring system has two comparators for under- and overvoltage, and has a pre-driver stop-controlling
system. Overvoltage provides a selectable pre-driver stop condition (SPI control), while undervoltage must stop
pre-driver operation under detection (no selectable). The system should return to normal operation automatically
after the undetected level.
+
VB
VB_OV
VB_UV
VREF
-
Figure 16. VB Monitor Block Diagram
7.2.9 Thermal Shutdown
The device has temperature sensors that produce pre-driver stop condition if the chip temperature exceeds 175
degrees.
IPTAT
TSD
Figure 17. Thermal Shutdown Block Diagram
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Feature Description (continued)
7.2.10 Oscillator
The oscillator block generates two 10-MHZ clock signals. OSC1 is the primary clock used for internal logicsynchronization and timing control. OSC2 is the secondary clock used to monitor the status of OSC1.
OSC1(OSC2)
VREF
Figure 18. Oscillator Block Diagram
7.2.11 I/O
VCC
VDD
VCC
VCC
VDD
VDD
DIN
SCK
CTLxx
TEST
VDD
Ru
CS
PRN
Level Shift
Level Shift
Rd
CLAMP
V5INT
V5INT
ENABLE
Rd
* V5INT is the internal power supply.
Figure 19. Input Buffer1 Block Diagram
VDD
VCC
VCC
Level Shift
FAULT
Figure 20. Output Buffer1 Block Diagram
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Feature Description (continued)
VDD
VCC
VCC
Level Shift
DOUT
EN
Figure 21. Output Buffer2 Block Diagram
VCC
VDD
VCC
R_RES
VCC
RES
Level Shift
Figure 22. Output Buffer3 Block Diagram
Table 1. Recommended Pin Termination
PIN NAME
DESCRIPTION
TERMINATION
TEST
Test mode input
OPEN
7.2.12 Fault Detection
Table 2. Fault Detection
SPI FLTFLG
Pre Driver (1)
FAULT (2)
RES
VB - Overvoltage
VBOV
Disable
L
H
VB - Undervoltage
VBUV
Disable
L
H
CP - Overvoltage
CPOV
Disable
L
H
CP - Undervoltage
CPUV
Disable
L
H
VCC - Overvoltage
VCCOV
Disable
L
H
-
Disable (3)
H
L
VCCOC
Disable
L
H
Motor - Overcurrent
MTOC
Disable
L
H
VDD - Overvoltage
VDDOV
Disable
L
H
VDD - Undervoltage
-
Disable (3)
H
L
ITEMS
VCC - Under Voltage
VCC - Overcurrent
Thermal shutdown
TSD
Disable
L
H
Watch Dog
-
-
H
L
Clock Monitor
-
-
H
L
SPI format error
-
-
H
H
(1)
(2)
(3)
Others
SPI serial out error bit
Pre-driver is disabled if the conditions occur and SDNEN register bits are 1.
FAULT pin is asserted to low if the conditions occur and FLTEN register bits are 1.
Pre-driver is disabled by VCC undervoltage and VDD undervoltage conditions regardless of SPI register setting.
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7.3 Register Maps
Table 3. SPI Serial Input Format
MSB
D14
D13
D12
D11
D10
D9
D8
RW[1]
RW[0]
Addr[5]
Addr[4]
Addr[3]
Addr[2]
Addr[1]
Addr[0]
D7
D6
D5
D4
D3
D2
D1
LSB
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
D8
DIN
DIN
Table 4. SPI Serial Output Data Format
MSB
D14
D13
D12
D11
D10
D9
0
Frame fault
0
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
LSB
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
DOUT
DOUT
SPI serial input and output format
RW[1:0]
: 01: write mode; 00: read mode
Addr[5:0]
: Address of SPI access
Data[7:0]
: Input data to write or output data to read
Frame fault
: 0: No error exists in the previous SPI frame.
: 1: Error exists in the previous SPI frame.
Table 5. SPI Register Map
Register
Name
Addr
(Hex)
Reserved
00
CFGUNLK
01
FLTCFG
02
Reserved
03
FLTEN0
04
FLTEN1
05
SDNEN0
06
SDNEN1
07
FLTFLG0
08
FLTFLG1
09
CSCFG
0A
PDCFG
0B
DIAG
0C
SPARE
0D
Reserved
b7
b6
b5
b4
b3
b2
b1
b0
RSVD
00
RSVD
CFGUNLK
FLGLATCH_EN
MTOCTH
00
RSVD
VCCUVTH
VBUVTH
00
FE_CPOV
FE_CPUV
FE_VBOV
FE_VBUV
FE_TSD
01
SE_CPOV
SE_CPUV
SE_VBOV
SE_VBUV
FF
SE_TSD
01
CPOV
CPUV
VBOV
VBUV
00
TSD
00
RSVD
FE_MTOC
FE_VCCOC
FE_VCCOV
FE_VDDOV
SE_MTOC
SE_VCCOC
SE_VCCOV
SE_VDDOV
MTOC
VCCOC
VCCOV
00
RSVD
RSVD
VDDOV
RSVD
RSVD
CSOFFSET
RSVD
VCCUVRST
SPARE
WDTRST
00
CMRST
SEL_COMP_HYS
RSVD
FF
00
DEADT
RSVD
0E-3F
Reset
(Hex)
00
00
00
7.3.1 Register Descriptions
Access type: R = Read and W = Write.
Reserved register: Read of reserved bits return 0 and write has no effect.
7.3.1.1 CFGUNLK (address 0x01): Configuration Unlock Register
Bit
Name
Type
Reset
Description
3:0
CFGUNLK
RW
0000
DRV3210-Q1 SPI register map has lock and unlock mode, and it is in lock mode by default. MCU
can write values of the following registers in unlock mode;
● FLTCFG
● FLTEN0 and FLTEN1
● SDNEN0 and SDNEN1
● CSCFG
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Bit
Name
SLVSC08B – MAY 2013 – REVISED JULY 2016
Type
Reset
Description
● PDCFG
● WDCFG
In lock mode, read returns the values, but writing the registers have no effect.
Device enters unlock mode by writing 0x5, 0x8, 0x7 to CFGUNLK register in series. Device exits
from unlock mode by writing 0x0.
7.3.1.2 FLTCFG (address 0x02): Fault Detection Configuration Register
Bit
Name
Type
Reset
Description
7
FLGLATCH_EN
RW
0
Fault-flag (FLTFLG*) latch enable
0: Fault events do not latch fault-flag register bits.
1: Latching of fault-flag register bits by the fault events occurs. The flag bits remain asserted until
cleared.
6:4
MTOCTH
RW
000
Motor overcurrent detection threshold
000: 2 V
001: 2.5 V
010: 3 V
011: 3.5 V
100: 4 V
Others: 2 V
3
RSVD
R
0
Reserved
2
VCCUVTH
RW
0
VCC undervoltage detection threshold
0: 4 V
1: 4.2 V
1:0
VBUVTH
RW
00
VB undervoltage detection threshold
00: 4 V
01: 4.5 V
10: 5 V
11: 5.5 V
7.3.1.3 FLTEN0 (address 0x04): FAULT Pin Enable Register 0
Bit
Name
Type
Reset
Description
7
FE_MTOC
RW
1
6
FE_VCCOC
RW
1
5
FE_VCCOV
RW
1
FAULT pin enable of FLTFLG0 register bits.
0: Assertion of the FAULT pin does not occur when the fault flag bit is 1
1: Assertion of the FAULT pin to low level occurs when the fault flag bit is 1. See Figure 23
4
FE_VDDOV
RW
1
3
FE_CPOV
RW
1
2
FE_CPUV
RW
1
1
FE_VBOV
RW
1
0
FE_VBUV
RW
1
7.3.1.4 FLTEN1 (address 0x05): FAULT Pin Enable Register 1
Bit
Name
Type
Reset
7:1
RSVD
R
0000 000 Reserved
Description
0
FE_TSD
RW
1
FAULT pin enable of TSD flag bit
0: Assertion of the FAULT pin does not occur when the fault flag bit is 1
1: Assertion of the FAULT pin to low level occurs when the TSD flag bit is 1. See Figure 23
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FE_MTOC
MTOC
FE_VCCOC
VCCOC
FE_VCCOV
VCCOV
FE_VDDOV
VDDOV
FE_CPOV
CPOV
FAULT
FE_CPUV
CPUV
FE_VBOV
VBOV
FE_VBUV
VBUV
FE_TSD
TSD
Figure 23. FAULT Pin Enable Logic
7.3.1.5 SDNEN0 (address 0x06): Pre-Driver Shutdown Enable Register 0
Bit
Name
Type
Reset
Description
7
SE_MTOC
RW
1
6
SE_VCCOC
RW
1
5
SE_VCCOV
RW
1
4
SE_VDDOV
RW
1
Pre-driver shutdown enable of FLTFLG0 register bits
0: Disabling of the pre-driver outputs does not occur when the fault flag bit is 1.
1: Disabling of the pre-driver outputs occurs when the fault flag bit is 1. Both the high-side
and low-side FETs turn off.
See Figure 24.
3
SE_CPOV
RW
1
2
SE_CPUV
RW
1
1
SE_VBOV
RW
1
0
SE_VBUV
RW
1
7.3.1.6 SDNEN1 (address 0x07): Pre-Driver Shutdown Enable Register 1
Bit
Name
Type
Reset
Description
7:1
RSVD
R
0000 000
Reserved
0
SE_TSD
RW
1
Pre-driver shutdown enable of TSD flag bits
0: Disabling of the pre-driver outputs does not occur when the TSD flag bit is 1.
1: Disabling of the pre-driver outputs occurs when the TSD flag bit is 1. Both the high-side and
low-side FETs turn off.
See Figure 24.
26
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SE_MTOC
MTOC
SE_VCCOC
VCCOC
SE_VCCOV
Pre-driver
control
VCCOV
SE_VDDOV
VDDOV
SE_CPOV
enable
CPOV
SE_CPUV
CPUV
SE_VBOV
VBOV
SE_VBUV
VBUV
SE_TSD
TSD
Figure 24. Pre-Driver Shutdown Logic
7.3.1.7 FLTFLG0 (address 0x08): Fault Flag Register 0
Bit
Name
Type (1)
Reset
Description
Fault flag bits of the following conditions; (2)
7
MTOC
RW
0
MTOC: Motor overcurrent. (OVAD)
6
VCCOC
RW
0
VCCOC: VCC overcurrent
5
VCCOV
RW
0
VCCOV: VCC overvoltage
4
VDDOV
RW
0
VDDOV: VDD overvoltage
3
CPOV
RW
0
CPOV: Charge-pump overvoltage
2
CPUV
RW
0
CPUV: Charge-pump undervoltage
1
VBOV
RW
0
VBOV: VB overvoltage
0
VBUV
RW
0
VBUV: VB undervoltage
If FLTCFG.FLGLATCH_EN = 1
0: Read = No fault condition exists since last cleared.
Write = No effect
1: Read = Fault condition exists.
Write = Clear the flag.
If FLTCFG.FLGLATCH_EN = 0
0: Read = No fault condition
Write = No effect
1: Read = Fault condition
Write = No effect
(1)
(2)
R: Read, W: Write
Assertion of the fault flags may occur during power up.
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7.3.1.8 FLGFLT1 (address 0x09): Fault Flag Register 1
Bit
Name
Type (1)
Reset
Description
7:1
RSVD
R
0000
000
Reserved
0
VBUV
RW
1
Fault flag bit of thermal shutdown condition. (2)
If FLTCFG.FLGLATCH_EN = 1
0: Read = No fault condition exists since last cleared.
Write = No effect
1: Read = Fault condition exists.
Write = Clear the flag
If FLTCFG.FLGLATCH_EN = 0
0: Read = No fault condition
Write = No effect
1: Read = Fault condition
Write = No effect
(1)
(2)
R: Read, W: Write
Assertion of the fault flags may occur during power up.
CS
SCK
Fault Event
Status N
Status N+1
Status N
SPI Read Buffer
Status N+1
FLTFLG*
Status N
SPI DOUT
Serial Output Format
FLTFLG*
Status N+1
Serial Output Format
Figure 25. SPI Data-Out Timing Chart of Fault Flag Registers
28
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0
FLGLATCH_EN
1
Fault
Status
0
FLTFLG
Fault
1
SPI Access
to FLTFLG
Read
Write 1
to cClear
(1)
FAULT
H
L
Pre-Driver(2)
Enable
Disable
(1)
Assertion of FAULT occurs if FLTEN = 1.
(2)
Disabling of pre-driveroccurs if SDNEN = 1.
Figure 26. FLGFLG and FLGLATCH_EN
7.3.1.9 CSCFG (address 0x0A): Current Sense Configuration Register
Bit
Name
Type (1)
Reset
Description
7:3
RSVD
R
0000 0
Reserved
2:0
CSOFFSET RW
000
Current-sense offset
000: 0.5 V
001: 1 V
010: 1.5 V
011: 2 V
100: 2.5 V
Others: 0.5 V
(1)
R: Read W: Write
7.3.1.10 PDCFG (address 0x0B): Pre-Driver Configuration Register
Bit
Name
Type (1)
Reset
7:2
RSVD
R
0000 00 Reserved
1:0
DEADT
RW
00
(1)
Description
Dead time (= tdead)
00: 2 µs
01: 1.5 µs
10: 1 µs
11: 0.5 µs
The actual dead time has ±0.2 µs variation from the typical value.
R: Read W: Write
7.3.1.11 DIAG (address 0x0C): Diagnosis Register
Bit
Name
Type
Reset
Description
7:3
RSVD
R
0000 0
Reserved
2
VCCUVRST
R
0
nRES reset source information
1
WDTRST
R
0
Bit 2 = VCCUVRST - VCC undervoltage
0
CMRST
R
0
Bit 1 = WDTRST - watchdog timer
Bit 0 = CMRST - clock monitor
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Bit
Name
Type
Reset
www.ti.com
Description
0: Read = Reset has not occurred.
Write = No effect
1: Read = A corresponding reset source caused the last reset condition.
Write = No effect
Read access to this register clears the bits.
7.3.1.12 SPARE (address 0x0D): Spare Register
Bit
Name
Type (1)
Reset
Description
7:2
SPARE
RW
0000
00
Spare registers for future use. Read and write have no effect.
1:0
SEL_COMP_HYS
RW
00
Select phase comparator hysteresis voltage. The following show the typical values.
MM 00: 0 V
MM 01: 25 mV
MM 10: 50 mV
MM 11: 100 mV
(1)
30
R: Read W: Write
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Typical Application
VB
VB
100nF
1uF
100uF
PGND
100uF
PGND
ALP
VCC
AREF
100nF
30KÖ
1KÖ
10nF
TEST
1mÖ
GND
ALM
GND
ALV
ALFB
30KÖ
1KÖ
4.7pF
CTLUH
CTLVH
UH
10Ö
CTLWH
UHS
CTLUL
CTLVL
UL
10Ö
CTLWL
DRV3210-Q1
Controller
PMV3
VH
10Ö
PMV2
PMV1
VHS
RES
VL
BLDC
Motor
10Ö
PRN
FAULT
CS
SCK
WH
10Ö
WHS
DIN
WL
10Ö
DOUT
VDD
1uF
GND
PGND
100nF
GND
PHTM
100KÖ
30KÖ
15pF
10KÖ
100KÖ
10KÖ
15pF
10KÖ
100KÖ
10KÖ
GND
ENABLE
2.2uF
PDCPV
VB
47nF
CPRD4
0Ö
1uF
PH1M
PH2M
15pF
10KÖ
100KÖ
10KÖ
15pF
10KÖ
CPRD3
100nF
CPRD2
47Ö
CPRD1
PH3M
NGND
GND
GND
PGND
Figure 27. Typical Application Schematic
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9 Device and Documentation Support
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
9.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV3210QPHPQ1
NRND
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV3210
DRV3210QPHPRQ1
NRND
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV3210
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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28-Jun-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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