SPI®/I2C® Compatible, 10-Bit Digital Temperature Sensor and 8-Channel ADC ADT7411* FEATURES PIN CONFIGURATION 10-bit temperature-to-digital converter 10-bit 8-channel ADC DC input bandwidth Input range: 0 V to 2.25 V, and 0 V to VDD Temperature range: –40°C to +120°C Temperature sensor accuracy of ±0.5°C Supply range: 2.7 V to 5.5 V Power-down current 1 µA Internal 2.25 VREF option Double-buffered input logic I2C, SPI, QSPI™, MICROWIRE™, and DSP compatible 4-wire serial interface SMBus packet error checking (PEC) compatible 16-lead QSOP package AIN6 1 16 AIN7 AIN5 2 15 AIN8 NC 3 ADT7411 14 AIN4 13 SCL/SCLK TOP VIEW GND 5 (Not to Scale) 12 SDA/DIN VDD 6 11 DOUT/ADD D+/AIN1 7 10 INT/INT D–/AIN2 8 9 NC = NO CONNECT AIN3 02882-A-005 CS 4 Figure 1. APPLICATIONS Portable battery-powered instruments Personal computers Smart battery chargers Telecommunications systems electronic test equipment Domestic appliances Process control GENERAL DESCRIPTION The ADT7411 combines a 10-bit temperature-to-digital converter and a 10-bit 8-channel ADC in a 16-lead QSOP package. This includes a band gap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of 0.25°C. The ADT7411 operates from a single 2.7 V to 5.5 V supply. The input voltage on the ADC channels has a range of 0 V to 2.25 V and the input bandwidth is dc. The reference for the ADC channels is derived internally. The ADT7411 provides two serial interface options: a 4-wire serial interface compatible with SPI, QSPI, MICROWIRE, and DSP interface standards, and a 2-wire SMBus/I2C interface. It features a standby mode that is controlled via the serial interface. The ADT7411’s wide supply voltage range, low supply current, and SPI/I2C compatible interface make it ideal for a variety of applications, including personal computers, office equipment, and domestic appliances. *Protected by the following U.S. Patent Numbers: 6,169,442; 5,867,012; 5,764174. Other patents pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADT7411 TABLE OF CONTENTS Specifications..................................................................................... 3 Conversion Speed....................................................................... 13 Functional Block Diagram .............................................................. 6 Functional Description.................................................................. 14 Absolute Maximum Ratings............................................................ 7 Analog Inputs.............................................................................. 14 ESD Caution.................................................................................. 7 Functional Description—Measurement.................................. 15 Pin Configuration and Functional Description ........................... 8 ADT7411 Registers .................................................................... 19 Terminology ...................................................................................... 9 Serial Interface ............................................................................ 27 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 34 Theory of Operation ...................................................................... 13 Ordering Guide .......................................................................... 34 Power-Up Calibration................................................................ 13 REVISION HISTORY Revision A 3/04–Data Sheet Changed from Rev. 0 to Rev. A Format Updated Universal Change to Equation.............................................................................17 8/03–Revision 0: Initial Version Rev. A | Page 2 of 36 ADT7411 SPECIFICATIONS Table 1. VDD = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Temperature ranges are −40°C to +120°C. Parameter1 ADC DC ACCURACY Resolution Total Unadjusted Error (TUE) Offset Error Gain Error ADC BANDWIDTH ANALOG INPUTS Input Voltage Range DC Leakage Current Input Capacitance Input Resistance THERMAL CHARACTERISTICS Internal Temperature Sensor Accuracy @ VDD = 3.3 V ± 10% Accuracy @ VDD = 5 V ± 5% Resolution Long-term Drift External Temperature Sensor Accuracy @ VDD= 3.3 V ± 10% Accuracy @ VDD = 5 V ± 5% Resolution Output Source Current CONVERSION TIMES Slow ADC VDD/AIN Internal Temperature External Temperature Fast ADC VDD/AIN Internal Temperature External Temperature 1 Min Typ 2 0 0 5 10 Max Unit 10 3 ±0.5 ±2 DC Bits % of FSR % of FSR % of FSR Hz 2.25 VDD ±1 20 V V µA pF MΩ Conditions/Comments Max VDD= 5 V. AIN1 to AIN8. C4 = 0 in Control Configuration 3. AIN1 to AIN8. C4 = 1 in Control Configuration 3. Internal reference used. Averaging on. ±1.5 ±3 ±5 ±3 ±5 10 °C °C °C °C °C Bits °C ±1.5 ±3 ±5 ±3 ±5 10 180 11 °C °C °C °C °C Bits µA µA 11.4 712 11.4 712 24.22 1.51 ms µs ms µs ms ms Averaging (16 samples) on. Averaging off. Averaging (16 samples) on. Averaging off. Averaging (16 samples) on. Averaging off. 712 44.5 2.14 134 14.25 890 µs µs ms µs ms µs Averaging (16 samples) on. Averaging off. Averaging (16 samples) on. Averaging off. Averaging (16 samples) on. Averaging off. ±0.5 ±2 ±2 ±3 0.25 ±2 ±3 See the Terminology section. Rev. A | Page 3 of 36 TA = 85°C. TA = 0°C to 85°C. TA = −40°C to +120°C. TA = 0°C to 85°C. TA = −40°C to +120°C. Equivalent to 0.25°C. Drift over 10 years if part is operated at 55°C. External transistor = 2N3906. TA = 85°C. TA = 0°C to 85°C. TA = −40°C to +120°C. TA = 0°C to 85°C. TA = −40°C to +120°C. Equivalent to 0.25°C. High Level. Low Level. Single-channel Mode. ADT7411 Parameter1 ROUND ROBIN UPDATE RATE2 Slow ADC @ 25°C Averaging On Averaging Off Averaging On Averaging Off Fast ADC @ 25°C Averaging On Averaging Off Averaging On Averaging Off ON-CHIP REFERENCE3 Reference Voltage Temperature Coefficient DIGITAL INPUTS1, 3 Input Current VIL, Input Low Voltage VIH, Input High Voltage Pin Capacitance SCL, SDA Glitch Rejection DIGITAL OUTPUT Output High Voltage, VOH Output Low Voltage, VOL Output High Current, IOH Output Capacitance, COUT INT/INT Output Saturation Voltage I2C TIMING CHARACTERISTICS4, 5 Serial Clock Period, t1 Data In Setup Time to SCL High, t2 Data Out Stable after SCL Low, t3 SDA Low Setup Time to SCL Low (Start Condition), t4 SDA High Hold Time after SCL High (Stop Condition), t5 SDA and SCL Fall Time, t6 SPI TIMING CHARACTERISTICS1, 3, 6 CS to SCLK Setup Time, t1 SCLK High Pulse Width, t2 SCLK Low Pulse Width, t3 Data Access Time after SCLK Falling Edge, t4 6 Data Setup Time Prior to SCLK Rising Edge, t5 Data Hold Time after SCLK Rising Edge, t6 Min Typ Max Unit Conditions/Comments Time to complete one measurement cycle through all channels. 125.4 17.1 140.36 12.11 ms ms ms ms AIN1 and AIN2 are selected on Pins 7 and 8. AIN1 and AIN2 are selected on Pins 7 and 8. D+ and D– are selected on Pins 7 and 8. D+ and D− are selected on Pins 7 and 8. 9.26 578.96 24.62 3.25 ms µs ms ms AIN1 and AIN2 are selected on Pins 7 and 8. AIN1 and AIN2 are selected on pins 7 and 8. D+ and D− are selected on Pins 7 and 8. D+ and D− are selected on Pins 7 and 8. 2.25 80 V ppm/°C ±1 0.8 10 50 µA V V pF ns 0.4 1 50 0.8 V V mA pF V ISOURCE = ISINK = 200 µA. IOL = 3 mA. VOH = 5 V. 2.5 50 0 µs ns ns Fast-Mode I2C. See Figure 2. 50 ns See Figure 2. ns ns See Figure 2. See Figure 2. ns ns ns See Figure 3. See Figure 3. See Figure 3. ns See Figure 3. 20 ns See Figure 3. 0 ns See Figure 3. 1.89 3 2.4 50 90 0 50 50 35 2 VIN = 0 V to VDD. All Digital Inputs. Input filtering suppresses noise spikes of less than 50 ns. IOUT = 4 mA. See Figure 2. Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5, AIN6, AIN7, and AIN8. 3 Guaranteed by design and characterization, not production tested. 4 The SDA and SCL timing is measured with the input filters turned on so as to meet the FAST-Mode I2C specification. Switching off the input filters improves the transfer rate, but has a negative effect on the EMC behavior of the part. 5 Guaranteed by design. Not tested in production. 6 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V. Rev. A | Page 4 of 36 ADT7411 Parameter1 CS to SCLK Hold Time, t7 CS to DOUT High Impedance, t8 Min 0 POWER REQUIREMENTS VDD VDD Settling Time IDD (Normal Mode)7 Typ Max 2.7 2.2 IDD (Power-Down Mode) Power Dissipation 40 Unit ns ns Conditions/Comments See Figure 3. See Figure 3. 5.5 50 3 3 10 10 10 33 V ms mA mA µA µA mW µW VDD settles to within 10% of its final voltage level. VDD = 3.3 V, VIH = VDD and VIL = GND. VDD = 5 V, VIH = VDD and VIL = GND. VDD = 3.3 V, VIH =VDD and VIL = GND. VDD = 5 V, VIH = VDD and VIL = GND. VDD = 3.3 V. Using normal mode. VDD = 3.3 V. Using shutdown mode. t1 SCL t5 t2 t4 SDA DATA IN 02882-A-002 t3 SDA DATA OUT t6 2 Figure 2. I C Bus Timing Diagram CS t1 t2 t7 SCLK DIN D7 D6 D5 t5 D4 D3 D2 t6 D1 t8 D0 X X X X X X X X D5 D4 D3 D2 D1 D0 t4 DOUT X X X X X X X X D7 D6 Figure 3. SPI Bus Timing Diagram 200µA 1.6V CL 50pF 200µA IOH 02882-A-004 TO OUTPUT PIN IOL Figure 4. Load Circuit for Access Time and Bus Relinquish Time 7 IDD specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded. Rev. A | Page 5 of 36 02882-A-003 t3 ADT7411 FUNCTIONAL BLOCK DIAGRAM ADT7411 INTERNAL TEMPERATURE VALUE REGISTER D+/AIN1 7 D–/AIN2 8 A-TO-D CONVERTER AIN3 9 THIGH LIMIT REGISTERS DIGITAL MUX EXTERNAL TEMPERATURE VALUE REGISTER ADDRESS POINTER REGISTER DIGITAL MUX ON-CHIP TEMPERATURE SENSOR LIMIT COMPARATOR ANALOG MUX VDD VALUE REGISTER AIN6 1 CONTROL CONFIG. 2 REGISTER AIN2 VALUE REGISTER AIN8 15 AIN3 VALUE REGISTER AINHIGH LIMIT REGISTERS CONTROL CONFIG. 1 REGISTER AIN1 VALUE REGISTER AIN7 16 VDD LIMIT REGISTERS AINLOW LIMIT REGISTERS AIN4 14 CONTROL CONFIG. 3 REGISTER STATUS REGISTERS 10 INTERRUPT MASK REGISTERS INT/INT AIN4 VALUE REGISTER VDD SENSOR AIN5 VALUE REGISTER SPI/SMBus INTERFACE AIN6 VALUE REGISTER AIN7 VALUE REGISTER AIN8 VALUE REGISTER 6 5 4 13 12 11 VDD GND CS SCL/SCLK SDA/DIN DOUT/ADD Figure 5. Functional Block Diagram Rev. A | Page 6 of 36 02882-A-001 AIN5 2 TLOW LIMIT REGISTERS ADT7411 ABSOLUTE MAXIMUM RATINGS Table 3. I2C Address Selection Table 2. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead QSOP Package Power Dissipation8 Thermal Impedance9 θJA Junction-to-Ambient θJC Junction-to-Case IR Reflow Soldering Peak Temperature Time at Peak Temperature Ramp-Up Rate Ramp-Down Rate 8 9 Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +120°C −65°C to +150°C 150°C ADD Pin Low Float High I2C Address 1001 000 1001 010 1001 011 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (TJmax − TA)/θJA 105.44°C/W 38.8°C/W 220°C (0°C/5°C) 10 sec to 20 sec 2°C/sec to 3°C/sec −6°C/sec Values relate to package being used on a 4-layer board Junction-to-case resistance is applicable to components featuring a preferential flow direction, e.g., components mounted on a heat sink. Junction-to-ambient resistance is more useful for air-cooled PCB-mounted components. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electro-static discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 36 ADT7411 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTION AIN6 1 16 AIN7 AIN5 2 15 AIN8 NC 3 14 AIN4 CS 4 ADT7411 SCL/SCLK TOP VIEW GND 5 (Not to Scale) 12 SDA/DIN 13 11 DOUT/ADD 10 INT/INT D–/AIN2 8 9 AIN3 NC = NO CONNECT 02882-A-005 VDD 6 D+/AIN1 7 Figure 6. Pin Configuration Table 4. Pin Function Description Pin No. 1 2 3 4 Mnemonic AIN6 AIN5 NC CS 5 6 7 GND VDD D+/AIN 8 D−/AIN2 9 10 AIN3 INT/INT 11 DOUT/ADD 12 SDA/DIN 13 SCL/SCLK 14 15 16 AIN4 AIN8 AIN7 Description Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD. No Connection to This Pin. SPI—Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode. Ground Reference Point for All Circuitry on the Part. Analog and digital ground. Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. D+. Positive connection to external temperature sensor. AIN1. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to 5 V. D−. Negative connection to external temperature sensor. AIN2. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to 5 V. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD. Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when temperature, VDD, or AIN limits are exceeded. Default is active low. Open-drain output, needs a pull-up resistor. SPI. Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling edge of SCLK. Open-drain output, needs a pull-up resistor. ADD. I2C serial bus address selection pin. Logic input. A low on this pin gives the Address 1001 000. Leaving it floating gives the address 1001 010, and setting it high gives the Address 1001 011. The I2C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. Any subsequent changes on this pin will have no effect on the I2C serial bus address. SDA. I2C serial data input. I2C serial data to be loaded into the part’s registers is provided on this input. An open-drain configuration, it needs a pull-up resistor. DIN. SPI serial data input. Serial data to be loaded into the part’s registers is provided on this input. Data is clocked into a register on the rising edge of SCLK. Open-drain configuration, needs a pull-up resistor. Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of the ADT7411 and also to clock data into any register that can be written to. An open-drain configuration, it needs a pull-up resistor. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD. Rev. A | Page 8 of 36 ADT7411 TERMINOLOGY Relative Accuracy Long -term Temperature Drift Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the ADC transfer function. A typical INL versus code plot can be seen in Figure 10. This is a measure of the change in temperature error with the passage of time. It is expressed in degrees Celsius. The concept of long-term stability has been used for many years to describe by what amount an IC’s parameter would shift during its lifetime. This is a concept that has been typically applied to both voltage references and monolithic temperature sensors. Unfortunately, integrated circuits cannot be evaluated at room temperature (25°C) for 10 years or so to determine this shift. As a result, manufacturers typically perform accelerated lifetime testing of integrated circuits by operating ICs at elevated temperatures (between 125°C and 150°C) over a shorter period of time (typically, between 500 and 1,000 hours). As a result of this operation, the lifetime of an integrated circuit is significantly accelerated due to the increase in rates of reaction within the semiconductor material. Total Unadjusted Error (TUE) Total unadjusted error is a comprehensive specification that includes the sum of the relative accuracy error, gain error, and offset error under a specified set of conditions. Offset Error This is a measure of the offset error of the ADC. It can be negative or positive. It is expressed in mV. Gain Error This is a measure of the span error of the ADC. It is the deviation in slope of the actual ADC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. DC Power Supply Rejection Ratio (PSRR) The power supply rejection ratio (PSRR) is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 100 mV sine wave applied to the VDD supply of frequency fs: PSRR (dB ) = 10 log (Pf Pfs ) Pf = power at frequency f in ADC output Pfs = power at frequency fs coupled into the VDD supply Round Robin This term is used to describe the ADT7411 cycling through the available measurement channels in sequence, taking a measurement on each channel. Rev. A | Page 9 of 36 ADT7411 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 2.00 ADC OFF 0.8 1.95 0.6 INL ERROR (LSB) ICC (mA) 0.4 1.90 1.85 0.2 0 –0.2 –0.4 1.80 02882-A-009 02882-A-006 –0.6 –0.8 1.75 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 VCC (V) –1.0 0 200 800 1000 Figure 10. ADC INL with Ref = VDD (3.3V) Figure 7. Supply Current vs. Supply Voltage at 25ºC 0 1.5 ±100mV RIPPLE ON VCC VREF = 2.25V VDD = 3.3V TEMPERATURE = 25°C EXTERNAL TEMPERATURE @ 5V INTERNAL TEMPERATURE @ 3.3V 1.0 –20 –30 –40 02882-A-007 –50 –60 1 10 FREQUENCY (kHz) 0.5 0 –0.5 EXTERNAL TEMPERATURE @ 3.3V INTERNAL TEMPERATURE @ 5V –1.0 –30 100 0 40 85 TEMPERATURE (°C) 02882-A-010 TEMPERATURE ERROR (°C) –10 AC PSRR (dB) 400 600 ADC CODE 120 Figure 11. Temperature Error at 3.3 V and 5 V Figure 8. PSRR vs. Supply Ripple Frequency 3 7 VDD = 3.3V 6 2 5 1 ERROR (LSB) 4 3 0 –1 GAIN ERROR 2 –2 02882-A-008 1 0 –3 –4 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 VCC (V) 02882-A-011 ICC (µA) OFFSET ERROR –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 12. ADC Offset Error and Gain Error vs. Temperature Figure 9. Power-Down Current vs. Supply Voltage at 25ºC Rev. A | Page 10 of 36 ADT7411 15 0 VDD = 3.3V TEMPERATURE = 25°C VDD = 3.3V 10 TEMPERATURE ERROR (°C) 5 D+ TO GND 0 –5 D+ TO VCC –10 –15 –20 –30 –40 –50 02882-A-012 –20 –25 0 10 20 30 40 50 60 70 80 90 02882-A-015 TEMPERATURE ERROR (°C) –10 –60 0 100 5 10 15 Figure 13. External Temperature Error vs. PCB Track Resistance 25 30 35 40 45 50 Figure 16. External Temperature Error vs. Capacitance between D+ and D− 70 10 VDD = 3.3V COMMON-MODE VOLTAGE = 100mV 4 2 0 02882-A-013 –2 –4 –6 100 200 300 400 NOISE FREQUENCY (Hz) 500 50 40 30 20 10 02882-A-016 6 1 VDD = 3.3V DIFFERENTIAL-MODE VOLTAGE = 100mV 60 TEMPERATURE ERROR (°C) 8 TEMPERATURE ERROR (°C) 20 CAPACITANCE (nF) PCB LEAKAGE RESISTANCE (MΩ) 0 –10 1 600 100 200 300 400 NOISE FREQUENCY (MHz) 500 600 Figure 17. External Temperature Error vs. Differential Mode Noise Frequency Figure 14. External Temperature Error vs. Common-Mode Noise Frequency 0.6 3 VDD = 3.3V OFFSET ERROR 0.4 TEMPERATURE ERROR (°C) 1 0 –1 GAIN ERROR –3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 0 –0.2 ±250mV –0.4 –0.6 5.5 VDD (V) Figure 15. ADC Offset Error and Gain Error vs. VDD 0.2 02882-A-017 –2 02882-A-014 ERROR (LSB) 2 1 100 200 300 400 NOISE FREQUENCY (Hz) 500 600 Figure 18. Internal Temperature Error vs. Power Supply Noise Frequency Rev. A | Page 11 of 36 ADT7411 140 EXTERNAL TEMPERATURE 100 INTERNAL TEMPERATURE 80 60 40 TEMPERATURE OF ENVIRONMENT CHANGED HERE 20 0 0 10 20 30 TIME (s) 02882-A-018 TEMPERATURE (°C) 120 40 50 60 Figure 19. Temperature Sensor Response to Thermal Shock Rev. A | Page 12 of 36 ADT7411 THEORY OF OPERATION Directly after the power-up calibration routine, the ADT7411 goes into idle mode. In this mode, the device is not performing any measurements and is fully powered up. To begin monitoring, write to the Control Configuration 1 register (Address 18h) and set Bit C0 = 1. The ADT7411 goes into its power-up default measurement mode, which is round robin. The device proceeds to take measurements on the VDD channel, internal temperature sensor channel, external temperature sensor channel, or AIN1 and AIN2, AIN3, AIN4, AIN5, AIN6, AIN7, and finally AIN8. Once it finishes taking measurements on the AIN8 channel, the device immediately loops back to start taking measurements on the VDD channel and repeats the same cycle as before. This loop continues until the monitoring is stopped by resetting Bit C0 of the Control Configuration 1 register to 0. It is also possible to continue monitoring as well as switching to single-channel mode by writing to the Control Configuration 2 register (Address 19h) and setting Bit C4 = 1. Further explanations of the single-channel and round robin measurement modes are given in later sections. All measurement channels have averaging enabled on them at power-up. Averaging forces the device to take an average of 16 readings before giving a final measured result. To disable averaging and consequently decrease the conversion time by a factor of 16, set C5 = 1 in the Control Configuration 2 register. There are eight single-ended analog input channels on the ADT7411: AIN1 to AIN8. AIN1 and AIN2 are multiplexed with the external temperature sensors D+ and D− terminals. Bits C1 and C2 of the Control Configuration 1 register (Address 18h) are used to select between AIN1/2 and the external temperature sensor. The input range on the analog input channels is dependent on whether the ADC reference used is the internal VREF or VDD. To meet linearity specifications, it is recommended that the maximum VDD value is 5 V. Bit C4 of the Control Configuration 3 register is used to select between the internal reference and VDD as the analog inputs’ ADC reference. The dual serial interface defaults to the I2C protocol on powerup. To select and lock in the SPI protocol, follow the selection process as described in the Serial Interface Selection section. The I2C protocol cannot be locked in, while the SPI protocol on selection is automatically locked in. The interface can only be switched back to I2C when the device is powered off and on. When using I2C, the CS pin should be tied to either VDD or GND. There are a number of different operating modes on the ADT7411 devices and all of them can be controlled by the configuration registers. These features consist of enabling and disabling interrupts, polarity of the INT/INT pin, enabling and disabling the averaging on the measurement channels, SMBus timeout, and software reset. POWER-UP CALIBRATION It is recommended that no communication to the part is initiated until approximately 5 ms after VDD has settled to within 10% of its final value. It is generally accepted that most systems take a maximum of 50 ms to power up. Power-up time is directly related to the amount of decoupling on the voltage supply line. During the 5 ms after VDD has settled the part is performing a calibration routine; any communication to the device will interrupt this routine and could cause erroneous temperature measurements. If it is not possible to have VDD at its nominal value by the time 50 ms has elapsed or that communication to the device has started prior to VDD settling, then it is recommended that a measurement be taken on the VDD channel before a temperature measurement is taken. The VDD measurement is used to calibrate out any temperature measurement error due to different supply voltage values. CONVERSION SPEED The internal oscillator circuit used by the ADC has the capability to output two different clock frequencies. This means that the ADC is capable of running at two different speeds when doing a conversion on a measurement channel. Thus the time taken to perform a conversion on a channel can be reduced by setting C0 of the Control Configuration 3 register (Address 1Ah). This increases the ADC clock speed from 1.4 kHz to 22 kHz. At the higher clock speed, the analog filters on the D+ and D− input pins (external temperature sensor) are switched off. This is why the power-up default setting is to have the ADC working at the slow speed. The typical times for fast and slow ADC speeds are given in the specification pages. The ADT7411 powers up with averaging on. This means every channel is measured 16 times and internally averaged to reduce noise. The conversion time can also be reduced by turning the averaging off. This is done by setting Bit C5 of the Control Configuration 2 register (Address 19h) to a 1. Rev. A | Page 13 of 36 ADT7411 FUNCTIONAL DESCRIPTION Single-Ended Inputs A CAP DAC AIN SW1 B ACQUISITION PHASE SW2 CONTROL LOGIC REF/2 COMPARATOR Figure 21. ADC Acquisition Phase When the ADC eventually goes into conversion phase (see Figure 22) SW2 opens and SW1 moves to position B, causing the comparator to become unbalanced. The control logic and the DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 24 shows the ADC transfer function for single-ended analog inputs. The ADC resolution is 10 bits and is mostly suitable for dc input signals or very slowly varying ac signals. Bits C1:2 of the Control Configuration 1 register (Address 18h) are used to set up Pins 7 and 8 as AIN1 and AIN2. Figure 20 shows the overall view of the 8-channel analog input path. VDD INT VREF REF SAMPLING CAPACITOR 02882-A-021 The ADT7411 offers eight single-ended analog input channels. The analog input range is from 0 V to 2.25 V or 0 V to VDD. To maintain the linearity specification it is recommended that the maximum VDD value be set at 5 V. Selection between the two input ranges is done by Bit C4 of the Control Configuration 3 register (Address 1Ah). Setting this bit to 0 sets up the analog input ADC reference to be sourced from the internal voltage reference of 2.25 V. Setting the bit to 1 sets up the ADC reference to be sourced from VDD. A VDD INT VREF ANALOG INPUTS REF SAMPLING CAPACITOR INT VREF VDD CAP DAC B ACQUISITION PHASE A AIN CAP DAC SW1 CONTROL LOGIC REF/2 REF SAMPLING CAPACITOR COMPARATOR B SW2 Figure 20. Octal Analog Input Path CONVERSION PHASE CONTROL LOGIC REF/2 Converter Operation COMPARATOR Figure 22. ADC Conversion Phase The analog input channels use a successive approximation ADC based around a capacitor DAC. Figure 21 and Figure 22 show simplified schematics of the ADC. Figure 21 shows the ADC during acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on AIN. VDD I N×I IBIAS OPTIONAL CAPACITOR, UP TO 3nF MAX. CAN BE ADDED TO IMPROVE HIGH FREQUENCY NOISE REJECTION IN NOISY ENVIRONMENTS REMOTE SENSING TRANSISTOR (2N3906) D+ VOUT+ C1 TO ADC D– LOW-PASS FILTER fC = 65kHz BIAS DIODE Figure 23. Signal Conditioning for External Diode Temperature Sensor Rev. A | Page 14 of 36 VOUT– 02882-A-020 SW2 02882-A-021 SW1 02882-A-022 AIN ADT7411 VDD ADC Transfer Function The output coding of the ADT7411 analog inputs is straight binary. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB). The LSB is VDD/1024 or Int VREF/1024, Int VREF = 2.25 V. The ideal transfer characteristic is shown in Figure 24. IBIAS VOUT+ TO ADC 111...000 BIAS DIODE VOUT– 02882-A-024 INTERNAL SENSE TRANSISTOR 111...111 111...110 Figure 25. Top Level Structure of Internal Temperature Sensor 011...111 1LSB = INT VREF/1024 1LSB = VDD/1024 100Ω 000...010 000...001 000...000 4pF 0V 1/2 LSB +VREF – 1LSB ANALOG INPUT 02882-A-025 AIN 02882-A-023 ADC CODE N×I I Figure 26. Equivalent Analog Input ESD Circuit Figure 24. Transfer Function AIN Interrupts To work out the voltage on any analog input channel, the following method can be used: 1 LSB = Reference (V ) 1024 Convert the value read back from the AIN value register into decimal. AINVoltage = AINValue(d ) × LSB size where d = decimal Example: Internal reference used. Therefore, VREF = 2.25 V. AIN value = 512d 1 LSB size = 2.25 V 1024 = 2.197 × 10 −3 AINVoltage = 512 × 2.197 × 10 −3 The measured results from the AIN inputs are compared with the AIN VHIGH (greater than comparison) and VLOW (less than or equal to comparison) limits. An interrupt occurs if the AIN inputs exceed or equal the limit registers. These voltage limits are stored in on-chip registers. Note that the limit registers are eight bits long while the AIN conversion result is 10 bits long. If the voltage limits are not masked out, any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1 register (Address 00h) and one or more out-of-limit results will cause the INT/INT output to pull either high or low, depending on the output polarity setting. It is good design practice to mask out interrupts for channels that are of no concern to the application. Figure 27 shows the interrupt structure for the ADT7411. It shows a block diagram representation of how the various measurement channels affect the INT/INT pin. FUNCTIONAL DESCRIPTION—MEASUREMENT Temperature Sensor = 1.125V Analog Input ESD Protection Figure 26 shows the input structure that provides ESD protection on any of the analog input pins. The diode provides the main ESD protection for the analog inputs. Care must be taken that the analog input signal never drops below the GND rail by more than 200 mV. If this happens, the diode will become forward biased and start conducting current into the substrate. The 4 pF capacitor is the typical pin capacitance and the resistor is a lumped component made up of the on resistance of the multiplexer switch. The ADT7411 contains an A/D converter with special input signal conditioning to enable operation with external and onchip diode temperature sensors. When the ADT7411 is operating in single-channel mode, the A/D converter continually processes the measurement taken on one channel only. This channel is preselected by bits C0:C3 in the Control Configuration 2 register (Address 19h). When in round robin mode the analog input multiplexer sequentially selects the VDD input channel, on-chip temperature sensor to measure its internal temperature, the external temperature sensor, or an AIN channel, and then the rest of the AIN channels. These signals are digitized by the ADC and the results stored in the various value registers. Rev. A | Page 15 of 36 ADT7411 The measured results from the temperature sensors are compared with the internal and external, THIGH, TLOW, limits. These temperature limits are stored in on-chip registers. If the temperature limits are not masked out, any out-of-limit comparisons generate flags that are stored in Interrupt Status 1 register. One or more out-of-limit results will cause the INT/INT output to pull either high or low, depending on the output polarity setting. Theoretically, the temperature measuring circuit can measure temperatures from –128°C to +127°C with a resolution of 0.25°C. However, temperatures outside TA are outside the guaranteed operating temperature range of the device. Temperature measurement from –128°C to +127°C is possible using an external sensor. Temperature measurement is initiated by three methods. The first method is applicable when the part is in single-channel measurement mode. The temperature is measured 16 times and internally averaged to reduce noise. In single-channel mode, the part is continuously monitoring the selected channel, i.e., as soon as one measurement is taken, another one is started on the same channel. The total time to measure a temperature channel with the ADC operating at slow speed is typically 11.4 ms (712 µs × 16) for the internal temperature sensor and 24.22 ms (1.51 ms × 16) for the external temperature sensor. The new temperature value is stored in two 8-bit registers and ready for reading by the I2C or SPI interface. The user has the option of disabling the averaging by setting Bit 5 in the Control Configuration 2 register (Address 19h). The ADT7411 defaults on power-up with the averaging enabled. The second method is applicable when the part is in round robin measurement mode. The part measures both the internal and external temperature sensors as it cycles through all possible measurement channels. The two temperature channels are measured each time the part runs a round robin sequence. In round robin mode, the part is continuously measuring all channels. Temperature measurement is also initiated after every read or write to the part when the part is in either single-channel measurement mode or round robin measurement mode. Once serial communication has started, any conversion in progress is stopped and the ADC is reset. Conversion will start again immediately after the serial communication has finished. The temperature measurement proceeds normally as described previously. S/W RESET INTERNAL TEMP INTERRUPT STATUS REGISTER 1 (TEMP AND AIN1 TO AIN4) STATUS BITS EXTERNAL TEMP READ RESET DIODE FAULT INT/INT (LATCHED OUTPUT) AIN1–AIN4 AIN5–AIN8 CONTROL CONFIGURATION REGISTER 1 INT/INT ENABLE BIT Figure 27. ADT7411 Interrupt Structure Rev. A | Page 16 of 36 02882-A-026 INTERRUPT STATUS REGISTER 2 (VDD AND AIN5 TO AIN8) INTERRUPT MASK REGISTERS STATUS BITS WATCHDOG LIMIT COMPARISONS VDD ADT7411 VDD Monitoring On-Chip Reference The ADT7411 also has the capability of monitoring its own power supply. The part measures the voltage on its VDD pin to a resolution of 10 bits. The resulting value is stored in two 8-bit registers, with the 2 LSBs stored in register Address 03h and the 8 MSBs stored in register Address 06h. This allows the user to have the option of just doing a 1-byte read if 10-bit resolution is not important. The measured result is compared with the VHIGH and VLOW limits. If the VDD interrupt is not masked out then any out-of-limit comparison generates a flag in the Interrupt Status 2 register, and one or more out-of-limit results will cause the INT/INT output to pull either high or low, depending on the output polarity setting. The ADT7411 has an on-chip 1.125 V band gap reference that is gained up by a switched capacitor amplifier to give an output of 2.25 V. The amplifier is powered up for the duration of the device monitoring phase and is powered down once monitoring is disabled. This saves on current consumption. The internal reference is used as the reference for the ADC. Measuring the voltage on the VDD pin is regarded as monitoring a channel along with the internal, external, and AIN channels. The user can select the VDD channel for single-channel measurement by setting Bit C4 = 1 and setting Bits C0 to C2 to all 0s in the Control Configuration 2 register. When measuring the VDD value, the reference for the ADC is sourced from the internal reference. Table 5 shows the data format. As the max VDD voltage measurable is 7 V, internal scaling is performed on the VDD voltage to match the 2.25 V internal reference value. The following is an example of how the transfer function works: 1 LSB = ADC Reference 210 = 2.25 1024 = 2.197 mV Scale Factor = Fullscale VCC ADC Reference = 7 2.25 = 3.11 Conversion Result = VDD/(Scale Factor × LSB Size) = 5 (3.11 × 2.197 mV ) = 2DBh Table 5. VDD Data Format, VREF = 2.25 V Digital Output Binary 01 0110 1110 01 1000 1011 01 1011 0111 10 0000 0000 10 0100 1001 10 1001 0010 10 1101 1011 11 0010 0100 11 0110 1101 11 1011 0110 11 1111 1111 Upon power-up, the ADT7411 goes into round robin mode, but monitoring is disabled. Setting Bit C0 of the Configuration 1 register to 1 enables conversions. It sequences through all available channels, taking a measurement from each in the following order: VDD, internal temperature sensor, external temperature sensor/(AIN1 and AIN2), AIN3, AIN4, AIN5, AIN6, AIN7, and AIN8. Pin 7 and Pin 8 can be configured as either external temperature sensor pins or standalone analog input pins. Once conversion is completed on the AIN8 channel, the device loops around for another measurement cycle. This method of taking a measurement on all the channels in one cycle is called round robin. Setting Bit 4 of the Control Configuration 2 register (Address 19h) disables the round robin mode and in turn sets up the single-channel mode. The singlechannel mode is where only one channel, e.g., the internal temperature sensor, is measured in each conversion cycle. The time taken to monitor all channels will normally not be of interest, as the most recently measured value can be read at any time. For applications where the round robin time is important, typical times at 25°C are given in the specification pages. ADC Reference = 2.25 V VDD Value (V) 2.5 2.7 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Round Robin Measurement Hex 16E 18B 1B7 200 249 292 2DB 324 36D 3B6 3FF Single-Channel Measurement Setting Bit C4 of the Control Configuration 2 register enables the single-channel mode and allows the ADT7411 to focus on one channel only. A channel is selected by writing to Bits C0:C3 in the Control Configuration 2 register. For example, to select the VDD channel for monitoring, write to the Control Configuration 2 register and set C4 to 1 (if not done so already), then write all 0s to Bits C0 to C3. All subsequent conversions will be done on the VDD channel only. To change the channel selection to the internal temperature channel, write to the Control Configuration 2 register and set C0 = 1. When measuring in single-channel mode, conversions on the channel selected occur directly after each other. Any communication to the ADT7411 stops the conversions, but they are restarted once the read or write operation is completed. Temperature Measurement Method Internal Temperature Measurement The ADT7411 contains an on-chip, band gap temperature sensor whose output is digitized by the on-chip ADC. The temperature data is stored in the internal temperature value register. As both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in Table 6. The thermal characteristics of the Rev. A | Page 17 of 36 ADT7411 measurement sensor could change and therefore an offset is added to the measured value to enable the transfer function to match the thermal characteristics. This offset is added before the temperature data is stored. The offset value used is stored in the internal temperature offset register. External Temperature Measurement The ADT7411 can measure the temperature of one external diode sensor or diode-connected transistor. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about −2 mV/°C. Unfortunately, the absolute value of VBE varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production. The technique used in the ADT7411 is to measure the change in VBE when the device is operated at two different currents. further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. Layout Considerations Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken: 1. Place the ADT7411 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clock generators, data/address buses, and CRTs are avoided, this distance can be 4 inches to 8 inches. 2. Route the D+ and D− tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. 3. Use wide tracks to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended (see Figure 28). This is given by: ∆V BE = KT q × In( N ) GND 10 MIL 10 MIL where: D+ K is Boltzmann’s constant q is the charge on the carrier T is the absolute temperature in Kelvin N is the ratio of the two currents 10 MIL 10 MIL D– 10 MIL GND Figure 23 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor. Figure 28. Arrangement of Signal Tracks 4. If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used, the base is connected to the D− input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D− input and the base to the D+ input. A 2N3906 is recommended as the external transistor. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D− input. As the sensor is operating in a noisy environment, C1 is provided as a noise filter. See the Layout Considerations section for more information on C1. To measure ∆VBE, the sensor is switched between operating currents of I, and N × I. The resulting waveform is passed through a low-pass filter to remove noise, then to a chopperstabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to ∆VBE. This voltage is measured by the ADC to give a temperature output in 10-bit twos complement format. To 10 MIL 02882-A-027 10 MIL Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D− path and at the same temperature. Thermocouple effects should not be a major problem as 1°C corresponds to about 240 µV, and thermocouple voltages are about 3 µV/°C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV. 5. Place 0.1 µF bypass and 2200 pF input filter capacitors close to the ADT7411. 6. If the distance to the remote sensor is more than 8 inches, the use of twisted-pair cable is recommended. This will work up to about 6 feet to 12 feet. 7. For long distances (up to 100 feet) use shielded twistedpair cable, such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D− and the shield to GND close to the ADT7411. Leave the remote end of the shield unconnected to avoid ground loops. Rev. A | Page 18 of 36 ADT7411 Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. 1 Ω series resistance introduces about 0.5°C error. Temperature Value Format One LSB of the ADC corresponds to 0.25°C. The ADC can theoretically measure a temperature span of 255°C. The internal temperature sensor is guaranteed to a low value limit of −40°C. It is possible to measure the full temperature span using the external temperature sensor. The temperature data format is shown in Table 6. The result of the internal or external temperature measurements is stored as twos complement format in the temperature value registers, and is compared with limits programmed into the internal or external high and low registers. Table 6. Temperature Data Format(Internal and External Temperature) Temperature (°C) −40 −25 −10 −0.25 0 +0.25 +10 +25 +50 +75 +100 +105 +125 Digital Output 11 0110 0000 11 1001 1100 11 1101 1000 11 1111 1111 00 0000 0000 00 0000 0001 00 0010 1000 00 0110 0100 00 1100 1000 01 0010 1100 01 1001 0000 01 1010 0100 01 1111 0100 Status 2 register (Address 01h). One or more out-of limit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. It is good design practice to mask out interrupts for channels that are of no concern to the application. Figure 27 shows the interrupt structure for the ADT7411. It gives a block diagram representation of how the various measurement channels affect the INT/INT pin. ADT7411 REGISTERS The ADT7411 contains registers that are used to store the results of external and internal temperature measurements, VDD value measurements, analog input measurements, high and low temperature limits, supply voltage and analog input limits, configure multipurpose pins, and generally control the device. See Table 7 for a detailed description of these registers. The register map is divided into registers of 8 bits. Each register has its own individual address but some consist of data that is linked with other registers. These registers hold the 10-bit conversion results of measurements taken on the temperature, VDD, and AIN channels. For example, the MSBs of the VDD measurement are stored in Register Address 06h while the two LSBs are stored in Register Address 03h. The link involved between these types of registers is that when the LSB register is read first, the MSB registers associated with that LSB register are locked out to prevent any updates. To unlock these MSB registers the user has only to read any one of them, which will have the effect of unlocking all previously locked out MSB registers. So for the example given above, if Register 03h was read first, MSB Registers 06h and 07h would be locked out to prevent any updates to them. If Register 06h was read this register and Register 07h would be subsequently unlocked. FIRST READ COMMAND LSB REGISTER OUTPUT DATA Positive Temperature = ADC Code 4 02882-A-028 Temperature Conversion Formula: LOCK ASSOCIATED MSB REGISTERS Negative Temperatur e = (ADC Code ∗ − 512 ) 4 Figure 29. Phase 1 of 10-Bit Read *DB9 is removed from the ADC Code. The measured results from the internal temperature sensor, external temperature sensor, VDD pin, and AIN inputs are compared with their THIGH/VHIGH (greater than coparison) and TLOW/VLOW (less than or equal to comparison) limits. An interrupt occurs if the measurement exceeds or equals the limit registers. These limits are stored in on-chip registers. Note that the limit registers are eight bits long while the conversion results are 10 bits long. If the limits are not masked out, then any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1 register (Address 00h) and the Interrupt MSB REGISTER UNLOCK ASSOCIATED MSB REGISTERS OUTPUT DATA 02882-A-029 SECOND READ COMMAND Interrupts Figure 30. Phase 2 of 10-Bit Read If an MSB register is read first, its corresponding LSB register is not locked out, thus leaving the user with the option of just reading back 8 bits (MSB) of a 10-bit conversion result. Reading an MSB register first does not lock out other MSB registers, and likewise reading an LSB register first does not lock out other LSB registers. Rev. A | Page 19 of 36 ADT7411 Interrupt Status 1 Register (Read-Only) [Address = 00h] Table 7. ADT7411 Registers RD/WR Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h–17h 18h 19h 1Ah 1Bh–1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h–2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h–4Ch 4Dh 4Eh 4Fh 50h–7Eh 7F 80h–FFh Name Interrupt Status 1 Interrupt Status 2 Reserved Internal Temp and VDD LSBs External Temp and AIN1–4 LSBs AIN5–8 LSBs VDD MSBs Internal Temperature MSBs External Temp MSBs/AIN1 MSBs AIN2 MSBs AIN3 MSBs AIN4 MSBs AIN5 MSBs AIN6 MSBs AIN7 MSBs AIN8 MSBs Reserved Control CONFIG 1 Control CONFIG 2 Control CONFIG 3 Reserved Interrupt Mask 1 Interrupt Mask 2 Internal Temp Offset External Temp Offset Reserved Reserved VDD VHIGH Limit VDD VLOW Limit Internal THIGH Limit Internal TLOW Limit External THIGH/AIN1 VHIGH Limits External TLOW/AIN1 VLOW Limits Reserved AIN2 VHIGH Limit AIN2 VLOW Limit AIN3 VHIGH Limit AIN3 VLOW Limit AIN4 VHIGH Limit AIN4 VLOW Limit AIN5 VHIGH Limit AIN5 VLOW Limit AIN6 VHIGH Limit AIN6 VLOW Limit AIN7 VHIGH Limit AIN7 VLOW Limit AIN8 VHIGH Limit AIN8 VLOW Limit Reserved Device ID Manufacturer’s ID Silicon Revision Reserved SPI Lock Status Reserved Power-On Default 00h 00h This 8-bit read-only register reflects the status of some of the interrupts that can cause the INT/INT pin to go active. This register is reset by a read operation, provided that any out-oflimit event has been corrected. It is also reset by a software reset. 00h 00h 00h xxh 00h 00h 00h 00h 00h 00h 00h 00h 00h Table 8. Interrupt Status 1 Register 08h 00h 00h D2 D7 0* D5 0* D4 0* D3 0* D2 0* D1 0* D0 0* *Default settings at power-up. Table 9. Bit D0 D1 00h 00h 00h 00h D3 C7h 62h 64h C9h FFh 00h D6 0* D4 D5 Function 1 when internal temperature value exceeds THIGH limit. Any internal temperature reading greater than the set limit will cause an out-of-limit event. 1 when internal temperature value exceeds TLOW limit. Any internal temperature reading less than or equal to the set limit will cause an out-of-limit event. This status bit is linked to the configuration of pins 7 and 8. If configured for external temperature sensor, this bit is 1 when external temperature value exceeds THIGH limit. The default value for this limit register is –1°C, so any external temperature reading greater than the limit set will cause an out-of-limit event. If configured for AIN1 and AIN2, this bit is 1 when AIN1 Input Voltage exceeds VHIGH or VLOW limits. 1 when external temperature value exceeds TLOW limit. The default value for this limit register is 0°C, so any external temperature reading less than or equal to the limit set will cause an out-of-limit event. 1 indicates a fault (open or short) for the external temperature sensor. 1 when AIN2 voltage is greater than corresponding VHIGH limit. 1 when AIN2 voltage is less than or equal to corresponding VLOW limit. 1 when AIN3 voltage is greater than corresponding VHIGH limit. 1 when AIN3 voltage is less than or equal to corresponding VLOW limit. 1 when AIN4 voltage is greater than corresponding VHIGH limit. 1 when AIN4 voltage is less than or equal to corresponding VLOW limit. FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h D6 02h 41h 04h 00h 00h 00h Table 10. Interrupt Status 2 Register D7 Interrupt Status 2 Register (Read-Only) [Address = 01h] This 8-bit read-only register reflects the status of the VDD and AIN5–AIN8 interrupts that can cause the INT/INT pin to go active. This register is reset by a read operation provided that any out-of-limit event has been corrected. It is also reset by a software reset. D7 N/A D6 N/A D5 N/A *Default settings at power-up. Rev. A | Page 20 of 36 D4 0* D3 0* D2 0* D1 0* D0 0* ADT7411 Table 11. Table 15 Bit D0 Bit D0 D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5:D7 Function 1 when AIN5 voltage is greater than the corresponding VHIGH limit. 1 when AIN5 voltage is less than or equal to the corresponding VLOW limit. 1 when AIN6 voltage is greater than the corresponding VHIGH limit. 1 when AIN6 voltage is less than or equal to the corresponding VLOW limit. 1 when AIN7 voltage is greater than the corresponding VHIGH limit. 1 when AIN7 voltage is less than or equal to the corresponding VLOW limit. 1 when AIN8 voltage is greater than the corresponding VHIGH limit. 1 when AIN8 voltage is less than or equal to the corresponding VLOW limit. 1 when VDD value is greater than the corresponding VHIGH limit. 1 when VDD is less than or equal to the corresponding VLOW limit. Reserved Function LSB of External Temperature Value or AIN1 Value. Bit 1 of External Temperature Value or AIN1 Value. LSB of AIN2 Value. Bit 1 of AIN2 Value. LSB of AIN3 Value. Bit 1 of AIN3 Value. LSB of AIN4 Value. Bit 1 of AIN4 Value. Analog Inputs 5 to 8 Registers LSBs (Read-Only) [Add. = 05h] This is an 8-bit read-only register. Bits D0 to D7 store the 2 LSBs of the analog inputs AIN5 to AIN8. The MSBs are stored in Registers 0Ch to 0Fh. Table 16. External Temperature and AIN5 to AIN8 LSBs Internal Temperature Value/VDD Value Register LSBs (Read-Only) [Add. = 03h] This internal temperature value and VDD value register is an 8-bit read-only register. It stores the 2 LSBs of the 10-bit temperature reading from the internal temperature sensor and also the 2 LSBs of the 10-bit supply voltage reading. Table 12. Internal Temperature/VDD LSBs D7 N/A N/A D6 N/A N/A D5 N/A N/A D4 N/A N/A D3 V1 0* D2 LSB 0* D1 T1 0* D0 LSB 0* *Default settings at power-up. Table 13. Bit D0 D1 D2 D3 Function LSB of Internal Temperature Value. B1 of Internal Temperature Value. LSB of VDD Value. B1 of VDD Value. D4 A3LSB 0* *Default settings at power-up. D3 A2 0* D2 A2LSB 0* D4 A7LSB 0* D3 A6 0* D2 A6LSB 0* D1 A5 0* D0 A5LSB 0* *Default settings at power-up. Table 17. Bit D0 D1 D2 D3 D4 D5 D6 D7 Function LSB of AIN5 Value. Bit 1 of AIN5 Value. LSB of AIN6 Value. Bit 1 of AIN6 Value. LSB of AIN7 Value. Bit 1 of AIN7 Value. LSB of AIN8 Value. Bit 1 of AIN8 Value. Table 18. VDD Value MSBs Table 14. External Temperature and AIN1–4 LSBs D5 A3 0* D5 A7 0* This 8-bit read-only register stores the supply voltage value. The 8 MSBs of the 10-bit value are stored in this register. This is an 8-bit read-only register. Bits D2–D7 store the 2 LSBs of the analog inputs AIN2–AIN4. Bits D0 and D1 are used to store the 2 LSBs of either the external temperature value or AIN1 input value. The type of input for D0 and D1 is selected by Bits 1:2 of the Control Configuration 1 register. D6 A4LSB 0* D6 A8LSB 0* VDD Value Register MSBs (Read-Only) [Address = 06h] External Temperature Value and Analog Inputs1 to 4 Register LSBs (Read-Only) [Address = 04h] D7 A4 0* D7 A8 0* D1 T/A 0* D0 T/ALSB 0* D7 V9 x* D6 V8 x* D5 V7 x* D4 V6 x* D3 V5 x* D2 V4 x* D1 V3 x* D0 V2 x* *Loaded with VDD value after power-up. Internal Temperature Value Register MSBs (Read-Only) [Address = 07h] This 8-bit read-only register stores the internal temperature value from the internal temperature sensor in twos complement format. This register stores the 8 MSBs of the 10-bit value. Table 19. Internal Temperature Value MSBs D7 T9 0* D6 T8 0* D5 T7 0* *Default settings at power-up. Rev. A | Page 21 of 36 D4 T6 0* D3 T5 0* D2 T4 0* D1 T3 0* D0 T2 0* ADT7411 External Temperature Value or Analog Input AIN1 Register MSBs (Read-Only) [Address = 08h] to give the full 10-bit conversion result of the analog value on the AIN5 pin. This 8-bit read-only register stores, if selected, the external temperature value or the analog input AIN1 value. Selection is done in Control Configuration 1 register. The external temperature value is stored in twos complement format. The 8 MSBs of the 10-bit value are stored in this register. Table 24. AIN5 MSBs D7 MSB 0* D6 A8 0* D5 A7 0* D4 A6 0* D3 A5 0* D2 A4 0* D1 A3 0* D0 A2 0* *Default settings at power-up. Table 20. External Temperature Value/Analog Inputs MSBs D7 T/A9 0* D6 T/A8 0* D5 T/A7 0* D4 T/A6 0* D3 T/A5 0* D2 T/A4 0* D1 T/A3 0* D0 T/A2 0* *Default settings at power-up. AIN2 Register MSBs (Read) [Address = 09h] This 8-bit read register contains the 8 MSBs of the AIN2 analog input voltage word. The value in this register is combined with Bits D2:3 of the external temperature value and Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full 10-bit conversion result of the analog value on the AIN2 pin. Table 21. AIN2 MSBs D7 MSB 0* D6 A8 0* D5 A7 0* D4 A6 0* D3 A5 0* D2 A4 0* D1 A3 0* D0 A2 0* *Default settings at power-up. AIN3 Register MSBs (Read) [Address = 0Ah] This 8-bit read register contains the 8 MSBs of the AIN3 analog input voltage word. The value in this register is combined with Bits D4:5 of the external temperature value and Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full 10-bit conversion result of the analog value on the AIN3 pin. D6 A8 0* D5 A7 0* D4 A6 0* D3 A5 0* D2 A4 0* D1 A3 0* D0 A2 0* *Default settings at power-up. AIN4 Register MSBs (Read) [Address = 0Bh] This 8-bit read register contains the 8 MSBs of the AIN4 analog input voltage word. The value in this register is combined with Bits D6:7 of the external temperature value and Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full 10-bit conversion result of the analog value on the AIN4 pin. Table 23. AIN4 MSBs D7 MSB 0* D6 A8 0* D5 A7 0* This 8-bit read register contains the 8 MSBs of the AIN6 analog input voltage word. The value in this register is combined with Bits D2:3 of the Analog Inputs 5 to 8 register LSBs, Address 05h, to give the full 10-bit conversion result of the analog value on the AIN6 pin. Table 25. AIN6 MSBs D7 MSB 0* D6 A8 0* D5 A7 0* D4 A6 0* D3 A5 0* D2 A4 0* D1 A3 0* D0 A2 0* *Default settings at power-up. AIN7 Register MSBs (Read) [Address = 0Eh] This 8-bit read register contains the 8 MSBs of the AIN7 analog input voltage word. The value in this register is combined with Bits D4:5 of the Analog Inputs 5 to 8 register LSBs, Address 05h, to give the full 10-bit conversion result of the analog value on the AIN7 pin. Table 26. AIN7 MSBs D7 MSB 0* D6 A8 0* D5 A7 0* D4 A6 0* D3 A5 0* D2 A4 0* D1 A3 0* D0 A2 0* *Default settings at power-up. AIN8 Register MSBs (Read) [Address = 0Fh] Table 22. AIN3 MSBs D7 MSB 0* AIN6 Register MSBs (Read) [Address = 0Dh] D4 A6 0* D3 A5 0* D2 A4 0* D1 A3 0* D0 A2 0* This 8-bit read register contains the 8 MSBs of the AIN8 analog input voltage word. The value in this register is combined with Bits D6:7 of the Analog Inputs 5 to 8 register LSBs, Address 05h, to give the full 10-bit conversion result of the analog value on the AIN8 pin. Table 27. AIN8 MSBs D7 MSB 0* D6 A8 0* D5 A7 0* D4 A6 0* D3 A5 0* D1 A3 0* D0 A2 0* *Default settings at power-up. Control Configuration 1 Register (Read/Write) [Address = 18h] This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7411. *Default settings at power-up. Table 28. Control Configuration 1 AIN5 Register MSBs (Read) [Address = 0Ch] D7 PD 0* This 8-bit read register contains the 8 MSBs of the AIN5 analog input voltage word. The value in this register is combined with Bits D0:1 of the Analog Inputs 5 to 8 register LSBs, Address 05h, D2 A4 0* D6 C6 0* D5 C5 0* *Default settings at power-up. Rev. A | Page 22 of 36 D4 C4 0* D3 C3 1* D2 C2 0* D1 C1 0* D0 C0 0* ADT7411 Table 29. Bit Bit C0 C4 C2:C1 C3 C4 C5 C6 PD Function This bit enables/disables conversions in round robin and single-channel mode. ADT7411 powers up in round robin mode, but monitoring is not initiated until this bit is set. Default = 0. 0 = Stop monitoring. 1 = Start monitoring. Selects between the two different analog inputs on Pins 7 and 8. The ADT7411 powers up with AIN1 and AIN2 selected. 00: AIN1 and AIN2 selected. 01: Undefined. 10: External TDM selected. 11: Undefined. Reserved. Write 1 only to this bit. Reserved. Write 0 only. 0: Enable INT/INT output. 1: Disable INT/INT output. Configures INT/INT output polarity. 0: Active low. 1: Active high. Power-Down Bit. Setting this bit to 1 puts the ADT7411 into standby mode. In this mode, the analog circuitry is fully powered down, but the serial interface is still operational. To power up the part again, write 0 to this bit. Control Configuration 2 Register (Read/Write) [Address = 19h] Table 30. Control Configuration 2 D6 C6 0* D5 C5 0* D4 C4 0* D3 C3 0* D2 C2 0* D1 C1 0* C7 Control Configuration 3 Register (Read/Write) [Address = 1Ah] This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7411. Table 32. Control Configuration 3 D7 C7 0* D6 C6 0* D5 C5 0* D4 C4 0* D3 C3 1* D2 C2 0* D1 C1 0* D0 C0 0* Table 33. Bit C0 D0 C0 0* *Default settings at power-up. Table 31. Bit C3:0 C6 *Default settings at power-up. This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7411. D7 C7 0* C5 Function 1010 to 1111 = Reserved. Selects between single-channel and round robin conversion cycle. Default is round robin. 0 = Round robin. 1 = Single-channel. Default condition is to average every measurement on all channels 16 times. This bit disables this averaging. Channels affected are temperature, analog inputs, and VDD. 0 = Enable averaging. 1 = Disable averaging. SMBus timeout on the serial clock puts a 25 ms limit on the pulse width of the clock, ensuring that a fault on the master SCL does not lock up the SDA line. 0 = Disable SMBus timeout. 1 = Enable SMBus timeout. Software Reset. Setting this bit to a 1 causes a software reset. All registers will reset to their default settings. Function In single-channel mode, these bits select between VDD, the internal temperature sensor, external temperature sensor/AIN1, AIN2 to AIN8 for conversion. The default is VDD. 0000 = VDD. 0001 = Internal Temperature Sensor. 0010 = External Temperature Sensor/AIN1. (Bits C1:C2 of Control Configuration 1 affect this selection.) 0011 = AIN2. 0100 = AIN3. 0101 = AIN4. 0110 = AIN5. 0111 = AIN6. 1000 = AIN7. 1001 = AIN8. C1:2 C3 C4 C5:C7 Function Selects between fast and normal ADC conversion speeds. 0 = ADC clock at 1.4 kHz. 1 = ADC clock at 22.5 kHz. D+ and D− analog filters are disabled. Reserved. Only write 0s. Reserved. Write only 1 to this bit. Selects the ADC reference to be either Internal VREF or VDD for analog inputs. 0 = Int VREF 1 = VDD Reserved. Only write 0s. Interrupt Mask 1 Register (Read/Write) [Address = 1Dh] This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the INT/INT pin to go active. Table 34. Interrupt Mask 1 D7 D7 0* D6 D6 0* D5 D5 0* *Default settings at power-up. Rev. A | Page 23 of 36 D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* ADT7411 thermal characteristics change. Because it is an 8-bit register, the temperature resolution is 1°C. Table 35. Bit D0 D1 D2 D3 D4 D5 D6 D7 Function 0 = Enable internal THIGH interrupt. 1 = Disable internal THIGH interrupt. 0 = Enable internal TLOW interrupt. 1 = Disable internal TLOW interrupt. 0 = Enable external THIGH interrupt or AIN1 interrupt. 1 = Disable external THIGH interrupt or AIN1 interrupt. 0 = Enable external TLOW interrupt. 1 = Disable external TLOW interrupt. 0 = Enable external temperature fault interrupt. 1 = Disable external temperature fault interrupt. 0 = Enable AIN2 interrupt. 1 = Disable AIN2 interrupt. 0 = Enable AIN3 interrupt. 1 = Disable AIN3 interrupt. 0 = Enable AIN4 interrupt. 1 = Disable AIN4 interrupt. Table 38. Internal Temperature Offset D7 D7 0* Table 36. Interrupt Mask 2 D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* *Default settings at power-up. Table 37. Bit D0 D1 D2 D3 D4 D5:D7 D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* External Temperature Offset Register (Read/Write) [Address = 20h] This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the INT/INT pin to go active. D6 D6 0* D5 D5 0* *Default settings at power-up. Interrupt Mask 2 Register (Read/Write) [Address = 1Eh] D7 D7 0* D6 D6 0* Function 0 = Enable AIN5 interrupt. 1 = Disable AIN5 interrupt. 0 = Enable AIN6 interrupt. 1 = Disable AIN6 interrupt. 0 = Enable AIN7 interrupt. 1 = Disable AIN7 interrupt. 0 = Enable AIN8 interrupt. 1 = Disable AIN8 interrupt. 0 = Enable VDD interrupts. 1 = Disable VDD interrupts. Reserved. Only write 0s. This register contains the offset value for the external temperature channel. A twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. In this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. Because it is an 8-bit register, the temperature resolution is 1°C. Table 39. External Temperature Offset D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* *Default settings at power-up VDD VHIGH Limit Register (Read/Write) [Address = 23h] This limit register is an 8-bit read/write register that stores the VDD upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured VDD value has to be greater than the value in this register. The default value is 5.46 V. Table 40. VDD VHIGH Limit D7 D7 1* D6 D6 1* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 1* D1 D1 1* D0 D0 1* *Default settings at power-up. VDD VLOW Limit Register (Read/Write) [Address = 24h] This limit register is an 8-bit read/write register that stores the VDD lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured VDD value has to be less than or equal to the value in this register. The default value is 2.7 V. Internal Temperature Offset Register (Read/Write) [Address = 1Fh] This register contains the offset value for the internal temperature channel. A twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. In this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the Table 41. VDD VLOW Limit D7 D7 0* D6 D6 1* D5 D5 1* *Default settings at power-up. Rev. A | Page 24 of 36 D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 1* D0 D0 0* ADT7411 Internal THIGH Limit Register (Read/Write) [Address = 25h] This limit register is an 8-bit read/write register that stores the twos complement of the internal temperature upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured internal temperature value has to be greater than the value in this register. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is +100°C. Table 42. Internal THIGH Limit D7 D7 0* D6 D6 1* D5 D5 1* D4 D4 0* D3 D3 0* D2 D2 1* D1 D1 0* D0 D0 0* *Default settings at power-up. Internal TLOW Limit Register (Read/Write) [Address = 26h] This limit register is an 8-bit read/write register that stores the twos complement of the internal temperature lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured internal temperature value has to be more negative than or equal to the value in this register. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is −55°C. Table 43. Internal TLOW Limit D7 D7 1* D6 D6 1* D5 D5 0* D4 D4 0* D3 D3 1* D2 D2 0* D1 D1 0* D0 D0 1* *Default settings at power-up. External THIGH/AIN1 VHIGH Limit Register (Read/Write) [Address = 27h] If Pins 7 and 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured external temperature value has to be greater than the value in this register. Because it is an 8-bit register, the temperature resolution is 1°C. The default value is −1°C. External TLOW/AIN1 VLOW Limit Register (Read/Write) [Address = 28h] If Pins 7 and 8 are configured for the external temperature sensor, this limit register is an 8-bit read/write register that stores the twos complement of the external temperature lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured external temperature value has to be more negative than or equal to the value in this register. Since it is an 8-bit register, the temperature resolution is 1°C. The default value is 0°C. If Pins 7 and 8 are configured for AIN1 and AIN2 single-ended inputs, this limit register is an 8-bit read/write register that stores the AIN1 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN1 value has to be less than or equal to the value in this register. Because it is an 8-bit register the resolution is four times less than the resolution of the 10-Bit ADC. Since the power-up default settings for Pins 7 and 8 are AIN1 and AIN2 single-ended inputs, the default value for this limit register is 0 V. Table 45. AIN1 VLOW Limit D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* *Default settings at power-up. AIN2 VHIGH Limit Register (Read/Write) [Address = 2Bh] This limit register is an 8-bit read/write register that stores the AIN2 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN2 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage. Table 46. AIN2 VHIGH Limit D7 D7 1* D6 D6 1* D5 D5 1* D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1* If Pins 7 and 8 are configured for AIN1 and AIN2 single-ended inputs, this limit register is an 8-bit read/write register that stores the AIN1 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN1 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. Since the power-up default settings for Pins 7 and 8 are AIN1 and AIN2 single-ended inputs, the default value for this limit register is full-scale voltage. This limit register is an 8-bit read/write register that stores the AIN2 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN2 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V. Table 44. AIN1 VHIGH Limit Table 47. AIN2 VLOW Limit D7 D7 1* D6 D6 1* D5 D5 1* *Default settings at power-up. D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1* *Default settings at power-up. AIN2 VLOW Limit Register (Read/Write) [Address = 2Ch] D7 D7 0* D6 D6 0* D5 D5 0* *Default settings at power-up. Rev. A | Page 25 of 36 D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* ADT7411 AIN3 VHIGH Limit Register (Read/Write) [Address = 2Dh] Table 51. AIN4 VLOW Limit This limit register is an 8-bit read/write register that stores the AIN3 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN3 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage. D7 D7 0* Table 48. AIN3 VHIGH Limit D7 D7 1* D6 D6 1* D5 D5 1* D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1* *Default settings at power-up. D6 D6 0* D5 D5 0* D4 D4 0* D7 D7 1* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* *Default settings at power-up. D6 D6 1* D5 D5 1* D4 D4 1* D7 D7 0* D5 D5 1* D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1* *Default settings at power-up. D1 D1 1* D0 D0 1* This limit register is an 8-bit read/write register that stores the AIN5 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN5 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V. This limit register is an 8-bit read/write register that stores the AIN4 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN4 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage. D6 D6 1* D2 D2 1* AIN5 VLOW Limit Register (Read/Write) [Address = 32h] Table 53. AIN5 VLOW Limit D7 D7 1* D3 D3 1* *Default settings at power-up. AIN4 VHIGH Limit Register (Read/Write) [Address = 2Fh] Table 50. AIN4 VHIGH Limit D0 D0 0* This limit register is an 8-bit read/write register that stores the AIN5 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN5 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage. Table 52. AIN5 VHIGH Limit D6 D6 0* D1 D1 0* AIN5 VHIGH Limit Register (Read/Write) [Address = 31h] This limit register is an 8-bit read/write register that stores the AIN3 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN3 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V. D7 D7 0* D2 D2 0* *Default settings at power-up. AIN3 VLOW Limit Register (Read/Write) [Address = 2Eh] Table 49. AIN3 VLOW Limit D3 D3 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* *Default settings at power-up. AIN6 VHIGH Limit Register (Read/Write) [Address = 33h] This limit register is an 8-bit read/write register that stores the AIN3 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN6 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage. AIN4 VLOW Limit Register (Read/Write) [Address = 30h] Table 54. AIN6 VHIGH Limit This limit register is an 8-bit read/write register that stores the AIN4 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN4 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V. D7 D7 1* D6 D6 1* D5 D5 1* D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1* *Default settings at power-up at power-up. AIN6 VLOW Limit Register (Read/Write) [Address = 34h] This limit register is an 8-bit read/write register that stores the AIN6 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the mea- Rev. A | Page 26 of 36 ADT7411 sured AIN6 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V. Table 55. AIN6 VLOW Limit D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* AIN8 VLOW Limit Register (Read/Write) [Address = 38h] This limit register is an 8-bit read/write register that stores the AIN8 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN8 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V. *Default settings at power-up. Table 59. AIN8 VLOW Limit AIN7 VHIGH Limit Register (Read/Write) [Address = 35h] D7 D7 0* This limit register is an 8-bit read/write register that stores the AIN7 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN7 value has to be greater than the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is full-scale voltage. Table 56. AIN7 VHIGH Limit D7 D7 1* D6 D6 1* D5 D5 1* D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1* *Default settings at power-up. AIN7 VLOW Limit Register (Read/Write) [Address = 36h] This limit register is an 8-bit read/write register that stores the AIN7 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN7 value has to be less than or equal to the value in this register. Because it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is 0 V. Table 57. AIN7 VLOW Limit D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* *Default settings at power-up. AIN8 VHIGH Limit Register (Read/Write) [Address = 37h] This limit register is an 8-bit read/write register that stores the AIN8 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured AIN8 value has to be greater than the value in this register. As it is an 8-bit register, the resolution is four times less than the resolution of the 10-bit ADC. The default value is fullscale voltage. Table 58. AIN8 VHIGH Limit D7 D7 1* D6 D6 1* D5 D5 1* *Default settings at power-up. D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0* *Default settings at power-up. Device ID Register (Read-Only) [Address = 4Dh] This 8-bit read-only register gives a unique identification number for this part. ADT7411 = 02h. Manufacturer’s ID Register (Read-Only) [Address = 4Eh] This register contains the manufacturer’s identification number. ADI’s is 41h. Silicon Revision Register (Read-Only) [Address = 4Fh] This register is divided into the four LSBs representing the stepping and the four MSBs representing the version. The stepping contains the manufacturer’s code for minor revisions or steppings to the silicon. The version is the ADT7411 version number, 0100b (4h). SPI Lock Status Register (Read-Only) [Address = 7Fh] Bit D0 (LSB) of this read-only register indicates whether the SPI interface is locked or not. Writing to this register will cause the device to malfunction. Default value is 00h. 0 = I2C interface. 1 = SPI interface selected and locked. SERIAL INTERFACE There are two serial interfaces that can be used on this part: I2C and SPI. The device will power up with the serial interface in I2C mode but it is not locked into this mode. To stay in I2C mode, it is recommended that the user tie the CS line to either VCC or GND. It is not possible to lock the I2C mode, but it is possible to select and lock the SPI mode. To select and lock the interface into the SPI mode, a number of pulses must be sent down the CS (Pin 4) line. The following section describes how this is done. Once the SPI communication protocol has been locked in, it cannot be unlocked while the device is still powered up. Bit D0 of the SPI Lock Status register (Address 7Fh) is set to 1 when a successful SPI interface lock has been accomplished. To reset the serial interface, the user must power down the part and power up again. A software reset does not reset the serial interface. Rev. A | Page 27 of 36 ADT7411 Serial Interface Selection The CS line controls the selection between I2C and SPI. Figure 16 shows the selection process necessary to lock the SPI interface mode. To communicate to the ADT7411 using the SPI protocol, send three pulses down the CS line as shown in Figure 33. On the third rising edge (marked as C in Figure 33), the part selects and locks the SPI interface. Communication to the device is now limited to the SPI protocol. As per most SPI standards, the CS line must be low during every SPI communication to the ADT7411, and high at all other times. Typical examples of how to connect the dual interface as I2C or SPI are shown in Figure 31 and Figure 32. VDD The ADT7411 supports SMBus packet error checking (PEC) and its use is optional. It is triggered by supplying the extra clocks for the PEC byte. The PEC is calculated using CRC-8. The frame clock sequence (FCS) conforms to CRC-8 by the polynomial C(x ) = x 8 + x 2 + x 1 + 1 Consult the SMBus specification (www.smbus.org) for more information. The serial bus protocol operates as follows: 1. VDD ADT7411 10kΩ 10kΩ CS SDA I2C ADDRESS = 1001 000 02882-A-030 SCL ADD The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master will write to the slave device. If the R/W bit is 1, the master will read from the slave device. Figure 31. Typical I2C Interface Connection LOCK AND SELECT SPI ADT7411 The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. CS VDD 820Ω 820Ω 820Ω SPI FRAMING EDGE 2. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device will pull the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. DOUT 02882-A-031 DIN SCLK Figure 32. Typical SPI Interface Connection The following sections describe in detail how to use the I2C and SPI protocols associated with the ADT7411. I2C Serial Interface Like all I2C compatible devices, the ADT7411 has a 7-bit serial address. The four MSBs of this address for the ADT7411 are set to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin can be configured three ways to give three different address options: low, floating, and high. Setting the ADD pin low gives a serial bus address of 1001 000, leaving it floating gives the Address 1001 010, and setting it high gives the Address 1001 011. The recommended pull-up resistor value is 10 kΩ. There is an enable/disable bit for the SMBus timeout. When this is enabled, the SMBus will timeout after 25 ms of no activity. To enable it, set Bit 6 of the Control Configuration 2 register. The power-up default is with the SMBus timeout disabled. Rev. A | Page 28 of 36 Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation. This is because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. ADT7411 The I2C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. This is the SCL cycle directly after the device has seen its own I2C serial bus address. Any subsequent changes on this pin will have no effect on the I2C serial bus address. followed by the data byte written to the selected data register. This is illustrated in Figure 35. To write to a different register, another START or repeated START is required. If more than one byte of data is sent in one communication operation, the addressed register will be repeatedly loaded until the last data byte has been sent. Reading Data From the ADT7411 Writing to the ADT7411 Reading data from the ADT7411 is done in a one-byte operation. Reading back the contents of a register is shown in Figure 36. The register address had previously been set up by a single-byte write operation to the Address Pointer register. To read from another register, write to the Address Pointer register again to set up the relevant register address. Thus, block reads are not possible, i.e., no I2C auto-increment. Depending on the register being written to, there are two different writes for the ADT7411. It is not possible to do a block write to this part, i.e., no I2C auto-increment. Writing to the Address Pointer Register for a Subsequent Read In order to read data from a particular register, the address pointer register must contain the address of that register. If it does not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in Figure 34. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data registers. A read operation is then performed to read the register. SPI Serial Interface The SPI serial interface of the ADT7411 consists of four wires: CS, SCLK, DIN, and DOUT. The CS is used to select the device when more than one device is connected to the serial clock and data lines. The CS is also used to distinguish between any two separate serial communications (see Figure 41 for a graphical explanation). The SCLK is used to clock data in and out of the part. The DIN line is used to write to the registers, and the DOUT line is used to read data back from the registers. The recommended pull-up resistor value is between 500 Ω and 820 Ω. Writing Data to a Register All registers are 8-bit registers so only one byte of data can be written to each register. Writing a single byte of data to one of these read/write registers consists of the serial bus address, the data register address written to the address pointer register, C B SPI FRAMING EDGE SPI LOCKED ON THIRD RISING EDGE A CS (START LOW) C B 02882-A-032 A CS (START HIGH) SPI FRAMING EDGE SPI LOCKED ON THIRD RISING EDGE Figure 33. Serial Interface—Selecting and Locking SPI Protocol 1 9 1 9 SCL 1 0 0 1 A2 A1 START BY MASTER A0 R/W P7 P6 P5 P4 P3 P2 P1 FRAME 1 SERIAL BUS ADDRESS BYTE P0 ACK. BY ADT7411 ACK. BY ADT7411 FRAME 2 ADDRESS POINTER REGISTER BYTE Figure 34. I2C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation Rev. A | Page 29 of 36 STOP BY MASTER 02882-A-033 SDA ADT7411 1 9 1 9 SCL SDA 1 0 0 1 A2 A1 A0 P7 R/W START BY MASTER P6 P5 P4 P3 P2 P1 P0 ACK. BY ADT7411 ACK. BY ADT7411 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7411 STOP BY MASTER FRAME 3 DATA BYTE 02882-A-034 SDA (CONTINUED) Figure 35. I2C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register 1 9 1 9 SCL 1 0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 ACK. BY ADT7411 START BY MASTER D0 NO ACK. BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 SINGLE DATA BYTE FROM ADT7411 STOP BY MASTER 02882-A-035 SDA Figure 36. I2C—Reading a Single Byte of Data from a Selected Register register will auto-increment from 00h to 3Fh and then loop back to start over again at 00h. The part operates in a slave mode and requires an externally applied serial clock to the SCLK input. The serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. Read Operation There are two types of serial operation: a read and a write. Command words are used to distinguish between a read and a write operation. These command words are given in Table 60. Address auto-incrementing is possible in SPI mode. Table 60. SPI Command Words Write 90h (1001 0000) Read 91h (1001 0001) Write Operation Figure 37 shows the timing diagram for a write operation to the ADT7411. Data is clocked into the registers on the rising edge of SCLK. When the CS line is high, the DIN and DOUT lines are in three-state mode. Only when the CS goes from a high to a low does the part accept any data on the DIN line. In SPI mode, the address pointer register is capable of auto-incrementing to the next register in the register map without having to load the address pointer register each time. In Figure 37, the register address portion of the diagram gives the first register that will be written to. Subsequent data bytes will be written into sequential writable registers. Thus, after each data byte has been written into a register, the address pointer register auto-increments its value to the next available register. The address pointer Figure 38 to Figure 40 show the timing diagrams of correct read operations. To read back from a register, first write to the address pointer register with the address to be read from. This operation is shown in Figure 38. Figure 39 shows the procedure for reading back a single byte of data. The read command is first sent to the part during the first eight clock cycles, during the following eight clock cycles the data contained in the register selected by the address pointer register is output onto the DOUT line. Data is output onto the DOUT line on the falling edge of SCLK. Figure 40 shows the procedure when reading data from two sequential registers. Multiple data reads are possible in SPI interface mode as the address pointer register is auto-incremental. The address pointer register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh. SMBus/SPI INT/INT The ADT7411 INT/INT output is an interrupt line for devices that want to trade their ability to master for an extra pin. The ADT7411 is a slave-only device and uses the SMBus/SPI INT/INT to signal the host device that it wants to talk. The SMBus/SPI INT/INT on the ADT7411 is used as an over/under limit indicator. Rev. A | Page 30 of 36 ADT7411 The INT/INT pin has an open-drain configuration that allows the outputs of several devices to be wired-AND together when the INT/INT pin is active low. Use C6 of the Control Configuration 1 register to set the active polarity of the INT/INT output. The power-up default is active low. The INT/INT output can be disabled or enabled by setting C5 of Control Configuration 1 register to a 1 or 0, respectively. The INT/INT output requires an external pull-up resistor. This can be connected to a voltage different from VDD, provided the maximum voltage rating of the INT/INT output pin is not exceeded. The value of the pull-up resistor depends on the application, but should be as large enough to avoid excessive sink currents at the INT/INT output, which can heat the chip and affect the temperature reading. The INT/INT output becomes active when either the internal temperature value, the external temperature value, VDD value, or any of the AIN input values exceed the values in their corresponding THIGH/VHIGH or TLOW/VLOW registers. The INT/INT output goes inactive again when a conversion result has the measured value back within the trip limits and when the status register associated with the out-of-limit event is read. The two Interrupt Status registers show which event caused the INT/INT pin to go active. SMBus Alert Response The INT/INT pin behaves the same way as an SMBus alert pin when the SMBus/I2C interface is selected. It is an open-drain output and requires a pull-up to VDD. Several INT/INT outputs can be wire-AND together, so that the common line will go low if one or more of the INT/INT outputs goes low. The polarity of the INT/INT pin must be set for active low for a number of outputs to be wire-AND together. CS 1 8 8 1 SCLK DIN D6 D7 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 D2 D1 D0 START WRITE COMMAND REGISTER ADDRESS CS (CONTINUED) 1 8 SCLK (CONTINUED) D6 D4 D5 D3 D2 D1 D0 02882-A-036 D7 DIN (CONTINUED) STOP DATA BYTE Figure 37. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register CS 1 8 8 1 SCLK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STOP START WRITE COMMAND REGISTER ADDRESS Figure 38. SPI—Writing to the Address Pointer Register to Select a Register for Subsequent Read Operation Rev. A | Page 31 of 36 02882-A-037 DIN ADT7411 CS 1 8 8 1 DIN D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X DOUT X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 STOP START READ COMMAND DATA BYTE 1 02882-A-038 SCLK Figure 39. SPI—Reading a Single Byte of Data from a Selected Register CS 1 8 8 1 SCLK DIN D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X DOUT X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 START READ COMMAND DATA BYTE 1 CS (CONTINUED) 1 8 DIN (CONTINUED) DOUT (CONTINUED) X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 02882-A-039 SCLK (CONTINUED) STOP DATA BYTE 2 Figure 40. SPI—-Reading Two Bytes of Data from Two Sequential Registers SPI READ OPERATION WRITE OPERATION 02882-A-040 CS Figure 41. SPI—Correct Use of CS during SPI Communications The INT/INT output can operate as an SMBALERT function. Slave devices on the SMBus can normally not signal to the master that they want to talk, but the SMBALERT function allows them to do so. SMBALERT is used in conjunction with the SMBus general call address. One or more INT/INT outputs can be connected to a common SMBALERT line connected to the master. When the SMBALERT line is pulled low by one of the devices, the following procedure occurs, as shown in Figure 42. Rev. A | Page 32 of 36 ADT7411 ALERT RESPONSE NO RD ACK DEVICE ADDRESS STOP ADDRESS ACK MASTER SENDS ARA AND READ COMMAND If more than one device’s INT/INT output is low, the one with the lowest device address will have priority, in accordance with normal SMBus specifications. DEVICE SENDS ITS ADDRESS 5. Once the ADT7411 has responded to the alert response address, it will reset its INT/INT output, provided that the condition that caused the out-of-limit event no longer exists and the status register associated with the out-oflimit event is read. If the SMBALERT line remains low, the master will send the ARA again. It will continue to do this until all devices whose SMBALERT outputs were low have responded. Figure 42. INT/INT Responds to SMBALERT ARA 1. SMBALERT is pulled low. 2. Master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. 3. The device whose INT/INT output is low responds to the alert response address and the master reads its device address. As the device address is seven bits long, an LSB of 1 is added. The address of the device is now known and it can be interrogated in the usual way. MASTER RECEIVES SMBALERT START ALERT RESPONSE ADDRESS MASTER SENDS ARA AND READ COMMAND DEVICE ACK RD ACK MASTER ACK DEVICE ACK ADDRESS DEVICE SENDS ITS ADDRESS PEC MASTER NACK NO ACK DEVICE SENDS ITS PEC DATA Figure 43. INT/INT Responds to SMBALERT ARA with Packet Error Checking (PEC) Rev. A | Page 33 of 36 STOP 02882-A-042 START 4. 02882-A-041 MASTER RECEIVES SMBALERT ADT7411 OUTLINE DIMENSIONS 0.193 BSC 9 16 0.154 BSC 1 0.236 BSC 8 PIN 1 0.069 0.053 0.065 0.049 0.010 0.025 0.004 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AB Figure 44. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Purchase of licensed I2C components of Analog Devices, Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ORDERING GUIDE Model ADT7411ARQ ADT7411ARQ-REEL ADT7411ARQ-REEL7 ADT7411ARQZ10 ADT7411ARQZ-REEL1 ADT7411ARQZ-REEL71 10 Temperature Range −40°C to +120°C −40°C to +120°C −40°C to +120°C −40°C to +120°C −40°C to +120°C −40°C to +120°C Package Description 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP Z = Pb-free part. Rev. A | Page 34 of 36 Package Option RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 Minimum Quantities/Reel N/A 2500 1000 N/A 2500 1000 ADT7411 NOTES Rev. A | Page 35 of 36 ADT7411 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.. C02882-0-3/04(A) Rev. A | Page 36 of 36