Fairchild FAN7319M Lcd backlight inverter drive ic Datasheet

FAN7319
LCD Backlight Inverter Drive IC
Features
Description
High-Efficiency Single-Stage Power Conversion
Wide Input Voltage Range: 10V to 24V
Backlight Lamp Ballast and Soft Dimming
Minimal Required External Components
Precision Voltage Reference Trimmed to 2%
ZVS or ZCS Push-Pull & Full-Bridge Topology
PWM Control at Fixed Frequency
ZCS Control by Sensing Resonant Tank Current
External Pulse Burst Dimming Function - Positive
Analog Dimming Function - Positive
Programmable Striking Frequency
Open-Lamp Protection
Open-Lamp Regulation
Short-Lamp Protection
CMP-High Protection
Dynamic Contrast Ratio Mode
Thermal Shutdown
20-Pin SOP
The FAN7319 is a LCD backlight inverter drive IC that
controls N-N push-pull topology or N-N full-bridge
topology using a proprietary phase-shift method.
The FAN7319 provides a low-cost solution and reduces
external components by integrating full-wave rectifiers for
open-lamp protection and regulation. The operating
voltage range is wide, so an external regulator isn’t
necessary to supply voltage to the IC.
The FAN7319 provides various protections, such as
open-lamp regulation, open-lamp protection, short-lamp
protection, CMP-high protection, and FB-high protection,
to increase the system reliability. The FAN7319 provides
burst dimming function and analog dimming.
The FAN7319 is available in a 20-Lead Small Outline
Integrated Circuit (SIOC) package.
Applications
LCD TV
LCD Monitor
Ordering Information
Part Number
Operating Temperature
Package
Packing Method
FAN7319M
-25 to +85°C
FAN7319MX
-25 to +85°C
20-Lead, SOIC, JEDEC
MS-013, .300 Inch, Wide Body
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
Rail
www.fairchildsemi.com
FAN7319 — LCD Backlight Inverter Drive IC
June 2011
FAN7319 — LCD Backlight Inverter Drive IC
Block Diagram
Figure 1. Internal Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
2
FAN7319 — LCD Backlight Inverter Drive IC
Pin Configuration
VOLP
1
20
ENA
REF
2
19
OVPR
BDIM
3
18
MODE
ADIM
4
17
OLP
CMP
5
16
OLR
TIMER
6
15
VIN
RT
7
14
OUTA
RT1
8
13
OUTB
SENSE
9
12
OUTC
GND
10
11
OUTD
F: Fairchild Logo
P: Assembly Site Code
XY: Year & Weekly Code
TT: Die Run Code
FAN7319: Device Name
Figure 2. Pin Diagram with Top Mark
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
3
Pin #
Name
1
VOLP
2
REF
This pin is 5V reference output.
3
BDIM
This pin is the input for burst dimming. Input type is PWM pulse signal, not DC voltage.
Dimming polarity is positive.
4
ADIM
This pin is for positive analog dimming.
5
CMP
Error amplifier output. Typically, a compensation capacitor is connected to this pin from the
ground.
6
TIMER
7
RT
This pin is for programming the normal switching frequency. Typically, a resistor is
connected to this pin from ground.
8
RT1
This pin is for programming the striking switching frequency. In striking mode, this pin is
connected to ground. Typically, a resistor is connected to this pin from the RT pin.
9
SENSE
10
GND
11
OUTD
This pin is lower NMOS gate-drive output 2. (Push-Pull : Disabled)
12
OUTC
This pin is upper NMOS gate-drive output 2. (Push-Pull : Disabled)
13
OUTB
This pin is lower NMOS gate-drive output 1. (Push-Pull : NMOS gate-drive output 2)
14
OUTA
This pin is upper NMOS gate-drive output 1. (Push-Pull : NMOS gate-drive output 1)
15
VIN
This pin is the supply voltage of the IC.
OLR
This pin is for open-lamp regulation. It is connected to the full-wave rectifier internally. If two
feedbacks are available, sum of feedback is inputted to this pin. When OLR input is between
2V and 3V, the error amplifier output current is limited to 3µA. When OLR input reaches 3V,
the error amplifier output current is 0A and its output voltage maintains constant. OLR input
is inputted to the negative of another error amplifier for feedback control of lamp voltage.
When OLR input is more than 3.3V, another error amplifier for OLR is operating and lamp
voltage is regulated.
17
OLP
This pin is for open-lamp protection and feedback control of lamp currents. It is connected to
the full-wave rectifier internally. If two feedbacks are available, sum of rectified feedback is
inputted to this pin. In striking mode, if OLP input is less than 1V; or in normal mode, if OLP
input is less than 0.5V; the IC shuts down to protect the system in open-lamp condition.
Shutdown time is programmed by the capacitor value connected to the TIMER pin. OLP
input is inputted to the negative of the error amplifier for feedback control of lamp current.
18
MODE
This pin is for topology selection. If this pin is connected to REF, it is push-pull topology;
OUTC & OUTD is disabled. If this pin is connected to GND, it is full-bridge topology.
19
OVPR
This pin is for reference voltage of Over-Voltage Protection (OVP).
20
ENA
16
Description
This pin is for reference voltage of open-lamp protection level in striking mode.
This pin is for protection delay setting. Typically, a capacitor is connected to this pin from
ground. OVP/OLP/High_CMP/SLP protection time is set by this capacitor value.
This pin is for sensing Zero Voltage Switching (ZVS) timing. If voltage cross 0V, CT voltage
is reset; and operating frequency is changed by ZVS timing. If this pin is not used, it must be
connected to REF.
This pin is the ground.
This pin is for turning on/off the IC. If enable voltage is lower than 2.1V, DCR mode is
disabled. If enable voltage is higher than 2.5V, DCR mode is activated and OLP is disabled.
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
4
FAN7319 — LCD Backlight Inverter Drive IC
Pin Definitions
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VIN
IC Supply Voltage
10
28
V
TA
Operating Temperature Range
-25
+85
°C
TJ
Operating Junction Temperature
+150
°C
+150
°C
90
°C/W
1.4
W
TSTG
Storage Temperature Range
-65
θJA
Thermal Resistance Junction-to-Air
PD
Power Dissipation
(1,2)
Notes:
1. Thermal resistance test board. Size: 76.2mm x 114.3mm x 1.6mm (1S0P); JEDEC standard: JESD51-2, JESD51-3.
2. Assume no ambient airflow.
Pin Breakdown Voltage
Pin #
Name
Value
1
RT
7
Unit
Pin #
Name
Value
11
OLR
±7
2
ENA
7
12
OLP
±7
3
CMP
7
13
GND
7
4
ADIM
7
14
OUTA
28
5
REF
7
15
OUTB
28
6
MODE
7
16
OUTC
28
7
BDIM
7
17
OUTD
28
8
OVPR
7
18
VIN
28
V
9
VOLR
7
19
TIMER
7
10
SENSE
±7
20
RT1
7
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
Unit
V
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FAN7319 — LCD Backlight Inverter Drive IC
Absolute Maximum Ratings
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to TA=
-25°C ~ 85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Start Threshold Voltage
8.0
8.7
9.4
V
Start Threshold Voltage Hysteresis
0.4
0.8
1.2
V
Under-Voltage Lockout Section (UVLO)
Vth
Vthhys
Ist
Startup Current
VIN = 9.0V
40
100
120
µA
Iop
Operating Supply Current
VIN = 15V,
Not Switching
0.5
2.0
3.5
mA
5.0
V
0.7
V
ON/OFF Section
Von
On-State Input Voltage
Voff
Off-State Input Voltage
Isb
Standby Current
RENA
1.4
VIN = 15V,
ENA = LOW
Pull-Down Resistor
100
160
200
µA
120
200
280
kΩ
4.9
5.0
5.1
V
Reference Section (Recommend 1µF X7R Capacitor)
V5
5V Regulation Voltage
0 ≤ I5 ≤ 3mA
V5line
5V Line Regulation
10 ≤ VIN ≤ 24V
4
50
mV
V5load
5V Load Regulation
I5 = 3mA
4
50
mV
Oscillator Section (Main)
fosc
fstr
Oscillation Frequency
Oscillator Frequency in Striking Mode
TA = 25°C,
RT = 50kΩ
48.50
50.0
51.50
RT = 50kΩ
48.25
50.00
51.75
TA = 25°C, RT =
50kΩ, RT1 = 100kΩ
68.90
71.45
74.00
RT = 50kΩ,
RT1 = 100kΩ
68.60
kHz
kHz
71.45
74.30
Vcth
CT High Voltage
2
V
Vctl
CT Low Voltage
0.45
V
Burst Dimming Section
Vbdim(ON)
Burst Dimming On Voltage
2
5
V
Vbdim(Off)
Burst Dimming Off Voltage
0
0.8
V
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
6
FAN7319 — LCD Backlight Inverter Drive IC
Electrical Characteristics
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to TA =
-25°C ~ 85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Error Amplifier Section
(3)
AV
Open-Loop Gain
24
Gm
Error Amplifier Transconductance
lsin
Output Sink Current
lsur1
dB
20
40
60
µmho
OLP = 2.25V
30
50
70
µA
Output Source Current 1
OLP = 0V
20
40
60
µA
lsur2
Output Source Current 2
CMP = 2.7V
1.4
2.0
2.6
µA
Ibsin
Burst CMP Sink Current
38
52
66
µA
Iolpi
OLP Input Current
OLP = 2V
-1
0
1
µA
Iolpo
OLP Output Current
OLP = -2V
10
20
30
µA
4
V
(3)
Volpr
OLP Input Voltage Range
Valim
ADIM Limit Voltage
Voff1
-4
ADIM = 2V
Error Amplifier Offset
1.5
V
TA = 25°C, VADIM = 1V
0.97
1.00
1.03
V
-25°C ≤ TA ≤ 85°C,
VADIM = 1V
0.96
1.00
1.04
V
Striking, OLR =
Volr1+0.05
2.5
3.0
3.5
µA
OLR = 3.1V
-1
0
1
µA
Open-Lamp Regulation Section
Iolr1
Iolr2
Error Amplifier Source Current for
Open-Lamp Regulation
Volr1
Open-Lamp Regulation Voltage 1
Striking
1.85
2.00
2.15
V
Volr2
Open-Lamp Regulation Voltage 2
Striking
2.8
3.0
3.2
V
Volr3
Open-Lamp Regulation Voltage 3
3.05
3.25
3.45
V
Iolrsi
OLR Error Amplifier Sink Current
Normal, OLR = 3.5V
15.0
42.5
70.0
µA
Iolri
OLR Input Current
OLR = 2.5V
-1
0
1
µA
Iolro
OLR Output Current
OLR = -2.5V
15
25
35
µA
4
V
Volrr
OLR Input Voltage Range
(3)
-4
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
7
FAN7319 — LCD Backlight Inverter Drive IC
Electrical Characteristics (Continued)
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to TA=
-25°C ~ 85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Protection Section
Volp0
Open-Lamp Protection Voltage 0
Open Lamp in Striking
Volp1
Open-Lamp Protection Voltage 1
Normal, Vena = 2V
Vcmpr
CMP-High Protection Voltage
VOLP
V
0.4
0.5
0.6
V
2.85
3.00
3.15
V
Vslp
Short-Lamp Protection Voltage
Normal, Vena = 2V
0.4
0.5
0.6
V
Vtmr1
Timer Threshold Voltage 1
Striking: Repeat 4 Times
2.9
3.0
3.1
V
Vtmr2
Timer Threshold Voltage 2
Normal
0.9
1.0
1.1
V
Itmr1
Timer Current 1
Open Lamp
1.6
2.0
2.4
µA
Itmr2
Timer Current 2
Short Lamp
40
50
60
µA
TSD
Thermal Shutdown
Vovp
Over-Voltage Protection Voltage
VDCR
ENA2.3V OLP Disable/Enable Change
Voltage
150
°C
VOVPR
V
2.1
2.3
2.5
V
VIN = 12V
VIN -0.5
VIN
VIN +0.5
V
VIN = 12V
-0.3
0
0.3
V
0
0.3
V
Output Section
Vndhv
NMOS Gate High Voltage
(3)
Vndlv
NMOS Gate Low Voltage
Vnuv
NMOS Gate Voltage with UVLO
Activated
VIN = 4.5V
Indsur
NMOS Gate Drive Source Current
VIN = 12V
200
mA
Indsin
NMOS Gate Drive Sink Current
VIN = 12V
300
mA
0
%
Maximum / Minimum Overlap
Minimum Overlap Between Diagonal
Switches
fosc = 100kHz,
See Figure 14
Maximum Overlap Between Diagonal
Switches
fosc = 100kHz
See Figure 14
86
tD_AB
NDR_A/NDR_B
See Figure 34
450
tD_CD
NDR_C/NDR_D
See Figure 35
450
90
%
550
650
ns
550
650
ns
Dead Time
Note:
3. These parameters, although guaranteed, are not 100% tested in production.
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
8
FAN7319 — LCD Backlight Inverter Drive IC
Electrical Characteristics (Continued)
8.8
8.79
8.78
8.77
8.76
8.75
8.74
8.73
8.72
8.71
8.7
1
Vthhys [V]
Vth [V]
0.9
0.8
0.7
0.6
0.5
-25
-15
0
25
50
70
-25
85
-15
0
TEMP [℃
℃]
25
50
70
85
TEMP [℃
℃]
Figure 3. Start Threshold Voltage vs. Temperature
Figure 4. Start Threshold Voltage Hysteresis
vs. Temperature
4
145
130
3
100
Iop1 [mA]
Ist [µA]
115
85
70
2
1
55
40
0
-25
-15
0
25
50
70
85
-25
-15
0
TEMP [℃
℃]
25
50
70
85
TEMP [℃
℃]
Figure 5. Startup Current vs. Temperature
Figure 6. Operating Current vs. Temperature
5.2
300
250
5.1
V5 [V]
Isb [µA]
200
150
100
5
4.9
50
0
4.8
-25
-15
0
25
50
70
85
-25
TEMP [℃
℃]
0
25
50
70
85
TEMP [℃
℃]
Figure 7. Standby Current vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
-15
Figure 8. 5V Regulation Voltage vs. Temperature
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9
FAN7319 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics
98
140
138
96
fstr [kHz]
fosc [kHz]
136
94
92
134
132
90
130
-25
-15
0
25
50
70
85
-25
-15
0
TEMP [℃
℃]
50
70
85
TEMP [℃
℃]
Figure 9. Oscillation Frequency vs. Temperature
Figure 10. Oscillation Frequency in Striking
vs. Temperature
0.6
1.05
0.55
Voff05 [V]
1.1
Voff1 [V]
25
1
0.95
0.5
0.45
0.9
0.4
-25
-15
0
25
50
70
85
-25
-15
0
TEMP [℃
℃]
25
50
70
85
TEMP [℃
℃]
Figure 11. Error Amplifier Offset 1 vs. Temperature
Figure 12. Error Amplifier Offset 05 vs. Temperature
-1
-20
-25
-1.5
-35
Isur2 [µA]
Isur1 [µA]
-30
-40
-45
-2
-2.5
-50
-55
-3
-25
-15
0
25
50
70
85
-25
TEMP [℃
℃]
0
25
50
70
85
TEMP [℃
℃]
Figure 13. Error Amplifier Source Current 1
vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
-15
Figure 14. Error Amplifier Source Current 2
vs. Temperature
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10
FAN7319 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
-2
90
-2.5
80
70
Isin [µA]
Iolr1 [µA]
-3
-3.5
-4
60
50
40
-4.5
30
-5
20
-25
-15
0
25
50
70
85
-25
-15
0
TEMP [℃
℃]
65
60
60
50
55
30
45
20
0
25
50
70
85
-25
-15
0
TEMP [℃
℃]
85
25
50
70
85
TEMP [℃
℃]
Figure 17. Burst CMP Sink Current vs. Temperature
Figure 18. OLR Error Amplifier Sink Current
vs. Temperature
3.2
0.55
3.1
Vcmpr [V]
0.6
Volp1 [V]
70
40
50
-15
50
Figure 16. Error Amplifier Sink Current
vs. Temperature
Iors [µA]
Ibsin [µA]
Figure 15. Error Amplifier Source Current for OLR
vs. Temperature
-25
25
TEMP [℃
℃]
0.5
0.45
0.4
3
2.9
2.8
-25
-15
0
25
50
70
85
-25
TEMP [℃
℃]
0
25
50
70
85
TEMP [℃
℃]
Figure 19. Open-Lamp Protection Voltage 1
vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
-15
Figure 20. High-CMP Protection Voltage
vs. Temperature
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FAN7319 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
0.7
2.3
0.6
2.2
2.1
Volr 1 [V]
Vslp [V]
0.5
0.4
2
1.9
0.3
1.8
0.2
1.7
-25
-15
0
25
50
70
85
-25
-15
0
TEMP [℃
℃]
25
50
70
85
TEMP [℃
℃]
Figure 21. Short-Lamp Protection Voltage
vs. Temperature
Figure 22. Open-Lamp Regulation Voltage 1
vs. Temperature
3.35
3.2
3.15
3.3
Volr3 [V]
Volr 2 [V]
3.1
3.25
3.05
3
3.2
2.95
2.9
3.15
-25
-15
0
25
50
70
85
-25
-15
0
TEMP [℃
℃]
25
50
70
85
TEMP [℃
℃]
Figure 23. Open-Lamp Regulation Voltage 2
vs. Temperature
Figure 24. Open-Lamp Regulation Voltage 3
vs. Temperature
3.3
1.1
3.2
1.05
Vtmr2 [V]
Vtmr1 [V]
3.1
3
2.9
1
0.95
2.8
2.7
0.9
-25
-15
0
25
50
70
85
-25
TEMP [℃
℃]
0
25
50
70
85
TEMP [℃
℃]
Figure 25. TIMER Threshold Voltage 1
vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
-15
Figure 26. TIMER Threshold Voltage 2
vs. Temperature
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FAN7319 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
2.1
70
65
2.05
Itmr2 [µA]
Itmr1 [µA]
60
2
1.95
55
50
45
1.9
40
-25
-15
0
25
50
70
85
-25
TEMP [℃
℃]
0
25
50
70
85
TEMP [℃
℃]
Figure 27. TIMER Current 1 vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
-15
Figure 28. TIMER Current 2 vs. Temperature
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13
FAN7319 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
UVLO
Analog Dimming
The under-voltage lockout (UVLO) circuit guarantees
stable operation of the IC control circuit by stopping and
starting it as a function of VIN. The UVLO circuit turns on
the control circuit when VIN exceeds 9V. When VIN is
lower than 8V, the IC startup current is less than 1
120µA.
For analog dimming, reference voltage of the internal
error amplifier can be controlled by the ADIM pin. Error
amplifier control average voltage of OLP input voltage.
The ADIM polarity of ADIM is positive.
The
he peak OLP voltage can be calculated as:
ENA
Applying voltage higher than 1.4V
V to the ENA pin
enables the IC. If VENA is higher than 2.5V, the IC enters
DCR mode. If VENA is lower than 2.1V, IC enters normal
mode. Applying voltage lower than 0.7V to the ENA pin
disables the IC.
max
VOLP
= V ADIM
The internal timing capacitors (CTs) are charged by the
reference current source, which is formed by the timing
resistor (RT). The timing resistor’s voltage is regulated at
2V.
V. The sawtooth waveform charges up to 2V. Once this
voltage is reached, the capacitors begin d
discharging
down to 0.5V.
V. Next, the timing capacitors start charging
again and a new switching cycle begins. The main
frequency can be programmed by adjusting the RT
values. The main frequency can be calculated as
as:
500
[kHz]
0.000189 • RT[kΩ ] + t delay
where tdelay is:
20 < RT[kΩ] < 30
30 < RT[kΩ] < 40
40 < RT[kΩ] < 60
60 < RT[kΩ] < 70
:
:
:
:
(4)
The lamp intensity is proportional to VADIM. As VADIM
increases, the lamp intensity increases; but ADIM voltage
is clamped by 1.5V internally. Even if ADIM voltage is
higher than 1.5V, internal error amplifier reference is set to
1.5V. Figure 30 shows an example of the relationship
between ADIM voltage and output current.
Main Oscillator
fOSC =
π
[V ]
2
(1)
0.00075
0.00070
0.00055
0.00050
Figure 30. ADIM Voltage vs. Output Current
Figure 31 shows the lamp current waveform vs. VADIM in
analog dimming mode.
Ichar =
2V
/ 20
Rt
1.3V
VADIM
0.5V
CMP
12pF
i max
Lamp
2V
Idis =
Rt
iLamp
0
0
Figure 29. Main Oscillator Circuit
Figure 31. Analog Dimming Waveforms
In striking mode, the timing resistor for striking (RT1) is
connected to ground internally. The
he total timing resistor is
the parallel connecting value of RT and RT1. The
calculation of the striking
triking frequency is similar with
Equation
quation (1). RT is only different with normal frequency.
RT value for striking frequency is calculate
calculated as:
RTstr =
RT • RT1
RT + RT1
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
(2)
www.fairchildsemi.com
14
FAN7319 — LCD Backlight Inverter Drive IC
Functional Description
Output Drives
Lamp intensity is controlled with the BDIM signal over a
wide range. When BDIM voltage is higher than 2V, the
lamp current is turned on. When BDIM voltage is lower
than 0.8V, the lamp current is turned off. The duty cycle
of the PWM pulse determines the lamp brightness. The
lamp intensity is proportional to BDIM pulse on duty; as
BDIM on duty increases, the lamp intensity increases.
Figure 32 shows the lamp current waveform vs. VBDIM.
FAN7319 can drive topologies for half-bridge and fullbridge in Super-IP applications. If the MODE pin is
connected to reference voltage, output drive is a pushpull topology. In Super-IP applications, push-pull
topology can drive a half-bridge resonant circuit. If the
MODE pin is connected to ground, output drive is a fullbridge topology. FAN7319 uses a phase-shift method for
full-bridge Cold Cathode Fluorescent Lighting (CCFL)
drive. As a result, the temperature difference between
the left and right leg is almost zero because ZVS occurs
in both of the legs by turns. The detail timing is shown in
Figure 34 and Figure 35.
FAN7319 drive voltage is same as VIN supply voltage, so
it can drive a pulse transformer without any additional
buffer. To prevent over-current in output drive, add a
series resistor between the OUT pin and the pulsetransformer (22~47Ω series resistor is enough).
Figure 32. Burst-Dimming Waveforms
During striking mode, burst-dimming operation is
disabled to guarantee continuous striking time. Figure 33
shows burst-dimming is disabled during striking mode.
Figure 34. Push-Pull Mode Gate Drive Signal
Fixed dead time
550ns
Fixed dead time
550ns
CT
CMP
SYNC
T
T1
OUTA
OUTB
OUTC
OUTD
Figure 33. Burst-Dimming During Striking Mode
Figure 35. Full-Bridge Mode Gate Drive Signal
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
15
FAN7319 — LCD Backlight Inverter Drive IC
Burst-Dimming
FAN7319 can be operated as zero current switching
(ZCS) or zero voltage switching (ZVS) mode using the
SENSE pin. Internal CT voltage is forced to discharge
when the SENSE pin voltage crosses the zero point. If
AC signal is applied to the SENSE pin, operating
frequency is synchronous with a frequency of input
signal. Figure 36 shows the synchronous operation in
push-pull topology.
During striking mode, the operating frequency is set to
fixed frequency by a resistor, regardless of the SENSE
pin zero crossing point.
Figure 37. Timer Charging Circuit
Assume that timer capacitor is 1µF.
The SENSE pin zero crossing frequency is faster than
set frequency. If zero crossing frequency is slower than
set frequency, frequency is abnormal due to irregular
discharging of CT voltage.
Striking time is one-time charging from zero to 3V and
four-times charging from 0.3V to 3V with 2µA current
source. The striking time is calculated as follows:
If SENSE zero crossing frequency is much faster than
set frequency, CT discharging voltage could be lower
than 1.5V. In this case, CT discharging voltage is held to
1.5V to prevent synchronous frequency being too high.
tstrike =
C∆Vstr 1µF • 3V
1µF • 2.7V
=
+4•
= 6.9s
Isur1
2µF
2 µF
(6)
The OVP and SLP delay times are calculated as:
t OVP _ SLP =
C∆Vnor 1µF • 1V
=
= 20ms
Isur 2
50µF
(7)
The CMP-HIGH protection and OLP delay times are
calculated as:
SENSE
t OLP _ CMPH =
2V
CT
C∆Vnor 1µF • 1V
=
= 500ms
Isur1
2µF
(8)
CMP
0.5V
Open-Lamp Regulation
When the maximum of the rectified OLR input voltages
max
is more than 3V, the IC enters regulation mode
V
OLR
and controls the CMP voltage. The IC limits the lamp
max
voltage by decreasing the CMP source current. If V
OLR
is between 2V and 3V, the CMP source current
max
reaches
decreases from 40µA to 3µA. Then, if V
OLR
3V, CMP source current decreases to 0µA, so CMP
voltage remains constant and the lamp voltage also
remains constant, as shown in Figure 38. Finally, if
max
is more than 3.25V, the error amplifier for OLR is
V
OLR
operating and CMP sink current increases, so CMP
voltage decreases and the lamp voltage maintains the
determined value.
SYNC
T
OUTA
OUTB
Figure 36. Synchronous Operation in Push-Pull Mode
Protections
The FAN7319 provides the following latch-mode
protections: Open-Lamp Regulation (OLR), Open-Lamp
Protection (OLP), Short-Lamp Protection (SLP), CMPHIGH Protection, and Thermal Shutdown (TSD). The
latch is reset when VIN falls to the UVLO voltage or ENA
is pulled down to GND.
max
is more than OVPR, the
OLR
50µA current source starts charging TIMER capacitor in
normal mode. When TIMER voltage reaches 1V, the IC
enters shutdown, as shown in Figure 40. This protection
is disabled in striking mode to ignite lamps reliably.
At the same time, while V
Protection timing can be calculated based on Figure 37.
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
16
FAN7319 — LCD Backlight Inverter Drive IC
Synchronous Drives
Figure 38. Open-Lamp Regulation in Striking Mode
Figure 41. Open-Lamp Protection in Striking Mode
Figure 39. Open-Lamp Regulation in Normal Mode
CMP
0
OVPR
OLR
Figure 42. Open-Lamp Protection in Normal Mode
0
-OVPR
1V
TIMER
0
OUTA
OUTB
0
OUTC
OUTD
0
Figure 40. Over-Voltage Protection in Normal Mode
Open-Lamp Protection
min
is
OLR
during initial operation, the IC operates in
If the minimum of the rectified OLP voltage V
less than VOLP
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
Figure 43. Open-Lamp Protection in DCR Mode
www.fairchildsemi.com
17
FAN7319 — LCD Backlight Inverter Drive IC
striking mode only for 6.9s, as shown in Figure 41. After
min
is less than 0.5V in normal mode, the
ignition, if V
OLR
IC is shut down after a delay of 500ms, as shown in
min
is less
Figure 42. In DCR mode (VENA>2.5V), if V
OLR
than 0.5V in normal mode; the IC operates normally
without shutdown, as shown in Figure 43.
Figure 44. Short-Lamp Protection in Normal Mode
Figure 46. CMP-High Protection in Normal Mode
Thermal Shutdown
The IC provides a function to detect abnormal overtemperature.
If
the
IC
temperature
exceeds
approximately 150°C, the thermal shutdown triggers.
Figure 45. Short-Lamp Protection in DCR Mode
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
18
FAN7319 — LCD Backlight Inverter Drive IC
CMP-High Protection
If CMP is 2.5V in normal mode, OLP peak voltage is
higher than ADIM voltage and CMP voltage is holding at
2.5V. If CMP is 2.5V in normal mode, OLP peak voltage
is lower than ADIM voltage and CMP is charged by 1µA
current source. If CMP is higher than 3V, the IC is shut
down after a delay of 500ms, as shown in Figure 46. This
protection is disabled in striking mode to ignite lamps
reliably. To remove CMP-HIGH protection, connect a
1MΩ resistor to CMP capacitor in parallel. Unless 1µA
sourcing current flows into the resistor, CMP voltage
cannot be charged.
Short-Lamp Protection
min
If the minimum of the rectified OLR voltages ( VOLR
) is
less than 0.5V in normal mode, the IC is shut down after
a delay of 20ms, as shown in Figure 44. In DCR mode
(VENA>2.5V), if V min is less than 0.5V in normal mode;
OLR
the IC operates normally without shutdown, as shown in
Figure 45. This protection is disabled in striking mode to
ignite lamps reliably.
Mode
Category
Item
Condition
Operation
OLR
VOLR(MAX)>2V
CMP Source = 3µA
VOLR(MAX)>3V
CMP Source = 0µA
VOLR(MAX)>3.25V
CMP Sink
VCMP>2.5V &
VADIM>VOLP(MAX)
CMP Source = 2µA
Regulation
CMP
Striking
Protection
OLP
VOLP(MAX)<VOLP
Timer = 2µA
OVP
VOLR(MAX)>OVPR
Timer = 2µA
SLP
Disabled
Disabled
Disabled
Disabled
VOLR(MAX)>3V
CMP Source = 0µA
VOLR(MAX)>3.25V
CMP Sink
CMP
VCMP>2.5V &
VADIM>VOLP(MAX)
CMP Source = 2µA
OLP
VOLP(MAX)<0.5V
Timer = 2µA
OVP
VOLR(MAX)>OVPR
Timer = 50µA
SLP
VOLR(MAX)<0.3V
Timer = 50µA
CMP-HIGH
VCMP>3V
Timer = 2µA
Regulation
Protection
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
Fault
Condition
Changing to
Normal
Frequency
Condition
VTIMER>3V,
5 Times
Repeat
CMP-HIGH
OLR
Normal
DCR Mode
VENA > 2.5V
Disabled
VOLP(max)>VOLP
&
VOLR(max)<OVPR
VTIMER>1V,
1 Time
Disabled
www.fairchildsemi.com
19
FAN7319 — LCD Backlight Inverter Drive IC
Table 1. Protection Condition Table
Application
Input Voltage Range
Number of Lamps
LCD TV (LIPS Type)
13±10%
CCFL/EEFL IP
OLR
PFC_OUT(380Vdc)
F1
450V
CN3
CN_CCFL
R16
FDPF7N50F
R101
R102
SOT-23
BAV70
R109
68R
R104
1k
OUTD
R105
12k
22R
1.8R
Q101
R103
Q2N2222A
12k
C102 SOT-23
1n
D8
BAV70
C3
27pF/6KV
M1
T1
CN4
CN_CCFL
1
2
1
Puls e
Trans form er
0
30k
R15
10k
2
1
L1 = 700uH / L2 = 400uH
K=0.98
22p
2
450V
C11
FUSE
1
C52
100uF
2
C51
100uF
C6
27pF/6KV
SOT-23
TO-220F
C101
OPEN
ZD101
open
SOD-123
C5
C7
15n\
600V
R12
10k
R14
10k
C8
15n
T3
D101
R108
R201
680nF
R202
M2
OUTC
22R
SOT-23
68R
R204
BAV70
1k
R205
12k
C202
1n
1.8R
R203
Q201
12k
Q2N2222A
SOT-23
0
TO-220F
C201
OPEN
ZD201
open
R33
SENSE
FDPF7N50F
SOD-123
R20
33
open
R21
OPEN
1W
1W
D10 BAV70
SOT-23
D201
R19
0
Puls e
Trans form er
T2
SOT-23
1k
OUTB
R302
R305
12k
22R
D301
1.8R
R303
Q301
Q2N2222A
C302 SOT-23
12k
1n
OLP
R401
ZD301
open
C401
OPEN
ZD401
open
FDPF7N50F
SOT-23
68R
R404
BAV70
1k
R405
12k
C402
1n
SOT-23
1W
0
SOD-123
R402
1.8R
R403
Q401
12k
Q2N2222A
R22
30k
R28
OPEN
1W
TO-220F
C301
OPEN
M4
FDPF7N50F
OUTA
22R
R27
33
M3
68R
R304
BAV70
R106
0
15k
R301
R107
R34
30k
TO-220F
SOD-123
D401
R56
ENA
22R
R58
33k
C27
100n
C28
1n
0
R57
VIN
R39
0
R38
10k
BDIM(External only)
ADIM
R40
open
C16
1n
R44
10k
C25
100n
4.7n
C15
CMP
C29
TIMER
1u
ADIM(Positive)
12505WR-5
0
R31
51k
SENSE
R35
15k
0
OLP
OLP
C26
1n
R59
OPEN
OLR
OLR
R60
0R
0
R52
VIN
VIN
OUTA
OUTB
OUTB
SENSE
OUTC
OUTC
GND
OUTD
OUTD
RT1
R30
82k
R55
47k
MODE
OUTA
RT
0
OVPR
FAN7319
BDIM
10k R53
1
2
3
4
5
R54
68k
ENA
REF
C24
1k
CN2
VOLP
100k
2.2u
VIN(10~24V)
REF
20-SOIC
IC2
C23
2.2u
C1
47uF
4.7R
25V
0
FAN7319
REF
Figure 47. Typical Full-Bridge Application Circuit
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
20
FAN7319 — LCD Backlight Inverter Drive IC
Typical Full-Bridge Application Circuit (LCD Backlight Inverter)
Application
Input Voltage Range
Number of Lamps
LCD TV (LIPS Type)
13±10%
CCFL/EEFL IP
OLR
PFC_OUT(380Vdc)
F1
C7
15n\
600V
CN4
CN_CCFL
1
2
1
0
30k
R15
10k
D8
BAV70
C3
25pF/6KV
C5
22p
R16
2
CN3
CN_CCFL
2
C11
FUSE
1
450V
2
C52
82uF
450V
1
C51
82uF
C6
25pF/6KV
SOT-23
R12
10k
R14
10k
C8
15n
T3
680nF
0
R33
SENSE
open
R20
33
R21
OPEN
1W
1W
R34
30k
D10 BAV70
SOT-23
R19
FDPF7N50F
Puls e
Trans form er
R301
R302
SOT-23
BAV70
1k
OUTB
68R
R304
22R
R305
12k
D301
R307
1.8R
R303
Q301
Q2N2222A
C302 SOT-23
12k
1n
R401
ZD301
15V
SOT-23
BAV70
68R
R404
1k
R405
12k
C402
1n
SOT-23
1W
C401
OPEN
ZD401
15V
1W
SOD-123
R402
1.8R
R403
Q401
12k
Q2N2222A
OLP
R22
30k
R28
OPEN
0
M4
FDPF7N50F
OUTA
22R
R27
33
TO-220F
C301
OPEN
0
15k
M3
T2
R306
0
TO-220F
SOD-123
D401
R56
ENA
22R
R58
33k
C27
100n
C28
1n
0
R57
VOLP
REF
C24
R38
10k
ADIM
R53
1
2
3
4
5
BDIM(External only)
10k
C16
1n
R44
10k
C25
100n
C15
CMP
C29
TIMER
1u
ADIM (Positive)
12505WR-5
10n
0
R31
33k
R30
open
SENSE
R35
15k
0
R55
47k
C26
1n
R59
0R
MODE
OLP
OLP
OLR
OLR
R60
OPEN
0
R52
VIN
VIN
OUTA
OUTA
RT1
OUTB
OUTB
SENSE
OUTC
GND
OUTD
RT
0
OVPR
FAN7319
BDIM
CN2
R54
68k
ENA
100k
2.2u
0
VIN
VIN(10~24V)
REF
20-SOIC
IC2
C23
2.2u
C1
47uF
4.7R
25V
0
FAN7319
REF
Figure 48. Typical Half-Bridge Application Circuit
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
21
FAN7319 — LCD Backlight Inverter Drive IC
Typical Half-Bridge Application Circuit (LCD Backlight Inverter)
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.51
0.35
PIN ONE
INDICATOR
0.25
M
0.65
1.27
1.27
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
0.33
0.20
C
0.75
0.25
X 45°
0.10 C
0.30
0.10
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
GAGE PLANE
(R0.10)
0.25
8°
0°
1.27
0.40
SEATING PLANE
(1.40)
DETAIL A
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 49. 20-Pin, Small-Outline Integrated Circuit (SOIC) Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
22
FAN7319 — LCD Backlight Inverter Drive IC
Physical Dimensions
FAN7319 — LCD Backlight Inverter Drive IC
© 2010 Fairchild Semiconductor Corporation
FAN7319 • 1.0.1
www.fairchildsemi.com
23