Infineon BTS7810K Trilithic Datasheet

TrilithIC
BTS 7810 K
Data Sheet
1
Overview
1.1
Features
•
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•
•
•
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•
•
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•
•
•
Quad D-MOS switch
Free configurable as bridge or quad-switch
Optimized for DC motor management applications
Low RDS ON: 26 mΩ high-side switch, 14 mΩ low-side
switch (typical values @ 25 °C)
Maximum peak current: typ. 42 A @ 25 °C
Very low quiescent current: typ. 4 µA @ 25 °C
Small outline, thermal optimized PowerPak
Load and GND-short-circuit-protection
Operates up to 40 V
Status flag for over temperature
Open load detection in Off-mode
Overtemperature shut down with hysteresis
Internal clamp diodes
Isolated sources for external current sensing
Under-voltage detection with hysteresis
P-TO263-15-1
Type
Ordering Code
Package
BTS 7810 K
Q67060-S6129
P-TO263-15-1
1.2
Description
The BTS 7810 K is part of the TrilithIC family containing three dies in one package:
One double high-side switch and two low-side switches. The drains of these three
vertical DMOS chips are mounted on separated leadframes. The sources are connected
to individual pins, so the BTS 7810 K can be used in H-bridge- as well as in any other
configuration. The double high-side is manufactured in SMART SIPMOS® technology
which combines low RDS ON vertical DMOS power stages with CMOS control circuit. The
high-side switch is fully protected and contains the control and diagnosis circuit. To
achieve low RDS ON and fast switching performance, the low-side switches are
manufactured in S-FET 2 logic level technology. The equivalent standard product is the
SPD30N06S2L-13.
Data Sheet
1
2003-03-11
BTS 7810 K
1.3
Pin Configuration
(top view)
Molding
Compound
NC
1
Heat-Slug 1
SL1
2
IL1
3
NC
4
IH1
5
18
DL1
Heat-Slug 2
ST1
6
SH1
7
DHVS
8
GND
9
IH2
10
ST2
11
SH2
12
17
DHVS
Heat-Slug 3
IL2
13
16
SL2
14
NC
15
DL2
Figure 1
Data Sheet
2
2003-03-11
BTS 7810 K
1.4
Pin Definitions and Functions
Pin No.
Symbol
Function
1
NC
Not connected
2
SL1
Source of low-side switch 1
3
IL1
Analog input of low-side switch 1
4
NC
Not connected
5
IH1
Digital input of high-side switch 1
6
ST1
Status of high-side switch 1; open Drain output
7
SH1
Source of high-side switch 1
8
DHVS
Drain of high-side switches and power supply voltage
9
GND
Ground of high-side switches
10
IH2
Digital input of high-side switch 2
11
ST2
Status of high-side switch 2; open Drain output
12
SH2
Source of high-side switch 2
13
IL2
Analog input of low-side switch 2
14
SL2
Source of low-side switch 2
15
NC
Not connected
16
DL2
Drain of low-side switch 2
Heat-Slug 3
17
DHVS
Drain of high-side switches and power supply voltage
Heat-Slug 2
18
DL1
Drain of low-side switch 1
Heat-Slug 1
Pins written in bold type need power wiring.
Data Sheet
3
2003-03-11
BTS 7810 K
1.5
Functional Block Diagram
DHVS
6
8, 17
ST1
ST2
IH1
IH2
11
5
10
Diagnosis
Biasing and Protection
Driver
IN OUT
0 0 L L
0 1 L H
1 0 H L
1 1 H H
RO1
RO2
12
16
SH2
DL2
9
GND
7
18
SH1
DL1
3
IL1
13
IL2
2
SL1
14
SL2
Figure 2
Block Diagram
Data Sheet
4
2003-03-11
BTS 7810 K
1.6
Circuit Description
Input Circuit
The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with
hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into
the necessary form for driving the power output stages. The inputs are protected by ESD
clamp-diodes.
The inputs IL1 and IL2 are connected to the gates of the standard N-channel vertical
power-MOS-FETs.
Output Stages
The output stages consist of a low RDS ON Power-MOS H-bridge. In H-bridge
configuration, the D-MOS body diodes can be used for freewheeling when commutating
inductive loads. If the high-side switches are used as single switches, positive and
negative voltage spikes which occur when driving inductive loads are limited by
integrated power clamp diodes.
Short Circuit Protection
The outputs are protected against
– output short circuit to ground
– overload (load short circuit).
An internal OP-amp controls the Drain-Source-voltage by comparing the DS-voltagedrop with an internal reference voltage. Above this trippoint the OP-Amp reduces the
output current depending on the junction temperature and the drop voltage.
In the case of overloaded high-side switches the status output is set to low.
Overtemperature Protection
The high-side switches incorporate an overtemperature protection circuit with hysteresis
which switches off the output transistors and sets the status output to low.
Undervoltage-Lockout (UVLO)
When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis.
The high-side output transistors are switched off if the supply voltage VS drops below the
switch off value VUVOFF.
Open Load Detection
Open load is detected by voltage measurement in off state. If the output voltage exceeds
a specified level the error flag is set with a delay.
Data Sheet
5
2003-03-11
BTS 7810 K
Status Flag
The two status flag outputs are an open drain output with Zener-diode which require a
pull-up resistor, c.f. the application circuit on page 15. ST1 and ST2 provide separate
diagnosis for each high-side switch. Various errors as listed in the table “Diagnosis” are
detected by switching the open drain output ST1/2 to low. Forward current in the
integrated body diode of the highside switch may cause undefined voltage levels at the
corresponding status output. The open load detection can be used to detect a short to
Vs as long as both lowside switches are off and ROL is disconnected from 5V by
BCR192W.
2
Truthtable and Diagnosis (valid only for the High-Side-Switches)
Flag
IH1
IH2
SH1
Inputs
SH2
ST1 ST2 Remarks
Outputs
0
0
1
1
0
1
0
1
L
L
H
H
L
H
L
H
1
1
1
1
1
1
1
1
stand-by mode
switch2 active
switch1 active
both switches
active
0
1
X
X
X
X
0
1
Z
H
X
X
X
X
Z
H
0
1
1
1
1
1
0
1
detected
Overtemperature high-side switch1 0
1
X
X
L
L
X
X
1
0
1
1
detected
Overtemperature high-side switch2 X
X
0
1
X
X
L
L
1
1
1
0
detected
Overtemperature both high-side
switches
0
X
1
0
1
X
L
L
L
L
L
L
1
1
0
1
0
1
detected
detected
Undervoltage
X
X
L
L
1
1
not detected
Normal operation;
identical with functional truth table
Open load at high-side switch 1
Open load at high-side switch 2
detected
Note: * multiple simultaneous errors are not shown in this table
Inputs:
Outputs:
Status:
0 = Logic LOW
Z = Output in tristate condition
1 = No error
1 = Logic HIGH
L = Output in sink condition
0 = Error
X = don’t care
H = Output in source condition
X = Voltage level undefined
Data Sheet
6
2003-03-11
BTS 7810 K
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
– 40 °C < Tj < 150 °C
Parameter
Symbol
Limit Values
min.
Unit Remarks
max.
High-Side-Switches (Pins DHVS, IH1,2 and SH1,2)
Supply voltage
Supply voltage for full short
circuit protection
HS-drain current
HS-input current
HS-input voltage
VS
VS(SCP)
– 0.3
IS
IIH
VIH
42
V
–
28
V
–
– 10
*
A
TC = 125°C; DC
–5
5
mA
Pin IH1 and IH2
– 10
16
V
Pin IH1 and IH2
– 0.3
5.4
V
–
–5
5
mA
Pin ST1 or ST2
Note: * internally limited
Status Output ST (Pins ST1 and ST2)
Status pull up voltage
Status Output current
VST
IST
Low-Side-Switches (Pins DL1,2, IL1,2 and SL1,2)
Drain- source break down
voltage
VDSL
55
–
V
VIL = 0 V; ID ≤ 1 mA
LS-drain current
IDL
IDL
–20
20
A
–
25
A
–
100
A
TC = 125°C; DC
tp < 100 ms; ν < 0.1
tp < 1 ms; ν < 0.1
VIL
– 20
20
V
Pin IL1 and IL2
Tj
Tstg
– 40
150
°C
–
– 55
150
°C
–
LS-drain current
TC = 85°C
LS-input voltage
Temperatures
Junction temperature
Storage temperature
Data Sheet
7
2003-03-11
BTS 7810 K
3.1
Absolute Maximum Ratings (cont’d)
– 40 °C < Tj < 150 °C
Parameter
Symbol
Limit Values
min.
Unit Remarks
max.
Thermal Resistances (one HS-LS-Path active)
LS-junction case
HS-junction case
Junction ambient
Rthja = Tj(HS)/(P(HS)+P(LS))
RthjC L
RthjC H
Rthja
–
0.6
K/W
–
0.75
K/W
–
35
K/W device soldered to
reference PCB with
6 cm2 cooling area
ESD Protection (Human Body Model acc. MIL STD 883D, method 3015.7 and EOS/
ESD assn. standard S5.1 - 1993)
Input LS-Switch
Input HS-Switch
Status HS-Switch
Output LS and HS-Switch
VESD
VESD
VESD
VESD
0.5
kV
1
kV
2
kV
4
kV
all other pins connected
to Ground
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
3.2
Operating Range
– 40 °C < Tj < 150 °C
Parameter
Symbol
Limit Values
min.
Unit
Remarks
max.
Supply voltage
VS
VUVOFF 42
V
After VS rising
above VUVON
Input voltages HS
VIH
VIL
IST
TjHS
– 0.3
15
V
–
– 0.3
20
V
–
0
2
mA
–
– 40
150
°C
–
Input voltages LS
Status output current
Junction temperature
Note: In the operating range the functions given in the circuit description are fulfilled.
Data Sheet
8
2003-03-11
BTS 7810 K
3.3
Electrical Characteristics
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symb
ol
Limit Values
Unit Test Condition
min.
typ.
max.
–
4
9
µA
IH1 = IH2 = 0 V
Tj = 85 °C
–
–
20
µA
IH1 = IH2 = 0 V
–
2.5
4.5
mA
IH1 or IH2 = 5 V
–
5
9
mA
IH1 and IH2 = 5 V
–
–
7
µA
2.2
10
mA
VIH = VSH = 0 V
Tj = 85 °C
IFH =5 A
Current Consumption HS-switch
Quiescent current
Supply current
IS Q
IS
Leakage current of
highside switch
ISH LK
Leakage current through
logic GND in free
wheeling condition
ILKCL = –
IFH + ISH
Current Consumption LS-switch
Input current
IIL
–
10
100
nA
Leakage current of
lowside switch
IDL LK
–
–
12
µA
VIL = 20 V
VDSL = 0 V
VIL = 0 V
VDSL = 40 V
Tj = 85 °C
Under Voltage Lockout (UVLO) HS-switch
Switch-ON voltage
Switch-OFF voltage
Switch ON/OFF
hysteresis
Data Sheet
VUVON
VUVOFF
VUVHY
–
–
5
V
1.8
–
4.5
V
–
1
–
V
9
VS increasing
VS decreasing
VUVON – VUVOFF
2003-03-11
BTS 7810 K
3.3
Electrical Characteristics (cont’d)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symb
ol
Limit Values
Unit Test Condition
min.
typ.
max.
Inverse diode of highside switch; Forwardvoltage
VFH
–
0.8
1.2
V
IFH = 5 A
Inverse diode of lowside
switch; Forward-voltage
VFL
–
0.8
1.2
V
IFL = 5 A
RDS ON H –
Static drain-source
on-resistance of highside
switch
26
35
mΩ
ISH = 5 A
Tj = 25 °C
RDS ON L –
14
17
mΩ
ISL = 5 A;
VIL = 5 V
Tj = 25 °C
–
100
mΩ
RDS ON H + RDS ON L
ISH = 5 A;
35
48
65
A
30
42
54
A
25
32
42
A
Tj = – 40 °C
Tj = + 25 °C
Tj = + 150 °C
Output stages
Static drain-source
on-resistance of lowside
switch
Static path on-resistance RDS ON
–
Short Circuit of highside switch to GND
Initial peak SC current
Initial peak SC current
Initial peak SC current
Note:
ISCP H
ISCP H
ISCP H
Integrated protection functions are designed to prevent IC destruction under fault conditions.
Protection functions are not designed for continuous or repetitive operation.
Peak SC current is significantly lower at VS > 18V
Short Circuit of highside switch to VS
Output pull-down-resistor RO
Data Sheet
7
14
10
42
kΩ
VDSL = 3 V
2003-03-11
BTS 7810 K
3.3
Electrical Characteristics (cont’d)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symb
ol
Limit Values
Unit Test Condition
min.
typ.
max.
Thermal shutdown
junction temperature
Tj SD
155
180
190
°C
–
Thermal switch-on
junction temperature
Tj SO
150
170
180
°C
–
Temperature hysteresis
∆T
–
10
–
°C
∆T = TjSD – TjSO
IST = 1.6 mA
VST = 5 V
IST = 1.6 mA
Thermal Shutdown
Status Flag Output ST of highside switch
Low output voltage
Leakage current
Zener-limit-voltage
VST L
IST LK
VST Z
td(SToffo+)
–
0.2
0.6
V
–
–
5
µA
–
V
5.4
–
–
20
µs
Status change after
td(SToffo-) –
negative input slope with
open load
–
700
µs
1.6
10
µs
RST = 47 kΩ
14
100
µs
RST = 47 kΩ
Status change after
positive input slope with
open load
Status change after
positive input slope with
overtemperature
td(STofft+) –
Status change after
td(STofft-)
negative input slope with
overtemperature
Note:
–
times are not subject to production test - specified by design
Open load detection in Off condition
Open load detection
voltage
Data Sheet
VOUT(OL) 2
3
11
4
V
2003-03-11
BTS 7810 K
3.3
Electrical Characteristics (cont’d)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symb
ol
Limit Values
min.
typ.
max.
Unit Test Condition
Switching times of highside switch
Turn-ON-time;
to 90% VSH
tON
–
100
220
µs
RLoad = 12 Ω
VS = 12 V
Turn-OFF-time;
to 10% VSH
tOFF
–
120
250
µs
RLoad = 12 Ω
VS = 12 V
–
0.5
1.1
V/µs RLoad = 12 Ω
VS = 12 V
–
0.7
1.3
V/µs RLoad = 12 Ω
VS = 12 V
dV/
dtON
VSH
Slew rate off 70 to 40% -dV/
dtOFF
VSH
Slew rate on 10 to 30%
Note:
switching times are not subject to production test - specified by design
Switching times of low-side switch
Turn-ON delay time;
VIL = 5V; RGate= 16Ω
td_ON_L
–
40
ns
resistive load
ISL = 10 A; VS = 12 V
Switch-ON time;
VIL= 5V; RGate = 16Ω
tON_L
–
170
ns
resistive load
ISL = 10 A; VS = 12 V
Switch-OFF delay time;
VIL= 5V; RGate = 16Ω
td_OFF_L –
100
ns
resistive load
ISL = 10 A; VS = 12 V
Switch-OFF time;
VIL= 5V; RGate = 16Ω
tOFF_L
–
200
ns
resistive load
ISL = 10 A; VS = 12 V
Input to source charge;
–
4.5
6
nC
–
16
24
nC
Input charge total;
QIS
QID
QI
–
55
69
nC
Input plateau voltage;
V(plateau) –
2.6
–
V
ISL = 10 A; VS = 40 V
ISL = 10 A; VS = 40 V
ISL = 10 A; VS = 40 V
VIL = 0 to 10 V
ISL = 10 A; VS = 40 V
Input to drain charge;
Note:
switching times and input charges are not subject to production test - specified by design
Data Sheet
12
2003-03-11
BTS 7810 K
3.3
Electrical Characteristics (cont’d)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symb
ol
Limit Values
min.
typ.
Unit Test Condition
max.
Control Inputs of highside switches IH 1, 2
H-input voltage
L-input voltage
Input voltage hysterese
H-input current
L-input current
Input series resistance
Zener limit voltage
VIH High
VIH Low
VIH HY
IIH High
IIH Low
RI
VIH Z
–
–
2.5
V
–
1
–
–
V
–
–
0.5
–
V
–
5
30
60
µA
5
14
25
µA
VIH = 5 V
VIH = 0.4 V
2.7
4
6
kΩ
–
5.4
–
–
V
IIH = 1.6 mA
VIL th
–
1.9
2.6
V
–
1.7
–
0.8
1.1
–
Tj = – 40 °C
Tj = + 25 °C
Tj = + 150 °C
Control Inputs IL1, 2
Gate-threshold-voltage
IDL = 1 mA
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
VS = 12 V.
Data Sheet
13
2003-03-11
BTS 7810 K
IS
VS
CL
100µF
CS
470nF
IFH1,2
IST LK1
IST1
DHVS
ST1
6
8, 17
VDSH2
VDSH1
-VFH2
-VFH1
IST LK2
IST2
ST2
11
IH1
5
IH2
10
Diagnosis
Biasing and Protection
VST1
VSTL1
VSTZ1
IIH1
VST2
VSTL2
VSTZ2
IIH1
VIH1
VIH2
Gate
Driver
RO1
GND
RO2
Gate
Driver
12
16
SH2
ISH2
DL2
IDL2
IDL LK 2
VUVON
SH1
ISH1
VUVOFF
DL1
IDL1
6
IGND
7
ILKCL
18
IDL LK 1
VIL1
IIL1
IL1
3
IIL2
IL2
13
VIL th 1
VIL2
VIL th 2
2
14
VDSL1
VDSL2
SL1
SL2
-VFL1
-VFL2
ISCP L 1
ISCP L 2
ISL1
ISL2
Figure 3
Test Circuit
HS-Source-Current
Named during Short
Circuit
Named during LeakageCond.
ISH1,2
ISCP H
IDL LK
Data Sheet
14
2003-03-11
BTS 7810 K
Watchdog
Reset
Q
RQ
100 kΩ
RQ
100 kΩ
Ω
WD R
CQ
22µF
VCC
TLE
4278G
I
D
CS
10µF
D01
Z39
CD
47nF
DHVS
ST1
RS
VS=12V
6
BCR192W
8, 17
10 kΩ
Ω
to µC
ST2 11
RS
Diagnosis
Biasing and Protection
10 kΩ
Ω
Can be replaced
by diode when
Short to Vs
detection is not
needed
ROL
560Ohm
IH1
5
IH2
10
optional for
open load
in off
Gate
Driver
RO1
GND
Gate
Driver
RO2
12
SH2
DL2
16
9
µP
7
18
IL1
3
IL2
13
GND
2
14
SL1
SL2
SH1
M
DL1
Figure 4
Application Circuit
Data Sheet
15
2003-03-11
BTS 7810 K
4
Package Outlines
P-TO263-15-1
(Plastic Transistor Single
21.6 ±0.2
8.3 X2, 1)
4.4
5.56 ±0.15
1.27 ±0.1
1±0.2 8.18 ±0.15
B
0.1
1±0.3
2.4
1)
4.7 ±0.5
7.65
14 x 1.4
0.05
2.7 ±0.3
A
9.25 ±0.2
(15)
4.8 X1, 1)
0...0.15
0.5 ±0.1
0.8 ±0.1
0.25
1)
M
8˚ MAX.
A B
0.1 B
Typical
Metal surface min. X1 = 3.57, X2 = 7.03, Y = 6.9
All metal surfaces tin plated, except area of cut.
Footprint
21.6
8.4
4
16
9.5
0.8
0.4
1
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
16
Dimensions in mm
2003-03-11
BTS 7810 K
Edition 2003-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 München, Germany
© Infineon Technologies AG 3/13/03.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet
17
2003-03-11