CM6523 / CM6523B USB Audio Sound Chip f DESCRIPTION FEATURES CM6523 / CM6523B are a USB 2.0 audio chip builds USB 2.0 full-speed compliant in 8051 for flexible applications. With internal USB Audio Class 1.0 compliant 2-channel ADC and DAC, S/PDIF in/out interface USB Human Interface Device (HID) Class 1.1 and USB 2.0 High speed switch makes it suits for compliant different kinds of Docking applications, such as Build in USB 2.0 High speed switch iDevice docking, Android Phone or Tablet/Slate 2 channel DAC for audio output interface docking device and Netbook/Notebook docking. 2 channel ADC for audio input interface CM6523 / CM6523B is compatible with USB audio Build in 96K/88.2K/48K/44.1KHz and 16/24bit Class 1.0, thus it can plug & play without additional S/PDIF transmitter software installation on the major operation systems. The internal DAC/ADC and S/PDIF out Build in Equalizer on both playback and recording paths interface support 96K/88.2K/48K/44.1KHz Build in AGC on recording path sampling rate and 16/24bit resolution. Support Digital Microphone interface CM6523 / CM6523B integrates the Equalizer on Support control, interrupt, bulk, and isochronous data transfers both playback and recording paths. With I2S in/out interface, it can connect external DAC to get Support Synchronous and Asynchronous audio data synchronization higher audio quality or external DSP to process the audio data Embedded 1T 8051 BLOCK DIAGRAM Master I2C control interface for external audio SPDIF In Mux 2 Channel I2S In USB Interface AGC ADC Mux Microphone In Control Bus SRAM Line In ROM MCU Crystal DAC Speaker/ Heaphone 2 Channel I2S Out SPDIF Out EEPROM GPIO x 32 Uart, SPI, I2C www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 1 CM6523 / CM6523B USB Audio Sound Chip Release Note Revision Date Description 0.9 2011/11/10 First release of preliminary technical information 0.91 2011/1/12 Modify some pin description 0.92 2012/02/10 -Modify GPIO default status 0.93 2012/04/03 -modify PDSW as DO pin -add information in chapter 6, 7 0.94 2012/04/20 -modify some wordings 0.95 2012/05/17 -add more audio quality test into audio performance chapter 0.96 2012/06/13 -modify power pin description 0.97 2012/06/21 -modify GPIO pin number, subtract 1 0.98 2012/06/29 -modify package part number to CM6523 1.00 2012/10/19 -Formal Release 1.01 2013/01/25 -Remove S/PDIF 32K sample rate support 1.02 2013/03/01 -Add CM6523B support. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 2 CM6523 / CM6523B USB Audio Sound Chip TABLE OF CONTENTS Release Note ............................................................................................................................................ 2 1 Description and Overview ............................................................................................................... 5 2 Features ............................................................................................................................................ 5 3 Applications ..................................................................................................................................... 7 4 Block Diagram ................................................................................................................................. 8 5 Pin Assignment ................................................................................................................................ 9 5.1 Pin-Out Diagram ................................................................................................................. 9 5.2 Pin Description...................................................................................................................11 6 USB Audio Topology ..................................................................................................................... 15 6.1 Headset Topology.............................................................................................................. 15 6.2 Speaker Topology.............................................................................................................. 16 6.3 Docking Topology............................................................................................................. 18 6.4 Microphone (Stereo) Topology ......................................................................................... 19 7 Function Description ...................................................................................................................... 20 7.1 Playback Equalizer ............................................................................................................ 20 7.1.1 5-band Equalizer ........................................................................................................... 20 7.1.2 4 preset EQ mode .......................................................................................................... 23 7.2 Recording Equalizer .......................................................................................................... 24 7.3 Recording AGC ................................................................................................................. 24 7.4 USB 2.0 switch ................................................................................................................. 26 7.5 HID Function .................................................................................................................... 26 7.5.1 HID interrupt in ...................................................................................................... 27 7.5.2 HID Set_Output_report .......................................................................................... 28 7.6 Vendor Command Definition ............................................................................................ 29 7.6.1 Vender Command Read ......................................................................................... 29 7.6.2 Vender Command Write ........................................................................................ 30 7.7 I2S Control description ..................................................................................................... 30 7.7.1 I2S Format description ........................................................................................... 30 7.7.2 I2S MCLK/BCLK/LRCK Ratio and Format for CM6523 / CM6523B ................ 32 7.8 SPDIF Control Description ............................................................................................... 34 7.8.1 SPDIF Frame Description ...................................................................................... 34 7.8.2 SPDIF Out Channel Status ..................................................................................... 36 7.8.3 SPDIF In Channel Status ....................................................................................... 36 7.9 Digital Mic ........................................................................................................................ 37 7.10 I2C Interface ..................................................................................................................... 38 www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 3 CM6523 / CM6523B USB Audio Sound Chip 8 9 7.10.1 I2C Master Mode ................................................................................................... 38 7.10.2 I2C-Master Read with clk_sync mode ................................................................... 38 7.10.3 I2C Slave Mode ..................................................................................................... 39 7.11 SPI Interface ...................................................................................................................... 39 7.11.1 SPI Master Mode ................................................................................................... 39 7.11.2 SPI transfer length 2B/3B ...................................................................................... 40 7.11.3 SPI latch data at high/low clock state .................................................................... 41 7.11.4 SPI Slave Mode ...................................................................................................... 45 Electrical Characteristics................................................................................................................ 47 8.1 Absolute Maximum Ratings ............................................................................................. 47 8.2 Recommended Operation Conditions ............................................................................... 47 8.3 Power Consumption .......................................................................................................... 47 8.4 DC Characteristics ............................................................................................................ 47 8.5 Audio Performance ........................................................................................................... 49 8.5.1 DAC Audio Quality ............................................................................................... 49 8.5.2 ADC Audio Quality ............................................................................................... 50 8.5.3 A-A path Audio Quality......................................................................................... 51 Package Dimension ........................................................................................................................ 53 www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 4 CM6523 / CM6523B USB Audio Sound Chip 1 Description and Overview CM6523 / CM6523B is a USB 2.0 audio chip builds in 8051 for flexible applications. With internal 2-channel ADC and DAC, S/PDIF in/out interface and USB 2.0 High speed switch makes it suits for different kinds of Docking applications, such as iDevice docking, Android Phone or Tablet/Slate docking device and Netbook/Notebook docking. CM6523 / CM6523B is compatible with USB audio Class 1.0, thus it can plug & play without additional software installation on the major operation systems. The internal DAC/ADC and S/PDIF out interface support 96K/88.2K/48K/44.1KHz sampling rate and 16/24bit resolution. CM6523 / CM6523B integrates the Equalizer on both playback and recording paths. With I2S in/out interface, it can connect external DAC to get higher audio quality or external DSP to process the audio data. 2 Features USB Compliance USB Spec. Rev.2.0 full-speed mode compatible 3 USB upstream ports for connecting to PC and IPOD at the same time Latest USB Audio Device Class Definition Release 1.0 compatible USB Human Interface Device (HID) Class Definition Release 1.1 compliant Supports USB suspend/resume/reset functions Supports control, interrupt, bulk, and isochronous data transfers Audio Engine Playback Streams: Default Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/88.2K/96K Supported Bit Length: 16/24 bit DMA supports 2-channel data to DAC/I2S output DMA supports S/PDIF output Capture Streams: Default Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/88.2K/96K Supported Bit Length: 16/24 bit DMA supports 2-channel data from ADC/I2S input DMA supports S/PDIF input Digital mixing/routing engine to mix input streams to output streams Audio I/O 2 pairs I2S or Left-Justified serial audio output interface 2 pairs I2S or Left-Justified serial audio input interface www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 5 CM6523 / CM6523B USB Audio Sound Chip 2 channel Mic in 2 channel digital Mic in 2 channel line in 2 channel line out Built-in 96K/88.2K/48K/44.1KHz and 16/24-bit S/PDIF receiver Built-in 96K/88.2K/48K/44.1KHz and 16/24-bit S/PDIF transmitter Integrated 8051 Micro-processor Embedded 8051 micro-processor to handle the comment/protocol transactions Connects to an external EEPROM memory for firmware codes HID interrupts can be implemented via firmware codes Provides maximum HW configuration flexibility with firmware code upgrade VID/PID/Product String can be customized via firmware code programming Control Interface Master I2C control interface for external audio devices or EEPROM access Master SPI control interface for external audio devices or EEPROM access Max. 32 GPIO pins can be configured via firmware programming GPIOs are configured as HID key and LED indicators and IR receiver General HW pin for USB Audio Class 1.0 application mode configuration including Speaker/Headset/Docking/Mic HW pin for A-A path enable/disable HW pin for Self-power or Bus-power mode selection HW EQ for both playback and record path HW pin for EQ enable/disable selection HW pin for PID selection Only single 12MHz crystal input is required (embedded PLL function) Single 5V power supply (embedded 5V to 1.8V regulator for digital core, 5V to 3.3V regulator for digital IO, 5V to 3.5V regulator for analog codec) 3.3V digital I/O pads with 5V tolerance Industrial standard LQFP-128 package (14x14 mm) Optional Value-added Software Features: www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 6 CM6523 / CM6523B USB Audio Sound Chip 3 Applications iDevice Docking Android Docking Notebook/Netbook Docking Audio Box USB DAC www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 7 CM6523 / CM6523B USB Audio Sound Chip 4 Block Diagram SPDIF In 2 Channel I2S In USB Interface ux M Microphone In AGC ADC ux M Control Bus SRAM Line In ROM MCU Crystal DAC Speaker/ Heaphone 2 Channel I2S Out SPDIF Out EEPROM GPIO x 32 Uart, SPI, I2C CM6523 / CM6523B Functional Block Diagram www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 8 CM6523 / CM6523B USB Audio Sound Chip Pin Assignment 5.1 NC NC NC 65 NC 73 66 NC 74 67 NC 75 NC RSTB 76 NC USB_DP_IPOD 77 68 USB_DM_IPOD 78 NC USB_DP_PC 79 69 USB_DM_PC 80 70 NC 81 NC NC 82 NC NC 83 71 AGND 84 72 XACREFR XLNIL XACREFL XLNIR 89 85 XMICBIAS2 90 86 XMICBIAS1 91 XMICR XVAG 92 XMICL XVBG_EXT 93 87 AGND 94 88 AGND 95 Pin-Out Diagram 96 5 NC 97 64 DGND NC 98 63 DV50 NC 99 62 XV33 NC 100 61 XV18 XV35_ADC 101 60 NC XVOLADJ 102 59 NC AGND 103 58 NC XLNOUTL 104 57 NC XLOCOM 105 56 NC XV35_DRIVER 106 55 NC AGND 107 54 VCC3IO XLNOUTR 108 53 USB_DM XV35_DAC 109 52 USB_DP AV50 110 51 GND18IO DAC_MCLK 111 50 SEL_1 DAC_BCLK 112 DAC_DOUT 113 DAC_LRCK 114 DAC_DIN 115 GPIO_23 116 GPIO_22 117 MODE_0 118 MODE_1 119 GND3IO CM6523 LQFP 128 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GPIO_3 VCC3IO GPIO_2 GPIO_1 I2C_SCLK I2C_SDAT GPIO_0 GPIO_31 GPIO_30 GPIO_28 GPIO_28 GPIO_27 GPIO_26 RESETN GPIO_25 GPIO_4 33 17 128 GPIO_5 GPIO_24 VCC3IO 16 34 GND3IO 127 15 GPIO_19 GPIO_8 EQ_EN 35 14 126 13 GPIO_18 GPIO_9 GPIO_6 36 A-A MIX_EN 125 12 SPDIF_O GPIO_10 11 37 GPIO_7 124 ADC_MCLK GPIO_17 GPIO_11 10 38 ADC_BCLK 123 9 GPIO_16 GPIO_12 ADC_DIN 39 8 122 ADC_LRCK PDSW GPIO_20 7 40 ADC_DOUT 121 6 GPIO_15 GPIO_21 SPDIF_I 41 5 TEST 120 SPI_MOSI GPIO_14 42 4 GPIO_13 43 SPI_MISO VCC18IO 44 3 XTAL_I 45 SPI_SCK XTAL_O 46 2 47 1 GND18IO NC SEL_2 48 SPI_CS0 49 www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 9 CM6523 / CM6523B NC NC NC NC NC 68 67 66 65 NC 73 NC NC 74 69 NC 75 70 RSTB 76 NC USB_DP_IPOD 77 NC USB_DM_IPOD 78 71 USB_DP_PC 79 72 NC NC 82 USB_DM_PC NC 83 80 AGND 84 81 XACREFR XLNIL 89 XACREFL XLNIR 90 85 XMICBIAS2 91 86 XMICBIAS1 92 XMICR XVAG 93 XMICL XVBG_EXT 94 87 AGND 95 88 AGND 96 USB Audio Sound Chip NC 97 64 DGND NC 98 63 DV50 NC 99 62 XV33 NC 100 61 XV18 XV35_ADC 101 60 NC XVOLADJ 102 59 NC AGND 103 58 NC XLNOUTL 104 57 NC XLOCOM 105 56 NC XV35_DRIVER 106 55 NC AGND 107 54 VCC3IO XLNOUTR 108 53 USB_DM XV35_DAC 109 52 USB_DP AV50 110 51 GND18IO DAC_MCLK 111 50 SEL_1 DAC_BCLK 112 DAC_DOUT 113 DAC_LRCK 114 DAC_DIN 115 GPIO_23 116 GPIO_22 117 MODE_0 118 MODE_1 119 GND3IO CM6523B LQFP 128 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GPIO_3 VCC3IO GPIO_2 GPIO_1 I2C_SCLK I2C_SDAT GPIO_0 GPIO_31 GPIO_30 GPIO_28 GPIO_28 GPIO_27 GPIO_26 RESETN GPIO_25 GPIO_4 33 17 128 GPIO_5 GPIO_24 VCC3IO 16 34 GND3IO 127 15 GPIO_19 GPIO_8 EQ_EN 35 14 126 13 GPIO_18 GPIO_9 GPIO_6 36 A-A MIX_EN 125 12 SPDIF_O GPIO_10 11 37 GPIO_7 124 ADC_MCLK GPIO_17 GPIO_11 10 38 ADC_BCLK 123 9 GPIO_16 GPIO_12 ADC_DIN 39 8 122 ADC_LRCK PDSW GPIO_20 7 40 ADC_DOUT 121 6 GPIO_15 GPIO_21 SPDIF_I 41 5 TEST 120 SPI_MOSI GPIO_14 42 4 GPIO_13 43 SPI_MISO VCC18IO 44 3 XTAL_I 45 SPI_SCK XTAL_O 46 2 47 1 GND18IO NC SEL_2 48 SPI_CS0 49 www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 10 CM6523 / CM6523B USB Audio Sound Chip 5.2 Pin # Pin Description Symbol I/O Description Clock 47 XTAL_O AO 12MHz crystal oscillator output 46 XTAL_I AI 12MHz crystal oscillator input USB2.0 BUS Interface 53 USB_DM AIO USB 2.0 data negative (USB D- signal) 52 USB_DP AIO USB 2.0 data positive (USB D+ signal) 78 USB_DM_IPOD AIO USB 2.0 data negative (USB D- signal) 77 USB_DP_IPOD AIO USB 2.0 data positive (USB D+ signal) 80 USB_DM_PC AIO USB 2.0 data negative (USB D- signal) 79 USB_DP_PC AIO USB 2.0 data positive (USB D+ signal) Power/Ground 63 DV50 PWR 45 VCC18IO AO 1.8V power for digital I/O 54 VCC3IO PWR 3.3V power for digital I/O 62 XV33 AO 48 GND18IO GND Digital Ground 128 VCC3IO PWR 3.3V power for digital I/O 20 VCC3IO PWR 3.3V power for digital I/O 51 GND18 GND Digital Ground 61 XV18 AO 120 GND3IO GND Digital Ground 16 GND3IO GND Digital Ground 64 DGND GND Digital Ground 110 AV50 PWR 5V analog power for 5/3.5 regulator 84 AGND GND Analog Ground 109 XV35_DAC AO Regulator 3.5V output, drive capacity 100mA for analog and amplifier 101 XV35_ADC AO 3.5V power for ADC and Voltage and Current Reference 95 AGND GND Analog Ground 96 AGND GND Analog Ground 103 AGND GND Analog Ground 106 XV35_DRIVER AO 107 AGND GND www.cmedia.com.tw Copyright © C-Media Electronics Inc. 5V digital power for 5/3.3 regulator Regulator 3.3V output, drive capacity 150mA for USB and digital I/O Regulator 1.8V output, drive capacity 100mA for digital core 3.5V power for Driver Analog Ground Rev. 1.02 ︱ Page 11 CM6523 / CM6523B USB Audio Sound Chip Audio Interface 85 XACREFL AO common reference voltage for input signal 86 XACREFR AO common reference voltage for input signal 87 XMICL AI Mic in left channel 88 XMICR AI Mic in right channel 89 XLINL AI Line in left channel 90 XLINR AI Line in right channel 91 XMICBIAS2 AO Microphone bias 92 XMICBIAS1 AO Microphone bias 93 XVAG AO Voltage reference cap filter 94 XVBG_EXT AI External bandgap reference voltage input(level:1.24V) 102 XVOLADJ AI Analog control voltage input for playback volume control 104 XLNOUTL AO Line out left channel 105 XLOCOM AO Line out common reference for cap-less connection 108 XLNOUTR AO Line out right channel 2-channel I2S DAC Interface 111 DAC_MCLK DO I2S master clock 112 DAC_BCLK DIO I2S bit clock 113 DAC_DOUT DO I2S serial data output for channel 0, 1 114 DAC_LRCK DIO I2S left/right clock 115 DAC_DIN DI Programmable 3.3V output buffer Programmable 3.3V bidirectional buffer, pull-down Programmable 3.3V output buffer Programmable 3.3V bidirectional buffer, pull-down Input from DSP to DAC for Playback 2-channel I2S ADC interface 7 ADC_ DOUT DO Output from ADC to DSP for data processing 8 ADC_ LRCK DIO 9 ADC_ DIN DI 10 ADC_ BCLK DIO 11 ADC_ MCLK DO I2S left/right clock Programmable 3.3V bidirectional buffer, pull-down I2S serial data input for channel 0, 1 Programmable 3.3V input buffer, Schmitt trigger, pull-down I2S bit clock Programmable 3.3V bidirectional buffer, pull-down I2S master clock Programmable 3.3V output buffer S/PDIF I/O 6 SPDIF_I DI 37 SPDIF_O DO S/PDIF receiver Programmable 3.3V output buffer S/PDIF transmitter Programmable 3.3V output buffer GPIO www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 12 CM6523 / CM6523B USB Audio Sound Chip 25 GPIO_0 DIO 22 GPIO_1 DIO 21 GPIO_2 DIO 19 GPIO_3 DIO 18 GPIO_4 DIO 17 GPIO_5 DIO 13 GPIO_6 DIO 12 GPIO_7 DIO 127 GPIO_8 DIO 126 GPIO_9 DIO 125 GPIO_10 DIO 124 GPIO_11 DIO 123 GPIO_12 DIO 44 GPIO_13 DIO 43 GPIO_14 DIO 41 GPIO_15 DIO 39 GPIO_16 DIO 38 GPIO_17 DIO 36 GPIO_18 DIO 35 GPIO_19 DIO 122 GPIO_20 DIO 121 GPIO_21 DIO 117 GPIO_22 DIO 116 GPIO_23 DIO 34 GPIO_24 DIO 33 GPIO_25 DIO 31 GPIO_26 DIO 30 GPIO_27 DIO 29 GPIO_28 DIO www.cmedia.com.tw Copyright © C-Media Electronics Inc. General purpose input/output (default Volume Up). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default Volume Down). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default Play Mute). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default Rec Mute). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default LED Live, 2K Hz). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default LED Play Mute). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default LED Rec Mute, 1K Hz). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default EQ Mode Select0). Programmable 3.3V/5V tolerance GPIO[8:7]=0,0: Normal bidirectional buffer, pull-down GPIO[8:7]=1,0: Communication General purpose input/output (default GPIO[8:7]=0,1: Gaming EQ Mode Selet1). GPIO[8:7]=1,1: Movie Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default Rec Clip Indicator). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default Wave Volume Up). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default Wave Volume Down). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default Play/Pause). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default Stop). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default Next). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default Previous). Programmable 3.3V/5V tolerance bidirectional buffer, pull-up General purpose input/output (default MCU_RXD). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default MCU_TRX). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output (default IR Module). Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down Rev. 1.02 ︱ Page 13 CM6523 / CM6523B USB Audio Sound Chip 28 GPIO_29 DIO 27 GPIO_30 DIO 26 GPIO_31 DIO General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down General purpose input/output Programmable 3.3V/5V tolerance bidirectional buffer, pull-down 2-Wire Master Serial Bus (I2C) 24 I2C_SDAT DIO 23 I2C_SCLK DIO 2-wire master serial data Programmable 3.3V/5V tolerant bidirectional buffer, pull-down 2-wire master serial clock Programmable 3.3V/5V tolerant bidirectional buffer, pull-down 4-Wire SPI Serial Bus 2 SPI_CS0 DO Chip Select 3 SPI_SCK DO Serial Clock 4 SPI_MISO DO Serial Data Out 5 SPI_MOSI DI Serial Data In Miscellaneous Power on reset 76 RSTB 32 RESETN 40 PDSW DO Power Down Switch Normal: 0 Suspend: 1 42 TEST DI For test 14 A-A MIX_EN DI 0: A-A path disable 1: A-A path enable 15 EQ_EN DI 0: Disable EQ/ 1: Enable EQ 49 SEL2 DI HW Select for different PID 50 SEL1 DI HW Select for different PID 118 MODE_0 DI 119 MODE_1 DI MODE_1= MODE_1= MODE_1= MODE_1= www.cmedia.com.tw Copyright © C-Media Electronics Inc. Reset pin 0, 0, 1, 1, MODE_0= MODE_0= MODE_0= MODE_0= 0 1 0 1 for for for for Headset Microphone Speaker Docking Rev. 1.02 ︱ Page 14 CM6523 / CM6523B USB Audio Sound Chip 6 USB Audio Topology CM6523 / CM6523B supports 4 types of topology by default. They are Headset, Docking, Speaker, Mic. Different topology can be selected by pin Mode_0 and Mode_1. The combinations are as below. MODE_1= 0, MODE_0= 0 for Headset MODE_1= 0, MODE_0= 1 for Microphone MODE_1= 1, MODE_0= 0 for Speaker MODE_1= 1, MODE_0= 1 for Docking 6.1 Headset Topology 0x05 FEA 0x09 MIXER 0x01 IT USB STREAM 0x03 OT SPEAKER 0x07 FEA 0x08 SEL 0x06 FEA 0x02 IT MIC USB STREAM Device Descriptor Offset 0 1 2 4 5 6 7 8 10 12 14 15 16 17 0x04 OT Field bLength bDescriptorType bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor idProduct bcdDevice iManufacturer iProduct iSerialNumber bNumConfigurations www.cmedia.com.tw Copyright © C-Media Electronics Inc. Size 1 1 2 1 1 1 1 2 2 2 1 1 1 1 Value (Hex) 12 01 0110 00 00 00 10 0D8C 0178~017F 0000 01 02 00 01 Description Descriptor length Device Descriptor USB 1.1 compliant Device class specified by interface Device subclass specified by interface Device protocol specified by interface Endpoint zero packet size Vendor ID Product ID Device release number Index of string descriptor describing manufacturer Index of string descriptor describing product Index of string descriptor describing serial number Number of configuration Rev. 1.02 ︱ Page 15 CM6523 / CM6523B USB Audio Sound Chip Configuration Descriptor Offset 0 1 2 Field bLength bDescriptorType wTotalLength Size 1 1 2 4 bNumInterfaces 1 5 6 7 8 bConfigurationValue iConfiguration bmAttributes bMaxPower 1 1 1 1 Value (Hex) Description 09 Descriptor length 02 Configuration Descriptor 011D Total length of data returned for this configuration: 285 Bytes 04 Number of interfaces supported by this Configuration: 00: Control 01: ISO-Out 02: ISO-In 03: INT-In (HID) 01 Configuration value 00 Index of string descriptor describing this configuration 80 Attributes(Bus Powered) 32 Maximum power consumption from bus = 100mA: 8’h32 (50x2 mA) (PWRSEL_2 = 1) Audio Control Interface 0 Descriptor 0 Offset 0 1 2 3 4 5 6 7 8 6.2 Field bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Size 1 1 1 1 1 1 1 1 1 Value (Hex) 09 04 00 00 00 01 01 00 00 Description Descriptor length Interface Descriptor Interface number Alternate interface Number of endpoint used by this interface Audio Interface Class Subclass code: AUDIO_CONTROL Protocol code Index of string descriptor describing this interface Speaker Topology 0x03 FEA 0x01 IT 0x02 OT USB STREAM SPEAKER Device Descriptor Offset 0 1 2 4 5 6 7 8 Field bLength bDescriptorType bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor www.cmedia.com.tw Copyright © C-Media Electronics Inc. Size 1 1 2 1 1 1 1 2 Value (Hex) 12 01 0110 00 00 00 10 0D8C Description Descriptor length Device Descriptor USB 1.1 compliant Device class specified by interface Device subclass specified by interface Device protocol specified by interface Endpoint zero packet size Vendor ID Rev. 1.02 ︱ Page 16 CM6523 / CM6523B USB Audio Sound Chip 10 12 14 15 16 17 idProduct bcdDevice iManufacturer iProduct iSerialNumber bNumConfigurations Configuration Descriptor 2 2 1 1 1 1 Offset 0 1 2 Field bLength bDescriptorType wTotalLength Size 1 1 2 4 bNumInterfaces 1 5 6 7 8 bConfigurationValue iConfiguration bmAttributes bMaxPower 1 1 1 1 0180~018F 0000 01 02 00 01 Value (Hex) Description 09 Descriptor length 02 Configuration Descriptor 0099 Total length of data returned for this configuration: 153 Bytes 03 Number of interfaces supported by this Configuration: 00: Control 01: ISO-Out 02: INT-In (HID) 01 Configuration value 00 Index of string descriptor describing this configuration 80 Attributes(Bus Powered) 32 Maximum power consumption from bus = 100mA: 8’h32 (50x2 mA) (PWRSEL_2 = 1) Audio Control Interface 0 Descriptor 0 Offset 0 1 2 3 4 5 6 7 8 Field bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface www.cmedia.com.tw Copyright © C-Media Electronics Inc. Size 1 1 1 1 1 1 1 1 1 Product ID Device release number Index of string descriptor describing manufacturer Index of string descriptor describing product Index of string descriptor describing serial number Number of configuration Value (Hex) 09 04 00 00 00 01 01 00 00 Description Descriptor length Interface Descriptor Interface number Alternate interface Number of endpoint used by this interface Audio Interface Class Subclass code: AUDIO_CONTROL Protocol code Index of string descriptor describing this interface Rev. 1.02 ︱ Page 17 CM6523 / CM6523B USB Audio Sound Chip 6.3 Docking Topology 0x08 FEA 0x10 MIX 0x01 IT USB STREAM SPEAKER 0x0D FEA 0x02 IT MIC 0x06 OT 0x09 FEA 0x0E FEA 0x0F SEL 0x03 IT 0x07 OT USB STREAM 0x0A FEA LINE-IN 0x0B FEA 0x04 IT SPDIF IN 0x0C FEA 0x05 IT STEREO MIXER Device Descriptor Offset 0 1 2 4 5 6 7 8 10 12 14 15 16 Field bLength bDescriptorType bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor idProduct bcdDevice iManufacturer iProduct iSerialNumber www.cmedia.com.tw Copyright © C-Media Electronics Inc. Size 1 1 2 1 1 1 1 2 2 2 1 1 1 Value (Hex) 12 01 0110 00 00 00 10 0D8C 01A8~01AF 0000 01 02 00 Description Descriptor length Device Descriptor USB 1.1 compliant Device class specified by interface Device subclass specified by interface Device protocol specified by interface Endpoint zero packet size Vendor ID Product ID Device release number Index of string descriptor describing manufacturer Index of string descriptor describing product Index of string descriptor describing serial number Rev. 1.02 ︱ Page 18 CM6523 / CM6523B USB Audio Sound Chip 17 bNumConfigurations Configuration Descriptor 1 Offset 0 1 2 Field bLength bDescriptorType wTotalLength Size 1 1 2 4 bNumInterfaces 1 5 6 7 8 bConfigurationValue iConfiguration bmAttributes bMaxPower 1 1 1 1 01 Value (Hex) Description 09 Descriptor length 02 Configuration Descriptor 016D Total length of data returned for this configuration: 365 Bytes 04 Number of interfaces supported by this Configuration: 00: Control 01: ISO-Out 02: ISO-In 03: HID 01 Configuration value 00 Index of string descriptor describing this configuration 80 Attributes(Bus Powered) 32 Maximum power consumption from bus = 100mA: 8’h32 (50x2 mA) (PWRSEL_2 = 1) Audio Control Interface 0 Descriptor 0 Offset 0 1 2 3 4 5 6 7 8 6.4 Field bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Size 1 1 1 1 1 1 1 1 1 Number of configuration Value (Hex) 09 04 00 00 00 01 01 00 00 Description Descriptor length Interface Descriptor Interface number Alternate interface Number of endpoint used by this interface Audio Interface Class Subclass code: AUDIO_CONTROL Protocol code Index of string descriptor describing this interface Microphone (Stereo) Topology 0x04 SEL 0x03 FEA 0x01 IT MIC USB STREAM Device Descriptor Offset 0 1 2 4 5 6 7 8 10 0x02 OT Field bLength bDescriptorType bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor idProduct www.cmedia.com.tw Copyright © C-Media Electronics Inc. Size 1 1 2 1 1 1 1 2 2 Value (Hex) 12 01 0110 00 00 00 10 0D8C 0190~019F Description Descriptor length Device Descriptor USB 1.1 compliant Device class specified by interface Device subclass specified by interface Device protocol specified by interface Endpoint zero packet size Vendor ID Product ID Rev. 1.02 ︱ Page 19 CM6523 / CM6523B USB Audio Sound Chip 12 14 15 16 17 bcdDevice iManufacturer iProduct iSerialNumber bNumConfigurations Configuration Descriptor 2 1 1 1 1 Offset 0 1 2 Field bLength bDescriptorType wTotalLength Size 1 1 2 4 bNumInterfaces 1 5 6 7 8 bConfigurationValue iConfiguration bmAttributes bMaxPower 1 1 1 1 0000 01 02 00 01 Value (Hex) Description 09 Descriptor length 02 Configuration Descriptor 00A0 Total length of data returned for this configuration: 160 Bytes 03 Number of interfaces supported by this Configuration: 00: Control 01: ISO-In 03: HID 01 Configuration value 00 Index of string descriptor describing this configuration 80 Attributes(Bus Powered) 32 Maximum power consumption from bus = 100mA: 8’h32 (50x2 mA) (PWRSEL_2 = 1) Audio Control Interface 0 Descriptor 0 Offset 0 1 2 3 4 5 6 7 8 7 Field bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Size 1 1 1 1 1 1 1 1 1 Device release number Index of string descriptor describing manufacturer Index of string descriptor describing product Index of string descriptor describing serial number Number of configuration Value (Hex) 09 04 00 00 00 01 01 00 00 Description Descriptor length Interface Descriptor Interface number Alternate interface Number of endpoint used by this interface Audio Interface Class Subclass code: AUDIO_CONTROL Protocol code Index of string descriptor describing this interface Function Description 7.1 Playback Equalizer 7.1.1 5-band Equalizer CM6523 / CM6523B has integrated 5-band hardware digital equalizer (EQ) engine inside the chips to fulfill various application usages. It provides up-to-4 preset modes on customer’s product design for different user scenarios including default/music, movies, Gaming and communication modes. Customers could also change the gain parameters for each of the preset application EQ mode via EEPROM coding. In addition, the EQ engine could also be utilized for compensating and fine-tuning the headphone driver for Sound Pressure Level (SPL) performance to a specific preference. In this case, customers could fully customize all EQ coefficients (center frequency, gain values, and bandwidth) to one optimized frequency response curve and setting in terms of the headphone driver and housing’s acoustics characteristics, also via EEPROM programming. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 20 CM6523 / CM6523B USB Audio Sound Chip Digital Equalizer Digital PCM Attenuation Digital-Analog (5-Band Fc, Gain, PCM Bandwidth, OPA Gain) PCM -Converter Analo Analog Analo g The EQ engine contains 5 frequency bands (Fc) of digital filters to conduct transfer functions of the frequency response over the audio band. It allows maximum +-12dB digital gain (Gain) for each band with 0.5dB adjustment per step. Each filter will have its bandwidth (BW) factor between 0 and 1.0. Fc: Center Frequency, F1~F5, 20<Fc<20K (Hz) Gain: Digital Frequency Gain, -12dB <= Gain <=+12dB, 0.5dB/step BW: Filter Bandwidth Factor, 0<BW<1 OPA Gain: Analog Gain Compensation setting for each equalizer mode The EQ engine already provides 4 preset modes/settings based on the same preset F1~F5 center frequencies and OPA gain: F1 (Bass)= 100Hz F2 = 350Hz F3 = 1KHz F4 = 3.5KHz F5 (Treble) = 13KHz With the 4 preset EQ modes, customers could use EEPROM parameters to change the gain values for each band of the center frequency and hence customize the 4-preset EQ curves based on the preset center frequencies and bandwidth. Alternatively, customers could also skip the 4 preset modes and create a customized EQ curve by changing the center frequencies, gain values and even the bandwidth factors in EEPROM parameters to make the headphone sound better or meet some frequency requirements. However, in this case, the product will always use one optimized EQ setting and could not allow users to dynamically change among different preset modes. Customer could also consider reporting Treble/Bass feature unit by EEPROM to Windows UAA driver to allow end-users to adjust Bass (F1) and Treble (F5) by themselves. Therefore there are three usage/application scenarios as the summary table below: www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 21 CM6523 / CM6523B USB Audio Sound Chip 3 EQ Usage/Application Scenarios No Scenario Gain Value Center Frequency / Number of User Control Bandwidth Factor Modes Type 1 4 Switchable Presets Configurable Fixed 4 Hardware 2 Full-Customized EQ Configurable Configurable 1 N.A. 3 Treble/Bass Feature Configurable Configurable 1 Software Unit Note: Hardware user control type means end-users could select which EQ mode they’re going to use by a hardware switch/button on the product; Software control means they could control the treble/bass gain values by GUI in Windows OS sound device advanced settings. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 22 CM6523 / CM6523B USB Audio Sound Chip 4 preset EQ mode 7.1.2 As mentioned above, EQ engine already provides 4 preset EQ modes for different user scenarios/applications. End users could use the hardware switch on the product (determined by 2 EQ configuration input pins) to dynamically change to different EQ modes. The following shows the frequency response of each mode. Mode GPIO8 GPIO7 Color Default 0 0 ---------------- Gaming 0 1 ---------------- Communication 1 0 ---------------- Movie 1 1 ---------------- Audio Precision 04/20/11 15:35:35 +1 -0 Gaming Communication -1 -2 Movie -3 d B r -4 Default -5 A -6 -7 -8 -9 -10 20 50 100 200 500 1k 2k Hz Sweep Trace Color Line Style Thick Data Axis Comment 1 2 3 4 1 1 1 1 Red Magenta Cyan Blue Solid Solid Solid Solid 2 2 2 2 Anlr.Ampl Anlr.Ampl Anlr.Ampl Anlr.Ampl Left Left Left Left 00 11 10 DA-EQ-SPDIF_In_DA_Out.at27 www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 23 5k 10k 20k CM6523 / CM6523B USB Audio Sound Chip 7.2 Recording Equalizer CM6523 / CM6523B also provide 5-band Equalizer for the input. It can be used to compensate the frequency response of Microphone unit. Customers could fully customize all EQ coefficients (center frequency, gain values, and bandwidth) through external EEPROM. 7.3 Recording AGC Automatic Gain Control (AGC) is an automatically controlled method to adjust with intensity of signal; AGC is closes the return circuit; that is by the negative response system too. AGC is by way of compressing volume, Will increase Gain first when AGC is started, Set up the upper and lower limits of the signal; compress the dynamic range of sound. Usually use the occasion of AGC, should be recording and producing and speaking sound, or volume is being changed under little environment. If the lasting low voice of volume, AGC will enlarge volume, volume is sustained loudly, AGC will reduce volume. FEATURES Programmable AGC Parameters Selectable Gain from –12 dB to 45 dB in 1-dB Steps Selectable Attack, Release and Hold Times AGC Enable/Disable Function Limiter Enable/Disable Function Pre-Detect Limiter Level Function Two-Channel AGC Independent Under input source types, to set AGC gain max/min limit I2S rec +12~ -16DB 0xf9= 0x1c (max)+fix gain(9db) = 0x25 0cfA= 0x00(min) Digmic +20 ~ -16DB 0xf9= 0x24 (max)+fix gain(9db) =0x2d 0xfA= 0x00(min) Analog mic +30 ~ 0DB 0xf9=0x0F+fix gain(9db) 0xfA=0x2D AGC Variable Description Fixed Gain: The normal gain of the device when the AGC is inactive. Limiter Level: The value that sets the maximum allowed output amplitude. Attack Time: The minimum time between two gain decrements. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 24 inv -> inv -> 0x39(max) 0x12(min) CM6523 / CM6523B USB Audio Sound Chip Release Time: The minimum time between two gain increments. Hold Time: The time it takes for the very first gain increment after the input signal amplitude decreases. Max Threshold Input Signal Max Threshold Output Signal Attack time Decrease Gain www.cmedia.com.tw Copyright © C-Media Electronics Inc. Hold time Release time Hold Gain increase Gain Rev. 1.02 ︱ Page 25 CM6523 / CM6523B USB Audio Sound Chip 7.4 USB 2.0 switch CM6523 / SW_USB<0> SW_USB<1> USB11 USB20 Analog PAD Digital PAD USB11 PHY USB switch interface IPOD USB_DP_IPOD USB_DM_IPOD USB_DP USB_DM Signal NAME BIT NUM I/O SW_USB<1:0> 2 I 7.5 PC Function Control bits for USB switch: USB20 Off, USB11 Off. USB20 Off, USB11 On. USB20 On, USB11 Off. USB20 On, USB11 On. USB_DP_PC USB_DM_PC Control Bits SW_USB<1,0>= (00) SW_USB<1,0>= (01) SW_USB<1,0>= (10) SW_USB<1,0>= (11) HID Function HID is Human Interface Device, it’s a type of computer device to interact with human for the input and output. The most common HID devices are the USB keyboard and Mouse. CM6523 / CM6523B also provide some basic HID buttons, such as Volume up, Volume down, Play back mute, etc. And also through set output report and get input report to communicate with external device. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 26 CM6523 / CM6523B USB Audio Sound Chip 7.5.1 HID interrupt in Input Data Format: byte 0 always 1 for org HID event report ID byte1 for defined HID event, and each event occupies one bit byte2 byte3 start address of returned data (H-start_addr) byte4 start address of returned data (L-start_addr) byte5 bit7 bit6:UART_INT bit5:GPI_INT bit4:SPIS_INT(slavemode int) bit3: SPIM_INT(mastermode int) bit2:I2CS_INT(slavemode int) bit1:I2CM_INT(mastermode int) bit0: IR_INT byte6 read data of [start_addr] byte7 read data of [start_addr+1] byte8 read data of [start_addr+2] byte9 read data of [start_addr+3] byte10 read data of [start_addr+4] byte11 read data of [start_addr+5] byte12 read data of [start_addr+6] byte13 read data of [start_addr+7] byte14 read data of [start_addr+8] byte15 read data of [start_addr+9] HID Get_Input_report Command Format: bmRequestType 8’h A1 bRequest 8’h 01 (Get_Report) wValue 16’h 01 01 (Rpt Type + Rpt ID) wIndex wLength 16’h 00 03 16’h 00 10 (Interface) (16 bytes) Data Report *Note: The Start_Addr value in the input reported is put in the Internal Register Address 0xff. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 27 CM6523 / CM6523B USB Audio Sound Chip Software must set the value of Start_Addr Register to make sure Get Input Report can read the proper data you want. Input Data Format: byte 0 always 1 for org HID event report ID byte1 for defined HID event, and each event occupies one bit byte2 byte3 start address of returned data (H-start_addr) byte4 start address of returned data (L-start_addr) byte5 bit7 bit6:UART_INT bit5:GPI_INT bit4:SPIS_INT(slavemode int) bit3: SPIM_INT(mastermode int) bit2:I2CS_INT(slavemode int) bit1:I2CM_INT(mastermode int) bit0: IR_INT 7.5.2 byte6 read data of [start_addr] byte7 read data of [start_addr+1] byte8 read data of [start_addr+2] byte9 read data of [start_addr+3] byte10 read data of [start_addr+4] byte11 read data of [start_addr+5] byte12 read data of [start_addr+6] byte13 read data of [start_addr+7] byte14 read data of [start_addr+8] byte15 read data of [start_addr+9] HID Set_Output_report Command Format: bmRequestType 8’h 21 www.cmedia.com.tw Copyright © C-Media Electronics Inc. bRequest wValue wIndex wLength 8’h 09 16’h 02 01 16’h 00 03 16’h 00 10 (Set_Report) (Rpt Type + Rpt (Interface) (16 bytes) Rev. 1.02 ︱ Page 28 Data Report CM6523 / CM6523B USB Audio Sound Chip ID) *Note: Byte5 is the beginning address of this write sequence. Output Data Format: 7.6 7.6.1 byte 0 always 1 for org HID event report ID byte1 start address of write reg (H-start_addr) byte2 start address of write reg (L-start_addr) byte3 effective write/read data length (<=12) byte4 write data to [start_addr] byte5 write data to [start_addr+1] byte6 write data to [start_addr+2] byte7 write data to [start_addr+3] byte8 write data to [start_addr+4] byte9 write data to [start_addr+5] byte10 write data to [start_addr+6] byte11 write data to [start_addr+7] byte12 write data to [start_addr+8] byte13 write data to [start_addr+9] byte14 write data to [start_addr+10] byte15 write data to [start_addr+11] Vendor Command Definition Vender Command Read Command Format: bmRequestType 8’h C3 www.cmedia.com.tw bRequest 8’h 02 (Command 2) Copyright © C-Media Electronics Inc. wValue wIndex 16’h -- -(Start Address of input Data) Rev. 1.02 ︱ Page 29 16’h 00 00 wLength 16’h 00 – (<=64 bytes) Data Data CM6523 / CM6523B USB Audio Sound Chip Input Data Format: Byte 0 Data of Reg[wValue] Byte 1 Data of Reg[wValue + 1] Byte 2 Data of Reg[wValue + 2] … … Byte 63 7.6.2 Data of Reg[wValue + 63] Vender Command Write Command Format: bmRequestType 8’h 43 bRequest 8’h 01 (Command 1) wValue wIndex 16’h -- -(Start Address of Output Data) 16’h 00 00 wLength 16’h 00 – (<=64 bytes) Data Data Output Data Format: Byte 0 Data of Reg[wValue] Byte 1 Data of Reg[wValue + 1] Byte 2 Data of Reg[wValue + 2] … Byte 63 7.7 … Data of Reg[wValue + 63] I2S Control description 7.7.1 I2S Format description I2S Interface Setting I2S has three clock signals, MCLK, BCLK and LRCK, and at least one data line depending on the channels supported. One data line contains two channels. Therefore, there have four data lines for a 8-channel I2S DAC controller. The three I2S clock symbols are explained below. MCLK = main clock. BCLK = bit clock. LRCK = left and right clock. Basic of I2S Bus Both master and slave modes of I2S are supported, namely I2S DAC, I2S ADC 1, I2S ADC 2, I2S ADC 3. Master mode means BCLK and LRCK are provided as shown in below left. On the contrary, slave mode means BCLK and www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 30 CM6523 / CM6523B USB Audio Sound Chip LRCK are provided by the I2S codecs as below right. MCLK I2S Interface MCLK BCLK I2S Interface Codec BCLK LRCK Codec LRCK Master mode Slave mode Figure -1 I2S Master/Slave Block Diagram Below figure indicates the basic waveform of I2S. Note that BCLK is generated at the positive edges of MCLK with the ratios 1, 1/2, 1/4, or 1/8, and LRCK is generated at the negative edges of BCLK with the ratios 1/64, 1/128, 1/256. Data lines are transited at the negative edges of BCLK, and are sampled at the positive edges of BCLK by codecs in case of playback or recording. Left Channel Right Channel LRCK BCLK DIN/ DOUT 1 2 3 MSB 4 n-1 n LSB 1 2 3 MSB 4 n-1 n LSB Figure -2 I2S timing diagram For the I2S DAC controller, the audio data is transformed from the parallel format to the serial format before transmitted. Then, the bit data is shifted out one by one with the MSB first via DOUT signal. If the I2S DAC controller is set to 32 bits, at least 32 BCLK clocks must exist in both LRCK left and right channels. In the same manner, the audio data is transformed from the coming serial format to the parallel format for a I2S ADC controller. Left Justified Mode In the left justified mode of the I2S DAC controller, the MSB data bit is clocked out at the negative edge of BCLK which is aligned to the transition of LRCK. In the left justified mode of I2S ADC controllers, the MSB data bit is clocked out by codecs and sampled at the first positive edge of BCLK which follows a LRCK transition. LRCK is high during left channel transmission and low during right channel transmission in the left justified mode. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 31 CM6523 / CM6523B USB Audio Sound Chip Left Channel Right Channel LRCK the MSB is sampled here BCLK where the MSB is clocked out DIN/ DOUT 1 2 3 4 n-1 1 n LSB MSB 2 3 4 n-1 n LSB MSB Figure -3 Left Justified mode timing diagram of I2S I2S Mode In the I2S mode of the I2S DAC controller, the MSB data bit is clocked out by CMI8788 at the first negative edge of BCLK which follows a LRCK transition. In the I2S mode of I2S ADC controllers, the MSB data bit is clocked out by codecs and sampled at the second positive edge of BCLK which follows a LRCK transition. LRCK is low during left channel transmission and high during right channel transmission in the I2S mode. Left Channel Right Channel LRCK the MSB is sampled here BCLK 1 BCLK where the MSB is clocked out DIN/ DOUT 1 2 3 MSB n-1 1 BCLK n 1 LSB 2 n-1 3 MSB n LSB Figure -4 I2S mode timing diagram of I2S 7.7.2 I2S MCLK/BCLK/LRCK Ratio and Format for CM6523 / CM6523B Internal Codec Sampling Freq. Default Resolution Format BCLK/LRCK MCLK/LRCK 24 bits Left Justified 64 256 64 256 8/11.025/16/ Others 22.5/32/44.1/48 /88.2/96 www.cmedia.com.tw Copyright © C-Media Electronics Inc. 16/24 bits Left Justified / I2S-Mode Rev. 1.02 ︱ Page 32 CM6523 / CM6523B USB Audio Sound Chip External Codec Sampling Freq. 8/11.025/16/ Master Mode 22.5/32/44.1/48 88.2/96 Slave Mode mclk from CM6523 / CM6523B Slave Mode mclk from external www.cmedia.com.tw 8/11.025/16/ 22.5/32/44.1/48 88.2/96 Resolution 16/24 bits 16/24 bits 16/24 bits 16/24 bits 8/11.025/16/ 22.5/32/44.1/48 /88.2/96 Copyright © C-Media Electronics Inc. 16/24 bits Format Left Justified / I2S-Mode Left Justified / I2S-Mode Left Justified / I2S-Mode Left Justified / I2S-Mode Left Justified / I2S-Mode Rev. 1.02 ︱ Page 33 BCLK/LRCK MCLK/LRCK 64 256/512 64 256 64 256/512 64 256 64 128/256/512 CM6523 / CM6523B USB Audio Sound Chip 7.8 SPDIF Control Description 7.8.1 SPDIF Frame Description Audio format : linear 16 bit default, up to 24 bit expandable Allowed sampling frequencies (Fs) of the audio: 44.1kHz from CD 48 kHz from DAT 32 kHz from DSR One way communication: from a transmitter to a receiver. Control information: V (validity) bit : indicates if audio sample is valid. U (user) bit : user free coding i.e. running time song, track number. C (channel status) bit : emphasis, sampling rate and copy permit. P (parity) bit : error detection bit to check for good reception. Coding format: biphase mark except the headers (preambles), for sync purposes. Bandwidth occupation : 100kHz up to 6Mhz (no DC!) Signal bitrate is 2.8Mhz (Fs=44.1kHz), 2Mhz (Fs=32kHz) and 3.1Mhz (Fs=48kHz). www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 34 CM6523 / CM6523B USB Audio Sound Chip Clock Data Signal 1 Biphase Mark Signal 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 0 Figure -17 Biphase Mark signal of SPDIF Preamble cell-order cell-order (last cell "0") (last cell "1") -----------------------------------------------------"B" 11101000 00010111 "M" 11100010 00011101 "W" 11100100 00011011 Preamble B: Marks a word containing data for channel A (left) at the start of the data-block. Preamble M: Marks a word with data for channel A that isn't at the start of the data-block. Preamble W: Marks a word containing data for channel B. (right, for stereo). When using more than 2 channels, this could also be any other channel (except for A). The number of subframes that are used depends on the number of channels that is transmitted. A CD-player uses Channels A and B (left/right) and so each frame contains two subframes. A block contains 192 frames and starts with a preamble "B": Sub-frame 0 3 Preamble 4 7 27 28 29 30 31 8 Aux Data LSB Audio Data Valid, U:User-Data, C:Channel-Status-Data, P:Parity-Bit Figure -5 SPDIF sub-frame description www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 35 MSB V U C P V: CM6523 / CM6523B USB Audio Sound Chip In each block, 384 bits of channel status and subcode info are transmitted. The Channel-status bits are equal for both subframes, so actually only 192 useful bits are transmitted: M ChannelA W ChannelA B ChannelA W ChannelA M ChannelA W ChannelA SubFrame SubFrame Frame 1 Frame 0 Frame 191 Figure -6 Preamble Description of 192 SPDIF frame 7.8.2 byte0 default SPDIF Out Channel Status bit0 bit1 consumer audio/ /professional non-audio 0(P) 0(P) bit2 copyright 1(P) byte1 default 0(P) bit5 bit6 pre-emphasis 0(P) 0(fixed) bit7 mode 0(fixed) 0(fixed) 0(fixed) 0(P) 0(P) L 0(P) 0(P) source number 0(fixed) byte3 default bit4 category code byte2 default bit3 0(fixed) 0(P) 0(P) 0(P) channel number 0(fixed) 0(fixed) 0(fixed) sampling frequency 0(P) 0(P) 0(fixed) clock accuracy 0(P) 0(P) 0(fixed) 0(fixed) 0(fixed) reserved 0(fixed) 0(fixed) 0(fixed) bit5 bit6 bit7 NOTE P : these bit can be programmed by USB HID or USB vendor command 7.8.3 byte0 default SPDIF In Channel Status bit0 bit1 consumer audio/ /professional non-audio 0( R) 0( R) bit2 copyright 1( R) byte1 default bit4 pre-emphasis 0( R) 0( R) mode 0( R) 0( R) category code 0( R) byte2 default bit3 0( R) 0( R) 0( R) L 0( R) source number 0( R) www.cmedia.com.tw Copyright © C-Media Electronics Inc. 0( R) 0( R) 0( R) 0( R) 0( R) 0( R) channel number 0( R) Rev. 1.02 ︱ Page 36 0( R) 0( R) 0( R) 0( R) CM6523 / CM6523B USB Audio Sound Chip byte3 default sampling frequency 0( R) 0( R) 0( R) clock accuracy 0( R) NOTE R : these bit can be read by USB HID or USB vendor command 7.9 Digital Mic Digital_Mic Clock and Data Timing www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 37 0( R) 0( R) reserved 0(fixed) 0(fixed) CM6523 / CM6523B USB Audio Sound Chip 7.10 I2C Interface 7.10.1 I2C Master Mode I2C protocol timing Write Transaction Slave Address 0 A Map Address Data0 A A Data1 A Read Transaction Slave Address 0 A Map Address Slave Address A 1 Data0 A A From Master to Slave From Slave to Master SCL 1. N Byte Write Transaction SDA Slave Address 0 A MAP A Data 1 Data A Data A Stop 2. N Byte Read Transaction SDA Slave Address 1 A Data 1 A Data Data A Stop SCL 3. Auto Read Transaction (= Write- MAP- Only + N Byte Read Transaction) SDA Slave Address 0 A Start 7.10.2 MAP A Slave Address 1 A Data Data A Stop Start from master to slave A = acknowledg e ( SDA Low ) from slave to master A = not acknowledg e ( SDA High ) I2C-Master Read with clk_sync mode www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 38 Stop MAP: Memory Address Pointer (the target register address in slave device ) CM6523 / CM6523B USB Audio Sound Chip 7.10.3 I2C Slave Mode Slave Mode Architecture “7-bit slave address = 7’b0001000 to 7’b0001011” CM6523 / CM6523B can serves as a slave device with bit rate up to 400Kbps (fast mode). External MCU can write data to CM6523 / CM6523B or read data from CM6523 / CM6523B (No Size limitation in I2C Interface). Since host side and MCU can both access to all the internal registers. CM6523 / CM6523B will transfer an interrupt to internal MCU until the INT bit of I2C control Register have been clean by internal MCU. The interrupt will be trigger when write transaction done or detect read-slave-address. The main usage of 2-wire slave bus is to become the interface between the CM6523 / CM6523B and a external micro control unit (EMCU). 7.11 7.11.1 SPI Interface SPI Master Mode The SPI interface is used to transfer control data between the CM6523 / CM6523B and external codecs. It is not a standard interface. Every vendor has its implementation, and the implementation is somewhat different, but generally speaking, all of them comprise four signals, spi_cen, spi_clock, spi_data_o, spi_data_i. Their meanings are as follows. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 39 CM6523 / CM6523B USB Audio Sound Chip spi_cen : the SPI chip enable signal that is used to inform a codec when it should latch the data. spi_clock : the SPI clock signal. spi_data_o : the SPI data output to codec. spi_data_i : the SPI data input from codec. The SPI Design Goal and SPI Transactions Our goal is to design a robust SPI interface which can be suitable for all the existing codec. After analyzing the SPI of codec, we have written down the following difference among them. 1). An SPI interface which can read data from codec and write data to codec has 4 wires, but some codec only support input data. In other words, the data in the codec registers cannot be retrieved by audio processor. This kind of codec only needs 3 wires. 2). An SPI transaction length is 2 or 3 bytes depending on the codec. 3). Some codec latch control data at SPI clock high state, but some codec latch control data at SPI clock low state 4). SPI clock polarity and data capture phase can be selected by CPOL/CPHA register. 5). The upmost SPI clock frequencies are different for the codec. For the difference 1 listed above, we have designed a 4-wire SPI interface, which is able to accommodate the 3-wire SPI interface as well. For difference 2 and 3, control bits in the SPI interface of the CM6523 / CM6523B is used to initiated a 2-byte or 3-byte data transfer, and maintain SPI clock high or low at codec latching data. 7.11.2 SPI transfer length 2B/3B data in address offset 40h data in address offset 41h 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 data in address offset 42h 8 7 6 5 4 3 2 1 0 MSB R/W bit is somewhere between bit23~bit16, depending on different codec High Impedance Fig. 28 An SPI 3-Byte Write transaction with codec latching data at spi_clk low state. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 40 CM6523 / CM6523B USB Audio Sound Chip data in address offset 40h Don’t care 23 22 21 20 19 18 17 16 High Impedance 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fig. 29 An SPI 3-Byte Read transaction with codec latching data at spi_clk high state. data in address offset 40h 15 14 13 12 11 10 9 data in address offset 41h 8 7 6 5 4 3 2 1 0 MSB R/W bit is somewhere between bit23~bit16, depending on different codec High Impedance Fig. 30 An SPI 2-Byte Write transaction with codec latching data at spi_clk high state. data in address offset 40h 15 14 13 12 11 10 9 High Impedance Don’t care 8 7 6 5 4 3 2 1 0 Fig. 31 An SPI 3-Byte Read transaction with codec latching data at spi_clk low state. 7.11.3 SPI latch data at high/low clock state www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 41 CM6523 / CM6523B USB Audio Sound Chip SPI 3-byte Write Transaction codec latch data at spi_clk = 1 spi_cen spi_clk data in address offset B0h spi_data_o data in address offset B1h 23 22 21 20 19 18 17 16 15 14 13 12 MSB 11 10 9 data in address offset B2h 8 7 6 5 4 3 2 1 0 LSB R/W bit is somewhere between bit23~bit16, depending on different codecs High impedance spi_data_i SPI 3-byte Write Transaction with High state Latch SPI 3-byte Write Transaction codec latch data at spi_clk = 0 spi_cen spi_clk data in address offset B0h spi_data_o 23 22 21 20 19 18 17 16 15 14 13 12 MSB spi_data_i data in address offset B1h 11 10 9 data in address offset B2h 8 7 6 5 R/W bit is somewhere between bit23~bit16, depending on different codecs 4 3 2 1 0 LSB High impedance SPI 3-byte Write Transaction with Low state Latch www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 42 CM6523 / CM6523B USB Audio Sound Chip SPI 3-byte Read Transaction (R/W bit is embedded in spi_data_o[23:16], but this bit position is dependent on codecs) RM5003 latch data at spi_clk=1 spi_cen spi_clk data in address offset 9Bh spi_data_o Don’t care 23 22 21 20 19 18 17 16 LSB MSB LSB MSB High impedance spi_data_i 15 14 13 12 The bit length of the high impedance is dependent on the individual codec. 11 10 9 8 7 6 5 4 3 2 1 0 data will be captured in address offset B1h, B2h This line is not fixed. It can be moved to the left or right depending on codecs SPI 3-byte Read Transaction with Low state Latch REG3E~3C 4 C1_80_02 Description CPOL=1/CPHA=1/MstIntEn/CodecLatch@SPICK_low/Len=2B SPI-Fig.4 1) The SPI of CPOL/CPHA selection A timing diagram showing clock polarity and phase www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 43 Figure SPI-Fig.4 CM6523 / CM6523B USB Audio Sound Chip In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide [1] names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention. The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device. • At CPOL=0 the base value of the clock is zero o For CPHA=0, data is captured on the clock's rising edge (low→high transition) and data is propagated on a falling edge (high→low clock transition). o For CPHA=1, data is captured on the clock's falling edge and data is propagated on a rising edge. • At CPOL=1 the base value of the clock is one (inversion of CPOL=0) o For CPHA=0, data is captured on clock's falling edge and data is propagated on a rising edge. o For CPHA=1, data is captured on clock's rising edge and data is propagated on a falling edge. That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle. For all CPOL and CPHA modes, the initial clock value must be stable before the chip select line goes active. Also, note that "data are read" in this document more typically means "data may be read". The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 44 CM6523 / CM6523B USB Audio Sound Chip This adds more flexibility to the communication channel between the master and slave. Some products use different naming conventions. For example, the TI MSP430 uses the name UCCKPL instead of CPOL, and its UCCKPH is the inverse of CPHA. When connecting two chips together, carefully examine the clock phase initialization values to be sure of using the right settings. REG3E~3C Description Figure 1 C1_C0_02 CPOL=1/CPHA=1/MstIntEn/Len=2B SPI-Fig.1 3 01_C0_02 CPOL=0/CPHA=0/MstIntEn/Len=2B SPI-Fig.3 2 41_C0_02 CPOL=0/CPHA=1/MstIntEn/Len=2B SPI-Fig.2 SPI-Fig.1 SPI-Fig.2 SPI-Fig.3 7.11.4 SPI Slave Mode In CM6523 / CM6523B, SPI-slave will trigger interrupt when receive 9th bit data in 3Byte mode. There are 6bits SPI-clocks reserved for MCU to prepare wanted read data. In this case, the SPI-clock operated at 800KHz and MCU have enough time to prepare read data. The procedure of MCU deal SPI-slave-read list below. Step1: MCU get interrupt and clear. Step2: MCU read REG3E[2] to determine it’s a read or write command. And REG3E[3] defined as HID flag. Step3: MCU read REG39 to get read address. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 45 CM6523 / CM6523B USB Audio Sound Chip Step4: MCU prepare the content of read address. Step5: MCU put the content into REG3B. SPI-slave can read correctly only if all MCU operation under 6 SPI-clocks. We can NOT support too faster SPI negotiation. 16b(2B-Addr-Phase) - 1b(R/W) - 1b(HID) - 8b(Addr) = 6b(Reserved) The procedure of MCU deal SPI-slave-write list below. Step1: MCU get interrupt and clear. Step2: MCU read REG3E[2] to determine it’s a read or write command. And REG3E[3] defined as HID flag. Step3: MCU read REG39 to get read address. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 46 CM6523 / CM6523B USB Audio Sound Chip 8 8.1 Electrical Characteristics Absolute Maximum Ratings Test Conditions: DV50 = 5V, AV50 = 5V, DGND =0V, TA=+25oC Parameter Symbol Min Typ Max Storge temperature - -25 - 150 o C Operating ambient temperature - 0 25 75 o C Digital supply voltage(DV50) - 4.5 5.0 5.5 V 4.5 5.0 5.5 V GND - VDD V Analog Supply Voltage(AV50) I/O pin voltage 8.2 ESD(Human Body Mode) ±4000 V ESD(Machine Mode) ±200 V Recommended Operation Conditions Parameter Analog Supply Voltage Symbol Min - Typ Max 5 Digital Supply Voltage 5 Operating Ambient Temperature 25 Crystal Clock 8.3 - Units - Units V o 12.000 C MHz Power Consumption o Test Conditions: DV50=5V, AV50 = 5V, DGND =0V, TA=+25 C Sample Rate=48Khz, 16Bits, Operation: HP-Out Playback+Mic-In Recording, EQ disable, Spdif out disable Parameter Symbol Min Typ Max Units - - 55 - mA Standby Power Consumption - - 50 - mA Suspend Mode Power Consumption - - 10 - uA Total Power Consumption (Playback+Record) 8.4 DC Characteristics o Test Conditions: DV50=5V, VDD = 3.3V, DGND =0V, TA=+25 C, VDD = 3.3V Parameter Symbol Min Typ Max Units Vin VDD-0.3 VDD VDD+0.3 V Vout 0 - VDD V High level input voltage Vih 0.7VDD - - V Low level input voltage Vil - - 0.3VDD V High level output voitage Voh 2.4 - - V Input voltage range Output voltage range www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 47 CM6523 / CM6523B USB Audio Sound Chip Low level output voltage Vol - 0.4 V Input leakage current Iil -10 - 10 uA Output leakage current Iol -10 - 10 uA Output buffer driver current - 2 8 16 mA SPDIF transmit output driver current - 2 8 16 mA www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 48 CM6523 / CM6523B USB Audio Sound Chip 8.5 Audio Performance 8.5.1 DAC Audio Quality TA=25℃, DV50=5V, AV50=5V Items Test Conditions Test Values Min 10KΩ loading Full scale output voltage fs=48KHz 32Ω loading fs=48KHz 10KΩ loading fs=48KHz/16bits,A-Weighted 10KΩ loading THD+N @ Vout=-3dB fs=96KHz/24bits, A-Weighted 32Ω loading fs=48KHz/16bits,A-Weighted 32Ω loading fs=96KHz/24bits,A-Weighted -67 -92 dB -67 -95 dB 32Ω loading fs=96KHz/24bits,A-Weighted 10KΩ loading fs=48KHz/16bits,A-Weighted 10KΩ loading fs=96KHz/24bits, A-Weighted 32Ω loading fs=48KHz/16bits,A-Weighted 32Ω loading fs=96KHz/24bits,A-Weighted Rev. 1.02 ︱ Page 49 Vrms dB 32Ω loading Copyright © C-Media Electronics Inc. 0.82 -94 fs=48KHz/16bits,A-Weighted www.cmedia.com.tw Vrms -79 fs=96KHz/24bits, A-Weighted 100Hz ~ 20KHz 0.95 dB 10KΩ loading Inter channel phase delay Unit -93 fs=48KHz/16bits,A-Weighted Noise level during system activity Max -78 10KΩ loading Dynamic range with signal present Typ +0.02 91 dB 94 dB 92 dB 94 dB 94 dB 96 dB 96 dB 94 dB +1.05 deg CM6523 / CM6523B USB Audio Sound Chip Sampling frequency accuracy 10KΩ loading fs=48KHz/16bits,A-Weighted 10KΩ loading Channel separation fs=48KHz/16bits,A-Weighted 32Ω loading fs=48KHz/16bits,A-Weighted Magnitud e Response 8.5.2 Frequency Response Passband Ripple 10KΩ loading fs=48KHz/16bits,A-Weighted -0.0043 +0.0015 % 98 119 dB 67 78 dB -0.085 -0.937 dB 0.291 dB 10KΩ loading fs=48KHz/16bits,A-Weighted ADC Audio Quality TA=25℃, DV50=5V, AV50=5V, Input test signal is 997Hz sine wave, measure bandwidth is 20Hz to 20KHz Items Full scale output voltage Test Conditions Test Values Min Microphone Line in Microphone THD+N @ Vout=-3dB fs=96KHz/24bits, A-Weighted Line in fs=48KHz/16bits,A-Weighted Line in fs=96KHz/24bits,A-Weighted Microphone fs=48KHz/16bits,A-Weighted Microphone Dynamic range with signal present fs=96KHz/24bits, A-Weighted Line in fs=48KHz/16bits,A-Weighted Line in fs=96KHz/24bits,A-Weighted www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 50 Unit Vrms 1.08 fs=48KHz fs=48KHz/16bits,A-Weighted Max 1.11 fs=48KHz Microphone Typ -81 -89 dB --82 -91 dB -82 -90 dB -82 -90 dB 90 dB 91 dB 90 dB 90 dB CM6523 / CM6523B USB Audio Sound Chip Microphone Sampling frequency accuracy fs=48KHz/16bits Line in fs=48KHz/16bits Microphone fs=48KHz/16bits Microphone Channel separation fs=96KHz/24bits Line in fs=48KHz/16bits Line in fs=96KHz/24bits Microphone Frequency Response fs=48KHz/16bits,A-Weighted Line in fs=48KHz/16bits,A-Weighted +0.009 -0.0048 -0.0034 81 91 dB 83 91 dB 86 89 87 90 -0.433 -0.484 -0.313 -0.695 Microphone Passband Ripple 0.204 fs=48KHz/16bits,A-Weighted Line in dB dB 0.159 fs=48KHz/16bits,A-Weighted 8.5.3 % +0.0001 A-A path Audio Quality TA=25℃, DV50=5V, AV50=5V Items Test Conditions Full scale output voltage Microphone to Line out THD+N @ Vout=-3dB Dynamic range with signal present Channel separation Frequency Response www.cmedia.com.tw Copyright © C-Media Electronics Inc. Microphone to Line out fs=48KHz/16bits,A-Weighted Test Values Min -80 Microphone to Line out fs=48KHz/16bits,A-Weighted Rev. 1.02 ︱ Page 51 Unit Vrms -81 92 fs=48KHz/16bits,A-Weighted fs=48KHz/16bits,A-Weighted Max 1.09 Microphone to Line out Microphone to Line out Typ dB dB 74 119 dB -0.194 +0.484 dB CM6523 / CM6523B USB Audio Sound Chip Passband Ripple www.cmedia.com.tw Copyright © C-Media Electronics Inc. Microphone fs=48KHz/16bits,A-Weighted Rev. 1.02 ︱ Page 52 0.1 dB CM6523 / CM6523B USB Audio Sound Chip 9 Package Dimension Operating Ambient Model Number Package CM6523 / 128-Pin LQFP 14mm×14mm×1.4mm (Plastic) Temperature CM6523B Outline Dimensions -15°C to +70°C *Dimensions shown in inches and (mm) 128-Lead Thin Plastic Quad Flatpack (LQFP) Package Dimension of CM6523 / CM6523B www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 53 Supply Range DVdd = 5V, AVdd = 5V CM6523 / CM6523B USB Audio Sound Chip －End of Specifications－ C-MEDIA ELECTRONICS INC. 6F., 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106 R.O.C. TEL：+886-2-8773-1100 FAX：+886-2-8773-2211 E-MAIL：[email protected] Disclaimer: Information furnished by C-Media Electronics Inc. is believed to be accurate and reliable. However, no responsibility is assumed by C-Media Electronics Inc. for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of C-Media. Trademark and registered trademark are the property of their respective owners. www.cmedia.com.tw Copyright © C-Media Electronics Inc. Rev. 1.02 ︱ Page 54