EMC EM78156E 8-bit microcontroller with mask rom Datasheet

EM78156E
8-Bit Microcontroller
with MASK ROM
Product
Specification
DOC. VERSION 1.3
ELAN MICROELECTRONICS CORP.
July 2004
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are trademarks of ELAN Microelectronics Corporation.
Copyright © 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
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The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be
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NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY
MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
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Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information
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Elan Microelectronics
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Contents
Contents
1
2
3
4
GENERAL DESCRIPTION ......................................................................................... 1
FEATURES ................................................................................................................. 1
PIN ASSIGNMENT ..................................................................................................... 2
FUNCTION DESCRIPTION ........................................................................................ 4
4.1
Operational Registers......................................................................................... 4
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.2
R0 (Indirect Addressing Register) .......................................................................4
R1 (Time Clock /Counter)....................................................................................4
R2 (Program Counter) & Stack ...........................................................................5
R3 (Status Register) ............................................................................................6
R4 (RAM Select Register)...................................................................................7
R5 ~ R6 (Port 5 ~ Port 6) ....................................................................................7
RF (Interrupt Status Register) .............................................................................7
R10 ~ R3F ...........................................................................................................7
Special Purpose Registers ................................................................................. 8
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
A (Accumulator)...................................................................................................8
CONT (Control Register).....................................................................................8
IOC5 ~ IOC6 (I/O Port Control Register) ............................................................8
IOCA (Prescaler Counter Register).....................................................................9
IOCB (Pull-down Control Register) .....................................................................9
IOCC (Open-drain Control Register)...................................................................9
IOCD (Pull-high Control Register).....................................................................10
IOCE (WDT Control Register) ...........................................................................10
IOCF (Interrupt Mask Register).........................................................................11
4.3
TCC/WDT & Prescaler ..................................................................................... 11
4.4
I/O Ports ........................................................................................................... 12
4.5
RESET and Wake-up ....................................................................................... 15
4.5.1
4.5.2
RESET ..............................................................................................................15
The Status of RST, T, and P of STATUS Register .............................................19
4.6
Interrupt ............................................................................................................ 20
4.7
Oscillator .......................................................................................................... 22
4.7.1
4.7.2
4.7.3
Oscillator Modes................................................................................................22
.Crystal Oscillator/Ceramic Resonators(XTAL) .................................................22
External RC Oscillator Mode.............................................................................23
4.8
CODE Option Register ..................................................................................... 25
4.9
Power On Considerations ................................................................................ 25
4.10 External Power On Reset Circuit...................................................................... 26
4.11 Residue-Voltage Protection.............................................................................. 26
4.12 Instruction Set .................................................................................................. 27
4.13 Timing Diagrams .............................................................................................. 30
Product Specification (V1.3) 07.29.2004
• iii
Contents
5
6
ABSOLUTE MAXIMUNM RATINGS ........................................................................ 31
ELECTRICAL CHARACTERISTICS ........................................................................ 31
6.1
DC Electrical Characteristic.............................................................................. 31
6.2
AC Electrical Characteristic.............................................................................. 32
6.3
Device Characteristic ....................................................................................... 33
APPENDIX
A
B
Package Types......................................................................................................... 43
Package Information............................................................................................... 43
Specification Revision History
Doc. Version
1.0
Initial version
1.1
Change set up time period
1.2
1.3
iv •
Revision Description
Date
04/19/2002
Change Power on reset content
07/01/2003
Change from EM78P156E to EM78156E
Add the Device Characteristic at section 6.3
07/29/2004
Product Specification (V1.3) 07.29.2004
EM78156E
8-Bit Microcontroller with MASK ROM
1
GENERAL DESCRIPTION
EM78156E is an 8-bit microprocessor with low-power and high-speed CMOS
technology. Integrated into a single chip are on-chip watchdog timer (WDT), RAM,
ROM, real time clock/counter, external and interrupt, power down mode, and tri-state
I/O.
2
FEATURES
Operating voltage range : 2.3V~5.5V
Operating temperature range: 0°C~70°C
Operating frequency rang (base on 2 clocks ):
• Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.
• ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
Low power consumption:
• Less then 2.0 mA at 5V/4MHz
• Typically 15 µA at 3V/32KHz
• Typically 1 µA during sleep mode
1K × 13 bits on chip ROM
One configuration register to accommodate user’s requirements
48× 8 bits on chip registers (SRAM, general purpose register)
2 bi-directional I/O ports
5 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and
overflow interrupt
Two clocks per instruction cycle
Power down (SLEEP) mode
Three available interruptions
• TCC overflow interrupt
• Input-port status changed interrupt (wake up from sleep mode)
• External interrupt
Programmable free running watchdog timer
8 programmable pull-high pins
7 programmable pull-down pins
8 programmable open-drain pins
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
•1
EM78156E
8-Bit Microcontroller with MASK ROM
2 programmable R-option pins
Package types:
•
•
•
•
18 pin DIP 300mil : EM78156EP
18 pin SOP(SOIC) 300mil : EM78156EM
20 pin SSOP 209mil : EM78156EAS
20 pin SSOP 209mil : EM78156EKM
99.9% single instruction cycle commands
The transient point of system frequency between HXT and LXT is around 400KHz
3
PIN ASSIGNMENT
P52
P51
18
1
17
P50
TCC
3
16
OSCI
/RESET
4
15
OSCO
Vss
5
14
VDD
P60/INT
6
13
P61
7
P62
P63
20
NC
2
19
P51
18
P50
17
OSCI
16
TCC
4
/RESET
5
Vss
6
P67
P60/INT
7
12
P66
P61
8
11
P65
9
10
P64
EM78156EP
EM78156EM
P53
3
P52
1
20
P51
P53
2
19
P50
18
OSCI
17
OSCO
16
VDD
15
VDD
14
P67
P66
TCC
3
/RESET
4
OSCO
Vss
5
15
VDD
Vss
6
14
P67
P60/INT
7
8
13
P66
P61
8
13
P62
9
12
P65
P62
9
12
P65
P63
10
11
P64
P63
10
11
P64
EM78156EKM
2
1
EM78156EAS
P53
NC
P52
Fig. 1 Pin Assignment
Table 1 EM78156EP and EM78156EM Pin Description
Symbol
Pin No.
Type
VDD
14
-
OSCI
16
I
OSCO
15
I/O
TCC
3
I
/RESET
4
I
P50~P53
17, 18,
1, 2
I/O
P60~P67
6~13
I/O
/INT
VSS
6
5
2•
I
-
Function
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Power supply.
XTAL type: Crystal input terminal or external clock input pin.
ERC type: RC oscillator input pin.
XTAL type: Output terminal for crystal oscillator or external clock input pin.
RC type: Instruction clock output.
External clock signal input.
The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
P50~P53 are bi-directional I/O pins.
P50 and P51 can also be defined as the R-option pins.
P50~P52 can be pulled-down by software.
P60~P67 are bi-directional I/O pins.
These can be pulled-high or can be open-drain by software programming.
P60~P63 can also be pulled-down by software.
External interrupt pin triggered by falling edge.
Ground.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Table 2 EM78156EAS Pin Description
Symbol
Pin No.
Type
Function
VDD
15
-
■ Power supply.
OSCI
17
I
OSCO
16
I/O
TCC
4
I
/RESET
5
I
P50~P53
18, 19,
2, 3
I/O
P60~P67
7~14
I/O
/INT
7
I
■ External interrupt pin triggered by falling edge.
VSS
6
-
■ Ground.
■
■
■
■
■
■
■
■
■
■
■
■
■
XTAL type: Crystal input terminal or external clock input pin.
ERC type: RC oscillator input pin.
XTAL type: Output terminal for crystal oscillator or external clock input pin.
RC type: Instruction clock output.
External clock signal input.
The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain keep in reset condition.
P50~P53 are bi-directional I/O pins.
P50 and P51 can also be defined as the R-option pins.
P50~P52 can also be pulled-down by software.
P60~P67 are bi-directional I/O pins.
These can be pulled-high or can be open-drain by software programming.
P60~P63 can be pulled-down also by software.
Table 3 EM78156EKM Pin Description
Symbol
Pin No.
Type
Function
VDD
15,16
-
OSCI
18
I
OSCO
17
I/O
TCC
3
I
/RESET
4
I
P50~P53
19, 20,
1, 2
I/O
P60~P67
7~14
I/O
/INT
7
I
■ External interrupt pin triggered by falling edge.
VSS
5, 6
-
■ Ground.
■ Power supply.
■
■
■
■
■
■
■
■
■
■
■
■
■
XTAL type: Crystal input terminal or external clock input pin.
ERC type: RC oscillator input pin.
XTAL type: Output terminal for crystal oscillator or external clock input pin.
RC type: Instruction clock output.
External clock signal input.
The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
P50~P53 are bi-directional I/O pins.
P50 and P51 can also be defined as the R-option pins.
P50~P52 can be pulled-down by software.
P60~P67 are bi-directional I/O pins.
These can be pulled-high or can be open-drain by software programming.
P60~P63 can also be pulled-down by software.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
•3
EM78156E
8-Bit Microcontroller with MASK ROM
4
FUNCTION DESCRIPTION
OSCO
/RESET
OSCI
WDT timer
TCC
/INT
Oscillator/Timing
Control
ROM
Prescaler
R2
Stack
IOCA
Interrupt
Controller
RAM
R4
ALU
Instruction
Register
R3
R1(TCC)
Instruction
Decoder
ACC
DATA & CONTROL BUS
IOC6
R6
I/O
PORT 6
P60//INT
P61
P62
P63
P64
P65
P66
P67
IOC5
R5
I/O
PORT 5
P50
P51
P52
P53
Fig. 2 Function Block Diagram
4.1 Operational Registers
4.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
4.1.2 R1 (Time Clock /Counter)
Increased by an external signal edge which is defined by TE bit (CONT-4) through
the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
Defined by resetting PAB(CONT-3).
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
The contents of the prescaler counter will be cleared only when TCC register is
written with a value.
4•
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
4.1.3 R2 (Program Counter) & Stack
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in Fig.3.
Generating 1024×13 bits on-chip ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
R2 is set as all "0"s when under RESET condition.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to go to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
"ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth
and tenth bits of the PC are cleared.
"MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits of the PC are cleared.
Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will
cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the
computed jump is limited to the first 256 locations of a page.
All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction
that would change the contents of R2. Such instruction will need one more
instruction cycle.
PC (A9 ~ A0)
000H
008H
User Memory
Space
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Reset Vector
Interrupt Vector
On-chip Program
Memory
3FFH
Fig. 3 Program Counter Organization
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
•5
EM78156E
8-Bit Microcontroller with MASK ROM
Address
R PAGE registers
IOC PAGE registers
00
R0
(IAR)
Reserve
01
R1
(TCC)
02
R2
(PC)
Reserve
03
R3
(Status)
Reserve
04
R4
(RSR)
Reserve
05
R5
(Port5)
IOC5
(I/O Port Control Register)
06
R6
(Port6)
IOC6
(I/O Port Control Register)
CONT
(Control Register)
07
Reserve
Reserve
08
Reserve
Reserve
09
Reserve
Reserve
0A
Reserve
IOCA
(Prescaler Control Register)
0B
Reserve
IOCB
(Pull-down Register)
0C
Reserve
IOCC
(Open-drain Control)
0D
Reserve
IOCD
(Pull-high Control Register)
0E
Reserve
IOCE
(WDT Control Register)
IOCF
(Interrupt Mask Register)
0F
RF
(Interrupt Status)
10
General Registers
︰
3F
Fig. 4 Data Memory Configuration
4.1.4 R3 (Status Register)
7
6
5
4
3
2
1
0
GP2
GP1
GP0
T
P
Z
DC
C
Bit 0 (C)
Carry flag
Bit 1 (DC) Auxiliary carry flag
Bit 2 (Z)
Zero flag.
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 3 (P)
Power down bit.
Set to 1 during power on or by a "WDTC" command and reset to 0 by a
"SLEP" command.
6•
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Bit 4 (T) Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and
reset to 0 by WDT time-out.
Bit5 ~7 (GP0 ~ 2) General purpose read/write bits.
4.1.5 R4 (RAM Select Register)
Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect
addressing mode.
Bits 6~7 are not used.(read only).
The Bits 6~7 set to “1” at all time.
Z flag of R3 will set to “1”, when R4 content is equal to “3F” When R4=R4+1,
R4 content will select as R0.
See the configuration of the data memory in Fig. 4.
4.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 and R6 are I/O registers.
Only the lower 4 bits of R5 are available.
4.1.7 RF (Interrupt Status Register)
7
6
5
4
3
2
1
0
-
-
-
-
-
EXIF
ICIF
TCIF
“1” means interrupt request, and “0” means no interrupt occur.
Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes,
reset by software.
Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
Bits 3 ~ 7 Not used.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
Note that the result of reading RF is the "logic AND" of RF and IOCF.
4.1.8 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
•7
EM78156E
8-Bit Microcontroller with MASK ROM
4.2 Special Purpose Registers
4.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding
It cannot be addressed.
4.2.2 CONT (Control Register)
7
6
5
4
3
2
1
0
-
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
Bit 4 (TE)
TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 5 (TS)
TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
Bit 6 (/INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
Bit 7
Not used.
CONT register is both readable and writable.
4.2.3 IOC5 ~ IOC6 (I/O Port Control Register)
"1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as
output.
8•
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Only the lower 4 bits of IOC5 can be defined.
IOC5 and IOC6 registers are both readable and writable.
4.2.4 IOCA (Prescaler Counter Register)
IOCA register is readable.
The value of IOCA is equal to the contents of Prescaler counter.
Down counter.
4.2.5 IOCB (Pull-down Control Register)
7
6
5
4
3
2
1
0
/PD7
/PD6
/PD5
/PD4
-
/PD2
/PD1
/PD0
Bit 0 (/PD0) Control bit is used to enable the pull-down of P50 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 1 (/PD1) Control bit is used to enable the pull-down of P51 pin.
Bit 2 (/PD2) Control bit is used to enable the pull-down of P52 pin.
Bit 3
Not used.
Bit 4 (/PD4) Control bit is used to enable the pull-down of P60 pin.
Bit 5 (/PD5) Control bit is used to enable the pull-down of P61 pin.
Bit 6 (/PD6) Control bit is used to enable the pull-down of P62 pin.
Bit 7 (/PD7) Control bit is used to enable the pull-down of P63 pin.
IOCB Register is both readable and writable.
4.2.6 IOCC (Open-drain Control Register)
7
6
5
4
3
2
1
0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Bit 0 (OD0) Control bit used to enable the open-drain of P60 pin.
0: Disable open-drain output
1: Enable open-drain output
Bit 1 (OD1) Control bit is used to enable the open-drain of P61 pin.
Bit 2 (OD2) Control bit is used to enable the open-drain of P62 pin.
Bit 3 (OD3) Control bit is used to enable the open-drain of P63 pin.
Bit 4 (OD4) Control bit is used to enable the open-drain of P64 pin.
Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
•9
EM78156E
8-Bit Microcontroller with MASK ROM
Bit 6 (OD6)
Control bit is used to enable the open-drain of P66 pin.
Bit 7 (OD7)
Control bit is used to enable the open-drain of P67 pin.
IOCC Register is both readable and writable.
4.2.7 IOCD (Pull-high Control Register)
7
6
5
4
3
2
1
0
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Bit 0 (/PH0)
Control bit is used to enable the pull-high of P60 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 1 (/PH1)
Control bit is used to enable the pull-high of P61 pin.
Bit 2 (/PH2)
Control bit is used to enable the pull-high of P62 pin.
Bit 3 (/PH3)
Control bit is used to enable the pull-high of P63 pin.
Bit 4 (/PH4)
Control bit is used to enable the pull-high of P64 pin.
Bit 5 (/PH5)
Control bit is used to enable the pull-high of P65 pin.
Bit 6 (/PH6)
Control bit is used to enable the pull-high of P66 pin.
Bit 7 (/PH7)
Control bit is used to enable the pull-high of P67 pin.
IOCD Register is both readable and writable.
4.2.8 IOCE (WDT Control Register)
7
6
5
4
3
2
1
0
WDTE
EIS
-
ROC
-
-
-
-
Bit 7 (WDTE) Control bit used to enable Watchdog timer.
0: Disable WDT.
1: Enable WDT.
WDTE is both readable and writable.
Bit 6 (EIS)
Control bit is used to define the function of P60(/INT) pin.
0: P60, bi-directional I/O pin.
1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit
0 of IOC6) must be set to "1".
When EIS is "0", the path of /INT is masked. When EIS is "1", the status
of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig.
7(a).
EIS is both readable and writable.
10 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Bit 4 (ROC) ROC is used for the R-option.
Setting the ROC to "1" will enable the status of R-option pins (P50∼P51)
that are read by the controller. Clearing the ROC will disable the R-option
function. If the R-option function is selected, user must connect the P51
pin or/and P50 pin to VSS with a 430KΩ external resistor (Rex). If the Rex
is connected/disconnected, the status of P50 (P51) is read as "0"/"1".
Refer to Fig. 8.
Bits 0~3,5 Not used.
4.2.9 IOCF (Interrupt Mask Register)
7
6
5
4
3
2
1
0
-
-
-
-
-
EXIE
ICIE
TCIE
Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
Bit 1 (ICIE) ICIF interrupt enable bit.
0: disable ICIF interrupt
1: enable ICIF interrupt
Bit 2 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
Bits 3~7
Not used.
Individual interrupt is enabled by setting its associated control bit in the
IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. Refer to Fig. 10.
IOCF register is both readable and writable.
4.3 TCC/WDT & Prescaler
An 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available
for either the TCC or WDT only at any given time, and the PAB bit of the CONT register
is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the
ratio. The prescaler is cleared each time the instruction is written to TCC under TCC
mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the
“WDTC” or “SLEP” instructions. Fig. 5 depicts the circuit diagram of TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or
external clock input (edge selectable from TCC pin). If TCC signal source is from
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 11
EM78156E
8-Bit Microcontroller with MASK ROM
internal clock, TCC will increase by 1 at every instruction cycle (without prescaler).
Referring to Fig. 5, CLK=Fosc/2 or CLK=Fosc/4 application is determined by the
CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and
CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external
clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (default).
Data Bus
CLK(=Fosc/2 or Fosc/4)
0
TCC
Pin
1
1
M
U
X
0
M
U
X
SYNC
2 cycles
TE
TS
TCC (R1)
TCC overflow interrupt
PAB
0
WDT
1
WTE
(in IOCE)
M
U
X
8-bit Counter
PAB
8-to-1 MUX
M
U
X
IOCA
PAB
PSR0~PSR2
0
Initial
value
1
MUX
PAB
WDT time-out
Fig. 5 Block Diagram of TCC and WDT
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can
be pulled high internally by software. In addition, Port 6 can also have open-drain
output by software. Input status change interrupt (or wake-up) function on Port 6. P50
~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be
defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6). P50~P51
are the R-option pins enabled by setting the ROC bit in the IOCE register to 1. When
the R-option function is used, it is recommended that P50~P51 are used as output pins.
When R-option is in enable state, P50~P51 must be programmed as input pins. Under
1
<Note>: Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
12 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
R-option mode, the current/power consumption by Rex should be taken into the
consideration to promote energy conservation.
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 and Port 6 are shown in the following Figures 6, 7(a), 7(b),
7(C)and Figure 8.
PCRD
P
R
Q
_
Q
PORT
C
L
D
P
R
Q
_
Q
C
L
PC W R
CLK
IO D
D
PD W R
CLK
PDRD
0
1
M
U
X
NOTE: Pull-down is not shown in the figure.
Fig. 6 The Circuit of I/O Port and I/O Control Register for Port 5
PC R D
Q
_
Q
P
R D
C L K
C
L
PC W R
Q
_
Q
P
R D
C L K
C
L
PD W R
P 6 0 /I N T
PO R T
B it 6 o f I O C E
P
R
C L K
C
L
D
0
Q
1
_
Q
IO D
M
U
X
PD R D
P
R
C L K
C
L
D
T 10
Q
_
Q
IN T
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7(a) The Circuit of I/O Port and I/O Control Register for P60(/INT)
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 13
EM78156E
8-Bit Microcontroller with MASK ROM
PCRD
P61~P67
PORT
0
1
Q
_
Q
P
R D
CLK
C
L
PCWR
Q
_
Q
P
R D
CLK
C
L
PDWR
IOD
M
U
X
TIN
PDRD
P
R
CLK
C
L
D
Q
_
Q
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67
IOCE.1
D
P
R
Q
Interrupt
CLK
_
C Q
L
RE.1
ENI Instruction
P
D R Q
T10
T11
CLK
_
C
L Q
P
Q R
D
CLK
_
Q C
L
T17
DISI Instruction
/SLEP
Interrupt
(Wake-up from SLEEP)
Next Instruction
(Wake-up from SLEEP)
Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up
14 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Table 4 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 input status changed Wake-up/Interrupt
(I) Wake-up from Port 6 Input Status change
(II) Port 6 Input Status Change Interrupt
(a) Before SLEEP
1. Disable WDT2 (using very carefully)
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI"
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt (Set IOCF.1)
3. Execute "ENI" or "DISI"
4. IF Port 6 change (interrupt)
4. Enable interrupt (Set IOCF.1)
→ Interrupt vector (008H)
5. Execute "SLEP" instruction
(b) After Wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
PCRD
VCC
ROC
Q
P
R
Q
C
L
Q
P
R
Q
C
L
Weakly
Pull-up
PORT
D
CLK
PCWR
IOD
D
PDWR
PDRD
0
1
Rex*
M
U
X
*The Rex is 430K ohm external resistor
Fig. 8 The Circuit of I/O Port with R-option(P50,P51)
4.5 RESET and Wake-up
4.5.1 RESET
A RESET is initiated by one of the following events(1) Power on reset.
2
NOTE: Software disables WDT (watchdog timer) but hardware must be enabled before applying Port
6 Changed Wake-up function. (CODE Option Register and Bit 11 (ENWDT) are set to “1”).
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 15
EM78156E
8-Bit Microcontroller with MASK ROM
(2) /RESET pin input "low",or
(3) WDT time-out (if enabled).
The device is kept in a RESET condition for a period of approx. 183ms (one oscillator
start-up timer period) after the reset is detected. Once the RESET occurs, the following
functions are performed. Refer to Fig.9.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag).
The bits of the IOCA register are set to all "1".
The bits of the IOCB register are set to all "1".
The IOCC register is cleared.
The bits of the IOCD register are set to all "1".
Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared.
Bits 0~2 of RF and bits 0~2 of IOCF register are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be awakened by(1) External reset input on /RESET pin,
(2) WDT time-out (if enabled), or
(3) Port 6 input status changes (if enabled).
The first two cases will cause the EM78156E to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up). The last case is considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) decides whether or not the controller branches to the interrupt vector
following wake-up. If ENI is executed before SLEP, the operation will restart from the
succeeding instruction right next to SLEP after wake-up.
Only one of Cases 2 and 3 can be enabled before entering the sleep mode. That is,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP , WDT must be
disabled. by software. However, the WDT bit in the option register remains
enabled. Hence, the EM78156E can be awakened only by Case 1 or 3.
3
NOTE: Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
16 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the EM78156E can be awakened only by Case 1 or 2. Refer to
the section on Interrupt.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78156E (Case [a]
above), the following instructions must be executed before SLEP:
MOV A, @xx000110b
; Select internal TCC clock
CONTW
CLR R1
; Clear TCC and prescaler
MOV A, @xxxx1110b
; Select WDT prescaler
CONTW
WDTC
; Clear WDT and prescaler
MOV A, @0xxxxxxxb
; Disable WDT
IOW RE
MOV R6, R6
; Read Port 6
MOV A, @00000x1xb
; Enable Port 6 input change interrupt
IOW RF
ENI (or DISI)
; Enable (or disable) global interrupt
SLEP
; Sleep
NOP
One problem user should be aware of, is that after waking up from the sleep mode,
WDT would enable automatically. The WDT operation (being enabled or disabled)
should be handled appropriately by software after waking up from the sleep mode.
Table 5 The Summary of the Initialized Values for Registers
Address
N/A
Name
IOC5
Reset Type
N/A
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
X
X
X
X
C53
C52
C51
C50
Power-On
U
U
U
U
1
1
1
1
/RESET and WDT
U
U
U
U
1
1
1
1
U
U
U
U
P
P
P
P
C67
C66
C65
C64
C63
C62
C61
C60
Wake-Up from Pin
Change
Bit Name
N/A
Bit 7
Power-On
1
1
1
1
1
1
1
1
IOC6
/RESET and WDT
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
CONT
Wake-Up from Pin
Change
Bit Name
X
/INT
TS
TE
PAB
Power-On
1
0
1
1
1
1
1
1
/RESET and WDT
1
0
1
1
1
1
1
1
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
PSR2 PSR1 PSR0
• 17
EM78156E
8-Bit Microcontroller with MASK ROM
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
Bit Name
0x00
R0(IAR)
Wake-Up from Pin
Change
Bit Name
0x01
R1(TCC)
Wake-Up from Pin
Change
Bit Name
0x02
R2(PC)
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin
Change
Bit Name
0x03
R3(SR)
GP2
GP1
GP0
T
P
Z
DC
C
Power-On
0
0
0
1
1
U
U
U
/RESET and WDT
0
0
0
T
t
P
P
P
P
P
P
T
t
P
P
P
-
-
-
-
-
-
-
-
Power-On
1
1
U
U
U
U
U
U
/RESET and WDT
1
1
P
P
P
P
P
P
Wake-Up from Pin
Change
Bit Name
0x04
0x05
R4(RSR)
P5
Wake-Up from Pin
Change
Bit Name
1
1
P
P
P
P
P
P
X
X
X
X
P53
P52
P51
P50
Power-On
0
0
0
0
U
U
U
U
/RESET and WDT
0
0
0
0
P
P
P
P
0
0
0
0
P
P
P
P
P67
P66
P65
P64
P63
P62
P61
P60
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
Bit Name
0x06
P6
Wake-Up from Pin
Change
Bit Name
0x0F
RF(ISR)
X
X
X
X
X
EXIF
ICIF
TCIF
Power-On
U
U
U
U
U
0
0
0
/RESET and WDT
U
U
U
U
U
0
0
0
U
U
U
U
U
P
P
P
-
-
-
-
-
-
-
-
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
Bit Name
0x0A
18 •
IOCA
**0/P **0/P **0/P **0/P **1/P **0/P **0/P **0/P
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Address
0x0B
Name
IOCB
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
/PD7
/PD6
/PD5
Power-On
1
1
1
/PD4
X
/PD2
/PD1
/PD0
1
U
1
1
1
/RESET and WDT
1
1
1
1
U
1
1
1
P
P
P
P
U
P
P
P
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
WDTE
EIS
X
ROC
X
X
X
X
Power-On
1
0
U
0
U
U
U
U
/RESET and WDT
1
0
U
0
U
U
U
U
1
P
U
P
U
U
U
U
Wake-Up from Pin
Change
Bit Name
0x0C
IOCC
Wake-Up from Pin
Change
Bit Name
0x0D
IOCD
Wake-Up from Pin
Change
Bit Name
0x0E
0x0F
IOCE
IOCF
Wake-Up from Pin
Change
Bit Name
X
X
X
X
X
EXIE
ICIE
TCIE
Power-On
U
U
U
U
U
0
0
0
/RESET and WDT
U
U
U
U
U
0
0
0
U
U
U
U
U
P
P
P
-
-
-
-
-
-
-
-
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Wake-Up from Pin
Change
Bit Name
0x10~0x2F
R10~R2F
** To jump address 0x08, or to execute the instruction which is next to the “SLEP”
instruction.
X: Not used. U: Unknown or don’t care. P: Previous value before reset. t: Check
Table 6
4.5.2 The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition,
2. A high-low-high pulse on /RESET pin, and
3. Watchdog timer time-out.
The values of T and P, listed in Table 6 are used to check how the processor wakes up.
Table 7 shows the events that may affect the status of T and P.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 19
EM78156E
8-Bit Microcontroller with MASK ROM
Table 6 The Values of RST, T and P after RESET
Reset Type
Power on
/RESET during Operating mode
/RESET wake-up during SLEEP mode
WDT during Operating mode
WDT wake-up during SLEEP mode
Wake-Up on pin change during SLEEP mode
T
P
1
1
*P
*P
1
0
0
1
0
*P
0
0
*P: Previous status before reset
Table 7 The Status of T and P Being Affected by Events.
T
P
Power on
Event
1
1
WDTC instruction
1
1
WDT time-out
0
*P
SLEP instruction
1
0
Wake-Up on pin change during SLEEP mode
1
0
*P: Previous value before reset
VDD
D
CLK
O scillator
Q
CLK
CLR
Power-on
R eset
V oltage
D etector
W DTE
WDT
W D T T im eout
Setup T im e
R E SE T
/R E SE T
Fig. 9 Block Diagram of Controller Reset
4.6 Interrupt
The EM78156E has three falling-edge interrupts listed below:
(1) TCC overflow interrupt
(2) Port 6 Input Status Change Interrupt
(3) External interrupt [(P60, /INT) pin].
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV
R6,R6") is necessary. Each pin of Port 6 will have this feature if its status changed.
20 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Any pin configured as output or P60 pin configured as /INT is excluded from this
function. The Port 6 Input Status Changed Interrupt can wake up the EM78156E from
the sleep mode if Port 6 is enabled prior to going into the sleep mode by executing
SLEP. When the chip wakes-up, the controller will continue to execute the succeeding
address if the global interrupt is disabled or branch to the interrupt vector 008H if the
global interrupt is enabled.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Fig. 10). The RETI instruction ends the interrupt
routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from address 001H.
VCC
D
/IRQn
P
R
CLK
C
L
Q
IRQn
INT
_
Q
RFRD
IRQm
RF
ENI/DISI
IOCF
Q
P
R
_
Q
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Fig. 10 Interrupt Input Circuit
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 21
EM78156E
8-Bit Microcontroller with MASK ROM
4.7 Oscillator
4.7.1 Oscillator Modes
The EM78156E can be operated in three different oscillator modes, such as External
RC oscillator mode (ERC), High XTAL oscillator mode(HXT), and Low XTAL oscillator
mode(LXT). User can select one of them by programming MS and HLF in the CODE
option register. Table 8 depicts how these three modes are defined.
The up-most limited operation frequency of crystal/resonator on the different VDDs is
listed in Table 9.
Table 8 Oscillator Modes Defined by MS and HLP
Mode
MS
HLF
ERC(External RC oscillator mode)
0
*X
HXT(High XTAL oscillator mode)
1
1
LXT(Low XTAL oscillator mode)
1
0
NOTE
1. X, Don’t care
2. The transient point of system frequency between HXT and LXY is around 400 KHz.
Table 9 The Summary of Maximum Operating Speeds
Conditions
Two cycles with two clocks
VDD
Fxt max.(MHz)
2.3
4.0
3.0
8.0
5.0
20.0
4.7.2 .Crystal Oscillator/Ceramic Resonators(XTAL)
EM78156E can be driven by an external clock signal through the OSCI pin as shown in
Fig. 11 below.
OSCI
Ext. Clock
OSCO
EM78156E
Fig. 11 Circuit for External Clock Input
22 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
In the most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Fig. 12 depicts such circuit. The same thing
applies whether it is in the HXT mode or in the LXT mode. Table 10 provides the
recommended values of C1 and C2. Since each resonator has its own attribute, user
should refer to its specification for appropriate values of C1 and C2. RS, a serial
resistor, may be necessary for AT strip cut crystal or low frequency mode.
C1
OSCI
EM78156E
XTAL
OSCO
C2
RS
Fig. 12 Circuit for Crystal/Resonator
Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Frequency
C1(pF)
C2(pF)
455 kHz
100~150
100~150
Ceramic Resonators
HXT
2.0 MHz
20~40
20~40
LXT
Crystal Oscillator
HXT
4.0 MHz
10~30
10~30
32.768kHz
25
15
100KHz
25
25
200KHz
455KHz
1.0MHz
25
20~40
15~30
25
20~150
15~30
2.0MHz
15
15
4.0MHz
15
15
4.7.3 External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC
oscillator (Fig. 15) offers a lot of cost savings. Nevertheless, it should be noted that the
frequency of the RC oscillator is influenced by the supply voltage, the values of the
resistor (Rext), the capacitor (Cext), and even by the operation temperature.
Moreover, the frequency also changes slightly from one chip to another due to the
manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they
cannot be kept in this range, the frequency is easily affected by noise, humidity, and
leakage.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 23
EM78156E
8-Bit Microcontroller with MASK ROM
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is layout, will affect the system frequency.
Vcc
Rext
OSCI
Cext
EM78156E
Fig. 13 Circuit for External RC Oscillator Mode
Table 11 RC Oscillator Frequencies
Cext
Rext
Average Fosc
5V,25°C
Average Fosc
3V,25°C
20 pF
3.3k
5.1k
10k
100k
3.92 MHz
2.67 MHz
1.39 MHz
149 KHz
3.65 MHz
2.60 MHz
1.40 MHz
156 KHz
100 pF
3.3k
5.1k
10k
100k
1.39 MHz
940 KHz
480 KHz
52 KHz
1.33 MHz
920 KHz
475 KHz
50 KHz
300 pF
3.3k
5.1k
10k
100k
595 KHz
400 KHz
200 KHz
21 KHz
560 KHz
390 KHz
200 KHz
20 KHz
NOTE
1. Measured on DIP packages.
2. For design reference only.
3. The frequency drift is about ±30%
24 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
4.8 CODE Option Register
The EM78156E has a CODE option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
LVDD
CLK
/ENWDT
HLF
MS
-
Bit 0 (LVDD):
Levels of the Operating Voltage.
0: Operating Voltage 2.3V ~ 5.5V, non-power saving.
1: Operating Voltage 4V ~ 5.5V, power saving.
Bit 1 (CLK):
Instruction period option bit.
0: two oscillator periods.
1: four oscillator periods.
Refer to the section on Instruction Set.
Bit 2 (/ENWDT): Watchdog timer enable bit.
0: Enable
1: Disable
Bit 3 (HLF):
XTAL frequency selection
0: XTAL2 type (low frequency, 32.768KHz)
1: XTAL1 type (high frequency)
This bit will affect system oscillation only when Bit4(MS) is “1”. When MS is”0”, HLF
must be “0”.
NOTE
The transient point of system frequency between HXT and LXY is around 400 KHz.
Bit 4 (MS):
Oscillator type selection.
0: RC type
1: XTAL type (XTAL1 and XTAL2)
Bit 5:
Reserved.
The bit is set to “1” all the time.
4.9 Power On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stays at its steady state.
EM78156E POR voltage range is 1.2V~1.8V. Under customer application, when
power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power
can be switched ON again. This way, the EM78156E will reset and work normally. The
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 25
EM78156E
8-Bit Microcontroller with MASK ROM
extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or
less). However, under most cases where critical applications are involved, extra
devices are required to assist in solving the power-up problems.
4.10 External Power On Reset Circuit
The circuit shown in Fig.16 implements an external RC to produce the reset pulse. The
pulse width (time constant) should be kept long enough for Vdd to reached minimum
operation voltage. This circuit is used when the power supply has slow rise time.
Because the current leakage from the /RESET pin is about ±5µA, it is recommended
that R should not be greater than 40 K. In this way, the /RESET pin voltage is held
below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent
high current or ESD (electrostatic discharge) from flowing to pin /RESET.
Vdd
R
/RESET
D
EM78156E
Rin
C
Fig. 14 External Power-Up Reset Circuit
4.11 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage remains.
The residue-voltage may trips below Vdd minimum, but not to zero. This condition may
cause a poor power on reset. Fig.17 and Fig.18 show how to build a residue-voltage
protection circuit.
Vdd
Vdd
33K
EM78156E
Q1
10K
/RESET
40K
1N4684
Fig. 15 Circuit 1 for the Residue Voltage Protection
26 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Vdd
Vdd
R1
EM78156E
Q1
/RESET
40K
R2
Fig. 16 Circuit 2 for the Residue Voltage Protection
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the
execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ", "DJZA") commands which were tested to be true, are executed within
two instruction cycles. The instructions that are written to the program counter also
take two instruction cycles.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/ 2 as
shown in Fig. 5.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 27
EM78156E
8-Bit Microcontroller with MASK ROM
The symbol "R" represents a register designator that specifies which one of the
registers (including operational registers and general purpose registers) is to be utilized
by the instruction. "b" represents a bit field designator that selects the value for the bit
which is located in the register "R", and affects operation. "k" represents an 8 or 10-bit
constant or literal value.
INSTRUCTION BINARY
HEX
MNEMONIC
0000
0001
0010
0011
0100
rrrr
0000
0001
0010
0000
0001
0002
0003
0004
000r
0010
0011
0012
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
0 0000 0001 0011
0013
RETI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0014
001r
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
0
0
28 •
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001 0100
0001 rrrr
01rr rrrr
1000 0000
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
STATUS
AFFECTED
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC, Enable
Interrupt
CONT → A
IOCR → A
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A∨R→A
A∨R→R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
None
C
None
T,P
T,P
None <Note1>
None
None
None
None
None
None <Note1>
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
INSTRUCTION BINARY
HEX
MNEMONIC
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 00kk kkkk kkkk
1kkk
CALL k
1
1
1
1
1
kkkk
kkkk
kkkk
kkkk
kkkk
1kkk
18kk
19kk
1Akk
1Bkk
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
1 1100 kkkk kkkk
1Ckk
RETL k
1 1101 kkkk kkkk
1Dkk
SUB A,k
1 1110 0000 0001
1E01
INT
1 1111 kkkk kkkk
1Fkk
ADD A,k
0
0
0
0
0
0
0
0111
0111
0111
100b
101b
110b
111b
01kk
1000
1001
1010
1011
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
kkkk
kkkk
kkkk
kkkk
kkkk
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
OPERATION
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A,
[Top of Stack] → PC
k-A → A
PC+1 → [SP],
001H → PC
k+A → A
STATUS
AFFECTED
None
None
None
None <Note2>
None <Note3>
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
Z,C,DC
NOTE
This instruction is applicable to IOC5~IOC6, IOCB~IOCF only.
This instruction is not recommended for RF operation.
This instruction cannot operate under RF.
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 29
EM78156E
8-Bit Microcontroller with MASK ROM
4.13 Timing Diagrams
AC Test Input/Output Waveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
30 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
5
ABSOLUTE MAXIMUNM RATINGS
Items
6
Rating
Temperature under bias
0°C to 70°C
Storage temperature
-65°C to 150°C
Input voltage
Vss-0.3V to Vdd+0.5V
Output voltage
Vss-0.3V to Vdd+0.5V
ELECTRICAL CHARACTERISTICS
6.1 DC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
FXT
ERC
Parameter
Condition
8.0
MHz
XTAL: VDD to 5V
Two cycle with two clocks
DC
20.0
MHz
F±30%
KHz
±1
µA
VIN = VDD, VSS
VIH1
Input High Voltage (VDD=5V)
Ports 5, 6
VIL1
Ports 5, 6
VIHX1
Input Low Voltage (VDD=5V)
Input High Threshold Voltage
(VDD=5V)
Input Low Threshold Voltage
(VDD=5V)
Clock Input High Voltage (VDD=5V)
VILX1
Clock Input Low Voltage (VDD=5V)
OSCI
VIH2
Input High Voltage (VDD=3V)
Ports 5, 6
VIL2
Input Low Voltage (VDD=3V)
Input High Threshold Voltage
(VDD=3V)
Input Low Threshold Voltage
(VDD=3V)
Clock Input High Voltage (VDD=3V)
Ports 5, 6
VIHT2
VILT2
VIHX2
Unit
DC
Input Leakage Current for input pins
VILT1
Max
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
VIHT1
Typ.
XTAL: VDD to 3V
ERC: VDD to 5V
IIL
Min
/RESET,TCC(Schmitt trigger)
F±30% 940
2.0
V
0.8
2.0
V
/RESET,TCC(Schmitt trigger)
OSCI
/RESET,TCC(Schmitt trigger)
0.8
3.5
V
V
1.5
1.5
V
V
0.4
1.5
V
V
/RESET,TCC(Schmitt trigger)
OSCI
V
0.4
2.1
V
V
VILX2
Clock Input Low Voltage (VDD=3V)
OSCI
VOH1
Output High Voltage (Ports 5)
Output High Voltage (Ports 6)
(Schmitt trigger)
Output Low Voltage(Port5)
Output Low Voltage (Ports 6)
(Schmitt trigger)
IOH = -12.0 mA
2.4
V
IOH = -12.0 mA
2.4
V
VOH1
VOL1
VOL1
IPH
Pull-high current
IPD
Pull-down current
ISB1
Power down current
ISB2
Power down current
0.9
V
IOL = 12.0 mA
0.4
V
IOL = 12.0 mA
0.4
V
Pull-high active, input pin at
VSS
Pull-down active, input pin at
VDD
All input and I/O pins at VDD,
output pin floating, WDT
disabled
All input and I/O pins at VDD,
output pin floating, WDT
enabled
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
-50
-70
-240
µA
25
50
120
µA
1
2
µA
10
µA
• 31
EM78156E
8-Bit Microcontroller with MASK ROM
Symbol
Parameter
ICC1
Operating supply current
(VDD=3V)
at two cycles/four clocks
ICC2
Operating supply current
(VDD=3V)
at two cycles/four clocks
ICC3
Operating supply current
(VDD=5.0V)
at two cycles/two clocks
ICC4
Operating supply current
(VDD=5.0V)
at two cycles/four clocks
Condition
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
disabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
enabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
Min
Typ.
Max
Unit
15
15
30
µA
20
35
µA
2.0
mA
4.0
mA
6.2 AC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Dclk
Input CLK duty cycle
Tins
Instruction cycle time
(CLKS="0")
Conditions
Min
Typ
Max
Unit
45
50
55
%
Crystal type
100
DC
ns
RC type
500
DC
ns
21.8
ms
Ttcc
TCC input period
Tdrh
Device reset hold time
Ta = 25°C
11.8
Trst
/RESET pulse width
Ta = 25°C
2000
Twdt
Watchdog timer period
Ta = 25°C
11.8
ns
(Tins+20)/N*
16.8
ns
16.8
21.8
ms
Tset
Input pin setup time
0
ns
Thold
Input pin hold time
20
ns
Tdelay
Output pin delay time
50
ns
Cload=20pF
* N= selected prescaler ratio.
32 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
6.3 Device Characteristic
The graphs provided in the following pages were derived based on a limited number of
samples and are shown here for reference only. The device characteristic illustrated
herein are not guaranteed for it accuracy. In some graphs, the data maybe out of the
specified warranted operating range.
Vih/Vil (Input pins with schmitt inverter)
2.5
Vih max (0℃ to 70℃)
Vih typ 25℃
Vih min (0℃ to 70℃)
Vih Vil(Volt)
2
1.5
1
Vil max (0℃ to 70℃)
Vil typ 25℃
Vil min (0℃ to 70℃)
0.5
0
2.5
3
3.5
4
4.5
5
5.5
Vdd(Volt)
Fig. 17 Vih, Vil of Port6 vs. VDD
Vth (Input thershold voltage) of I/O pins
1.8
1.6
1.4
Typ 25℃
Max(0℃ to 70℃)
Vth(Volt)
1.2
1
Min(0℃ to 70℃)
0.8
0.6
0.4
0.2
0
2.5
3
3.5
4
4.5
5
5.5
VDD(Volt)
Fig. 18 Vth (Threshold voltage) of Port5 vs. VDD
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 33
EM78156E
8-Bit Microcontroller with MASK ROM
Voh/Ioh (VDD=5V)
Voh/Ioh (VDD=3V)
0
0
-5
-2
Min 70℃
-10
-4
Ioh(mA)
Ioh(mA)
Min 70℃
Typ 25℃
-15
Typ 25℃
-6
Min 0℃
Min 0℃
-20
-8
-25
-10
0
1
2
3
4
5
Voh(Volt)
Fig. 19 Port5 and Port6 Voh vs. Ioh, DD=5V
34 •
0
0.5
1
1.5
2
2.5
3
Voh(Volt)
Fig. 20 Port5 and Port6 Voh vs. Ioh, VDD=3V
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Vol/Iol (VDD=5V)
Vol/Iol (VDD=3V)
35
80
Max 0℃
Max 0℃
70
30
Typ 25℃
60
Typ 25℃
25
Min 70℃
Iol(mA)
Iol(mA)
50
40
30
20
20
Min 70℃
15
10
10
5
0
0
1
2
3
4
5
Vol(Volt)
0
0
0.5
1
1.5
2
2.5
3
Vol(Volt)
Fig. 22 Port5, Port6 Vol vs. Iol, VDD = 3V
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
Fig. 21 Port5, Port6 Vol vs. Iol, VDD = 5V
• 35
EM78156E
8-Bit Microcontroller with MASK ROM
WDT Time_ o u t
40
35
30
WDT period (mS)
Max 70℃
25
Typ 25℃
20
Min 0℃
15
10
5
0
2
3
4
5
6
VDD (Volt)
Fig. 23 WDT time out period vs. VDD,perscaler set to 1:1
36 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Cext = 100pF, Typical RC Frequency vs. VDD
1.8
R = 3.3K
1.6
Frequency(M Hz)
1.4
1.2
R = 5.1K
1
0.8
R = 10K
0.6
0.4
0.2
R = 100K
0
2.5
3
3.5
4
4.5
5
5.5
VDD(Volt)
Fig. 24 Typical RC OSC Frequency vs. VDD (Cext= 100pF, Temperature at 25℃)
VDD = 5V
VDD = 3V
Fig. 25 Typical RC OSC Frequency vs. VDD (R and C are ideal components)
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 37
EM78156E
8-Bit Microcontroller with MASK ROM
Four conditions exist with the Operating Current ICC1 to ICC4. These conditions are
as follows:
ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disable
ICC2: VDD=3V, Fosc=32K Hz, 2 clocks, WDT enable
ICC3: VDD=5V, Fosc=4M Hz, 2 clocks, WDT enable
ICC4: VDD=5V, Fosc=10M Hz, 2 clocks, WDT enable
Typical ICC1 and ICC2 vs. Temperature
15
Current (uA)
14
13
Typ ICC2
12
Typ ICC1
11
10
9
0
10
20
30
40
50
60
70
Temperature (℃)
Fig. 26 Typical operating current (ICC1 and ICC2) vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
23
22
Current (uA)
21
20
19
Max ICC2
18
Max ICC1
17
16
15
0
10
20
30
40
50
60
70
Temperature (℃)
Fig. 27 Maximum operating current (ICC1 and ICC2) vs. Temperature
38 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Typical ICC3 and ICC4 vs. Temperature
4
Current (mA)
3.5
Typ ICC4
3
2.5
2
Typ ICC3
1.5
1
0.5
0
0
10
20
30
40
50
60
70
Temperature (℃)
Fig. 28 Typical operating current (ICC3 and ICC4) vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
4.5
Max ICC4
Current (mA)
4
3.5
3
2.5
Max ICC3
2
1.5
1
0
10
20
30
40
50
60
70
Temperature (℃)
Fig. 29 Maximum operating current (ICC3 and ICC4) vs. Temperature
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 39
EM78156E
8-Bit Microcontroller with MASK ROM
Two conditions exist with the Standby Current ISB1 and ISB2. These conditions are as
follows:
ISB1: VDD=5V, WDT disable
ISB2: VDD=5V, WDT enable
Typical ISB1 and ISB2 vs. Temperature
10
Current (uA)
8
Typ ISB2
6
4
2
Typ ISB1
0
0
10
20
30
40
50
60
70
Temperature (℃)
Fig. 30 Typical standby current (ISB1 and ISB2) vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
Current (uA)
10
Max ISB2
8
6
4
Max ISB1
2
0
0
10
20
30
40
50
60
70
Temperature (℃)
Fig. 31 Maximum standby current (ISB1 and ISB2) vs. Temperature
40 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
Fig. 32 Operating voltage in temperature range from 0℃ to 70℃
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 41
EM78156E
8-Bit Microcontroller with MASK ROM
EM78156E-J HXT V-I
2.5
2.25
2
1.75
I(mA)
1.5
1.25
1
0.75
0.5
0.25
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 33 Operating current range (based on high Freq. @ =25℃) vs. Voltage
EM78156E-J LXT V-I
70
60
I(uA)
50
40
30
20
10
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 34 Operating current range (based on low Freq. @ =25℃) vs. Voltage
42 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
EM78156E
8-Bit Microcontroller with MASK ROM
APPENDIX
A Package Types
MASK MCU
Package Type
Pin Count
Package Size
EM78156EP
EM78156EM
EM78156EAS
EM78156EKM
DIP
SOP
SSOP
SSOP
18
18
20
20
300 mil
300 mil
209 mil
209 mil
B Package Information
18-Lead Plastic Dual in line (PDIP) — 300 mil
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
• 43
EM78156E
8-Bit Microcontroller with MASK ROM
18-Lead Plastic Small Outline (SOP) — 300 mil
20-Lead Plastic Small Outline (SSOP) — 209 mil
44 •
Product Specification (V1.3) 07.29.2004
(This specification is subject to change without further notice)
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