AD ADSP-BF538BBCZ-4F4 Blackfin embedded processor Datasheet

Blackfin®
Embedded Processor
ADSP-BF538/ADSP-BF538F
a
Preliminary Technical Data
FEATURES
Memory management unit providing memory protection
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI® and external
memory
Up to 500 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of programming and compiler friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core VDD with on-chip voltage regulation
3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package
PERIPHERALS
Parallel peripheral interface (PPI/GPIO)
supporting ITU-R 656 video data formats
Four dual-channel, full-duplex synchronous serial ports, supporting 16 stereo I2S® channels
Two DMA controllers supporting 26 DMA channels
Controller area network (CAN) 2.0B controller
Three SPI-compatible ports
Three timer/counters with PWM support
Three UARTs with support for IrDA®
Two TWI controllers compatible with I2C® industry standard
Up to 54 general-purpose I/O pins (GPIO)
Real time clock, watchdog timer, and core timer
On-chip PLL capable of 0.5x To 64x frequency multiplication
Debug/JTAG interface
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K bytes or 1M byte of flash memory (ADSP-BF538F parts
only)
Four dual-channel memory DMA controllers
GPIO
PORT
C
GPIO
PORT
D
GPIO
PORT
E
CAN 2.0B
PERIPHERAL ACCESS BUS
TWI0-1
B
L1
INSTRUCTION
MEMORY
GPIO
SPI1-2
DMA ACCESS
BUS 1
INTERRUPT
CONTROLLER
L1
DATA
MEMORY
WATCHDOG
TIMER
RTC
PPI
TIMER0-2
DMA CORE
BUS 1
DMA CORE
BUS 0
DMA ACCESS
BUS 0
UART1-2
SPORT2-3
PERIPHERAL ACCESS BUS
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
DMA
CONTROLLER1
EXTERNAL PORT
FLASH, SDRAM CONTROL
DMA
EXTERNAL
BUS 1
512 KB OR 1 MB
FLASH MEMORY
DMA
CONTROLLER0
DMA
EXTERNAL
BUS 0
GPIO
PORT
F
SPI0
UART0
SPORT0-1
BOOT ROM
(ADSP-BF538F ONLY)
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrD
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However, no responsibility is assumed by Analog Devices for its use, nor for any
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Fax: 781.461.3113
© 2006 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
TABLE OF CONTENTS
Operating Conditions ........................................... 22
General Description ................................................. 3
Operating Conditions—Applies to 5V Tolerant pins .... 22
Low Power Architecture ......................................... 3
Electrical Characteristics ....................................... 22
System Integration ................................................ 3
Absolute Maximum Ratings ................................... 23
ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3
Package Information ............................................ 23
Blackfin Processor Core .......................................... 4
ESD Sensitivity ................................................... 23
Memory Architecture ............................................ 5
Timing Specifications ........................................... 24
DMA Controllers .................................................. 8
Clock and Reset Timing ..................................... 24
Real Time Clock ................................................... 9
Asynchronous Memory Read Cycle Timing ............ 25
Watchdog Timer .................................................. 9
Asynchronous Memory Write Cycle Timing ........... 27
Timers ............................................................... 9
SDRAM Interface Timing .................................. 29
Serial Ports (SPORTs) .......................................... 10
External Port Bus Request and Grant Cycle Timing .. 30
Serial Peripheral Interface (SPI) Ports ...................... 10
Parallel Peripheral Interface Timing ...................... 32
Two Wire Interface ............................................. 10
Serial Port Timing ............................................ 35
UART Ports ...................................................... 10
Serial Peripheral Interface Port—Master Timing ...... 39
General-Purpose Ports ......................................... 11
Serial Peripheral Interface Port—Slave Timing ........ 40
Parallel Peripheral Interface ................................... 11
General-Purpose Port Timing ............................. 41
Controller Area Network (CAN) Interface ................ 12
Timer Cycle Timing .......................................... 42
Dynamic Power Management ................................ 12
JTAG Test And Emulation Port Timing ................. 43
Voltage Regulation .............................................. 14
Output Drive Currents ......................................... 44
Clock Signals ..................................................... 14
Power Dissipation ............................................... 46
Booting Modes ................................................... 15
Test Conditions .................................................. 46
Instruction Set Description ................................... 15
Thermal Characteristics ........................................ 50
Development Tools ............................................. 16
316-Ball Mini-BGA Pinout ....................................... 51
Designing an Emulator Compatible Processor Board ... 17
Outline Dimensions ................................................ 54
Voltage Regulator Layout Guidelines ....................... 17
Surface Mount Design .......................................... 55
Pin Descriptions .................................................... 18
Ordering Guide ..................................................... 55
Specifications ........................................................ 22
REVISION HISTORY
5/06—Revision PrD:
For this revision, the following sections were changed.
Functional Block Diagram ......................................... 1
Booting Modes ...................................................... 15
Pin Descriptions .................................................... 18
Output Drive Currents ............................................ 44
Power Dissipation .................................................. 46
Test Conditions ..................................................... 46
316-Ball Mini-BGA Pinout ....................................... 51
Rev. PrD |
Page 2 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
GENERAL DESCRIPTION
The ADSP-BF538/ADSP-BF538F processors are members of
the Blackfin family of products, incorporating the Analog
Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing
engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data
(SIMD) multimedia capabilities into a single instruction set
architecture.
The ADSP-BF538/ADSP-BF538F processors are completely
code compatible with other Blackfin processors, differing only
with respect to performance, peripherals, and on-chip memory.
Specific performance, peripherals, and memory configurations
are shown in Table 1.
ADSP-BF538F8
ADSP-BF538
Feature
ADSP-BF538F4
Table 1. Processor Features
Maximum Performance
500 MHz 1000 MMACs
Instruction SRAM/Cache
16 K bytes
Instruction SRAM
64 K bytes
Data SRAM/Cache
32 K bytes
Data SRAM
32 K bytes
Scratchpad
4 K bytes
Flash
NA
4
SPIs
3
TWIs (connection to I2C
compatible devices)
2
UARTs
3
CAN
1
PPI
1
Package Option
The ADSP-BF538/ADSP-BF538F processors are highly integrated system-on-a-chip solution for the next generation of
consumer and industrial applications including audio and video
signal processing. By combining advanced memory configurations, such as on-chip flash memory, with industry-standard
interfaces with a high performance signal processing core, users
can develop cost-effective solutions quickly without the need for
costly external components. The system peripherals include
three UART ports, three SPI ports, four serial ports (SPORT),
one CAN interface, 2 two wire interfaces (TWI), four generalpurpose timers (three with PWM capability), a real-time clock, a
watchdog timer, a parallel peripheral interface, general-purpose
I/O, and general-purpose I/O pins.
The ADSP-BF538/ADSP-BF538F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see the block diagram
on Page 1). The general-purpose peripherals include functions
such as UART, Timers with PWM (pulse width modulation)
and pulse measurement capability, general-purpose I/O pins, a
real time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is
augmented by the system expansion capabilities of the device. In
addition to these general-purpose peripherals, the
ADSP-BF538/ADSP-BF538F processors contain high speed
serial and parallel ports for interfacing to a variety of audio,
video, and modem codec functions. A CAN 2.0B controller is
provided for automotive control networks. An interrupt controller manages interrupts from the on-chip peripherals or
external sources. Power management control functions tailor
the performance and power characteristics of the processors
and system to many application scenarios.
See Ordering Guide on Page 55
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like programmability, multimedia support and leading edge signal
processing in one integrated package.
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and
performance. Blackfin processors are designed in a low power
and low voltage design methodology and feature dynamic
power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
Rev. PrD |
SYSTEM INTEGRATION
ADSP-BF538/ADSP-BF538F PROCESSOR
PERIPHERALS
512 K bytes 1 M byte
SPORTs
substantial reduction in power consumption, compared with
just varying the frequency of operation. This translates into
longer battery life and lower heat dissipation.
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real time clock, and timers, are supported by a flexible
DMA structure. There are also two separate memory DMA controllers dedicated to data transfers between the processor's
various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to
133 MHz provide enough bandwidth to keep the processor core
running along with activity on all of the on-chip and external
peripherals.
The ADSP-BF538/ADSP-BF538F processors include an on-chip
voltage regulator in support of the ADSP-BF538/ADSP-BF538F
processor’s dynamic power management capability. The voltage
regulator provides a range of core voltage levels from a single
2.25 V to 3.6 V input. The voltage regulator can be bypassed at
the user's discretion.
Page 3 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
BLACKFIN PROCESSOR CORE
bit and 8-bit adds with clipping, 8-bit average operations, and 8bit subtract/absolute value/accumulate (SAA) operations. Also
provided are the compare/select and vector search instructions.
As shown in Figure 2 on Page 4, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register
file.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations, 16-
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C style indexed stack
manipulation).
ADDRESS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
P1
P0
I3
L3
B3
M3
I2
I1
I0
L2
L1
L0
B2
B1
B0
M2
M1
M0
DAG0
DAG1
SEQUENCER
ALIGN
DECODE
LD0 32 BITS
LD1 32 BITS
SD 32 BITS
R7
R6
R5
R4
R7.H
R6.H
R5.H
R4.H
R7.L
R6.L
R5.L
R4.L
R3 R3.H
R3.L
R2 R2.H
R1 R1.H
R2.L
R1.L
R0 R0.H
R0.L
LOOP BUFFER
16
16
8
8
BARREL
SHIFTER
8
8
40
A0
40
A1
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Rev. PrD |
Page 4 of 56 |
May 2006
CONTROL
UNIT
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
RESERVED
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Management Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
0xFFA0 8000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTE)
0xFF90 4000
The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
RESERVED
INTERNAL MEMORY MAP
SCRATCHPAD SRAM (4K BYTE)
0xFFB0 0000
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTE)
0xFF80 4000
RESERVED
0xEF00 0000
RESERVED
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF538/ADSP-BF538F processors view memory as a
single unified 4 Gbyte address space, using 32-bit addresses. All
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip
memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132 Mbytes of physical
memory.
The memory DMA controllers provide high bandwidth data
movement capability. They can perform block transfers of code
or data between the internal memory and the external memory
spaces.
Rev. PrD |
ASYNC MEMORY BANK 3 (1M BYTE) OR
ON-CHIP FLASH
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE) OR
ON-CHIP FLASH
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE) OR
ON-CHIP FLASH
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE) OR
ON-CHIP FLASH
0x2000 0000
EXTERNAL MEMORY MAP
0x2040 0000
RESERVED
0x0800 0000
SDRAM MEMORY (16M BYTE - 128M BYTE)
0x0000 0000
Figure 3. ADSP-BF538/ADSP-BF538F Internal/External Memory Map
Internal (On-chip) Memory
The ADSP-BF538/ADSP-BF538F processors have three blocks
of on-chip memory providing high bandwidth access to the
core.
The first is the L1 instruction memory, consisting of 80 Kbytes
SRAM, of which 16 Kbytes can be configured as a four way setassociative cache. This memory is accessed at full processor
speed.
The second on-chip memory block is the L1 data memory, consisting of two banks of up to 32 Kbytes each. Each memory bank
is configurable, offering both two-way set-associative cache and
SRAM functionality. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
Page 5 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128 Mbytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
When connected to AMS3–1 the flash memory will appear as
non-volatile memory in the processor memory map shown in
Figure 3 on Page 5.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1 Mbyte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully populated with 1 Mbyte of memory.
The ADSP-BF538F4 and ADSP-BF538F8 flash memory may be
programmed before or after mounting on the printed circuit
board.
Flash Memory Programming
To program the flash prior to mounting on the printed circuit
board, use a hardware programming tool that can provide the
data, address, and control stimuli to the flash die through the
external pins on the package. During this programming, VDDEXT
and GND must be provided to the package and the Blackfin
must be held in reset with bus request (BR) asserted and a
CLKIN provided.
Flash Memory
The ADSP-BF538F4 and ADSP-BF538F8 processors contain a
separate flash die, connected to the EBIU bus, within the package of the processors. Figure 4 on Page 6 shows how the flash
memory die and Blackfin processor die are connected.
The VisualDSP++® tools may be used to program the flash
memory after the device is mounted on a printed circuit board.
ADDR19-1
ARE
AWE
ARDY
DATA15-0
To use the sector protection feature, a high voltage (+12 V nominal) must be applied to the flash FRESET pin. Refer to the flash
datasheet for details.
A18-0
OE
WE
RY/BY
DQ15-0
VSS
VCC
BYTE
CE
RESET
GND
VDDEXT
AMS3-0
RESET
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the
4 Gbyte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Flash die
Blackfin die
ADDR19-1
ARE
AWE
ARDY
DATA15-0
GND
VDDEXT
Flash Memory Sector Protection
FCE
FRESET
RESET
AMS3-0
ADSP-BF538Fx
package
Booting
The ADSP-BF538/ADSP-BF538F processors contain a small
boot kernel, which configures the appropriate peripheral for
booting. If the processors are configured to boot from boot
ROM memory space, the processors start executing from the
on-chip boot ROM. For more information, see Booting Modes
on Page 15.
Figure 4. Internal Connection of Flash Memory (ADSP-BF538Fx)
The ADSP-BF538F4 contains a 512 Kbits bottom boot sector
flash memory. The ADSP-BF538F8 contains a 1 Mbit bottom
boot sector flash memory. Features include the following.
• access times as fast as 70 ns (EBIU registers must be set
appropriately)
Event Handling
The Blackfin processor connects to the flash memory die with
address, data, chip enable, write enable, and output enable controls as if it were an external memory device.
The event controller on the ADSP-BF538/ADSP-BF538F processors handle all asynchronous and synchronous events to the
processors. The processor provides event handling that supports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller
provides support for five different types of events:
The flash chip enable pin FCE must be connected to AMS0 or
AMS3–1 through a printed circuit board trace. When connected
to AMS0 the Blackfin processor can boot from the flash die.
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• sector protection
• one million write cycles per sector
• 20 year data retention
• Reset – This event resets the processor.
Rev. PrD |
Page 6 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
• Non-maskable interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
support the peripherals of the processor. Table 2 describes the
inputs to the CEC, identifies their names in the event vector
table (EVT), and lists their priorities.
• Exceptions – Events that occur synchronously to program
flow (the exception are taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
The system interrupt controllers (SIC0, SIC1) provide the mapping and routing of events from the many peripheral interrupt
sources to the prioritized general-purpose interrupt inputs of
the CEC. Although the ADSP-BF538/ADSP-BF538F processors
provide a default mapping, the user can alter the mappings and
priorities of interrupt events by writing the appropriate values
into the interrupt assignment registers (IAR). Table 3 describes
the inputs into the SICs and the default mappings into the CEC.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processors are saved on the
supervisor stack.
The ADSP-BF538/ADSP-BF538F processor’s event controllers
consist of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). the core event controller
works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
0
Event Class
Emulation/Test Control
EVT Entry
EMU
1
Reset
RST
2
Non-Maskable Interrupt
NMI
3
Exception
EVX
4
Reserved
—
5
Hardware Error
IVHW
6
Core Timer
IVTMR
7
General Interrupt 7
IVG7
8
General Interrupt 8
IVG8
9
General Interrupt 9
IVG9
10
General Interrupt 10
IVG10
11
General Interrupt 11
IVG11
12
General Interrupt 12
IVG12
13
General Interrupt 13
IVG13
14
General Interrupt 14
IVG14
15
General Interrupt 15
IVG15
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
Rev. PrD |
System Interrupt Controllers (SIC)
Table 3. System and Core Event Mapping
Event Source
Core
Event Name
PLL Wakeup Interrupt
IVG7
DMA Controller 0 Error
IVG7
DMA Controller 1 Error
IVG7
PPI Error Interrupt
IVG7
SPORT0 Error Interrupt
IVG7
SPORT1 Error Interrupt
IVG7
SPORT2 Error Interrupt
IVG7
SPORT3 Error Interrupt
IVG7
SPI0 Error Interrupt
IVG7
SPI1 Error Interrupt
IVG7
SPI2 Error Interrupt
IVG7
UART0 Error Interrupt
IVG7
UART1 Error Interrupt
IVG7
UART2 Error Interrupt
IVG7
CAN Error Interrupt
IVG7
Real Time Clock Interrupts
IVG8
DMA0 Interrupt (PPI)
IVG8
DMA1 Interrupt (SPORT0 RX)
IVG9
DMA2 Interrupt (SPORT0 TX)
IVG9
DMA3 Interrupt (SPORT1 RX)
IVG9
DMA4 Interrupt (SPORT1 TX)
IVG9
DMA8 Interrupt (SPORT2 RX)
IVG9
DMA9 Interrupt (SPORT2 TX)
IVG9
DMA10 Interrupt (SPORT3 RX)
IVG9
DMA11 Interrupt (SPORT3 TX)
IVG9
DMA5 Interrupt (SPI0)
IVG10
DMA14 Interrupt (SPI1)
IVG10
DMA15 Interrupt (SPI2)
IVG10
DMA6 Interrupt (UART0 RX)
IVG10
DMA7 Interrupt (UART0 TX)
IVG10
DMA16 Interrupt (UART1 RX)
IVG10
DMA17 Interrupt (UART1 TX)
IVG10
Page 7 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
• SIC interrupt mask registers (SIC_IMASKx)– These registers control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servicing the event.
Table 3. System and Core Event Mapping (Continued)
Event Source
Core
Event Name
DMA18 Interrupt (UART2 RX)
IVG10
DMA19 Interrupt (UART2 TX)
IVG10
Timer0, Timer1, Timer2 Interrupts
IVG11
TWI0 Interrupt
IVG11
TWI1 Interrupt
IVG11
CAN Receive Interrupt
IVG11
CAN Transmit Interrupt
IVG11
Port F GPIO Interrupts A and B
IVG12
MDMA0 Stream 0 Interrupt
IVG13
MDMA0 Stream 1 Interrupt
IVG13
MDMA1 Stream 0 Interrupt
IVG13
MDMA1 Stream 1 Interrupt
IVG13
Software Watchdog Timer
IVG13
• SIC interrupt status registers (SIC_ISRx) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.
• SIC interrupt wakeup enable registers (SIC_IWRx) – By
enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the
core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 12.)
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
Event Control
The ADSP-BF538/ADSP-BF538F processors provide the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 16 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corresponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
Rev. PrD |
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF538/ADSP-BF538F processors have multiple,
independent DMA controllers that support automated data
transfers with minimal overhead for the processor core. DMA
transfers can occur between the processor internal memories
and any of its DMA capable peripherals. Additionally, DMA
transfers can be accomplished between any of the DMA capable
peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller and the
asynchronous memory controller. DMA capable peripherals
include the SPORTs, SPI port, UART, and PPI. Each individual
DMA capable peripheral has at least one dedicated DMA
channel.
The DMA controllers support both 1-dimensional (1D) and 2dimensional (2D) DMA transfers. DMA transfer initialization
can be implemented from registers or from sets of parameters
called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
Page 8 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be deinterleaved on the fly.
RTXI
RTXO
R1
Examples of DMA types supported by the processor DMA controller include:
X1
• A single, linear buffer that stops upon completion
C1
C2
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10M OHM
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
four memory DMA channels provided for transfers between the
various memories of the ADSP-BF538/ADSP-BF538F processor’s systems. This enables transfers of blocks of data between
any of the memories—including external SDRAM, ROM,
SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very
flexible descriptor based methodology or by a standard register
based autobuffer mechanism.
REAL TIME CLOCK
The ADSP-BF538/ADSP-BF538F processor’s real time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the processor. The RTC peripheral has dedicated power supply pins so that it can remain
powered up and clocked even when the rest of the processors
are in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute,
hour, or day clock ticks, interrupt on programmable stopwatch
countdown, or interrupt at a programmed alarm time.
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60 second counter, a 60 minute
counter, a 24 hour counter, and an 32,768 day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the ADSPBF538/ADSP-BF538F processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup
event can wake up the processor from deep sleep mode, and
wake up the on-chip internal voltage regulator from a powered
down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 5.
Rev. PrD |
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
Figure 5. External Components for RTC
WATCHDOG TIMER
The ADSP-BF538/ADSP-BF538F processors include a 32-bit
timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by
forcing the processor to a known state through generation of a
hardware reset, non-maskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by
software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF538/ADSP-BF538F processors. Three timers have
an external pin that can be configured either as a pulse width
modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an
external clock input to the PF1 pin, an external clock input to
the PPI_CLK pin, or to the internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
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In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
SERIAL PORTS (SPORTs)
The ADSP-BF538/ADSP-BF538F processors incorporate four
dual-channel synchronous serial ports for serial and multiprocessor communications. The SPORTs support the following
features:
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most significant bit
first or least significant bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability – Each SPORT supports 128 channels out of a 1024 channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF538/ADSP-BF538F processors incorporate three
SPI compatible ports that enable the processor to communicate
with multiple SPI compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSIx, and master input-slave
output, MISOx) and a clock pin (serial clock, SCKx). An SPI
chip select input pin (SPIxSS) lets other SPI devices select the
Rev. PrD |
processor. For SPI0, seven SPI chip select output pins
(SPI0SEL7–1) let the processor select other SPI devices. The SPI
select pins are reconfigured GPIO pins. SPI1 and SPI2 have a
single SPI select for SPI point-to-point communication. Using
these pins, the SPI ports provide a full-duplex, synchronous
serial interface, which supports both master/slave modes and
multimaster environments.
The SPI ports’ baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. Each
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
f SCLK
SPI Clock Rate = --------------------------------------2 × SPIx_BAUD
Where the 16-bit SPIx_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
TWO WIRE INTERFACE
The ADSP-BF538/ADSP-BF538F processors have 2 two wire
interface (TWI) modules that are compatible with the Philips
Inter-IC bus standard. The TWI modules offer the capabilities
of simultaneous master and slave operation, support for 7-bit
addressing and multimedia data arbitration. The TWI also
includes master clock synchronization and support for clock
low extension.
The TWI interface uses two pins for transferring clock (SCLx)
and data (SDAx) and supports the protocol at speeds up to
400 kbits/sec.
The TWI interface pins are compatible with 5V logic levels.
UART PORTs
The ADSP-BF538/ADSP-BF538F processors incorporate three
full-duplex Universal Asynchronous Receiver/Transmitter
(UART) ports, which are fully compatible with PC standard
UARTs. The UART ports provide a simplified UART interface
to other peripherals or hosts, supporting full-duplex, DMA supported, asynchronous transfers of serial data. The UART ports
include support for 5 to 8 data bits, 1 or 2 stop bits, and none,
even, or odd parity. The UART ports support two modes of
operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
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Preliminary Technical Data
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DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.
• Flag interrupt sensitivity registers – The two flag interrupt
sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
Table 4. GPIO Ports
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = ----------------------------------------------16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions, autobaud detection is supported.
The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) Serial Infrared
Physical Layer Link Specification (SIR) protocol.
GENERAL-PURPOSE PORTS
The ADSP-BF538/ADSP-BF538F processors have up to 54 general-purpose I/O pins that are multiplexed with other
peripherals. They are arranged into ports C, D, E, and F as
shown in Table 4.
The general-purpose I/O pins may be individually controlled by
manipulation of the control and status registers. These pins may
be polled to determine their status.
• GPIO direction control register – Specifies the direction of
each individual GPIOx pin as input or output.
• GPIO control and status registers – The processor employs
a “write one to modify” mechanism that allows any combination of individual GPIO to be modified in a single
instruction, without affecting the level of any other GPIO.
Four control registers and a data register are provided for
each GPIO port. One register is written in order to set
GPIO values, one register is written in order to clear GPIO
values, one register is written in order to toggle GPIO values, and one register is written in order to specify a GPIO
input or output. Reading the GPIO Data allows software to
determine the state of the input GPIO pins.
In addition to the GPIO function described above, the 16 port F
pins can be individually configured to generate interrupts.
• Flag interrupt mask registers – The two Flag interrupt
mask registers allow each individual PFx pin to function as
an interrupt to the processor. similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as
Rev. PrD |
Peripheral
Alternate GPIO Port Function
PPI
GPIO Port F15–0
SPORT2
GPIO Port E7–0
SPORT3
GPIO Port E15–8
SPI1
GPIO Port D4–0
SPI2
GPIO Port D9–5
UART1
GPIO Port D11–10
UART2
GPIO Port D13–12
CAN
GPIO Port C1–0
GPIO
GPIO Port C9–4
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF538/ADSP-BF538F processors provide a parallel
peripheral interface (PPI) that can connect directly to parallel
A/D and D/A converters, video encoders and decoders, and
other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and
at up to 16 data pins. The input clock supports parallel data rates
at up to fSCLK/2 MHz, and the synchronization signals can be configured as either inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bi-directional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bi-directional transfer of 8- or 10-bit video data. Additionally, on-chip
decode of embedded start-of-line (SOL) and start-of-field (SOF)
preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
• Input mode – frame syncs and data are inputs into the PPI.
• Frame capture mode – frame syncs are outputs from the
PPI, but data are inputs.
• Output mode – frame syncs and data are outputs from the
PPI.
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Input Mode
CONTROLLER AREA NETWORK (CAN) INTERFACE
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_Count register. Data widths of 8-bits, and 10-bits through
16-bits are supported, and are programmed using the
PPI_CONTROL register.
The ADSP-BF538/ADSP-BF538F processors provide a CAN
controller that is a communication controller implementing the
Controller Area Network (CAN) V2.0B protocol. This protocol
is an asynchronous communications protocol used in both
industrial and automotive control systems. CAN is well suited
for control applications due to its capability to communicate
reliably over a network since the protocol incorporates CRC
checking message error tracking, and fault node confinement.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The ADSP-BF538/ADSP-BF538F processors control when to read from the video source(s). PPI_FS1
is an HSYNC output and PPI_FS2 is a VSYNC output.
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hardware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applications. Three distinct submodes are supported:
• Active video only mode
• Vertical blanking only mode
• Entire field mode
Active Video Only Mode
Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_Count register).
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
Rev. PrD |
The CAN controller is based on a 32 entry mailbox RAM and
supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification,
revision 2.0, part B.
Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the network. If the identifier in the transmitted message matches an
identifier in one of it's mailboxes, then the module knows that
the message was meant for it, passes the data into it's appropriate mailbox, and signals the processor of message arrival with an
interrupt.
The CAN controller can wake up the processor from sleep mode
upon generation of a wakeup event, such that the processor can
be maintained in a low power mode during idle conditions.
Additionally, a CAN wakeup event can wake up the processor
from deep sleep, and wake up the on-chip internal voltage regulator from a powered-down state.
The electrical characteristics of each network connection are
very stringent, therefore the CAN interface is typically divided
into 2 parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF538/ADSP-BF538F CAN module represents the controller part of the interface. This module's network I/O is a
single transmit output and a single receive input, which connect
to a line transceiver.
The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF538/ADSP-BF538F processors provide five operating modes, each with a different performance/power profile.
In addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 5 for a summary of the power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the powerup default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
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Preliminary Technical Data
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Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Table 5. Power Settings
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation.
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
preserved. Since VDDEXT is still supplied in this mode, all of the
external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up either by a real time
clock wakeup, by CAN bus traffic, by asserting the RESET pin
or by an external source.
Power Savings
Core
Clock
(CCLK)
System
Clock
(SCLK)
Core
Power
Mode
PLL
PLL
Bypassed
Full On
Enabled
No
Enabled
Enabled
On
Active
Enabled/
Disabled
Yes
Enabled
Enabled
On
Sleep
Enabled
Disabled Enabled
On
Deep Sleep Disabled
Disabled Disabled On
Hibernate
Disabled Disabled Off
Disabled
As shown in Table 6, the ADSP-BF538/ADSP-BF538F processors support three different power domains. The use of multiple
power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating
the internal logic of the processor into its own power domain,
separate from the RTC and other I/O, the processor can take
advantage of Dynamic Power Management, without affecting
the RTC or other I/O devices. There are no sequencing requirements for the various power domains.
Table 6. Power Domains
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the
processor. When in the Sleep mode, assertion of wakeup causes
the processor to sense the value of the BYPASS bit in the PLL
control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full on mode. If BYPASS is enabled, the
processor will transition to the Active mode. When in the sleep
mode, system DMA access to L1 memory is not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running, but will not be able to
access internal resources or external memory. This powered
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the processor to transition to the Full On mode.
Hibernate Operating Mode—Maximum Static Power
Savings
VDD Range
RTC crystal I/O and logic
VDDRTC
All internal logic except RTC
VDDINT
All I/O except RTC
VDDEXT
The power dissipated by a processors are largely a function of
the clock frequency of the processors and the square of the operating voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in power dissipation, while reducing
the voltage by 25% reduces power dissipation by more than
40%. Further, these power savings are additive, in that if the
clock frequency and supply voltage are both reduced, the power
savings can be dramatic.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
Power Savings Factor
f CCLKRED
V DDINTRED 2
T RED
= -------------------------- × ⎛ --------------------------------⎞ × ⎛ --------------- ⎞
⎝ T NOM ⎠
f CCLKNOM ⎝ V DDINTNOM⎠
where the variables in the equations are:
The hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
Rev. PrD |
Power Domain
• fCCLKNOM is the nominal core clock frequency
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
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May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
• VDDINTRED is the reduced internal supply voltage
Alternatively, because the ADSP-BF538/ADSP-BF538F processors include an on-chip oscillator circuit, an external crystal
may be used. The crystal should be connected across the CLKIN
and XTAL pins, with two capacitors connected as shown in
Figure 7. Capacitor values are dependent on crystal type and
should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal
should be used.
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The Power Savings Factor is calculated as:
% Power Savings = ( 1 – Power Savings Factor ) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.8 V to
1.2V(–5%/+10%) from an external 2.7 V to 3.6 V supply.
Figure 6 shows the typical external components required to
complete the power management system.† The regulator controls the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while I/O power (VDDRTC, VDDEXT) is still supplied.
While in hibernate mode, I/O power is still being applied, eliminating the need for external buffers. The voltage regulator can
be activated from this power-down state either through an RTC
wakeup, a CAN wakeup, a general-purpose wakeup, or by
asserting RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user’s
discretion.
10 µH
VDDINT
0.1 µF
100 µF
1 µF
CLKOUT
BLACKFIN
PROCESSOR
Figure 7. External Crystal Connections
As shown in Figure 8 on Page 14, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1× to 63× multiplication factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the
PLL_DIV register.
VDDEXT
100 µF
XTAL
CLKIN
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
2.25V - 3.6V
INPUT VOLTAGE
RANGE
“COURSE” ADJUSTMENT
ON-THE-F LY
FDS9431A
CLKIN
ZHCS1000
PLL
0.5x - 64x
ⴜ 1, 2, 4, 8
CCLK
ⴜ 1:15
SCLK
VCO
VROUT1-0
SCLK ≤ CCLK
SCLK ≤ 133 MHz
EXTERNAL COMPONENTS
NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
Figure 8. Frequency Modification Methods
Figure 6. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF538/ADSP-BF538F processors can be clocked by
an external crystal, a sine wave input, or a buffered, shaped
clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
†
See EE-228: Switching Regulator Design Considerations for ADSP-BF533
Blackfin Processors.
Rev. PrD |
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios:
Table 7. Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios (MHz)
SSEL3–0
VCO/SCLK
VCO
SCLK
0001
1:1
0110
6:1
300
50
1010
10:1
500
50
Page 14 of 56 |
May 2006
100
100
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. This programmable core clock capability is useful for
fast core frequency modifications.
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
VCO
CCLK
00
1:1
300
300
01
2:1
300
150
10
4:1
500
125
11
8:1
200
25
BOOTING MODES
The ADSP-BF538/ADSP-BF538F processors have three mechanisms (listed in Table 9) for automatically loading internal L1
instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.
Table 9. Booting Modes
BMODE1–0 Description
00
Execute from 16-bit external memory
(bypass boot ROM)
01
Boot from 8-bit or 16-bit flash (ADSP-BF538 only) or
Boot from on board flash (ADSP-BF538F only)
10
Boot from SPI serial master
11
Boot from SPI serial slave EEPROM /flash
(8-,16-, or 24-bit address range, or Atmel
AT45DB041, AT45DB081, or AT45DB161serial flash)
The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The 8-bit
flash boot routine located in boot ROM memory space is
set up using asynchronous memory bank 0. If FCE is connected to AMS0, then the on-chip flash is booted from the
Rev. PrD |
ADSP-BF538F. All configuration settings are set for the
slowest device possible (3-cycle hold time; 15-cycle R/W
access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) – The SPI uses the PF2 output pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-, or
24-bit, or Atmel addressable device is detected, and begins
clocking data into the processor at the beginning of L1
instruction memory.
• Boot from SPI host device – The Blackfin processor operates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is chosen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
To augment the boot modes, a secondary software loader is provided that adds additional booting mechanisms. This secondary
loader provides the capability to boot from 16-bit flash memory,
fast flash, variable baud rate, and other sources. In all boot
modes except bypass, program execution starts from on-chip L1
memory address 0xFFA0 0000.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
Page 15 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• View mixed C/C++ and assembly code (interleaved source
and object information).
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.
• Insert breakpoints.
• All registers, I/O, and memory are mapped into a unified
4 Gbyte memory space, providing a simplified programming model.
• Trace instruction execution.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Fill, dump, and graphically plot the contents of memory.
• Set conditional breakpoints on registers, memory,
and stacks.
• Perform linear or statistical profiling of program execution.
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
The ADSP-BF538/ADSP-BF538F processors are supported with
a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and
VisualDSP++® development environment. The same emulator
hardware that supports other Blackfin processors also fully
emulates the ADSP-BF538/ADSP-BF538F processors.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processors have architectural features that improve the efficiency of
compiled C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll
the processors as they are running the program. This feature,
unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without
interrupting the real time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly
and efficiently. By using the profiler, the programmer can focus
on those areas in the program that impact performance and take
corrective action.
Rev. PrD |
• Perform source level debugging.
• Create custom debugger windows.
The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphical and textual environments.
Analog Devices emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-BF538/ADSP-BF538F processors to
monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing
Page 16 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
inspection and modification of memory, registers, and processor stacks. Non intrusive in-circuit emulation is assured by the
use of the processor’s JTAG interface—the emulator does not
affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real time operating
systems, and block diagram design tools.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
erence on the Analog Devices web site (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
VOLTAGE REGULATOR LAYOUT GUIDELINES
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1-0 traces
and voltage regulator external components should be considered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the ADSPBF538/ADSP-BF538F processors as possible.
For further details on the on-chip voltage regulator and related
board design guidelines, see the EE-228: Switching Regulator
Design Considerations for ADSP-BF533 Blackfin Processors
applications note on the Analog Devices web site (www.analog.com)—use site search on “EE-228.”.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, nonintrusive emulation.
DESIGNING AN EMULATOR COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see EE-68: Analog Devices JTAG Emulation Technical Ref-
Rev. PrD |
Page 17 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
PIN DESCRIPTIONS
ADSP-BF538/ADSP-BF538F processor pin definitions are listed
in Table 10. In order to maintain maximum functionality and
reduce package size and pin count, some pins have dual, multi-
plexed functionality. In cases where pin functionality is
reconfigurable, the default state is shown in plain text, while
alternate functionality is shown in italics.
Table 10. Pin Descriptions
Pin Name
I/O
Function
Driver Type
Memory Interface
ADDR19–1
O
Address Bus for Async/Sync Access
A
DATA15–0
I/O
Data Bus for Async/Sync Access
A
ABE1–0/SDQM1–0
O
Byte Enables/Data Masks for Async/Sync Access
A
BR
I
Bus Request (This pin should be pulled HIGH when not used.)
BG
O
Bus Grant
A
BGH
O
Bus Grant Hang
A
AMS3–0
O
Bank Select
A
ARDY
I
Hardware Ready Control (This pin should always be pulled LOW when not used.)
AOE
O
Output Enable
A
ARE
O
Read Enable
A
AWE
O
Write Enable
A
FCE
I
Flash Enable (This pin should be left unconnected if not used.)
FRESET
I
Flash Reset (This pin should be left unconnected if not used.)
SRAS
O
Row Address Strobe
A
SCAS
O
Column Address Strobe
A
SWE
O
Write Enable
A
SCKE
O
Clock Enable
A
CLKOUT
O
Clock Output
B
SA10
O
A10 Pin
A
SMS
O
Bank Select
A
Asynchronous Memory Control
Flash Control
Synchronous Memory Control
Timers
TMR0
I/O
Timer 0
C
TMR1/PPI_FS1
I/O
Timer 1/PPI Frame Sync1
C
TMR2/PPI_FS2
I/O
Timer 2/PPI Frame Sync2
C
2
Two Wire Interface Port (These pins are open drain and require a pullup resistor. See version 2.1 of the I C specification for
proper resistor values.)
SDA0
I/O 5V
TWI0 Serial Data
E
SCL0
I/O 5V
TWI0 Serial Clock
E
SDA1
I/O 5V
TWI1 Serial Data
E
SCL1
I/O 5V
TWI1 Serial Clock
E
Rev. PrD |
Page 18 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 10. Pin Descriptions (Continued)
Pin Name
I/O
Function
Driver Type
Serial Port0
RSCLK0
I/O
SPORT0 Receive Serial Clock
D
RFS0
I/O
SPORT0 Receive Frame Sync
C
DR0PRI
I
SPORT0 Receive Data Primary
DR0SEC
I
SPORT0 Receive Data Secondary
TSCLK0
I/O
SPORT0 Transmit Serial Clock
D
TFS0
I/O
SPORT0 Transmit Frame Sync
C
DT0PRI
O
SPORT0 Transmit Data Primary
C
DT0SEC
O
SPORT0 Transmit Data Secondary
C
RSCLK1
I/O
SPORT1 Receive Serial Clock
D
RFS1
I/O
SPORT1 Receive Frame Sync
C
DR1PRI
I
SPORT1 Receive Data Primary
DR1SEC
I
SPORT1 Receive Data Secondary
TSCLK1
I/O
SPORT1 Transmit Serial Clock
D
TFS1
I/O
SPORT1 Transmit Frame Sync
C
DT1PRI
O
SPORT1 Transmit Data Primary
C
DT1SEC
O
SPORT1 Transmit Data Secondary
C
MOSI0
I/O
SPI0 Master Out Slave In
C
MISO0
I/O
SPI0 Master In Slave Out (This pin should always be pulled HIGH through a 4.7 C
KΩ resistor if booting via the SPI port.)
SCK0
I/O
SPI0 Clock
RX0
I
UART Receive
TX0
O
UART Transmit
C
PPI3–0
I/O
PPI3–0
C
PPI_CLK
I
PPI Clock
Serial Port1
SPI0 Port
D
UART0 Port
PPI Port
Port C: Controller Area Network/GPIO
CANTX/PC0
I/O 5V
CAN Transmit/GPIO
C
CANRX/PC1
I/O 5V
CAN Receive/GPIO
C
PC[9:4]
I/O
GPIO
Port D: SPI1/SPI2/UART1/UART2/GPIO
MOSI1/PD0
I/O
SPI1 Master Out Slave In/GPIO
C
MISO1/PD1
I/O
SPI1 Master In Slave Out/GPIO
C
SCK1/PD2
I/O
SPI1 Clock/GPIO
D
SPI1SS/PD3
I/O
SPI1 Slave Select Input/GPIO
C
SPI1SEL/PD4
I/O
SPI1 Slave Select Enable/GPIO
C
MOSI2/PD5
I/O
SPI2 Master Out Slave In/GPIO
C
MISO2/PD6
I/O
SPI2 Master In Slave Out/GPIO
C
Rev. PrD |
Page 19 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 10. Pin Descriptions (Continued)
Pin Name
I/O
Function
Driver Type
SCK2/PD7
I/O
SPI2 Clock/GPIO
D
SPI2SS/PD8
I/O
SPI2 Slave Select Input/GPIO
C
SPI2SEL/PD9
I/O
SPI2 Slave Select Enable/GPIO
C
RX1/PD10
I/O
UART1 Receive/GPIO
C
TX1/PD11
I/O
UART1 Transmit/GPIO
C
RX2/PD12
I/O
UART2 Receive/GPIO
C
TX2/PD13
I/O
UART2 Transmit/GPIO
C
RSCLK2/PE0
I/O
SPORT2 Receive Serial Clock/GPIO
D
RFS2/PE1
I/O
SPORT2 Receive Frame Sync/GPIO
C
DR2PRI /PE2
I/O
SPORT2 Receive Data Primary/GPIO
C
DR2SEC/PE3
I/O
SPORT2 Receive Data Secondary/GPIO
C
TSCLK2/PE4
I/O
SPORT2 Transmit Serial Clock/GPIO
D
Port E: SPORT2/SPORT3/GPIO
TFS2/PE5
I/O
SPORT2 Transmit Frame Sync/GPIO
C
DT2PRI/PE6
I/O
SPORT2 Transmit Data Primary/GPIO
C
DT2SEC/PE7
I/O
SPORT2 Transmit Data Secondary/GPIO
C
RSCLK3/PE8
I/O
SPORT3 Receive Serial Clock/GPIO
D
RFS3/PE9
I/O
SPORT3 Receive Frame Sync/GPIO
C
DR3PRI/PE10
I/O
SPORT3 Receive Data Primary/GPIO
C
DR3SEC/PE11
I/O
SPORT3 Receive Data Secondary/GPIO
C
TSCLK3/PE12
I/O
SPORT3 Transmit Serial Clock/GPIO
D
TFS3/PE13
I/O
SPORT3 Transmit Frame Sync/GPIO
C
DT3PRI/PE14
I/O
SPORT3 Transmit Data Primary/GPIO
C
DT3SEC/PE15
I/O
SPORT3 Transmit Data Secondary/GPIO
C
Port F: Parallel Peripheral Interface Port/SPI0/Timers/GPIO
SPI0SS/PF0
I/O
SPI Slave Select Input/GPIO
C
SPI0SEL1/TMRCLK/PF1
I/O
SPI Slave Select Enable 1/External Timer Reference/GPIO
C
SPI0SEL2/PF2
I/O
SPI Slave Select Enable 2/GPIO
C
PPI_FS3/SPI0SEL3/PF3
I/O
PPI Frame Sync 3/SPI Slave Select Enable 3/GPIO
C
PPI15/SPI0SEL4/PF4
I/O
PPI 15/SPI Slave Select Enable 4/GPIO
C
PPI14/SPI0SEL5/PF5
I/O
PPI 14/SPI Slave Select Enable 5/GPIO
C
PPI13/SPI0SEL6/PF6
I/O
PPI 13/SPI Slave Select Enable 6/GPIO
C
PPI12/SPI0SEL7/PF7
I/O
PPI 12/SPI Slave Select Enable 7/GPIO
C
PPI11/PF8
I/O
PPI 11/GPIO
C
PPI10/PF9
I/O
PPI 10/GPIO
C
PPI9/PF10
I/O
PPI 9/GPIO
C
PPI8/PF11
I/O
PPI 8/GPIO
C
PPI7/PF12
I/O
PPI 7/GPIO
C
PPI6/PF13
I/O
PPI 6/GPIO
C
PPI5/PF14
I/O
PPI 5/GPIO
C
PPI4/PF15
I/O
PPI 4/GPIO
C
Rev. PrD |
Page 20 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 10. Pin Descriptions (Continued)
Pin Name
I/O
Function
Driver Type
RTXI
I
RTC Crystal Input
RTXO
O
RTC Crystal Output
TCK
I
JTAG Clock
TDO
O
JTAG Serial Data Out
TDI
I
JTAG Serial Data In
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This pin should be pulled LOW if the JTAG port will not be used.)
EMU
O
Emulation Output
CLKIN
I
Clock/Crystal Input
XTAL
O
Crystal Output
RESET
I
Reset
NMI
I
Non-maskable Interrupt (This pin should be pulled HIGH when not used.)
BMODE1–0
I
Boot Mode Strap
VROUT0
O
External FET Drive 0
VROUT1
O
External FET Drive 1
GPW
I/O
General-purpose regulator wakeup (This pin should be pulled HIGH when not
used)
VDDEXT
P
I/O Power Supply
VDDINT
P
Internal Power Supply
Real Time Clock
JTAG Port
C
C
Clock
Mode Controls
Voltage Regulator
Supplies
VDDRTC
P
Real Time Clock Power Supply
GND
G
Ground
Rev. PrD |
Page 21 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter1
Min
Nominal
Max
Unit
VDDINT
Internal Supply Voltage
0.8
1.2
1.32
V
VDDEXT
External Supply Voltage
2.25
3.3
3.6
V
VDDRTC
Real Time Clock Power Supply Voltage
2.25
3.6
V
VIH
High Level Input Voltage2, @ VDDEXT =maximum
2.0
3.6
V
VIHCLKIN
High Level Input Voltage3, @ VDDEXT =maximum
2.2
3.6
V
VIL
Low Level Input Voltage2, 4, @ VDDEXT =minimum
–0.3
0.6
V
1
Specifications subject to change without notice.
The 3.3 V tolerant pins are capable of accepting up to 3.6 V maximum VIH The following bi-directional pins are 3.3 V tolerant: DATA15–0, MISO0, MOSI0, PF15–0, PPI3–0,
SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2, RFS2,
TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, SCK0, TFS0, TFS1, and TMR2–0. The following
input-only pins are 3.3 V tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY, BMODE1–0, BR, DR0PRI, DR0SEC, DR1PRI, DR1SEC, NMI, PPI_CLK, RTXI, and GP.
3
Parameter value applies to the CLKIN pins.
4
Parameter value applies to all input and bi-directional pins.
2
OPERATING CONDITIONS—APPLIES TO 5V TOLERANT PINS
Parameter1
Min
Max
Unit
VIH5V2
High Level Input Voltage, @ VDDEXT =maximum
2.0
5.5
V
Low Level Input Voltage, @ VDDEXT =minimum
–0.3
0.8
V
2
VIL5V
Nominal
1
Specifications subject to change without notice.
2
The 5.V tolerant pins are capable of accepting up to 5.5 V maximum VIH. The following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, CANRX, CANTX.
ELECTRICAL CHARACTERISTICS
Parameter1
VOH
High Level Output Voltage2
VOL
Low Level Output Voltage
IIH
High Level Input Current3
2
4
Test Conditions
Min
@ VDDEXT =3.0V, IOH = –0.5 mA
2.4
Max
Unit
V
@ VDDEXT =3.0V, IOL = 2.0 mA
0.4
V
@ VDDEXT =maximum, VIN = VDD maximum
TBD
μA
IIL
Low Level Input Current
@ VDDEXT =maximum, VIN = 0 V
TBD
μA
IOZH
Three-State Leakage Current4
@ VDDEXT = maximum, VIN = VDD maximum
10
μA
IOZL
Three-State Leakage Current5
@ VDDEXT = maximum, VIN = 0 V
10
μA
CIN
Input Capacitance5, 6
fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
TBD
pF
1
Specifications subject to change without notice.
Applies to output and bidirectional pins.
3
Applies to input pins.
4
Applies to three-statable pins.
5
Applies to all signal pins.
6
Guaranteed, but not tested.
2
Rev. PrD |
Page 22 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
The information presented in Figure 9 and Table 12 provides
information about how to read the package brand and relate it
to specific product features. For a complete listing of product
offerings, see the Ordering Guide on Page 55.
Parameter
Internal (Core) Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Input Voltage1
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Junction Temperature Under bias
1
Rating
–0.3 V to +1.4 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to +5.5 V
–0.5 V to VDDEXT +0.5 V
200 pF
–65°C to +150°C
+125°C
The 5.V tolerant pins are capable of accepting up to 5.5 V maximum VIH. The
following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1,
CANRX, CANTX. For other duty cycles, see Table 11.
Table 11. Maximum Duty Cycle for Input1 Transient Voltage
VIN Max (V)2
3.63
3.80
3.90
4.00
4.10
4.20
4.30
1
2
VIN Min (V)
–0.33
–0.50
–0.60
–0.70
–0.80
–0.90
–1.00
Maximum Duty Cycle
100%
48%
30%
20%
10%
8%
5%
a
ADSP-BF5xx
tppZccc
vvvvvv.x n.n
yyww country_of_origin
B
Figure 9. Product Information on Package
Table 12. Package Brand Information
Brand Key
t
pp
Z
ccc
vvvvvv.x
n.n
yyww
Field Description
Temperature Range
Package Type
Lead Free Option (optional)
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
Applies to all signal pins with the exception of CLKIN, XTAL, and VROUT1–0.
Only one of the listed options can apply to a particular design.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF538/ADSP-BF538F processors feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD |
Page 23 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
TIMING SPECIFICATIONS
Table 13 describes the timing requirements for the ADSPBF538/ADSP-BF538F processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock, system clock and Voltage Controlled Oscillator
(VCO) operating frequencies, as described in Absolute Maximum Ratings on Page 23. Table 14 describes Phase Locked
Loop operating conditions.
Table 13. Core and System Clock Requirements—ADSP-BF538/ADSP-BF538F—500 MHz
Parameter
Min
Max
Unit
fCCLK
Core Clock Frequency (VDDINT = 1.2 V minimum)
500
MHz
fCCLK
Core Clock Frequency (VDDINT = 1.045 V minimum)
444
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.95 V minimum)
400
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.85 V minimum)
333
MHz
Min
Max
Unit
50
Max CCLK
MHz
Table 14. Phase Locked Loop Operating Conditions
Parameter
fVCO
Voltage Controlled Oscillator (VCO) Frequency
Clock and Reset Timing
Table 15 and Figure 10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 23, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 500/133 MHz.
Table 15. Clock and Reset Timing
Parameter
Min
Max
Unit
100.0
ns
Timing Requirements
tCKIN
CLKIN Period
20.0
tCKINL
CLKIN Low Pulse1
8.0
ns
8.0
ns
11 tCKIN
ns
1
tCKINH
CLKIN High Pulse
tWRST
RESET Asserted Pulsewidth Low2
1
2
Applies to bypass mode and non-bypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH
tWRST
RESET
Figure 10. Clock and Reset Timing
Rev. PrD |
Page 24 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Asynchronous Memory Read Cycle Timing
Table 16 and Table 17 on Page 26 and Figure 11 and Figure 12
on Page 26 describe asynchronous memory read cycle operations for synchronous and for asynchronous ARDY.
Table 16. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
0.8
ns
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
TBD
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
TBD
ns
tDO
Output Delay After CLKOUT
tHO
1
1
Output Hold After CLKOUT
2.1
ns
1
6.0
ns
0.8
ns
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tSARDY
tHARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. PrD |
Page 25 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 17. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
ns
tHDAT
DATA15–0 Hold After CLKOUT
0.8
ns
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT2
1
2
ns
(S + RA – 2) × tSCLK
0.0
2
ns
6.0
ns
0.8
ns
S = number of programmed setup cycles, RA = number of programmed read access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROG RAM M ED READ ACCESS
4 CYCLES
HO LD
1 CYCL E
ACCESS EXTENDED
CLK OUT
tD O
tH
AM Sx
ABE 1–0
BE, ADDRESS
ADDR19–1
AOE
tD O
tH O
ARE
tH A A
tD A N R
ARDY
tS D A T
tH D A T
DATA15–0
READ
Figure 12. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. PrD |
Page 26 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Asynchronous Memory Write Cycle Timing
Table 18 and Table 19 on Page 28 and Figure 13 and Figure 14
on Page 28 describe asynchronous memory write cycle operations for synchronous and for asynchronous ARDY.
Table 18. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
TBD
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
TBD
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT1
1
6.0
1.0
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
ACCESS
EXTENDED
1 CYCLE
PROGRAMMED WRITE
ACCESS 2 CYCLES
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t SARDY
ARDY
t SARDY
t ENDAT
DATA15–0
ns
6.0
0.8
t HARD Y
t HARDY
t DDAT
WRITE DATA
Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Rev. PrD |
Page 27 of 56 |
May 2006
ns
ns
ns
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 19. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
(S + WA – 2) × tSCLK
ns
Timing Requirements
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
0.0
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT2
2
1.0
Output Hold After CLKOUT
0.8
S = number of programmed setup cycles, WA = number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
tDANW
tHAA
ARDY
t ENDAT
DATA15–0
WRITE DATA
Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. PrD |
Page 28 of 56 |
May 2006
ns
ns
6.0
2
tHO
1
6.0
ns
ns
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
SDRAM Interface Timing
Table 20. SDRAM Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
2.1
ns
tHSDAT
DATA Hold After CLKOUT
0.8
ns
Switching Characteristics
tSCLK
CLKOUT Period
7.5
ns
tSCLKH
CLKOUT Width High
2.5
ns
tSCLKL
CLKOUT Width Low
2.5
ns
tDCAD
Command, ADDR, Data Delay After CLKOUT
tHCAD
Command, ADDR, Data Hold After CLKOUT1
tDSDAT
Data Disable After CLKOUT
tENSDAT
Data Enable After CLKOUT
1
1
6.0
0.8
ns
6.0
1.0
tSCLKH
CLKOUT
tSSDAT
tSCLKL
t HSDAT
DATA (IN)
tDCAD
tENSDAT
t DCAD
CMND ADDR
(OUT)
t HCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 15. SDRAM Interface Timing
Rev. PrD |
Page 29 of 56 |
tD SDA T
tHCAD
DATA(OUT)
May 2006
ns
ns
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
t SCLK
ns
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
External Port Bus Request and Grant Cycle Timing
Table 21 and Table 22 on Page 31 and Figure 16 and Figure 17
on Page 31 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tBS
BR Setup to Falling Edge of CLKOUT
TBD
ns
tBH
Falling Edge of CLKOUT to BR Deasserted Hold Time
TBD
ns
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
ns
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
4.5
ns
tDBG
CLKOUT High to BG High Setup
3.6
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH High Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 16. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. PrD |
Page 30 of 56 |
May 2006
tEBH
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 22. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tWBR
BR Pulsewidth
2 x tSCLK
ns
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
tSE
tDBG
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH High Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
4.5
ns
CLKOUT Low to xMS, Address, and RD/WR enable
4.5
ns
CLKOUT High to BG High Setup
3.6
ns
CLKOUT
tWBR
BR
tSD
tSE
AMSx
tSD
tSE
ADDR19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 17. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. PrD |
Page 31 of 56 |
May 2006
tEBH
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Parallel Peripheral Interface Timing
Table 23 and Figure 18, Figure 19, Figure 20, and Figure 21
describe Parallel Peripheral Interface operations.
Table 23. Parallel Peripheral Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
PPI_CLK Width
6.0
1
ns
tPCLK
PPI_CLK Period
tSFSPE
External Frame Sync Setup Before PPI_CLK
tHFSPE
External Frame Sync Hold After PPI_CLK
3.0
ns
tSDRPE
Receive Data Setup Before PPI_CLK
2.0
ns
tHDRPE
Receive Data Hold After PPI_CLK
4.0
ns
15.0
ns
3.0
ns
Switching Characteristics — GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
tDDTPE
Transmit Data Delay After PPI_CLK
tHDTPE
Transmit Data Hold After PPI_CLK
1
10.0
0.0
PPI_CLK frequency cannot exceed fSCLK/2
FRAME
SYNC IS
DRIVEN
OUT
DATA0
IS
SAMPLED
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
t
ns
10.0
0.0
DFSPE
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tSDRPE
tHDRPE
PPI_DATA
Figure 18. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. PrD |
Page 32 of 56 |
May 2006
ns
ns
ns
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
FRAME
SYNC IS
SAMPLED
FOR
DATA0
DATA0 IS
SAMPLED
DATA1 IS
SAMPLED
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
tSFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
t
SDRPE
HDRPE
PPI_DATA
Figure 19. PPI GP Rx Mode with External Frame Sync Timing
FRAME
SYNC IS
SAMPLED
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
HFSPE
t
SFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tHDTPE
PPI_DATA
DATA0
tDDTPE
Figure 20. PPI GP Tx Mode with External Frame Sync Timing
Rev. PrD |
Page 33 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
FRAME
SYNC IS
REFERENCED
TO THIS CLOCK
EDGE
DATA0 IS
DRIVEN
OUT
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
t
DFSPE
tHOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
tDDTPE
t
HDTPE
PPI_DATA
DATA0
Figure 21. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. PrD |
Page 34 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Serial Port Timing
Table 24 through Table 27 on Page 36 and Figure 22 on Page 36
through Figure 24 on Page 38 describe Serial Port operations.
Table 24. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
1
3.0
ns
tHFSE
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)
3.0
ns
tSDRE
Receive Data Setup Before RSCLK1
3.0
ns
1
tHDRE
Receive Data Hold After RSCLK
3.0
ns
tSCLKEW
TSCLK/RSCLK Width
4.5
ns
tSCLKE
TSCLK/RSCLK Period
15.0
ns
Switching Characteristics
tDFSE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSE
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tDDTE
Transmit Data Delay After TSCLK
2
tHDTE
Transmit Data Hold After TSCLK2
1
2
10.0
0.0
ns
ns
10.0
0.0
ns
ns
Referenced to sample edge.
Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
8.0
ns
tHFSI
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)1
–2.0
ns
tSDRI
Receive Data Setup Before RSCLK1
6.0
ns
tHDRI
Receive Data Hold After RSCLK1
0.0
ns
tSCLKEW
TSCLK/RSCLK Width
4.5
ns
tSCLKE
TSCLK/RSCLK Period
15.0
ns
Switching Characteristics
tDFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
2
tHOFSI
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
tDDTI
Transmit Data Delay After TSCLK2
tHDTI
Transmit Data Hold After TSCLK
tSCLKIW
TSCLK/RSCLK Width
1
2
3.0
–1.0
ns
3.0
2
ns
ns
–2.0
ns
4.5
ns
Referenced to sample edge.
Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
Min
Max
Unit
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLK1
tDDTTE
Data Disable Delay from External TSCLK
tDTENI
Data Enable Delay from Internal TSCLK1
tDDTTI
Data Disable Delay from Internal TSCLK1
1
0
1
10.0
–2.0
Page 35 of 56 |
May 2006
ns
ns
3.0
Referenced to drive edge.
Rev. PrD |
ns
ns
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 27. External Late Frame Sync
Parameter
Min
Max
Unit
10.0
ns
Switching Characteristics
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
tDDTLFSE
Data Enable from late FS or MCE = 1, MFD = 0
tDTENLFS
1, 2
0
ns
1
MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE.
2
If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
DATA RECEIVE- INTERNAL CLOCK
DATA RECEIVE- EXTERNAL CLOCK
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSE
tDFSE
tHOFSE
tSFSI
tHFSI
tHOFSE
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT- INTERNAL CLOCK
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
tHOFSE
TFS
tSFSE
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDTENI
tDDTTI
DT
Figure 22. Serial Ports
Rev. PrD |
Page 36 of 56 |
May 2006
tHFSE
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tHOFSE/I
tSFSE/I
RFS
tDDTE/I
tDTENLFSE
tHDTE/I
1ST BIT
DT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDTENLFSE
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 23. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. PrD |
Page 37 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I
tHDTE/I
tDTENLSCK
DT
1ST BIT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDTENLSCK
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLSCK
Figure 24. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. PrD |
Page 38 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Port—Master Timing
Table 28 and Figure 25 describe SPI port master operations.
Table 28. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
7.5
ns
tHSPIDM
SCK Sampling Edge to Data Input Invalid
–1.5
ns
Switching Characteristics
tSDSCIM
SPI0SELx Low to First SCK edge (x=0 or 1)
2tSCLK –1.5
ns
tSPICHM
Serial Clock High period
2tSCLK –1.5
ns
tSPICLM
Serial Clock Low period
2tSCLK –1.5
ns
tSPICLK
Serial Clock Period
4tSCLK –1.5
ns
tHDSM
Last SCK Edge to SPI0SELx High (x=0 or 1)
2tSCLK –1.5
ns
tSPITDM
Sequential Transfer Delay
2tSCLK –1.5
ns
tDDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
0
6
ns
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
–1.0
4.0
ns
SPISELx
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
MSB
CPHA=1
tSSPIDM
MISO
(INPUT)
LSB
tHSPIDM
tSSPIDM
MSB VALID
LSB VALID
tDDSPIDM
MOSI
(OUTPUT)
CPHA=0
MISO
(INPUT)
tHSPIDM
tHDSPIDM
MSB
tSSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrD |
Page 39 of 56 |
May 2006
tSPITDM
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Port—Slave Timing
Table 29 and Figure 26 describe SPI port slave operations.
Table 29. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
Serial Clock High Period
2tSCLK –1.5
ns
tSPICLS
Serial Clock low Period
2tSCLK –1.5
ns
tSPICLK
Serial Clock Period
4tSCLK –1.5
ns
tHDS
Last SCK Edge to SPI0SS Not Asserted
2tSCLK –1.5
ns
tSPITDS
Sequential Transfer Delay
2tSCLK –1.5
ns
tSDSCI
SPI0SS Assertion to First SCK Edge
2tSCLK –1.5
ns
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
1.6
ns
tHSPID
SCK Sampling Edge to Data Input Invalid
1.6
ns
Switching Characteristics
tDSOE
SPI0SS Assertion to Data Out Active
tDSDHI
SPI0SS Deassertion to Data High impedance
0
8
ns
tDDSPID
SCK Edge to Data Out Valid (Data Out Delay)
0
10
ns
tHDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
0
10
ns
0
8
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MISO
(OUTPUT)
tSSPID
MOSI
(INPUT)
LSB
tHSPID
tSSPID
tHSPID
MSB VALID
tDSOE
LSB VALID
tDDSPID
tDSDHI
MSB
LSB
tHSPID
CPHA=0
MOSI
(INPUT)
tDSDHI
MSB
CPHA=1
MISO
(OUTPUT)
tDDSPID
tSSPID
MSB VALID
LSB VALID
Figure 26. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrD |
Page 40 of 56 |
May 2006
ns
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
General-Purpose Port Timing
Table 30 and Figure 27 describe general-purpose operations.
Table 30. General-Purpose Port Timing
Parameter
Min
Max
Unit
Timing Requirement
tWFI
GP Port Pin Input Pulse Width
tSCLK + 1
ns
Switching Characteristic
tGPOD
GP Port Pin Output Delay From CLKOUT Low
0
CLKOUT
tGPOD
GPP OUTPUT
tWFI
GPP INPUT
Figure 27. Programmable Flags Cycle Timing
Rev. PrD |
Page 41 of 56 |
May 2006
6
ns
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Timer Cycle Timing
Table 31 and Figure 28 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of fSCLK/2 MHz.
Table 31. Timer Cycle Timing
Parameter
Min
Max
Unit
Timing Characteristics
tWL
Timer Pulsewidth Input Low1 (measured in SCLK cycles)
1
SCLK
tWH
Timer Pulsewidth Input High1 (measured in SCLK cycles)
1
SCLK
Switching Characteristic
Timer Pulsewidth Output2 (measured in SCLK cycles)
tHTO
1
2
1
(232 – 1)
SCLK
The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
tWL
tWH
Figure 28. Timer PWM_OUT Cycle Timing
Rev. PrD |
Page 42 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
JTAG Test And Emulation Port Timing
Table 32 and Figure 29 describe JTAG port operations.
Table 32. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
tSTAP
TDI, TMS Setup Before TCK High
4
ns
tHTAP
TDI, TMS Hold After TCK High
4
ns
tSSYS
System Inputs Setup Before TCK High1
4
ns
1
tHSYS
System Inputs Hold After TCK High
tTRSTW
TRST Pulsewidth2 (measured in TCK cycles)
ns
5
ns
4
TCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
0
1
10
ns
12
ns
System Inputs=ARDY, BMODE1–0, BR, DATA15–0.DR0PRI, DR0SEC, DR1PRI, DR1SEC, MISO0, MOSI0, NMI, PF15–0, PPI_CLK, PPI3–0.SCL0, SCL1, SDA0, SDA1,
SCK, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2,
RFS2, TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RESET, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, RX0,.SCK0, TFS0,
TFS1, and TMR2–0,
2
50 MHz Maximum
3
System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15–0, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MISO0, MOSI0, PF15–0, PPI3–0, SCK1, MISO1, MOSI1, SPI1SS,
SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DR2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, TSCLK3,
DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, CLKOUT, TX0, SA10, SCAS, SCK0, SCKE, SMS, SRAS,
SWE, and TMR2–0.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 29. JTAG Port Timing
Rev. PrD |
Page 43 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
OUTPUT DRIVE CURRENTS
150
120
V D DE XT = 2.25V @ 95°C
100
V D DE XT = 2.50V @ 25°C
SOURCE CURRENT (mA)
80
VD D EX T = 2. 25V @ 95°C
V DD E XT = 2.50V @ 25° C
100
VD DE XT = 2.75V @ -40°C
SOURCE CURRENT (mA)
Figure 30 through Figure 37 on Page 45 shows typical currentvoltage characteristics for the output drivers of the ADSPBF538/ADSP-BF538F processors. The curves represent the current drive capability of the output drivers as a function of output
voltage.
50
V OH
0
-50
V OL
V D DE XT = 2.75V @ -40°C
-100
V OH
-150
60
40
0
20
0.5
1. 0
1.5
2.0
0
3.0
Figure 32. Drive Current B (Low VDDEXT)
-20
-40
V OL
-60
200
-80
V DD E XT = 3.0V @ 95°C
150
-100
0
0.5
1.0
1.5
2.0
100
SOURCE CURRENT (mA)
Figure 30. Drive Current A (Low VDDEXT)
150
VD D EX T = 3.0V @ 95°C
VD D EX T = 3.3V @ 25°C
100
V DD E XT = 3.3V @ 25°C
VD D EX T = 3.6V @ - 40°C
3. 0
2.5
SOURCE VOL TAGE (V)
VD D EX T = 3.6V @ -40°C
SOURCE CURRENT (mA)
2.5
SOURCE VOLTAGE (V)
VO H
50
0
-50
-100
VOL
-150
50
-200
VO H
0
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
Figure 33. Drive Current B (High VDDEXT)
-50
VOL
-100
-150
0
0.5
1.0
1.5
2.0
2.5
3. 0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 31. Drive Current A (High VDDEXT)
Rev. PrD |
Page 44 of 56 |
May 2006
3. 0
3.5
4.0
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
80
150
V D DE XT = 3.0V @ 95° C
V D DE XT = 3.3V @ 25° C
VD D EXT = 2.25V @ 95°C
60
VD D EXT = 2.50V @ 25°C
100
V DD E XT = 3.6V @ -40°C
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
VD D EX T = 2.75V @ -40°C
40
V OH
20
0
-20
VOL
50
VOH
0
-50
V OL
-100
-40
-60
-150
0
0.5
1. 0
1.5
2.0
2.5
0
3.0
0.5
1.0
1.5
Figure 34. Drive Current C (Low VDDEXT)
2.5
3. 0
3.5
4.0
Figure 37. Drive Current D (High VDDEXT)
0
100
VD D EX T = 3. 0V @ 95°C
80
V DD E XT = 2.25V @ 95°C
VD D EX T = 3. 3V @ 25°C
V DD E XT = 3.6V @ -40°C
V DD E XT = 2.50V @ 25°C
VD D EX T = 2.75V @ -40° C
-10
SOURCE CURRENT (mA)
60
SOURCE CURRENT (mA)
2.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
40
VOH
20
0
-20
-40
VO L
-20
-30
V OL
-40
-50
-60
-60
-80
0
0.5
1.0
1.5
2.0
2.5
3. 0
3.5
0
4.0
0.5
1.0
Figure 35. Drive Current C (High VDDEXT)
2.0
2.5
3.0
Figure 38. Drive Current E (Low VDDEXT)
100
0
V D DE XT = 2.25V @ 95°C
80
V D DE XT = 2.50V @ 25°C
-10
VD D EX T = 3.0V @ 95°C
-20
V D D EXT = 3.6V @ -40°C
VD D EX T = 3.3V @ 25°C
SOURCE CURRENT (mA)
VD D E XT = 2.75V @ -40°C
60
SOURCE CURRENT (mA)
1.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
40
VOH
20
0
-20
-40
-30
-40
VOL
-50
-60
V OL
-70
-60
-80
-80
0
0.5
1.0
1.5
2.0
2. 5
3.0
0
SOURCE VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
Figure 36. Drive Current D (Low VDDEXT)
Figure 39. Drive Current E (High VDDEXT)
Rev. PrD |
Page 45 of 56 |
May 2006
3. 0
3.5
4.0
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
POWER DISSIPATION
TEST CONDITIONS
Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 33 through Table 35 show the power
dissipation for internal circuitry (VDDINT).
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 40
shows the measurement point for AC measurements (except
output enable/disable). The measurement point VMEAS is 1.5 V
for VDDEXT (nominal) = 2.5/3.3 V.
See the ADSP-BF53x Blackfin Processor Hardware Reference
Manual for definitions of the various operating -modes and for
instructions on how to minimize system power.
INPUT
OR
OUTPUT
Many operating conditions can affect power dissipation. System
designers should refer to EE-TBD: Estimating Power for
ADSP-BF538/ADSP-BF538F Blackfin Processors.” This document will provide detailed information for optimizing your
design for lowest power.
Table 33. Internal Power Dissipation (Hibernate mode)
IDD (nominal1)
Unit
IDDHIBERNATE2
TBD
μA
3
TBD
μA
IDDRTC
1
Nominal assumes an operating temperature of 25°C.
2
Measured at VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V).
3
Measured at VDDRTC = 3.3 V at 25°C.
1.5V
1.5V
Figure 40. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of Figure 41, “Output Enable/Disable,” on page 47.
VDDINT1
IDD (nominal2)
Unit
0.80
19.00
mA
0.90
25.00
mA
The time tENA_MEASURED is the interval, from when the reference
signal switches, to when the output voltage reaches VTRIP(high)
or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for
VDDEXT (nominal) = 2.5/3.3 V. Time tTRIP is the interval from
when the output starts driving to when the output reaches the
VTRIP(high) or VTRIP(low) trip voltage.
1.00
32.00
mA
Time tENA is calculated as shown in the equation:
1.10
40.00
mA
t ENA = t ENA_MEASURED – t TRIP
1.26
54.00
mA
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Table 34. Internal Power Dissipation (Deep Sleep mode)
1
2
Assumes VDDINT is regulated externally.
Nominal assumes an operating temperature of 25°C.
Output Disable Time Measurement
Table 35. Internal Power Dissipation (Full On1 mode)
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 41.
t DIS = t DIS_MEASURED – t DECAY
VDDINT2 @ fCCLK (MHz)
IDD (nominal3)
Unit
0.8 @ 50 MHz
32.00
mA
0.8 @ 250 MHz
72.00
mA
0.9 @ 300 MHz
98.00
mA
1.0 @ 350 MHz
132.00
mA
1.1 @ 444 MHz
180.00
mA
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay time
can be approximated by the equation:
1.26 @ 500 MHz
235.00
mA
t DECAY = ( C L ΔV ) ⁄ I L
1
Processor executing 75% dual MAC, 25% ADD with moderate data bus
activity.
2
Assumes VDDINT is regulated externally.
3
Nominal assumes an operating temperature of 25°C.
Rev. PrD |
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.5 V for VDDEXT (nominal) = 2.5/3.3 V.
The time tDIS+_MEASURED is the interval from when the reference signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
Page 46 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Example System Hold Time Calculation
Capacitive Loading
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF538/ADSP-BF538F
processor’s output voltage and the input threshold for the
device requiring the hold time. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be tDECAY plus the various output disable times as specified in the Timing Specifications on
Page 24 (for example tDSDAT for an SDRAM write cycle as shown
in Table 20 on Page 29).
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 42). VLOAD is 1.5 V for VDDEXT
(nominal) = 2.5/3.3 V. Figure 43 through Figure 52 on Page 49
show how output rise time varies with capacitance. The delay
and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
ABE0 (133 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C
RISE AND FALL TIME ns (10% t0 90%)
14
REFERENCE
SIGNAL
tDIS_MEASURED
tDIS
tENA-MEASURED
tENA
VOH
(MEASURED)
VOL
(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VOH
2.0V (MEASURED)
VOL (MEASURED) + ⌬V
1.0V
tDECAY
VOL
(MEASURED)
tTRIP
12
RISE TIME
10
FALL TIME
8
6
4
2
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
0
0
50
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
200
250
Figure 43. Typical Output Delay or Hold for Driver A at VDDEXT MIN
Figure 41. Output Enable/Disable
50⍀
TO
OUTPUT
PIN
100
150
LOAD CAPACITANCE (pF)
ABE0 (133 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C
1.5V
RISE AND FALL TIME ns (10% to 90%)
12
30pF
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 44. Typical Output Delay or Hold for Driver A at VDDEXT MAX
Rev. PrD |
Page 47 of 56 |
May 2006
250
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
CLKOUT (CLKOUT DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C
10
RISE TIME
8
FALL TIME
6
30
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
12
4
0
50
100
150
LOAD CAPACITANCE (pF)
200
15
FALL TIME
10
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 47. Typical Output Delay or Hold for Driver C at VDDEXT MIN
CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C
9
8
RISE TIME
7
6
FALL TIME
5
4
3
2
1
PF9 (33 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C
20
RISE AND FALL TIME ns (10% to 90%)
10
RISE AND FALL TIME ns (10% to 90%)
RISE TIME
20
0
0
250
Figure 45. Typical Output Delay or Hold for Driver B at VDDEXT MIN
0
25
5
2
0
PF9 (33 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C
18
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 46. Typical Output Delay or Hold for Driver B at VDDEXT MAX
Rev. PrD |
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 48. Typical Output Delay or Hold for Driver C at VDDEXT MAX
Page 48 of 56 |
May 2006
250
Preliminary Technical Data
SCK (66 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C
18
PH0 VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C
36
16
14
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
ADSP-BF538/ADSP-BF538F
RISE TIME
12
10
FALL TIME
8
6
4
32
28
RISE TIME
24
20
16
FALL TIME
12
8
2
4
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 49. Typical Output Delay or Hold for Driver D at VDDEXT MIN
Figure 51. Typical Output Delay or Hold for Driver E at VDDEXT MIN
SCK (66 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C
PH0 VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C
36
12
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
14
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
32
28
RISE TIME
24
20
16
FALL TIME
12
8
4
0
0
Figure 50. Typical Output Delay or Hold for Driver D at VDDEXT MAX
50
100
150
LOAD CAPACITANCE (pF)
200
Figure 52. Typical Output Delay or Hold for Driver E at VDDEXT MAX
Rev. PrD |
Page 49 of 56 |
May 2006
250
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE + ( Ψ JT × P D )
where:
TJ = Junction temperature (ⴗC)
TCASE = Case temperature (ⴗC) measured by customer at top
center of package.
ΨJT = From Table 36
PD = Power dissipation (see Power Dissipation on Page 46 for
the method to calculate PD)
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
T J = T A + ( θ JA × P D )
where:
TA = Ambient temperature (ⴗC)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heatsink is
required.
Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 36, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Table 36. Thermal Characteristics 316-ball BGA
Parameter
Condition
Typical
Unit
θJA
0 linear m/s air flow
TBD
ⴗC/W
θJMA
1 linear m/s air flow
TBD
ⴗC/W
θJMA
2 linear m/s air flow
TBD
ⴗC/W
θJB
TBD
ⴗC/W
θJC
TBD
ⴗC/W
TBD
ⴗC/W
ψJT
0 linear m/s air flow
Rev. PrD |
Page 50 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
316-BALL MINI-BGA PINOUT
Table 37 on Page 52 lists the mini-BGA pinout by pin number.
Table 38 on Page 53 lists the mini-BGA pinout by signal.
A1 BALL
A1 BALL
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VDDINT
GND
VDDRTC
NC
VDDEXT
I/O
VROUTx
FLASH CONTROL
Y
20 19 18 17 16 15 14 13 12 11 10 9
GND
VDDINT
VDDRTC
VDDEXT
Figure 53. 316-Ball Mini-BGA Pin Configuration (Top View)
I/O
VROUTx
8
7
6
5
4
3
2
1
NC
FLASH CONTROL
Figure 54. 316-Ball Mini-BGA Pin Configuration (Bottom View)
Rev. PrD |
Page 51 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 37. 316-Ball Mini-BGA Pin Assignment (Numerically by Pin Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
C3
C4
C5
C6
Signal
GND
PF10
PF11
PPI_CLK
PPI0
PPI2
PF15
PF13
VDDRTC
RTXO
RTXI
GND
CLKIN
XTAL
GND
NC
GND
GPW
VROUT1
GND
PF8
GND
PF9
PF3
PPI1
PPI3
PF14
PF12
SCL0
SDA0
CANRX
CANTX
NMI
RESET
VDDEXT
GND
PC9
GND
GND
VROUT0
PF6
PF7
GND
GND
RX1
TX1
Ball No.
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
D2
D3
D7
D8
D9
D10
D11
D12
D13
D14
D18
D19
D20
E1
E2
E3
E7
E8
E9
E10
E11
E12
E13
E14
E18
E19
E20
F1
F2
F3
F7
Signal
SPI2SEL
SPI2SS
MOSI2
MISO2
SCK2
VDDINT
SPI1SEL
MISO1
SPI1SS
MOSI1
SCK1
GND
PC6
SCKE
PF4
PF5
DT1SEC
GND
GND
GND
GND
GND
GND
GND
GND
GND
PC7
SMS
PF1
PF2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PC5
ARDY
PF0
MISO0
GND
GND
Ball No.
F8
F9
F10
F11
F12
F13
F14
F18
F19
F20
G1
G2
G3
G7
G8
G9
G10
G11
G12
G13
G14
G18
G19
G20
H1
H2
H3
H7
H8
H9
H10
H11
H12
H13
H14
H18
H19
H20
J1
J2
J3
J7
J8
J9
J10
J11
Signal
GND
GND
GND
GND
GND
GND
GND
DT3PRI
PC4
PC8
SCK0
MOSI0
DT0SEC
GND
GND
GND
GND
GND
GND
GND
GND
BR
CLKOUT
SRAS
DT1PRI
TSCK1
DR1SEC
GND
GND
GND
GND
GND
GND
GND
GND
FCE
SCAS
SWE
TFS1
DR1PRI
DR0SEC
GND
GND
GND
GND
GND
Ball No.
J12
J13
J14
J18
J19
J20
K1
K2
K3
K7
K8
K9
K10
K11
K12
K13
K14
K18
K19
K20
L1
L2
L3
L7
L8
L9
L10
L11
L12
L13
L14
L18
L19
L20
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
M18
Rev. PrD |
Signal
GND
GND
GND
AMS0
AMS2
SA10
RFS1
TMR2
VDDEXT
GND
GND
GND
GND
GND
GND
GND
GND
AMS3
AMS1
AOE
RSCK1
TMR1
GND
GND
GND
GND
GND
GND
GND
GND
GND
TSCK3
ARE
AWE
DT0PRI
TMR0
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
TFS3
Page 52 of 56 |
Ball No.
M19
M20
N1
N2
N3
N7
N8
N9
N10
N11
N12
N13
N14
N18
N19
N20
P1
P2
P3
P7
P8
P9
P10
P11
P12
P13
P14
P18
P19
P20
R1
R2
R3
R7
R8
R9
R10
R11
R12
R13
R14
R18
R19
R20
T1
T2
May 2006
Signal
ABE0
ABE1
TFS0
DR0PRI
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
DT3SEC
ADDR1
ADDR2
TSCK0
RFS0
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
DR3SEC
ADDR3
ADDR4
TX0
RSCK0
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
DR3PRI
ADDR5
ADDR6
RX0
EMU
Ball No.
T3
T7
T8
T9
T10
T11
T12
T13
T14
T18
T19
T20
U1
U2
U3
U7
U8
U9
U10
U11
U12
U13
U14
U18
U19
U20
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
Signal
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
RFS3
ADDR7
ADDR8
TRST
TMS
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
RSCK3
ADDR9
ADDR10
TDI
GND
GND
BMODE1
BMODE0
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
DR2SEC
BG
BGH
DT2SEC
GND
GND
ADDR11
ADDR12
Ball No.
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Signal
TCK
GND
DATA15
DATA13
DATA11
DATA9
DATA7
DATA5
DATA3
DATA1
RSCK2
DR2PRI
DT2PRI
RX2
TX2
ADDR18
ADDR15
ADDR13
GND
ADDR14
GND
TDO
DATA14
DATA12
DATA10
DATA8
DATA6
DATA4
DATA2
DATA0
RFS2
TSCK2
TFS2
FRESET
SCL1
SDA1
ADDR19
ADDR17
ADDR16
GND
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 38. 316-Ball Mini-BGA Pin Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CANRX
CANTX
CLKIN
CLKOUT
DATA0
DATA1
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
Ball No.
M19
M20
N19
U20
V19
V20
W18
W20
W17
Y19
Y18
W16
Y17
N20
P19
P20
R19
R20
T19
T20
U19
J18
K19
J19
K18
K20
E20
L19
L20
V14
V15
V5
V4
G18
B11
B12
A13
G19
Y10
W10
Y5
W5
Y4
W4
Y3
W3
Signal
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DR2PRI
DR2SEC
DR3PRI
DR3SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
DT2PRI
DT2SEC
DT3PRI
DT3SEC
EMU
FCE
FRESET
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
Y9
W9
Y8
W8
Y7
W7
Y6
W6
N2
J3
J2
H3
W12
V13
R18
P18
M1
G3
H1
D3
W13
V16
F18
N18
T2
H18
Y14
A1
A12
A20
B2
B18
B19
C3
C4
C18
D7
D8
D9
D10
D11
D12
D13
D14
D18
E3
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
E7
E8
E9
F8
F9
F10
F11
F12
F13
F14
G7
G8
G9
E10
E11
E12
E13
E14
E18
F3
F7
G10
G11
G12
G13
G14
H7
H8
H9
H10
H11
H12
H13
H14
J7
J8
J9
J10
J11
J12
J13
J14
K7
K8
K9
K10
Rev. PrD |
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
K11
K12
K13
L13
L14
M3
M8
M9
M10
M11
M12
M13
N3
K14
L3
L7
L8
L9
L10
L11
L12
N8
N9
N10
N11
N12
N13
P3
P8
P9
P10
P11
P12
P13
R3
R8
R9
R10
R11
R12
R13
T3
U3
V2
V3
V6
Page 53 of 56 |
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GPW
MISO0
MISO1
MISO2
MOSI0
MOSI1
MOSI2
NC
NMI
PC4
PC5
PC6
PC7
PC8
PC9
PF0
PF1
PF10
PF11
PF12
PF13
PF14
PF15
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
May 2006
Ball No.
V17
V18
W2
W19
Y1
Y20
A15
B16
A17
A18
F2
C14
C10
G2
C16
C9
A16
B13
F19
E19
C19
D19
F20
C17
F1
E1
A2
A3
B8
A8
B7
A7
E2
B4
D1
D2
C1
C2
B1
B3
A4
A5
B5
A6
B6
B14
Signal
RFS0
RFS1
RFS2
RFS3
RSCK0
RSCK1
RSCK2
RSCK3
RTXI
RTXO
RX0
RX1
RX2
SA10
SCAS
SCK0
SCK1
SCK2
SCKE
SCL0
SCL1
SDA0
SDA1
SMS
SPI1SEL
SPI1SS
SPI2SEL
SPI2SS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TFS2
TFS3
TMR0
TMR1
TMR2
TMS
TRST
TSCK0
TSCK1
TSCK2
TSCK3
Ball No.
P2
K1
Y11
T18
R2
L1
W11
U18
A11
A10
T1
C5
W14
J20
H19
G1
C17
C11
C20
B9
Y15
B10
Y16
D20
C13
C15
C7
C8
G20
H20
W1
V1
Y2
N1
J1
Y13
M18
M2
L2
K2
U2
U1
P1
H2
Y12
L18
Signal
TX0
TX1
TX2
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
R1
C6
W15
K3
B15
T8
T9
T10
T11
U7
U8
U9
U10
U11
V7
M7
N7
P7
R7
T7
V8
V9
V10
V11
C12
M14
N14
P14
R14
T12
T13
T14
U12
U13
U14
V12
A9
B20
A19
A14
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
OUTLINE DIMENSIONS
Dimensions in Figure 55—316-Ball Mini Ball Grid Array
(BC-316) are shown in millimeters.
15.20 BSC SQ
17.00 BSC SQ
A1 BALL
0.80 BSC BALL PITCH
A1 BALL INDICATOR
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
TOP VIEW
0.30 MIN
0.12 MAX
COPLANARITY
1.70
1.61
1.46
SIDE VIEW
0.50
BALL DIAMETER 0.45
0.40
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM,
WITH THE EXCEPTION OF BALL DIAMETER.
3. CENTER DIMENSIONS ARE NOMINAL.
Figure 55. 316-Ball Mini Ball Grid Array (BC-316)
Rev. PrD |
Page 54 of 56 |
May 2006
SEATING PLANE
DETAIL A
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
SURFACE MOUNT DESIGN
Table 39 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pattern Standard.
Table 39. BGA Data for Use with Surface Mount Design
Solder Mask
Package
Ball Attach Type
Opening
Ball Pad Size
316-Ball Mini Ball Grid Array Solder Mask Defined 0.40 mm diameter 0.50 mm diameter
(BC-316)
ORDERING GUIDE
Model 1
ADSP-BF538BBCZ-4A
Temperature
Range2
Instruction Flash
Rate (Max) Memory
–40ºC to +85ºC 400 MHz
NA
Operating Voltage
(Nominal)
Package Description
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
Package
Option
BC-316
ADSP-BF538BBCZ-4F4
–40ºC to +85ºC 400 MHz
512K byte
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
BC-316
ADSP-BF538BBCZ-4F8
–40ºC to +85ºC 400 MHz
1M byte
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
BC-316
ADSP-BF538BBCZ-5A
–40ºC to +85ºC 500 MHz
NA
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
BC-316
ADSP-BF538BBCZ-5F4
–40ºC to +85ºC 500 MHz
512K byte
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
BC-316
ADSP-BF538BBCZ-5F8
–40ºC to +85ºC 500 MHz
1M byte
1.2 V internal, 2.5 V or 3.3 V I/O 316-Ball Mini BGA
BC-316
1
2
Z = Pb-free part.
Referenced temperature is ambient temperature.
Rev. PrD |
Page 55 of 56 |
May 2006
Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06172-0-5/06(PrD)
Rev. PrD |
Page 56 of 56 |
May 2006